WO2022206733A1

WO2022206733A1 - Signal transmission network, chip, and signal processing device

Info

Publication number: WO2022206733A1
Application number: PCT/CN2022/083590
Authority: WO
Inventors: 严波; 方超敏; 王悦
Original assignee: 普源精电科技股份有限公司
Priority date: 2021-03-29
Filing date: 2022-03-29
Publication date: 2022-10-06
Also published as: CN113078923A; CN113078923B

Abstract

Disclosed are a signal transmission network, a chip, and a signal processing device. The signal transmission network comprises: an impedance unit comprising a signal input end and a plurality of signal output ends, the impedance unit being configured to perform different degrees of gain adjustment on an input signal received by the signal input end and then convert the input signal into a plurality of different current signals, and the plurality of different current signals being respectively supplied to the plurality of signal output ends; and a gating switch unit comprising a plurality of switch input ends and a switch output end, the plurality of switch input ends being connected to the plurality of signal output ends in a one-to-one correspondence manner, and the gating switch unit being configured to selectively turn on one switch input end and the switch output end so as to output a current signal.

Description

Signal transmission network, chip and signal processing device

This application claims the priority of the Chinese patent application with application number 202110335542.4 filed with the China Patent Office on March 29, 2021, the entire contents of which are incorporated herein by reference.

technical field

The present application relates to the technical field of integrated circuits, for example, to a signal transmission network, a chip and a signal processing device.

Background technique

Various types of signal processing devices, such as desktop oscilloscopes, virtual oscilloscopes and data acquisition cards, can process and analyze the signals they receive. Usually, the signal received by the signal processing device is a voltage signal, and a signal transmission path configured to transmit and process the received voltage signal is provided in the signal processing device. The transmission mode of high-frequency signals on chips and printed circuit boards (Printed Circuit Board, PCB) mainly uses active and passive devices, builds networks and buffers, and transmits high-frequency voltage signals to the next through amplitude adjustment. stage circuit.

However, the signal is propagated step by step in the network in the form of voltage, which has high requirements on the bandwidth of each segment of the network. The overall bandwidth of the network depends on the minimum bandwidth of the devices used, while the bandwidth and linearity of the signal buffer composed of active devices The bandwidth of the signal transmission path cannot be guaranteed, so that the bandwidth of the signal transmission path cannot be further improved; at the same time, the signal transmission network is very sensitive to the wire length, parasitic resistance and parasitic capacitance, and the process deviation will affect the bandwidth of the signal transmission path; When a large signal is input or the signal chain is long, additional signal amplitude adjustment is required to match the input amplitude range of the subsequent circuit, which will increase the complexity of the circuit.

SUMMARY OF THE INVENTION

The present application provides a signal transmission network, a chip and a signal processing device to simplify the circuit structure and further improve the bandwidth of the signal transmission path.

The present application provides a signal transmission network, including:

The impedance unit includes a signal input end and a plurality of signal output ends, the impedance unit is configured to convert the input signal received by the signal input end into a plurality of different current signals after performing different gain adjustments to the signal input end, the plurality of different current signals. different current signals are respectively provided to the plurality of signal output terminals;

The gating switch unit includes a plurality of switch input ends and a switch output end, the plurality of switch input ends and the plurality of signal output ends are connected in one-to-one correspondence, and the gating switch unit is configured to selectively conduct one a switch input terminal and the switch output terminal to output a current signal.

The present application also provides a chip, including: the above-mentioned signal transmission network.

The present application also provides a signal processing device, comprising: the above-mentioned chip.

Description of drawings

1 is a schematic structural diagram of a signal transmission network provided by an embodiment of the present application;

2 is a schematic structural diagram of an impedance unit provided by an embodiment of the present application;

3 is a schematic structural diagram of another impedance unit provided by an embodiment of the present application;

4a is a schematic structural diagram of another impedance unit provided by an embodiment of the present application;

FIG. 4b is a schematic structural diagram of another impedance unit provided by an embodiment of the present application;

5 is a schematic structural diagram of a signal attenuation network provided by an embodiment of the present application;

6 is a schematic diagram of a circuit structure of a signal attenuation network provided by an embodiment of the present application;

7 is a schematic structural diagram of another signal transmission network provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of another signal transmission network provided by an embodiment of the present application.

Detailed ways

The present application will be described below with reference to the accompanying drawings and embodiments. The specific embodiments described herein are merely used to explain the present application. For the convenience of description, only the parts related to the present application are shown in the drawings.

Embodiments of the present application provide a signal transmission network, which can perform different degrees of gain adjustment on an input signal, and the signal transmission network can be set in a chip, the chip can be integrated in a signal processing device, and the signal processing Devices include, but are not limited to, oscilloscopes.

FIG. 1 is a schematic structural diagram of a signal transmission network provided by an embodiment of the present application. As shown in FIG. 1 , the impedance unit 10 of the signal transmission network includes a signal input terminal In10 and a plurality of signal output terminals (Out11, Out12, Out13, . . . , Out1n). The impedance unit 10 processes the input signal Vin received by the signal input terminal In10 After different degrees of gain adjustment, it is converted into multiple different current signals (I1, I2, I3, ..., In), and the multiple different current signals (I1, I2, I3, ..., In) are respectively provided to multiple signals Output terminals (Out11, Out12, Out13, . In22, In23, . ..., or In2n) and the switch output terminal Out20 to output a corresponding current signal (I1, I2, I3, ..., or In).

The implementations of the impedance unit 10 and the gating switch unit 20 are related to the functions to be implemented by themselves, and those skilled in the art can set them according to actual conditions, which are not limited here. The input signal Vin received by the signal input terminal In10 of the impedance unit 10 is usually a voltage signal, and the voltage signal Vin is converted into a plurality of current signals after being adjusted by the impedance unit 10 to different degrees of gain, so that the input signal Vin is in the form of a current signal. Compared with the direct transmission of voltage signals, the impedance unit 10 converts the input signal Vin into a current signal for transmission, which enables the impedance unit 10 to have a larger bandwidth, thereby It is beneficial to improve the bandwidth of the signal transmission network, thereby helping to improve the accuracy of the signal transmitted by the signal transmission network; at the same time, the impedance unit 10 is used to adjust the gain of the input signal Vin to different degrees, and it is not necessary to set the gain adjustment to achieve different degrees. Multiple signal transmission paths can simplify the structure of the signal transmission path, and can solve the problem that when multiple signal transmission paths are set due to different degrees of gain adjustment, there are process deviations between different signal transmission paths and thus affect the overall bandwidth of the signal transmission path. technical problem.

FIG. 1 only exemplarily shows that the impedance unit 10 includes one signal input terminal In10 and n signal output terminals (Out11, Out12, Out13, . Similarly, FIG. 1 only exemplarily shows that the gate switch unit 20 includes n switch input terminals (In21, In22, In23, . . . , In2n) and one switch output terminal Out20, and in this In the embodiment of the application, the gating switch unit may also include a plurality of switch output terminals. The number of signal input ends of the impedance unit in the embodiment of the present application may be smaller than the number of signal output ends thereof, and the number of switch input ends of the gating switch unit may be greater than the number of switch output ends thereof. For ease of description, the embodiments of the present application exemplarily take the impedance unit including one signal input end and n signal output ends, and the gating switch unit including n switch input ends and one switch output end as examples. The technical solution is exemplified.

Exemplarily, the impedance unit 10 can convert the input signal Vin received by the signal input terminal In10 into a plurality of different current signals (I1, I2, I3, . When the unit 20 chooses to turn on one of its switch input terminals (In21, In22, In23, ..., or In2n) and the switch output terminal Out20, it can transmit the corresponding current signal (I1, I2, I3, ..., or In) as a signal The output signal Iout of the network. For example, when the impedance unit 10 needs to output the current signal I1 after the gain adjustment and conversion as the output signal Iout, the gating switch unit 20 selects to turn on the switch input terminal In21 and the switch output terminal Out20, so that the current signal I1 is transmitted by the switch Output terminal Out20 output.

When the impedance unit 10 needs to perform gain adjustment and output other current signals (I2, I3, . In2n) is turned on with the switch output terminal Out20, and its technical principle and control method are similar to the above-mentioned selection of the output current signal I1. This will not be repeated here.

The realization forms of the impedance unit 10 and the gating switch unit 20 are related to their own functions, and those skilled in the art can set them according to the actual situation. The structures of the impedance unit 10 and the gating switch unit 20 are exemplarily described below for examples only.

Optionally, FIG. 2 is a schematic structural diagram of an impedance unit provided by an embodiment of the present application. 1 and 2, on the basis of the above embodiment, the impedance unit 10 further includes a plurality of signal attenuation networks (111, 112, 113, ..., 11n); a plurality of signal attenuation networks (111, 112, 113) , ..., 11n) is connected between the signal input terminal In10 and multiple signal output terminals (Out11, Out12, Out13, ..., Out1n); multiple signal attenuation networks (111, 112, 113, ..., 11n) are set to be respectively The input signal Vin is converted into a number of different current signals (I1, I2, I3, ..., In) after being adjusted with different degrees of gain, and the multiple different current signals (I1, I2, I3, ..., In) They are respectively provided to multiple signal output terminals (Out11, Out12, Out13, . . . , Out1n).

Exemplarily, taking the impedance unit 10 including n signal attenuation networks (111, 112, 113, ..., 11n) as an example, the n signal attenuation networks (111, 112, 113, ..., 11n) can Different degrees of gain adjustment are converted into corresponding current signals (I1, I2, I3, . The current signal I1 converted by the network 111 is output as the output signal Iout. Correspondingly, when the switch module 20 turns on other switch input terminals (In22, In23, . The converted current signal (I2, I3, . . . , or In) is output as the output signal Iout. In this way, the gating switch unit 20 selectively turns on the switch input terminals (In21, In22, In23, . ..., or In) is output as the output signal Iout.

According to the degree to which each signal attenuation network (111, 112, 113, . )Structure. Exemplarily, taking the attenuation degree of the n signal attenuation networks (111, 112, 113, . 111, 112, 113, ..., 11n) can be composed of one or more RC series-parallel circuits, and the number of RC series-parallel circuits set in the signal attenuation network with a small attenuation degree can be smaller than that of a signal with a large attenuation degree. The number of RC series-parallel circuits set up in the network.

FIG. 2 is only an exemplary drawing of the embodiment of the present application, and FIG. 2 exemplarily shows that the signal attenuation networks (111, 112, 113, . . . , 11n) with different attenuation degrees are independent of each other; In order to achieve different degrees of gain adjustment in the application embodiment, the n signal attenuation networks ( 111 , 112 , 113 , . . . , 11n ) in the impedance unit 10 may also be set in other manners.

Optionally, FIG. 3 is a schematic structural diagram of another impedance unit provided by an embodiment of the present application. As shown in FIG. 3 , n signal attenuation networks ( 111 , 112 , 113 , . . . , 11n ) of the impedance unit 10 are cascaded. Wherein, the connection relationship of the cascaded set of signal attenuation networks may be: the input terminal of the first-stage signal attenuation network 111 is connected to the signal input terminal In10, from the first-level signal attenuation network 111 to the nth-level signal attenuation network 11n. One end of the other signal attenuation networks (112, 113, ...) in between is connected to the signal attenuation network of the previous stage, and the other end is connected to the signal attenuation network of the next stage. For example, one end of the signal attenuation network 112 is connected to the signal attenuation network 111. The other end of the attenuation network 112 is connected to the signal attenuation network 113; and the n signal attenuation networks (111, 112, 113, ..., 11n) can be one-to-one with the n signal output terminals (Out11, Out12, Out13, ..., Out1n) corresponding connection. In this way, when the signal attenuation network is composed of an RC series-parallel circuit, the attenuation levels of the n signal attenuation networks (111, 112, 113, ..., 11n) from the signal attenuation network 111 to the signal attenuation network 11n are increased or sequentially On the premise of reduction, it is beneficial to reduce the number of RC series-parallel circuits set in the entire impedance unit 10 .

Optionally, FIG. 4a is a schematic structural diagram of another impedance unit provided by an embodiment of the present application. As shown in FIG. 4a, the impedance unit 10 may further include at least one filter network 12 on the basis of including multiple signal attenuation networks (111, 112, 113, . . . , 11n ); The attenuation networks (111, 112, 113, ..., 11n) are cascaded and arranged between the signal input terminal In10 and the filter network 12 in turn; the first-level signal attenuation network 111 to the last-level signal attenuation network 11n for each level of signal The attenuation input terminal of the attenuation network (112, 113, ...) is electrically connected to the attenuation cascade terminal of the previous stage signal attenuation network, the attenuation input terminal of the first stage signal attenuation network 111 is connected to the signal input terminal In10, and the last stage signal The attenuation cascade terminal of the attenuation network 11n is connected to the filter network 12; the attenuation output terminals of the n signal attenuation networks (111, 112, 113, ..., 11n) and the n signal output terminals (Out11, Out12, Out13, ..., Out1n) ) are connected in one-to-one correspondence; the filtering network 12 is set to filter out signals within a preset frequency range.

Referring to FIG. 1 and FIG. 4 a , in the actual working process, the gain adjustment degree of the input signal Vin can be selected according to the voltage of the input signal Vin. Exemplarily, when the input signal Vin input to the signal input terminal In10 is a signal with a relatively large voltage, it can be attenuated by a multi-stage signal attenuation network and then output, and when the input signal Vin input to the signal input terminal In10 is a signal with a relatively high voltage When the signal is small, it can be attenuated by fewer stages of signal attenuation network and then output. For example, the implementation can be as follows: when the voltage of the input signal Vin received by the signal input terminal In10 is in the first voltage range, the gate switch unit 20 can The switch input terminal In21 and the switch output terminal Out20 are selected to be turned on, so that the input signal Vin is attenuated by the first-stage signal attenuation network 111 and converted into the corresponding current signal I1 and then output; when the voltage of the input signal Vin received by the signal input terminal In10 In the second voltage range, the gating switch unit 20 can selectively turn on the switch input terminal In22 and the switch output terminal Out20, so that the input signal Vin is sequentially attenuated through the first-stage signal attenuation network 111 and the second-stage signal attenuation network 112 and then It is converted into a corresponding current signal I2 and then output; when the voltage of the input signal Vin received by the signal input terminal In10 is in the third voltage range, the gating switch unit 20 can selectively turn on the switch input terminal In23 and the switch output terminal Out20, so that the input The signal Vin is attenuated by the first-level signal attenuation network 111, the second-level signal attenuation network 112 and the third-level signal attenuation network 113 in turn and converted into the corresponding current signal I3 and then output; and so on, when the signal input terminal In10 receives When the voltage of the input signal Vin is in the nth voltage range, the gating switch unit 20 can selectively turn on the switch input terminal In2n and the switch output terminal Out20, so that the input signal Vin passes through the first-stage signal attenuation network 111 and the second-stage signal in turn. The attenuation network 112 , the third-level signal attenuation network 113 , . . . and the nth-level signal attenuation network 11 n are attenuated and converted into corresponding current signals In and then output. Wherein, the voltage in the first voltage range is smaller than the voltage in the second voltage range, the voltage in the second voltage range is smaller than the voltage in the third voltage range, . . . , the voltage in the nth voltage range is greater than the other voltages voltage within the voltage range.

At the same time, a filter network 12 is electrically connected to the attenuation cascade end of the n-th signal attenuation network 11n to filter out the signal within the preset frequency range, so as to filter out the noise in the signal transmission path, especially the first-level signal in sequence. The noise in the current signal In converted after attenuation by the attenuation network 111, the second-level signal attenuation network 112, the third-level signal attenuation network 113, . . , Out12, Out13, .

When n signal attenuation networks ( 111 , 112 , 113 , . . . , 11n ) in the impedance unit 10 are cascaded between the signal input terminal In10 and the filter network 12 , those skilled in the art can convert the n signals according to actual needs. The structure of the decay network is set to be the same or different.

In one embodiment, when the impedance unit includes a plurality of filter circuits, each filter circuit can be set at the connection point between the adjacent two-stage signal attenuation networks, and each filter circuit and the subsequent stage can be controlled by a switch The relationship of the signal attenuation network. Referring to Fig. 4b, a filter circuit 12 can be designed for the first-stage signal attenuation network 111, and the filter circuit 12 is arranged between the first-stage signal attenuation network 111 and the second-stage signal attenuation network 112. When the second-level signal attenuation network 112 is used, the filter circuit 12 cannot affect the current transmission between the first-level signal attenuation network 111 and the second-level signal attenuation network 112 . Similarly, corresponding filter circuits 12 can be designed for other signal attenuation networks (112, 113, . . . , 11(n-1)).

Optionally, FIG. 5 is a schematic structural diagram of a signal attenuation network provided by an embodiment of the present application. As shown in FIG. 5 , each signal attenuation network includes a DC signal attenuation network 1111 and a high-frequency signal attenuation network 1112; the DC signal attenuation network 1111 and the high-frequency signal attenuation network 1112 are connected in series and/or parallel; wherein the DC signal attenuation The network 1111 is set to convert the DC type input signal Vin received by the signal input terminal In10 into a corresponding current signal after gain adjustment; the high frequency signal attenuation network 1112 is set to convert the high frequency type input signal Vin received by the signal input terminal In10 After the gain adjustment is performed, it is converted into the corresponding current signal.

The DC signal attenuation network 1111 and the high-frequency signal attenuation network 1112 of the signal attenuation network 111 may be connected in parallel, in series, or in a series-parallel connection. Exemplarily, taking the connection of the DC signal attenuation network 1111 and the high-frequency signal attenuation network 1112 in a series-parallel connection as an example, the DC signal attenuation network 1111 and the high-frequency signal attenuation network 1112 have the same input terminal, which is the same as the signal input terminal. The terminal In10 or the signal attenuation network of the previous stage is connected. The DC signal attenuation network 1111 and the high frequency signal attenuation network 1112 also have the same output terminal, and both are connected to the same signal output terminal Out11. In this way, the signal attenuation network 111 can have a fixed impedance from the DC frequency band to the designated high frequency frequency band to ensure that the signal has a corresponding amplitude value in the entire frequency band, so that each signal attenuation network can have good frequency response characteristics.

For other signal attenuation networks ( 112 , 113 , . . . , 11n ), they may include a DC signal attenuation network 1111 and a high-frequency signal attenuation network 1112 , the technical principle and structure of which are similar to the above-mentioned signal attenuation network 111 . The description of the signal attenuation network 111 will not be repeated here. For ease of description, the following takes the structure of the signal attenuation network 111 as an example to illustrate the implementation of the signal attenuation network.

Both the DC signal attenuation network 1111 and the high frequency signal attenuation network 1112 may include active devices and/or passive devices, and the implementation of the DC signal attenuation network 1111 and the high frequency signal attenuation network 1112 is not limited. Wherein, the active device may be, for example, a device such as a transistor, and the passive device may be, for example, a device such as a resistor, a capacitor, or the like.

Optionally, FIG. 6 is a schematic diagram of a circuit structure of a signal attenuation network provided by an embodiment of the present application. 5 and 6, the DC signal attenuation network 1111 includes a first resistor R1 and a second resistor R2 connected in series; the high-frequency signal attenuation network 1112 includes a third resistor R3, a first capacitor C1, a third resistor R3, a first capacitor C1, a Four resistors R4 and a second capacitor C2; wherein, the first resistor R1 is connected in parallel with the first capacitor C1, and the second resistor R2 is connected in parallel with the second capacitor C2.

Exemplarily, when the resistance value of the first resistor R1 is 2R and the resistance value of the second resistor R2 is R, the current signal I1 of the input signal Vin transmitted to the signal output terminal Out11 after passing through the DC signal attenuation network 1111 is Vin/3R. ; Similarly, the frequency response curve of the high-frequency signal attenuation network 1112 is determined by the size of the third resistor R3, the fourth resistor R4, and the first capacitor C1 and the second capacitor C2; can make the third resistor R3 and the fourth resistor R4 The resistance value is smaller than the high-frequency impedance of the first capacitor C1 and the second capacitor C2, and the capacitance value of the first capacitor C1 is set to C, and the capacitance value of the second capacitor C2 is set to 2C, so that the input signal Vin is passed through the high-frequency signal attenuation network 1112. The effective value of the current signal I1 then transmitted to the signal output terminal Out11 is approximately Vin*(ω*C)/3; where ω is the angular frequency.

Illustratively, it is taken as an example that multiple signal attenuation networks of the impedance unit 10 are cascaded between the signal input terminal In10 and the filter network 12 . FIG. 7 is a schematic structural diagram of another signal transmission network provided by an embodiment of the present application. As shown in FIG. 7 , the structure of each signal attenuation network in the impedance unit 10 is the same, and each signal transmission network (111, 112, 113, . . . , 11n) may include a first resistor R1, a second resistor R2, a first Capacitor C1, third resistor R3, fourth resistor R4 and second capacitor C2.

The resistance values of different resistors in the same signal attenuation network can be the same or different, and the capacitance values of different capacitors in the same signal attenuation network can be the same or different; the resistance values of corresponding resistors and/or corresponding capacitors in different signal attenuation networks The capacitance values of the resistors can also be the same or different; in the embodiments of the present application, the resistance values of the resistors and the capacitance values of the capacitors can be set according to actual needs, which are not limited in the embodiments of the present application.

For the DC signal attenuation path, the resistance value of the first resistor R1 of each signal attenuation network is 2R, and the resistance value of the second resistor R2 of each signal attenuation network is R, and other signal attenuation after the signal attenuation network 113 The resistance value of the resistor that adjusts the frequency response of the DC type signal in the network and the filter network 12 is equivalent to 2R, and the gating switch unit 20 selects and turns on one switch input terminal (In21, In22, In23, . . . , or In2n) and switch output terminal Out20, other switch input terminals are grounded as an example, when the switch input terminal In21 and switch output terminal Out20 are turned on, and the other switch input terminals (In22, In23, ..., In2n) are grounded, the input signal Vin will pass through After the signal attenuation network 111, the current signal I1 output by the switch output terminal Out20 is:

When the switch input terminal In22 is connected to the switch output terminal Out20, and the other switch input terminals (In21, In23, ..., In2n) are grounded, the input signal Vin passes through the signal attenuation network 111 and the signal attenuation network 112. The output current signal I2 is:

When the switch input terminal In23 is connected to the switch output terminal Out20, and the other switch input terminals (In21, In22, . The current signal I3 output by the switch output terminal Out20 is:

It can be seen from this that the current signals output by the multiple signal attenuation networks are attenuated proportionally, so that the input signal can be converted into a current signal, and the amplitude of the current signal can be adjusted to achieve different degrees of gain adjustment.

Similarly, for the high-frequency signal attenuation path, the resistance values of the third resistors R3 of multiple signal attenuation networks are the same and all are R, and the fourth resistor R4 of each signal attenuation network can be adjusted according to the actual circuit frequency response characteristics. And, the capacitance value of the first capacitor C1 of each signal attenuation network is C, the capacitance value of the second capacitor C2 of each signal attenuation network is 2C, and the angular frequency of the input signal Vin is ω. For example, when the switch input terminal When In21 is connected to the switch output terminal Out20, and other switch input terminals (In22, In23, ..., In2n) are grounded, after the input signal Vin passes through the signal attenuation network 111, the current signal I1 output by the switch output terminal Out20 is:

It can be seen from this that by setting the capacitance values of the first capacitor C1 and the second capacitor C2, it is possible to ensure that the high-frequency current signal and the DC current signal have a consistent amplitude adjustment ratio within a certain signal input frequency range, so that the signal transmission network is relatively stable. It has a constant impedance characteristic in a large frequency range, and can transmit signals from the DC frequency band to the specified high frequency frequency band, so that the signal transmission network has a wider bandwidth.

FIG. 7 is only an exemplary diagram of the embodiment of the present application, and FIG. 7 only exemplarily shows the cascaded configuration of n signal attenuation networks ( 111 , 112 , 113 , . . . , 11n ). The multiple signal attenuation networks can also be set in other manners, and by determining the implementation manner of the multiple signal attenuation networks as required, the input signal can be adjusted to different degrees of gain.

Meanwhile, FIG. 7 only exemplarily shows that the filter network 12 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5 The fifth resistor R5 is connected in series with the third capacitor C3 to form a first RC series circuit, and the sixth resistor R6 is connected in series with the fourth capacitor C4 to form a second RC series circuit; the first RC series circuit and the second RC series circuit are connected with the seventh The resistor R7 is connected in parallel to form a first filter circuit; the eighth resistor R8 is connected in parallel with the fifth capacitor C5 to form a second filter circuit; wherein the first filter circuit and the second filter circuit are connected in series to the last stage signal attenuation network 11n and ground Between the terminals, the first filter circuit and the second filter circuit connected in series can filter out the signal in the corresponding frequency range, so as to improve the accuracy of the signal transmitted by the impedance unit 10 . However, in the embodiment of the present application, the implementation manner of the filtering network is not limited to this, and may be set according to actual needs, which is not limited in the embodiment of the present application.

Optionally, continuing to refer to FIG. 7 , the gating switch unit 20 further includes a plurality of switch subunits (21, 22, 23, ..., 2n); each switch subunit (21, 22, 23, ..., 2n) ) is electrically connected between the switch input terminals (In21, In22, In23, ..., In2n) and the switch output terminal Out20; the gating switch unit 20 is set to match each switch subunit (21, 22, 23, ..., 2n) conduction state.

The impedance unit 10 can convert the input signal Vin into a plurality of different current signals (I1, I2, I3, . . . , In) after performing gain adjustment to different degrees. At this time, the gating switch unit 20 can determine the gain adjustment degree corresponding to the input signal Vin according to the voltage of the input signal Vin, and select the corresponding switch subunits (21, 22, 23, ..., or 2n) to be turned on. The signal transmission network 10 includes a plurality of cascaded signal attenuation networks (111, 112, 113, ..., 11n), and a plurality of switch subunits (21, 22, 23, ..., 2n) and a plurality of signal attenuation networks ( 111, 112, 113, . . . , 11n) are in one-to-one electrical connection of the attenuation output terminals as an example. When the voltage of the input signal Vin is in the first voltage range, the impedance unit 10 can attenuate the input signal Vin to a small extent, and the gate switch unit 20 can control the switch sub-unit 21 to be turned on, while the other switch sub-units ( 22, 23, . , ..., 2n) are in the off state; when the voltage of the input signal Vin is in the third voltage range, the gate switch unit 20 can control the switch subunit 23 to conduct, while the other switch subunits (21, 22, ..., 2n) are in the disconnected state; by analogy, when the voltage of the input signal Vin is in the nth voltage range, the impedance unit 10 can attenuate the input signal Vin to a large extent, and the gating switch unit 20 can control the switch at this time. The subunit 2n is turned on, and the other switch units (21, 22, 23, . . . ) are all turned off. In this way, the impedance unit 10 combined with each switch subunit (21, 22, 23, .

7 only exemplarily shows the structure of each switch subunit (21, 22, 23, ..., 2n) of the gating switch module 20, that is, each switch subunit (21, 22, 23, ..., 2n) can be a single-pole double-throw switch, and when the switch subunits (21, 22, 23, . 111, 112, 113, ..., or 11n) converted current signals (I1, I2, I3, ..., or In) are transmitted to the switch output terminal Out20; ) is in the disconnected state, its contacts S1 and S3 are electrically connected, so that the attenuation output terminal of the corresponding signal attenuation network (111, 112, 113, ..., or 11n) is grounded. However, the implementation form of the plurality of switch subunits (111, 112, 113, ..., 11n) is not limited to the form shown in FIG. 7, and those skilled in the art can 11n) functions and practical requirements The multiple switch subunits (111, 112, 113, . . . , 11n) are designed into different structures.

Optionally, FIG. 8 is a schematic structural diagram of still another signal transmission network provided by an embodiment of the present application. As shown in FIG. 8 , on the basis of the above embodiment, the signal transmission network further includes a current-voltage conversion unit 30, which is electrically connected to the switch output terminal Out20; the current-voltage conversion unit 30 is configured to convert the current signal Convert it into a voltage signal and output the voltage signal for subsequent analysis and processing. The implementation manner of the current-voltage conversion unit 30 is related to the function to be implemented by itself, and those skilled in the art can set it according to the actual situation, which is not limited here.

Exemplarily, the current-voltage conversion unit 30 may include an operational amplifier U1, the switch output terminal Out20 of the gating switch unit 20 may be electrically connected to the inverting input terminal In- of the operational amplifier U1 in the current-voltage conversion unit 30, and the The non-inverting input terminal In+ can receive the reference signal Vref; at this time, the corresponding gain adjustment degree can be selected as required, and the gating switch module 20 can be controlled to select the corresponding switch input terminal (In21, In22, In23, ..., or In2n) to be turned on. and the switch output terminal Out20, so that the corresponding current signal (I1, I2, I3, ..., or In) is transmitted to the inverting input terminal In- of the operational amplifier U1, and the current signal (I1, I2, I3, ..., ... , or In) after inverting amplification processing by the operational amplifier U1, the corresponding voltage signal Vout is output, that is, the operational amplifier U1 can convert the current signal (I1, I2, I3, ..., or In) into the corresponding voltage signal Vout , and at the same time, a corresponding degree of gain adjustment can be performed on the converted voltage signal Vout.

When the current-voltage conversion unit 30 includes an operational amplifier U1, the operational amplifier U1 may be a transimpedance amplifier, so that the operational amplifier U1 can switch the current signal (I1, I2, I3, . . . , or In) output by the gating switch module 20 It is converted into a corresponding voltage signal and output after amplitude adjustment; or, when the operational amplifier U1 is any other operational amplifier well known to those in the art, the output end of the operational amplifier U1 is also electrically connected to its inverting input end In-, to A corresponding feedback circuit is formed. At this time, the operational amplifier U1 can also realize the function of converting the current signal into a voltage signal.

An embodiment of the present application further provides a chip, and the chip includes the signal transmission network provided by the embodiment of the present application. Therefore, the chip provided by the embodiment of the present application includes the technical features of the signal transmission network provided by the embodiment of the present application, and can achieve the implementation of the present application. For the technical effect of the signal transmission network provided by the example, for the similarities, reference may be made to the above description of the signal transmission network provided by the embodiment of the present application, and details are not repeated here.

Embodiments of the present application further provide a signal processing apparatus, where the signal processing apparatus includes but is not limited to an oscilloscope. The signal processing apparatus provided by the embodiment of the present application includes the chip provided by the embodiment of the present application. Therefore, the signal processing apparatus provided by the embodiment of the present application also includes the technical features of the signal transmission network provided by the embodiment of the present application, and can achieve the requirements provided by the embodiment of the present application. For the technical effect of the signal transmission network, the same can be referred to the above description of the signal transmission network provided by the embodiment of the present application, and details are not repeated here.

Claims

A signal transmission network comprising:

The impedance unit includes a signal input end and a plurality of signal output ends, the impedance unit is configured to convert the input signal received by the signal input end into a plurality of different current signals after performing different gain adjustments to the signal input end, the plurality of different current signals. different current signals are respectively provided to the plurality of signal output terminals;

The gating switch unit includes a plurality of switch input ends and a switch output end, the plurality of switch input ends and the plurality of signal output ends are connected in one-to-one correspondence, and the gating switch unit is configured to selectively conduct one a switch input terminal and the switch output terminal to output a current signal.
The signal transmission network of claim 1, wherein the impedance unit further comprises a plurality of signal attenuation networks;

The multiple signal attenuation networks are connected between the signal input terminals and the multiple signal output terminals; the multiple signal attenuation networks are configured to convert the input signal into the desired signal after performing different degrees of gain adjustment respectively. The plurality of different current signals are provided, and the plurality of different current signals are respectively provided to the plurality of signal output terminals.
3. The signal transmission network of claim 2, wherein the plurality of signal attenuation networks are arranged in cascade.
The signal transmission network of claim 2, wherein the impedance unit further comprises at least one filter network;

The multiple signal attenuation networks are cascaded and arranged between the signal input end and the at least one filter network in sequence; the attenuation of each stage of the signal attenuation network between the first stage signal attenuation network and the last stage signal attenuation network The input terminal is connected to the attenuation cascade terminal of the previous stage signal attenuation network, the attenuation input terminal of the first stage signal attenuation network is electrically connected to the signal input terminal, and the attenuation cascade terminal of the last stage signal attenuation network is electrically connected. connected with the at least one filter network; the attenuation output terminals of the multiple signal attenuation networks are connected with the multiple signal output terminals in a one-to-one correspondence;

The at least one filter network is configured to filter out signals within a predetermined frequency range.
The signal transmission network according to claim 2, wherein each signal attenuation network comprises a direct current signal attenuation network and a high frequency signal attenuation network; the direct current signal attenuation network and the high frequency signal attenuation network are in series and parallel connection. at least one way to connect;

The DC signal attenuation network is configured to perform gain adjustment on the DC-type input signal received by the signal input end and convert it into a current signal corresponding to the DC-type input signal;

The high-frequency signal attenuation network is configured to convert the high-frequency type input signal received by the signal input end into a current signal corresponding to the high-frequency type input signal after gain adjustment.
The signal transmission network of claim 5, wherein the DC signal attenuation network comprises a first resistor and a second resistor connected in series;

The high-frequency signal attenuation network includes a third resistor, a first capacitor, a fourth resistor and a second capacitor connected in series in sequence;

The first resistor is connected in parallel with the first capacitor, and the second resistor is connected in parallel with the second capacitor.
The signal transmission network according to claim 1, wherein the gating switch unit further comprises a plurality of switch subunits; each switch subunit is electrically connected between a switch input end and the switch output end;

The gating switch unit is configured to match the conduction state of each switch subunit according to the target gain.
The signal transmission network of claim 1, further comprising:

A current-to-voltage conversion unit is electrically connected to the switch output end, and the current-to-voltage conversion unit is configured to convert the one current signal into a voltage signal and output the voltage signal.
A chip, comprising: the signal transmission network according to any one of claims 1 to 8.
A signal processing device, comprising: the chip of claim 9 .