WO2022205519A1 - 源驱动芯片及显示装置 - Google Patents

源驱动芯片及显示装置 Download PDF

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Publication number
WO2022205519A1
WO2022205519A1 PCT/CN2021/087753 CN2021087753W WO2022205519A1 WO 2022205519 A1 WO2022205519 A1 WO 2022205519A1 CN 2021087753 W CN2021087753 W CN 2021087753W WO 2022205519 A1 WO2022205519 A1 WO 2022205519A1
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Prior art keywords
signal
source driver
driver chip
row latch
delay control
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PCT/CN2021/087753
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English (en)
French (fr)
Inventor
刘金风
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Tcl华星光电技术有限公司
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Publication of WO2022205519A1 publication Critical patent/WO2022205519A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management

Definitions

  • the present application relates to the field of display technology, and in particular, to a source driver chip and a display device.
  • ESD Electro-Static Discharge, Electrostatic Discharge
  • a display device has a wide range of applications, and its anti-ESD capability has attracted more and more attention.
  • Components such as chips in display devices are easily disturbed by electrostatic shocks.
  • the interference intensity has reached Class C (Class C), which will eventually cause the test result to fail.
  • the present application provides a source driving chip and a display device, which alleviate the technical problem that the source driving chip is susceptible to electrostatic interference.
  • the present application provides a source driver chip, which includes an OR logic operator, a clock buffer, a shift register, and an AND logic operator; the OR logic operator is used to latch a signal and a first output according to an accessed row The data delay control enable signal generates and outputs the corresponding second output data delay control enable signal; the clock buffer is connected to the OR logic operator, and is used for delay control according to the first clock signal and the second output data.
  • the shift register is connected to the clock buffer for generating a plurality of initial row latch sub-signals according to the row latch signal and the second clock signal; AND logic operator AND OR logic The arithmetic unit is connected to the shift register, and is used for generating the corresponding target row latch sub-signal according to the initial row latch sub-signal and the second output data delay control enable signal.
  • the phase difference between two adjacent target row latch sub-signals is the same.
  • the row latch signal is the same as one of the target row latch sub-signals.
  • the second output data delay control enable signal is a pulse signal; when the second output data delay control enable signal is at a low level, the clock buffer stops outputting the second clock signal.
  • the driving capability of the second clock signal is greater than the driving capability of the first clock signal.
  • the shift register includes at least two flip-flops outputting in parallel; the trigger terminal of at least one flip-flop is connected to the output terminal of the clock buffer; the input terminal of at least one flip-flop is connected to the row latch signal.
  • the AND logic operator includes a plurality of AND logic units; an input end of each AND logic unit is connected to an output end of a flip-flop; the other input end of each AND logic unit AND-OR logic operation connected to the output of the device.
  • the source driver chip is used to output the corresponding data signal; the rising edge of the row latch signal is used to instruct the source driver chip to latch the data signal; the falling edge of the row latch signal is used to instruct the source driver chip to output the data signal .
  • the source driver chip further includes a clock module; the output end of the clock module is connected to the input end of the clock buffer.
  • the present application provides a display device, which includes a timing controller and a source driver chip in any of the above embodiments, where the source driver chip is connected to the timing controller.
  • the second output data delay control enable signal is obtained through the OR logic operation of the row latch signal and the first output data delay control enable signal, and the initial row latch
  • the AND logic operation of the signal and the second output data delay control enable signal can reduce or eliminate the electrostatic interference received by the row latch signal, thereby improving the anti-static interference capability of the source driver chip.
  • FIG. 1 is a schematic diagram of a first structure of a source driver chip provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a first timing sequence of a source driver chip provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a second timing sequence of a source driver chip provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a second structure of a source driver chip provided by an embodiment of the present application.
  • FIG. 5 is a third timing diagram of the source driver chip provided by the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a liquid crystal display device provided by an embodiment of the present application.
  • the source driver chip may include a clock buffer 1 and a shift register 2 ; the output end of the clock buffer 1 is connected to the trigger input end of the shift register 2 .
  • the signal input terminal of the shift register 2 is used to access the row latch signal TPX.
  • An input end of the clock buffer 1 is used to access the output data delay control enable signal ODDC1-EN; the other input end of the clock buffer 1 is used to access the initial pulse signal CLK1, and the output end of the clock buffer 1 is used for to output the modulated target pulse signal CLK1X.
  • the shift register 2 is configured to generate and output a plurality of row latch sub-signals TPX1 to TPX80 with different phase delays according to the row latch signal TPX.
  • the source driver chip with this structure is subjected to strong electrostatic interference, the voltage output by the source driver chip is likely to be lower than the voltage during normal display, which in turn causes a picture abnormality in a local area of the display device.
  • the source driver chip When the source driver chip outputs the pixel data of the Nth pixel row LINE(N), first, under the control of the command start signal CS in the received signal control command CMD, the source driver chip delays according to the received data.
  • the enable signal ODDC1-EN and the row latch signal TPX are controlled to start generating row latch sub-signals TPX1 to TPX80 of the Nth pixel row LINE(N).
  • the source driver chip ends the row latch sub-signals TPX1 to TPX80 of the Nth pixel row LINE(N) according to the command end signal CE in the received signal control command CMD.
  • the pixel data of the N+1th pixel line LINE(N+1) starts.
  • the sequence is the pixel data of the N+2th pixel row LINE(N+2) and the pixel data of the N+3th pixel row LINE(N+3) and so on.
  • the row latch sub-signal TPX1 follows the row latch signal TPX to act, and the row latch sub-signal TPX80 is in the row.
  • the action is delayed after the TD1 period.
  • the row latch sub-signal TPX80 is at a low level, after a delay of the TD2 period, the data delay control enable signal ODDC1-EN is pulled down to a low level.
  • the data delay control enable signal ODDC1-EN is pulled up to a high level, and after a delay of the TD period, the row latch signal TPX is pulled up to a high level.
  • TD1 is the delay time of the output data delay control signal.
  • the output data delay control signal (ODDC, Output data Delay Control) is used to adjust the charging rate of different positions, which can improve the display taste.
  • the data delay control enable signal ODDC1-EN is used to control the opening and closing of the output data delay control signal.
  • the data delay control enable signal ODDC1-EN is pulled high to a high level, and after the delay TD period, the line The latch signal TPX is pulled high to a high level.
  • the high level period of the row latch signal TPX is within the high level period of the data delay control enable signal ODDC1-EN.
  • the row latch sub-signals TPX1 to TPX80 normally follow the row latch signal TPX.
  • electrostatic interference causes the high potential period of the row latch signal TPX to be abnormally widened, resulting in the row latch sub-signals TPX1 ⁇ TPX80.
  • the high-potential period is then extended, which compresses the charging time of the current amplifier.
  • the data delay control enable signal ODDC1-EN is abnormally pulled low to a low level, as shown at S10 and S20 in Figure 3, resulting in the data corresponding to the N+2 pixel row LINE (N+2).
  • the delay control enable signal ODDC1-EN is lost.
  • the row corresponding to the N+2 pixel row LINE(N+2) is latched
  • the signal TPX is pulled high to a high potential, so that the row latch sub-signals TPX1 ⁇ TPX80 corresponding to the N+2 pixel row LINE (N+2) are also pulled high to a high potential, and the N+2 pixel row LINE ( N+2)
  • the corresponding row latch signal TPX is pulled down to a low level.
  • the data delay control enable signal ODDC1-EN corresponding to the N+3 pixel row LINE(N+3) is pulled high to a high level, so that the row corresponding to the N+2 pixel row LINE(N+2) is latched
  • the sub-signals TPX1 to TPX80 are sequentially pulled down to a low level.
  • the row latch signal TPX corresponding to the N+3 pixel row LINE(N+3) is pulled up to a high level.
  • the data delay control enable signal ODDC1-EN corresponding to the N+3 pixel row LINE(N+3) is pulled down to a low level, and the row latch signal corresponding to the N+3 pixel row LINE(N+3) TPX is pulled low.
  • the row latch corresponding to the N+3 pixel row LINE(N+3) After the data delay control enable signal ODDC1-EN corresponding to the N+3 pixel row LINE(N+3) is at a low level, the row latch corresponding to the N+3 pixel row LINE(N+3) The signals TPX1 to TPX80 cannot follow the row latch signal TPX corresponding to the N+2 pixel row LINE (N+2) in time to be pulled down to a low level. The charging capability of the current amplifier is insufficient, and the output voltage of the source driver chip cannot reach the normal level, and so on.
  • this embodiment provides a source driver chip 100 , which includes an OR logic operator 10 , a clock buffer 20 , a shift register 30 , and an AND logic operator 40 ; an OR logic operator 10 is used for generating and outputting the corresponding second output data delay control enable signal ODDC-ENX according to the row latch signal TP of the access and the first output data delay control enable signal ODDC-EN; the clock buffer 20 It is connected with the OR logic operator 10, and is used for delaying the control enable signal ODDC-ENX according to the first clock signal CLK and the second output data, and outputting the corresponding second clock signal CLKX; the shift register 30 is connected with the clock buffer 20 , used to generate a plurality of initial row latch sub-signals PTP1 ⁇ PTP80 according to the row latch signal TP and the second clock signal CLKX; connected with the logic operator 40 and the OR logic operator 10 and the shift register 30, used for according to The initial row latch sub-signals PTP1 to PTP80
  • the source driver chip 100 obtained by the present application obtains the second output data delay control enable signal ODDC through the OR logic operation of the row latch signal TP and the first output data delay control enable signal ODDC-EN. -ENX, and the AND logic operation of the initial row latch sub-signals PTP1 ⁇ PTP80 and the second output data delay control enable signal ODDC-ENX can reduce or eliminate the electrostatic interference of the row latch signal TP, thereby improving the The anti-static interference capability of the source driver chip 100 .
  • the easily disturbed first output data delay control enable signal ODDC-EN signal is no longer directly output to the clock buffer 20 (CK Buffer), but by adding an OR logic
  • the arithmetic unit 10 outputs the generated second output data delay control enable signal ODDC-ENX signal after the first output data delay control enable signal ODDC-EN and the row latch signal TP pass through the OR gate, and then outputs it to the output data delay control enable signal ODDC-ENX signal.
  • Clock buffer 20 (CK Buffer).
  • the high-potential period of the row latch signal TP is abnormally widened, and the high-potential period of the target row latch sub-signals TP1 ⁇ TP80 is lengthened accordingly.
  • the first output data delay control enable signal ODDC-EN corresponding to the N+1th pixel row LINE(N+1) is pulled down to a low level, resulting in the N+2th pixel row LINE(N+1). +2) The corresponding first output data delay control enable signal ODDC-EN is lost.
  • the N+2 pixel row LINE(N+2) corresponding to The row latch signal TP is pulled up to a high level, so that the second output data delay control enable signal ODDC-ENX is continuously at a high level, and the initial row latch sub-signals PTP1 ⁇ PTP80 are pulled up to a high level.
  • the row latch signal TP, the target row latch sub-signals TP1 ⁇ TP80 and the first output data delay control enable signal ODDC- EN are all low potentials, which can ensure that the normal timing is restored from the start of the N+3 pixel row LINE(N+3).
  • the first output data delay control enable signal ODDC-EN corresponding to the N+1th pixel row LINE(N+1) is at a low level, because the row latch signal TP is at this time.
  • the second output data delay control enable signal ODDC-ENX after being output by the OR logic operator 10 can be kept at a high level, thereby avoiding the first output data delay control enable signal ODDC-EN Screen abnormality caused by static electricity.
  • the target row latch sub-signals TP1 to TP80 can be forcibly pulled to a low level at this time.
  • the target row latch sub-signals TP1 to TP80 of different phases can be output in sequence normally.
  • this embodiment can enhance the anti-ESD capability of the source driver chip 100 and improve product reliability.
  • phase difference between two adjacent target row latch sub-signals TP1 ⁇ TP80 is the same.
  • phase difference between the target row latch sub-signals TP1 ⁇ TP80TP1 and the target row latch sub-signals TP1 ⁇ TP80TP2 is the same as the phase difference between the target row latch sub-signals TP1 ⁇ TP80TP2 and the target row latch sub-signals TP1 ⁇ TP80TP3
  • the phase differences are equal.
  • the row latch signal TP is the same as one of the target row latch sub-signals TP1 ⁇ TP80 .
  • the frequency and phase of the row latch signal TP may be the same as the frequency and phase of the target row latch sub-signals TP1 to TP80TP1.
  • the second output data delay control enable signal ODDC-ENX is a pulse signal; when the second output data delay control enable signal ODDC-ENX is at a low level, the clock buffer 20 stops outputting the first Two clock signals CLKX.
  • the clock buffer 20 may decide whether to output the second clock signal CLKX according to the potential of the second output data delay control enable signal ODDC-ENX.
  • the driving capability of the second clock signal CLKX is greater than the driving capability of the first clock signal CLK.
  • the clock buffer 20 can be used to enhance the driving capability of the first clock signal CLK, therefore, the driving capability of the second clock signal CLKX is greater than the driving capability of the first clock signal CLK.
  • the shift register 30 includes at least two flip-flops outputting in parallel; the trigger terminal of at least one flip-flop is connected to the output terminal of the clock buffer 20; the input terminal of at least one flip-flop is connected to the row latch signal TP connection.
  • the AND logic operator 40 includes a plurality of AND logic units; an input end of each AND logic unit is connected to an output end of a flip-flop; the other input end of each AND logic unit is AND-OR logic unit The output terminal of the arithmetic unit 10 is connected.
  • the source driver chip 100 is used to output the corresponding data signal; the rising edge of the row latch signal TP is used to instruct the source driver chip 100 to latch the data signal; the falling edge of the row latch signal TP is used to instruct the source driver The chip 100 outputs data signals.
  • the source driver chip 100 further includes a clock module; the output terminal of the clock module is connected to the input terminal of the clock buffer 20 .
  • the present application provides a display device 1000 , which includes a timing controller 200 and the source driver chip 100 in any of the above embodiments, the source driver chip 100 and the timing controller 200 connect.
  • the display device 1000 obtained by the present application obtains the second output data delay control enable signal ODDC-EN through the OR logic operation of the row latch signal TP and the first output data delay control enable signal ODDC-EN.
  • ENX, and the AND logic operation of the initial row latch sub-signals PTP1 ⁇ PTP80 and the second output data delay control enable signal ODDC-ENX can reduce or eliminate the electrostatic interference received by the row latch signal TP, thereby improving the source The anti-static interference capability of the driver chip 100 .
  • the display device 1000 receives a low-voltage differential (LVDS) signal through the timing controller 200 (TCON) and transmits a corresponding data signal to the source driver chip 100 , and outputs an inversion signal (POL to the source driver chip 100 ) at the same time.
  • LVDS low-voltage differential
  • TCON timing controller 200
  • the inversion signal is a pulse signal, generally the level changes once within the duration of one frame
  • the source driver chip 100 changes the polarity of the output signal voltage after the level of the inversion signal changes.
  • the source driver chip 100 latches the data signal when the rising edge of the row latch signal TP arrives, and outputs it after the falling edge of the row latch signal TP arrives.
  • the signal voltage corresponding to the latched data signal is applied to the data line, and the TFT (Thin Film Transistor) that is turned on row by row is used to input the signal voltage to each pixel row by row to realize the driving of the liquid crystal panel.
  • TFT Thin Film Transistor
  • the display device in this application can be, but is not limited to, a liquid crystal panel, which includes a polarizing film, a glass substrate, a black matrix, a color filter, a protective film, a common electrode, an alignment layer, a liquid crystal layer ( Liquid crystal, spacer, sealant), capacitor, display electrode, prism layer, light-scattering layer.
  • a liquid crystal panel which includes a polarizing film, a glass substrate, a black matrix, a color filter, a protective film, a common electrode, an alignment layer, a liquid crystal layer ( Liquid crystal, spacer, sealant), capacitor, display electrode, prism layer, light-scattering layer.
  • Polarizer is also known as polarizer.
  • the polarizer is divided into upper polarizer and lower polarizer.
  • the polarizing functions of the upper and lower polarizers are perpendicular to each other, and their function is like a fence, blocking light wave components as required, such as blocking and
  • the polarizer fences the vertical light wave components, and only allows the light wave components parallel to the fence to pass.
  • a glass substrate can be divided into an upper substrate and a lower substrate in a liquid crystal display, and its main function is to clamp the liquid crystal material in the space between the two substrates.
  • the material of the glass substrate is generally alkali-free borosilicate glass with excellent mechanical properties, heat resistance and chemical corrosion resistance.
  • TFT-LCD one glass substrate is distributed with TFTs, and the other glass substrate is deposited with color filters.
  • Black Matrix uses materials with high shading properties to separate the three primary colors of red, green and blue in the color filter (to prevent color confusion) and prevent light leakage, thereby helping to improve the contrast of each color block.
  • the black matrix can also mask the internal electrode traces or thin film transistors.
  • Color filter also known as color filter, is used to generate three primary colors of red, green and blue light to achieve full color display of liquid crystal displays.
  • Alignment Layer also known as Alignment Layer or Alignment Layer, is used to enable liquid crystal molecules to achieve uniform arrangement and orientation on a microscopic scale.
  • the transparent electrode is divided into a common electrode and a pixel electrode, and the input signal voltage is loaded between the two electrodes of the pixel electrode and the common electrode.
  • the transparent electrode is usually formed by depositing an indium tin oxide (ITO) material on a glass substrate to form a transparent conductive layer.
  • ITO indium tin oxide
  • the liquid crystal material plays a role similar to a light valve in the LCD, which can control the brightness and darkness of the transmitted light, so as to obtain the effect of information display.
  • the driver IC is actually a set of integrated circuit chip devices, which is used to adjust and control the phase, peak value, frequency, etc. of the potential signal on the transparent electrode, establish the driving electric field, and finally realize the information display of the liquid crystal.
  • the active matrix liquid crystal display screen is composed of a twisted nematic (TN) type liquid crystal material enclosed between two glass substrates.
  • the upper glass substrate close to the display screen is deposited with red, green and blue (RGB) color filters (or color filters), a black matrix and a common transparent electrode.
  • the lower glass substrate (the substrate farther from the display screen) is installed with thin film transistor (TFT) devices, transparent pixel electrodes, storage capacitors, gate lines, signal lines, and the like.
  • TFT thin film transistor
  • An alignment film (or an alignment layer) is prepared on the inner side of the two glass substrates to align the liquid crystal molecules.
  • Liquid crystal material is poured between the two glass substrates, and spacers are distributed to ensure the uniformity of the gap.
  • the surrounding area is bonded by means of frame sealing glue to play a sealing role; the common electrodes of the upper and lower glass substrates are connected by means of a silver dispensing process.
  • the outer sides of the upper and lower glass substrates are respectively attached with polarizers (or polarizing films).
  • polarizers or polarizing films.
  • LCD product is a kind of non-active light-emitting electronic device, which does not have light-emitting characteristics. It must rely on the emission of light source in the backlight module to obtain display performance. Therefore, the brightness of LCD is determined by its backlight module. It can be seen that the performance of the backlight module directly affects the display quality of the liquid crystal panel.
  • the backlight module includes a lighting source, a reflective plate, a light guide plate, a diffuser, a brightness enhancement film (prism sheet), a frame, and the like.
  • the backlight modules used in LCD can be mainly divided into two categories: edge-lit backlight modules and direct-illuminated backlight modules.
  • Mobile phones, notebook computers and monitors (15 inches) mainly use edge-lit backlight modules, while LCD TVs mostly use direct-illuminated backlight modules as light sources.
  • the light source of the backlight module is mainly cold cathode fluorescent lamp (Cold Cathode Fluorescent Lamp, CCFL) and Light Emitting Diode (LED) light sources are backlight sources for LCDs.
  • Cold Cathode Fluorescent Lamp CCFL
  • LED Light Emitting Diode
  • the reflector sheet also known as the reflector, is mainly used to completely send the light emitted by the light source into the light guide plate, so as to reduce the useless loss as much as possible.
  • the main function of the light guide plate is to guide the light emitted by the side light source to the front of the panel.
  • Prism Film also known as Brightness Film Enhancement Film
  • the main function is to refract and totally reflect each scattered light through the film layer, concentrate it at a certain angle, and then emit it from the backlight source to achieve a brightening display effect on the screen.
  • the main function of the diffuser is to correct the edge light of the backlight module into a uniform surface light source to achieve the effect of optical diffusion.
  • the diffuser is divided into an upper diffuser and a lower diffuser.
  • the upper diffusion sheet is located between the prism sheet and the liquid crystal assembly, and is closer to the display panel.
  • the lower diffuser is located between the light guide plate and the prism sheet, which is closer to the backlight.
  • LCD is a display that uses liquid crystal as material.
  • Liquid crystal is a kind of organic compound between solid and liquid. Under normal temperature conditions, it exhibits both the fluidity of liquid and the optical anisotropy of crystal. It will become a transparent liquid when heated, and will become crystalline after cooling. turbid solid.
  • the liquid crystal molecules Under the action of the electric field, the liquid crystal molecules will change in arrangement, which will affect the change in the intensity of the incident light beam passing through the liquid crystal. Accordingly, by controlling the electric field of the liquid crystal, the light and dark changes of the light can be realized, so as to achieve the purpose of information display. Therefore, the liquid crystal material acts like a small "light valve".
  • LCD usually needs to configure an additional light source for the display panel.
  • the main light source system is called a "backlight module”. Light, its role is mainly to provide a uniform backlight.
  • LCD technology is to pour liquid crystal between two planes with thin grooves.
  • the grooves in these two planes are perpendicular to each other (intersecting at 90 degrees). That is, if the molecules on one plane are aligned north-south, then the molecules on the other plane are aligned east-west, and the molecules located between the two planes are forced into a state of 90-degree twist. Since the light travels along the direction of the arrangement of the molecules, the light is also twisted by 90 degrees as it passes through the liquid crystal. When a voltage is applied to the liquid crystal, the liquid crystal molecules will rotate, changing the light transmittance, thereby realizing multi-grayscale display.
  • LCDs usually consist of two polarizers that are perpendicular to each other.
  • the polarizer acts like a fence, blocking light wave components as required. For example, the light wave component perpendicular to the polarizer fence is blocked, and only the light wave component parallel to the fence is allowed to pass. Natural light is scattered randomly in all directions.
  • Two polarizers, perpendicular to each other, should normally block all natural light trying to penetrate. However, since the two polarizers are filled with twisted liquid crystal, after the light passes through the first polarizer, it will be twisted 90 degrees by the liquid crystal molecules, and finally pass through the second polarizer.
  • each pixel is usually composed of 3 liquid crystal cells, each of which is preceded by red, green or blue (RGB) The three-color filter. In this way, the light passing through different cells can display different colors on the screen.
  • RGB red, green or blue
  • Color filters are typically deposited on the front glass substrate of the display, along with the black matrix and common transparent electrode.
  • Color LCDs can create colorful images in high-resolution environments.
  • the human eye When multiple images are generated at a speed exceeding 24 frames/s, the human eye will perceive a continuous picture. This is also the origin of the movie playback speed of 24 frames per second. If the display speed is lower than this standard, people will obviously feel the pause and discomfort of the picture. Calculated according to this indicator, the display time of each picture needs to be less than 40ms. High-definition high-definition display of fast moving pictures, and the general image movement speed exceeds 60 frames/s. That is to say, the interval time of each frame of the active picture is 16.67ms.
  • response time of the liquid crystal is greater than the interval time between each frame of the picture, people will feel that the picture is a little blurred when viewing fast-moving images.
  • Response time is a special indicator of LCDs.
  • the response time of the LCD refers to the speed at which each pixel of the display responds to the input signal, that is, the response time of the liquid crystal from "dark to bright” or "bright to dark". The smaller the value, the better, and the fast enough response time can ensure the coherence of the picture. If the response time is too long, it may cause the LCD to have a trailing trailing feeling when displaying dynamic images.
  • the general response time of LCD is 2 ⁇ 5ms.
  • TFT refers to the transistor array on the glass substrate of the liquid crystal panel, so that each pixel of the LCD has its own semiconductor switch.
  • Each pixel can control the liquid crystal between the two glass substrates through dot pulses, that is, through an active switch to achieve independent and precise control of each pixel "point-to-point". Therefore, each node of the pixel is relatively independent and can be controlled continuously.
  • the TFT type LCD is mainly composed of a glass substrate, a gate electrode, a drain electrode, a source electrode, a semiconductor active layer (a-Si) and the like.
  • the TFT array is generally co-deposited on the rear glass substrate of the display screen (substrate farther from the display screen) together with transparent pixel electrodes, storage capacitors, gate lines, signal lines, etc.
  • the configuration of such a transistor array helps to improve the response speed of the liquid crystal display screen, and can also control the display grayscale, thereby ensuring that the color of the LCD image is more vivid and the picture quality is more pleasing to the eye. Therefore, most LCDs, LCD TVs and some mobile phones are driven by TFT, whether it is a small and medium-sized LCD with a narrow viewing angle twisted nematic (TN) mode, or a large-size LCD with a wide viewing angle (IPS) mode.
  • LCD-TVs Liquid crystal televisions
  • TFT-LCDs Liquid crystal televisions

Abstract

公开了一种源驱动芯片(100)及显示装置(1000)，源驱动芯片(100)包括或逻辑运算器(10)、时钟缓冲器(20)、移位寄存器(30)以及与逻辑运算器(40)；通过行锁存信号(TP)和第一输出数据延时控制使能信号(ODDC-EN)的或逻辑运算得到第二输出数据延时控制使能信号(ODDC-ENX)，以及通过初始行锁存子信号(PTP1~PTP80)和第二输出数据延时控制使能信号(ODDC-ENX)的与逻辑运算，可以降低行锁存信号(TP)受到的静电干扰。

Description

源驱动芯片及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种源驱动芯片及显示装置。
 背景技术
ESD（Electro-Static Discharge，静电放电）是一种常见的近场电磁危害源，危害大。显示装置作为一种常用电子设备，应用领域广泛，其抗ESD的能力越来越受到关注。显示装置中的芯片等元器件容易受到静电冲击干扰，例如，测试源驱动芯片的ESD时，会出现源驱动芯片工作异常致使的画异现象，需要重新开关机进行恢复，其所收到的静电干扰强度已经达到了等级C（Class C），最终会导致测试结果失败。后经测试总结发现，当静电干扰强度较大时，容易导致显示装置的局部区域出现画面异常。
需要注意的是，上述关于背景技术的介绍仅仅是为了便于清楚、完整地理解本申请的技术方案。因此，不能仅仅由于其出现在本申请的背景技术中，而认为上述所涉及到的技术方案为本领域所属技术人员所公知。
 技术问题
本申请提供一种源驱动芯片及显示装置，缓解了源驱动芯片容易受到静电干扰的技术问题。
 技术解决方案
第一方面，本申请提供一种源驱动芯片，其包括或逻辑运算器、时钟缓冲器、移位寄存器以及与逻辑运算器；或逻辑运算器用于根据接入的行锁存信号和第一输出数据延时控制使能信号，生成并输出对应的第二输出数据延时控制使能信号；时钟缓冲器与或逻辑运算器连接，用于根据第一时钟信号和第二输出数据延时控制使能信号，输出对应的第二时钟信号；移位寄存器与时钟缓冲器连接，用于根据行锁存信号和第二时钟信号，生成多个初始行锁存子信号；与逻辑运算器与或逻辑运算器和移位寄存器连接，用于根据初始行锁存子信号和第二输出数据延时控制使能信号，生成对应的标的行锁存子信号。
在其中一个实施方式中，两两相邻的标的行锁存子信号之间的相位差是相同的。
在其中一个实施方式中，行锁存信号与标的行锁存子信号中的一个相同。
在其中一个实施方式中，第二输出数据延时控制使能信号为脉冲信号；当第二输出数据延时控制使能信号为低电位时，时钟缓冲器停止输出第二时钟信号。
在其中一个实施方式中，当第二输出数据延时控制使能信号为高电位时，第二时钟信号的驱动能力大于第一时钟信号的驱动能力。
在其中一个实施方式中，移位寄存器包括至少两个并行输出的触发器；至少一个触发器的触发端与时钟缓冲器的输出端连接；至少一个触发器的输入端与行锁存信号连接。
在其中一个实施方式中，与逻辑运算器包括多个与逻辑单元；每个与逻辑单元的一输入端与一触发器的输出端连接；每个与逻辑单元的另一输入端与或逻辑运算器的输出端连接。
在其中一个实施方式中，源驱动芯片用于输出对应的数据信号；行锁存信号的上升沿用于指示源驱动芯片锁存数据信号；行锁存信号的下降沿用于指示源驱动芯片输出数据信号。
在其中一个实施方式中，源驱动芯片还包括时钟模块；时钟模块的输出端与时钟缓冲器的输入端连接。
第二方面，本申请提供一种显示装置，其包括时序控制器和上述任一实施方式中的源驱动芯片，源驱动芯片与时序控制器连接。
 有益效果
本申请提供的源驱动芯片及显示装置，通过行锁存信号和第一输出数据延时控制使能信号的或逻辑运算得到第二输出数据延时控制使能信号，以及通过初始行锁存子信号和第二输出数据延时控制使能信号的与逻辑运算，可以降低或者消除行锁存信号受到的静电干扰，进而提高了源驱动芯片的抗静电干扰能力。
 附图说明
图1为本申请实施例提供的源驱动芯片的第一种结构示意图。
图2为本申请实施例提供的源驱动芯片的第一种时序示意图。
图3为本申请实施例提供的源驱动芯片的第二种时序示意图。
图4为本申请实施例提供的源驱动芯片的第二种结构示意图。
图5为本申请实施例提供的源驱动芯片的第三种时序示意图。
图6为本申请实施例提供的液晶显示装置的结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图1所示，在其中一个实施例中，源驱动芯片可以包括时钟缓冲器1和移位寄存器2；时钟缓冲器1的输出端与移位寄存器2的触发输入端连接。移位寄存器2的信号输入端用于接入行锁存信号TPX。时钟缓冲器1的一输入端用于接入输出数据延时控制使能信号ODDC1-EN；时钟缓冲器1的另一输入端用于接入初始脉冲信号CLK1，时钟缓冲器1的输出端用于输出经过调制后的标的脉冲信号CLK1X。在标的脉冲信号CLK1X的控制下，移位寄存器2用于根据行锁存信号TPX生成并输出多个不同相位延迟的行锁存子信号TPX1~TPX80。
但是，该种结构的源驱动芯片在受到较大强度的静电干扰时，容易导致源驱动芯片输出的电压低于正常（Normal）显示时的电压，进而导致显示装置的局部区域出现画面异常。
具体地，经过不断的研发论证，画面异常时，行锁存信号TPX、数据延时控制使能信号ODDC1-EN以及行锁存子信号TPX1~TPX80之间存在连接关系，当行锁存信号TPX受到静电干扰（ESD）后，会导致数据延时控制使能信号ODDC1-EN出现异常。
其中，如图2所示，数据延时控制使能信号ODDC1-EN与行锁存子信号TPX1~TPX80之间的时序关系为：
源驱动芯片在输出第N个像素行LINE（N）的像素数据时，首先，在接收到的信号控制指令CMD中的指令起始信号CS的控制下，源驱动芯片根据接收到的数据延时控制使能信号ODDC1-EN和行锁存信号TPX，开始生成第N个像素行LINE（N）的行锁存子信号TPX1~TPX80。然后，源驱动芯片根据接收到的信号控制指令CMD中的指令结束信号CE，结束第N个像素行LINE（N）的行锁存子信号TPX1~TPX80。然后经过一个水平消隐周期HBK之后，开始第N+1个像素行LINE（N+1）的像素数据。按照上述过程类推，依次是第N+2个像素行LINE（N+2）的像素数据以及第N+3个像素行LINE（N+3）的像素数据等等。
其中，当第N个像素行LINE（N）的数据延时控制使能信号ODDC1-EN为高电位时，行锁存子信号TPX1跟随行锁存信号TPX动作，行锁存子信号TPX80在行锁存子信号TPX1的基础上延迟TD1时段后动作，行锁存子信号TPX80为低电位时，延迟TD2时段后，拉低数据延时控制使能信号ODDC1-EN为低电位。指令结束信号CE到来后，数据延时控制使能信号ODDC1-EN拉高至高电位，延时TD时段后，行锁存信号TPX拉高为高电位。其中，TD1为输出数据延时控制信号的延迟时间。输出数据延时控制信号（ODDC，Output data Delay Control）用于调整不同位置的充电率，可改善显示品味。数据延时控制使能信号ODDC1-EN用于控制输出数据延时控制信号的开启和关闭。
未受到静电干扰时，假如对应的为第N个像素行LINE（N），指令结束信号CE结束时，数据延时控制使能信号ODDC1-EN拉高为高电位，延时TD时段后，行锁存信号TPX拉高为高电位。行锁存信号TPX的高电位时段在数据延时控制使能信号ODDC1-EN的高电位时段内，此时，行锁存子信号TPX1~TPX80正常跟随行锁存信号TPX动作。
如图3所示，在第N+1个像素行LINE（N+1）时，受到静电干扰，导致行锁存信号TPX的高电位时段异常加宽，致使行锁存子信号TPX1~TPX80的高电位时段随之加长，这样会压缩电流放大器的充电时间。延迟TD2时段后，数据延时控制使能信号ODDC1-EN异常拉低为低电位，如图3中的S10处和S20处，致使第N+2个像素行LINE（N+2）对应的数据延时控制使能信号ODDC1-EN丢失。
第N+1个像素行LINE（N+1）对应的数据延时控制使能信号ODDC1-EN拉低为低电位前，第N+2个像素行LINE（N+2）对应的行锁存信号TPX拉高为高电位，使第N+2个像素行LINE（N+2）对应的行锁存子信号TPX1~TPX80也随之拉高为高电位，第N+2个像素行LINE（N+2）对应的行锁存信号TPX拉低为低电位。第N+1个像素行LINE（N+1）对应的数据延时控制使能信号ODDC1-EN拉低为低电位之后，第N+2个像素行LINE（N+2）对应的行锁存子信号TPX1~TPX80无法跟随第N+2个像素行LINE（N+2）对应的行锁存信号TPX及时拉低为低电位。
第N+3个像素行LINE（N+3）对应的数据延时控制使能信号ODDC1-EN拉高为高电位，使第N+2个像素行LINE（N+2）对应的行锁存子信号TPX1~TPX80依次拉低为低电位，此时，第N+3个像素行LINE（N+3）对应的行锁存信号TPX拉高为高电位。第N+3个像素行LINE（N+3）对应的数据延时控制使能信号ODDC1-EN拉低为低电位，第N+3个像素行LINE（N+3）对应的行锁存信号TPX拉低为低电位。在第N+3个像素行LINE（N+3）对应的数据延时控制使能信号ODDC1-EN为低电位后，第N+3个像素行LINE（N+3）对应的行锁存子信号TPX1~TPX80无法跟随第N+2个像素行LINE（N+2）对应的行锁存信号TPX及时拉低为低电位。电流放大器的充电能力不足，源驱动芯片的输出电压无法达到正常准位，如此往复。
基于上述分析，如图4所示，本实施例提供了一种源驱动芯片100，其包括或逻辑运算器10、时钟缓冲器20、移位寄存器30以及与逻辑运算器40；或逻辑运算器10用于根据接入的行锁存信号TP和第一输出数据延时控制使能信号ODDC-EN，生成并输出对应的第二输出数据延时控制使能信号ODDC-ENX；时钟缓冲器20与或逻辑运算器10连接，用于根据第一时钟信号CLK和第二输出数据延时控制使能信号ODDC-ENX，输出对应的第二时钟信号CLKX；移位寄存器30与时钟缓冲器20连接，用于根据行锁存信号TP和第二时钟信号CLKX，生成多个初始行锁存子信号PTP1~PTP80；与逻辑运算器40与或逻辑运算器10和移位寄存器30连接，用于根据初始行锁存子信号PTP1~PTP80和第二输出数据延时控制使能信号ODDC-ENX，生成对应的标的行锁存子信号TP1~TP80。
可以理解的是，本申请提供的源驱动芯片100，通过行锁存信号TP和第一输出数据延时控制使能信号ODDC-EN的或逻辑运算得到第二输出数据延时控制使能信号ODDC-ENX，以及通过初始行锁存子信号PTP1~PTP80和第二输出数据延时控制使能信号ODDC-ENX的与逻辑运算，可以降低或者消除行锁存信号TP受到的静电干扰，进而提高了源驱动芯片100的抗静电干扰能力。
具体地，如图4和图5所示，易被干扰的第一输出数据延时控制使能信号ODDC-EN信号不再直接输出到时钟缓冲器20（CK Buffer），而是通过增加或逻辑运算器10，将第一输出数据延时控制使能信号ODDC-EN和行锁存信号TP经过或门后输出生成的第二输出数据延时控制使能信号ODDC-ENX信号，再输出给到时钟缓冲器20（CK Buffer）。
如图5所示，具体的工作原理及增强抗ESD能力的实现机理如下：
第N+1个像素行LINE（N+1）时，受到静电干扰，导致行锁存信号TP的高电位时段异常加宽，致使标的行锁存子信号TP1~TP80的高电位时段随之加长。延迟TD2时段后，第N+1个像素行LINE（N+1）对应的第一输出数据延时控制使能信号ODDC-EN拉低为低电位，致使第N+2个像素行LINE（N+2）对应的第一输出数据延时控制使能信号ODDC-EN丢失。第N+1个像素行LINE（N+1）对应的第一输出数据延时控制使能信号ODDC-EN拉低为低电位前，第N+2个像素行LINE（N+2）对应的行锁存信号TP拉高为高电位，使第二输出数据延时控制使能信号ODDC-ENX持续为高电位，并将初始行锁存子信号PTP1~PTP80拉高为高电位。第N+2个像素行LINE（N+2）对应的行锁存信号TP拉低为低电位时，由于第一输出数据延时控制使能信号ODDC-EN已经处于低电位，使第二输出数据延时控制使能信号ODDC-ENX也拉低为低电位，从而可以强制拉低标的行锁存子信号TP1~TP80至低电位。
第N+2个像素行LINE（N+2）对应的指令结束信号CE结束前，行锁存信号TP、标的行锁存子信号TP1~TP80以及第一输出数据延时控制使能信号ODDC-EN均为低电位，可以保证从第N+3个像素行LINE（N+3）开始时，恢复至正常的时序。
其中，如图5中的S30处，第N+1个像素行LINE（N+1）对应的第一输出数据延时控制使能信号ODDC-EN为低电位，由于此时行锁存信号TP处于高电位，则经过或逻辑运算器10运算输出后的第二输出数据延时控制使能信号ODDC-ENX可以保持高电位，由此可以避免第一输出数据延时控制使能信号ODDC-EN受到静电干扰时导致的画面异常。
其中，如图5中的S40处，当第二输出数据延时控制使能信号ODDC-ENX为低电位时，此时可以强制拉低标的行锁存子信号TP1~TP80至低电位。
其中，如图5中的S50处，从第N+3个像素行LINE（N+3）开始，可以正常依次输出不同相位的标的行锁存子信号TP1~TP80。
可以理解的是，本实施例可以增强源驱动芯片100的抗ESD能力，提高产品可靠性。
在其中一个实施例中，两两相邻的标的行锁存子信号TP1~TP80之间的相位差是相同的。
例如，标的行锁存子信号TP1~TP80TP1与标的行锁存子信号TP1~TP80TP2之间的相位差，与标的行锁存子信号TP1~TP80TP2与标的行锁存子信号TP1~TP80TP3之间的相位差是相等的。
在其中一个实施例中，行锁存信号TP与标的行锁存子信号TP1~TP80中的一个相同。
例如，行锁存信号TP的频率、相位可以与标的行锁存子信号TP1~TP80TP1的频率、相位均对应相同。
在其中一个实施例中，第二输出数据延时控制使能信号ODDC-ENX为脉冲信号；当第二输出数据延时控制使能信号ODDC-ENX为低电位时，时钟缓冲器20停止输出第二时钟信号CLKX。
需要进行说明的是，时钟缓冲器20可以根据第二输出数据延时控制使能信号ODDC-ENX的电位，决定是否输出第二时钟信号CLKX。
在其中一个实施例中，当第二输出数据延时控制使能信号ODDC-ENX为高电位时，第二时钟信号CLKX的驱动能力大于第一时钟信号CLK的驱动能力。
需要进行说明的是，时钟缓冲器20可以用于增强第一时钟信号CLK的驱动能力，因此，第二时钟信号CLKX的驱动能力大于第一时钟信号CLK的驱动能力。
在其中一个实施例中，移位寄存器30包括至少两个并行输出的触发器；至少一个触发器的触发端与时钟缓冲器20的输出端连接；至少一个触发器的输入端与行锁存信号TP连接。
在其中一个实施例中，与逻辑运算器40包括多个与逻辑单元；每个与逻辑单元的一输入端与一触发器的输出端连接；每个与逻辑单元的另一输入端与或逻辑运算器10的输出端连接。
在其中一个实施例中，源驱动芯片100用于输出对应的数据信号；行锁存信号TP的上升沿用于指示源驱动芯片100锁存数据信号；行锁存信号TP的下降沿用于指示源驱动芯片100输出数据信号。
在其中一个实施例中，源驱动芯片100还包括时钟模块；时钟模块的输出端与时钟缓冲器20的输入端连接。
如图6所示，在其中一个实施例中，本申请提供一种显示装置1000，其包括时序控制器200和上述任一实施方式中的源驱动芯片100，源驱动芯片100与时序控制器200连接。
可以理解的是，本申请提供的显示装置1000，通过行锁存信号TP和第一输出数据延时控制使能信号ODDC-EN的或逻辑运算得到第二输出数据延时控制使能信号ODDC-ENX，以及通过初始行锁存子信号PTP1~PTP80和第二输出数据延时控制使能信号ODDC-ENX的与逻辑运算，可以降低或者消除行锁存信号TP受到的静电干扰，进而提高了源驱动芯片100的抗静电干扰能力。
需要进行说明的是，该显示装置1000通过时序控制器200(TCON)接收低电压差分(LVDS)信号并传输对应的数据信号至源驱动芯片100，同时向源驱动芯片100输出反转信号(POL)及行锁存信号TP，反转信号为脉冲信号，一般为一帧画面的时长内电平变化一次，源驱动芯片100在反转信号的电平变化后将其输出的信号电压的极性反转，防止液晶极化，而行锁存信号TP为脉冲信号，源驱动芯片100在行锁存信号TP的上升沿到来时锁存数据信号，在行锁存信号TP的下降沿到来后输出与锁存的数据信号对应的信号电压至数据线，搭配逐行开启的TFT（Thin Film Transistor，薄膜晶体管），使信号电压逐行输入各个像素中，实现液晶面板的驱动。
需要进行说明的是，本申请中的显示装置可以但不限于为液晶面板，该液晶面板包括偏振膜、玻璃基板、黑色矩阵、彩色滤光片、保护膜、普通电极、校准层、液晶层(液晶、间隔、密封剂)、电容、显示电极、棱镜层、散光层。
偏振膜又称偏光片(Polarizer)，偏光片分为上偏光片和下偏光片，上下两偏光片的偏振功能相互垂直，其作用就像是栅栏一般，按照要求阻隔光波分量，例如阻隔掉与偏光片栅栏垂直的光波分量，而只准许与栅栏平行的光波分量通过。
玻璃基板(Glass Substrate)在液晶显示器中可分为上基板和下基板，其主要作用在于两基板之间的间隔空间夹持液晶材料。玻璃基板的材料一般采用机械性能优良、耐热与耐化学腐蚀的无碱硼硅玻璃。对于TFT-LCD而言，一层玻璃基板分布有TFT，另一层玻璃基板则沉积彩色滤光片。
黑色矩阵(Black Matrix)借助于高度遮光性能的材料，用以分隔彩色滤光片中红、绿、蓝三原色(防止色混淆)、防止漏光，从而有利于提高各个色块的对比度。此外，在TFT-LCD中，黑色矩阵还能遮掩内部电极走线或者薄膜晶体管。
彩色滤光片(Color Filter)又称滤色膜，其作用是产生红、绿、蓝3种基色光，实现液晶显示器的全彩色显示。
取向膜(Alignment Layer)又称配向膜或定向层，其作用是让液晶分子能够在微观尺寸的层面上实现均匀的排列和取向。
透明电极(Transparent Electrode)分为公共电极与像素电极，输入信号电压就是加载在像素电极与公共电极两电极之间。透明电极通常是在玻璃基板上沉积氧化铟锡(ITO)材料构成透明导电层。
液晶材料(Liquid Crystal Material)在LCD中起到一种类似光阀的作用，可以控制透射光的明暗，从而取得信息显示的效果。
驱动IC其实就是一套集成电路芯片装置，用来对透明电极上电位信号的相位、峰值、频率等进行调整与控制，建立起驱动电场，最终实现液晶的信息显示。
在液晶面板中，有源矩阵液晶显示屏是在两块玻璃基板之间封入扭曲向列(TN)型液晶材料构成的。其中，接近显示屏的上玻璃基板沉积有红、绿、蓝(RGB)三色彩色滤光片(或称彩色滤色膜)、黑色矩阵和公共透明电极。下玻璃基板(距离显示屏较远的基板)，则安装有薄膜晶体管(TFT)器件、透明像素电极、存储电容、栅线、信号线等。两玻璃基板内侧制备取向膜(或称取向层)，使液晶分子定向排列。两玻璃基板之间灌注液晶材料，散布衬垫(Spacer)，以保证间隙的均匀性。四周借助于封框胶黏结，起到密封作用；借助于点银胶工艺使上下两玻璃基板公共电极连接。
上下两玻璃基板的外侧，分别贴有偏光片(或称偏光膜)。当像素透明电极与公共透明电极之间加上电压时，液晶分子的排列状态会发生改变。此时，入射光透过液晶的强度也随之发生变化。液晶显示器正是根据液晶材料的旋光性，再配合上电场的控制，便能实现信息显示。
LCD产品是一种非主动发光电子器件，本身并不具有发光特性，必须依赖背光模组中光源的发射才能获得显示性能，因此LCD的亮度要由其背光模组来决定。由此可见，背光模组的性能好坏直接影响到液晶面板的显示品质。
背光模组包括照明光源、反射板、导光板、扩散片、增亮膜(棱镜片)及框架等。LCD采用的背光模组主要可分为侧光式背光模组和直射式背光模组两大类。手机、笔记本电脑与监视器(15英寸)主要采用侧光式背光模组，而液晶电视大多采用直射式背光模组光源。背光模组光源，主要以冷阴极荧光灯(Cold Cathode Fluorescent Lamp，CCFL)和发光二极管(LED)光源为LCD的背光源。
反射板(Reflector Sheet)又称反射罩，主要作用是将光源发出的光线完全送入导光板，尽可能地减少无益的耗损。
导光板(Light Guide Plate)主要作用是将侧面光源发出的光线导向面板的正面。
棱镜片(Prism Film)又称增亮膜(Brightness Enhancement Film)，主要作用是将各散射光线通过该膜片层的折射和全反射，集中于一定的角度再从背光源发射出去，起到屏幕增亮的显示效果。
扩散片(Diffuser)主要作用是把背光模组的侧光式光线修正为均匀的面光源，以达到光学扩散的效果。扩散片有上扩散片与下扩散片之分。上扩散片，处于棱镜片与液晶组件之间，更接近于显示面板。而下扩散片处于导光板与棱镜片之间，更接近于背光源。
LCD是一种采用液晶为材料的显示器。液晶是一类介于固态和液态间的有机化合物，在常温条件下，呈现出既有液体的流动性，又有晶体的光学各向异性，加热会变成透明液态，冷却后会变成结晶的混浊固态。
在电场作用下，液晶分子会发生排列上的变化，从而影响入射光束透过液晶产生强度上的变化，这种光强度的变化，进一步通过偏光片的作用表现为明暗的变化。据此，通过对液晶电场的控制可以实现光线的明暗变化，从而达到信息显示的目的。因此，液晶材料的作用类似于一个个小的“光阀”。
由于在液晶材料周边存在控制电路和驱动电路。当LCD中的电极产生电场时，液晶分子就会发生扭曲，从而将穿越其中的光线进行有规则的折射(液晶材料的旋光性)，再经过第二层偏光片的过滤而显示在屏幕上。
值得指出的是，液晶材料因为本身并不发光，所以LCD通常都需要为显示面板配置额外的光源，主要光源系统称之为“背光模组”，其中，背光板是由荧光物质组成，可以发射光线，其作用主要是提供均匀的背光源。
LCD技术是把液晶灌入两个列有细槽的平面之间。这两个平面上的槽互相垂直(相交成90度)。也就是说，若一个平面上的分子南北向排列，则另一平面上的分子东西向排列，而位于两个平面之间的分子被强迫进入一种90度扭转的状态。由于光线顺着分子的排列方向传播，所以光线经过液晶时也被扭转90度。当液晶上加一个电压时，液晶分子便会转动，改变光透过率，从而实现多灰阶显示。
LCD通常由两个相互垂直的偏光片构成。偏光片的作用就像是栅栏一般，按照要求阻隔光波分量。例如阻隔掉与偏光片栅栏垂直的光波分量，而只准许与栅栏平行的光波分量通过。自然光线是朝四面八方随机发散的。两个相互垂直的偏光片，在正常情况下应该阻断所有试图穿透的自然光线。但是，由于两个偏光片之间充满了扭曲液晶，所以在光线穿出第一个偏光片后，会被液晶分子扭转90度，最后从第二个偏光片中穿出。
对于笔记本电脑或者桌面型的LCD，需要采用更加复杂的彩色显示器。
就彩色LCD而言，还需要具备专门处理彩色显示的色彩过滤层，即所谓的“彩色滤光片(Color Filter)”，又称“滤色膜”。在彩色LCD面板中，每一个像素通常都是由3个液晶单元格构成，其中每一个单元格前面都分别有红色、绿色或蓝色(RGB)的三色滤光片。这样，通过不同单元格的光线就可以在屏幕上显示出不同的颜色。
彩色滤光片与黑色矩阵和公共透明电极一般都沉积在显示屏的前玻璃基板上。彩色LCD能在高分辨率环境下创造色彩斑斓的画面。
人类视觉器官(眼睛)对动态影像的感知存在所谓“视觉残留”的现象，即高速运动的画面在人脑中会形成短暂的印象。早期的动画片、电影，一直到当下最新的游戏节目正是应用了“视觉残留”的原理，让一系列渐变的图像在人眼前快速连续显示，便形成动态的影像。
当多幅影像产生的速度超过24帧/s，人的眼睛会感觉到连续的画面。这也是电影每秒24帧播放速度的由来。如果显示速度低于这一标准，人就会明显感到画面的停顿和不适。按照这一指标计算，每张画面显示的时间需要小于40ms。快速活动画面高清晰显示，一般影像的运动速度超过60帧/s。这就是说，活动画面每帧的间隔时间为16.67ms。
如果液晶的响应时间大于画面每帧的间隔时间，人们在观看快速运动的影像时，就会感觉到画面有些模糊。响应时间是LCD的一个特殊指标。LCD的响应时间指的是显示器各像素点对输入信号反应的速度，就是液晶由“暗转亮”或由“亮转暗”的反应时间。此值是越小越好，足够快的响应时间才能保证画面的连贯。如果响应时间太长了，就有可能使LCD在显示动态图像时，有尾影拖曳的感觉。LCD一般的响应时间在2～5ms。
所谓TFT是指液晶面板玻璃基片上的晶体管阵列，让LCD每个像素都设有自身的一个半导体开关。每个像素都可以通过点脉冲控制两片玻璃基板之间的液晶，即通过有源开关来实现对各个像素“点对点”的独立精确控制。因此，像素的每一个节点都是相对独立的，并且可以进行连续控制。
TFT型LCD主要由玻璃基板、栅极、漏极、源极、半导体活性层(a-Si)等组成。
TFT阵列一般与透明像素电极、存储电容、栅线、信号线等，共同沉积在显示屏的后玻璃基板(距离显示屏较远的基板)上。这样一种晶体管阵列的配制，有助于提高液晶显示屏的反应速度，而且还可以控制显示灰度，从而保证LCD的影像色彩更为逼真、画面品质更为赏心悦目。因此，大多数的LCD、液晶电视及部分手机均采用TFT实施驱动，无论是采用窄视角扭曲向列(TN)模式的中小尺寸LCD，还是采用宽视角的平行排列(IPS)等模式的大尺寸液晶电视(LCD-TV)，它们通称为“TFT—LCD”。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种源驱动芯片，包括：
    或逻辑运算器，用于根据接入的行锁存信号和第一输出数据延时控制使能信号，生成并输出对应的第二输出数据延时控制使能信号；
    时钟缓冲器，与所述或逻辑运算器连接，用于根据第一时钟信号和所述第二输出数据延时控制使能信号，输出对应的第二时钟信号；
    移位寄存器，与所述时钟缓冲器连接，用于根据所述行锁存信号和所述第二时钟信号，生成多个初始行锁存子信号；以及
    与逻辑运算器，与所述或逻辑运算器和所述移位寄存器连接，用于根据所述初始行锁存子信号和所述第二输出数据延时控制使能信号，生成对应的标的行锁存子信号。
  2. 根据权利要求1所述的源驱动芯片，其中，两两相邻的所述标的行锁存子信号之间的相位差是相同的。
  3. 根据权利要求2所述的源驱动芯片，其中，所述行锁存信号与所述标的行锁存子信号中的一个相同。
  4. 根据权利要求1所述的源驱动芯片，其中，所述第二输出数据延时控制使能信号为脉冲信号；当所述第二输出数据延时控制使能信号为低电位时，所述时钟缓冲器停止输出所述第二时钟信号。
  5. 根据权利要求4所述的源驱动芯片，其中，当所述第二输出数据延时控制使能信号为高电位时，所述第二时钟信号的驱动能力大于所述第一时钟信号的驱动能力。
  6. 根据权利要求1所述的源驱动芯片，其中，所述移位寄存器包括至少两个并行输出的触发器；至少一个所述触发器的触发端与所述时钟缓冲器的输出端连接；至少一个所述触发器的输入端与所述行锁存信号连接。
  7. 根据权利要求6所述的源驱动芯片，其中，所述与逻辑运算器包括多个与逻辑单元；每个所述与逻辑单元的一输入端与一所述触发器的输出端连接；每个所述与逻辑单元的另一输入端与所述或逻辑运算器的输出端连接。
  8. 根据权利要求1所述的源驱动芯片，其中，所述源驱动芯片用于输出对应的数据信号；所述行锁存信号的上升沿用于指示所述源驱动芯片锁存所述数据信号；所述行锁存信号的下降沿用于指示所述源驱动芯片输出所述数据信号。
  9. 根据权利要求1所述的源驱动芯片，其中，所述源驱动芯片还包括时钟模块；所述时钟模块的输出端与所述时钟缓冲器的输入端连接。
  10. 一种显示装置，包括：
    时序控制器；和
    如权利要求1所述的源驱动芯片，与所述时序控制器连接。
  11. 根据权利要求10所述的显示装置，其中，两两相邻的所述标的行锁存子信号之间的相位差是相同的。
  12. 根据权利要求11所述的显示装置，其中，所述行锁存信号与所述标的行锁存子信号中的一个相同。
  13. 根据权利要求10所述的显示装置，其中，所述第二输出数据延时控制使能信号为脉冲信号；当所述第二输出数据延时控制使能信号为低电位时，所述时钟缓冲器停止输出所述第二时钟信号。
  14. 根据权利要求13所述的显示装置，其中，当所述第二输出数据延时控制使能信号为高电位时，所述第二时钟信号的驱动能力大于所述第一时钟信号的驱动能力。
  15. 根据权利要求10所述的显示装置，其中，所述移位寄存器包括至少两个并行输出的触发器；至少一个所述触发器的触发端与所述时钟缓冲器的输出端连接；至少一个所述触发器的输入端与所述行锁存信号连接。
  16. 根据权利要求15所述的显示装置，其中，所述与逻辑运算器包括多个与逻辑单元；每个所述与逻辑单元的一输入端与一所述触发器的输出端连接；每个所述与逻辑单元的另一输入端与所述或逻辑运算器的输出端连接。
  17. 根据权利要求10所述的显示装置，其中，所述源驱动芯片用于输出对应的数据信号；所述行锁存信号的上升沿用于指示所述源驱动芯片锁存所述数据信号；所述行锁存信号的下降沿用于指示所述源驱动芯片输出所述数据信号。
  18. 根据权利要求10所述的显示装置，其中，所述源驱动芯片还包括时钟模块；所述时钟模块的输出端与所述时钟缓冲器的输入端连接。
  19. 根据权利要求10所述的显示装置，其中，所述显示装置为液晶显示装置。
  20. 根据权利要求10所述的显示装置，其中，所述行锁存信号和所述标的行锁存子信号中的至少一个为脉冲信号。
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