TW479408B - Digital output buffer circuit - Google Patents

Abstract

The present invention discloses a digital output buffer circuit, which comprises a pull-up network and a pull-down network. The pull-up network is used to pull-up the output voltage at the output and the pull-down network is used to pull-down the output voltage at the output. Each network is provided with a MOS device to provide the output load; at least a gate voltage feedback pull-up (GVFPUL) loop coupled with the MOS device, in which when the GVFPUL loop is connected, the gate voltage of the MOS device will be pulled up around a predetermined value; a delay device, for delaying transmitting signal to keep the gate voltage around the predetermined value for a period of time; and, an uni-directional switch, which is coupled with the GVFPUL loop and the delay element to control the transmission direction of the signal so as to prevent the signal competition between the GVFPUL loop and the delay device.

Description

479408 V. Description of the invention (1) Field of the invention: The present invention relates to a digital output buffer circuit, especially a gate voltage feedback loop to control the slew rate and reduce the short-circuit current (crOwbar) during switching. current) digital output buffer circuit. -BACKGROUND OF THE INVENTION: With the continuous and rapid development of the semiconductor industry, after entering the development and design of ultra large integrated circuits (ULSI), in order to meet the trend of high-density integrated circuits, the sizes of various components on the chip are Sub-micron. In addition, due to the miniaturization of the two-body circuit size, the operating voltage, current, and even the permissible resistance of various components must meet strict requirements. Therefore, when designing integrated circuits, in addition to further increasing the density of the integrated circuits, it is also necessary to consider how to reduce the interference and influence between the components in the situation where the components are becoming denser, so that the circuit made == ”

Set specifications. # 々I Generally speaking, in integrated circuits, output loads are often used to drive external loads. And, because the size of the external load is not fixed, when designing the output buffer, it must provide enough current to drive the maximum negative that can be generated =, /, This industry usually uses a large enough Transistor, or a secret transistor as the output buffer. However, this conventional device such as the device, when it is turned on and off quickly, it will produce a sharp electrical buffer potential change, so that

Page 4 479408 Description of the invention Such as power lines, ground lines, data lines, etc., generate huge noise spikes, which leads to data errors, latch-up, and other problems in digital circuits. To overcome this shortcoming, the industry has developed a control slew rate

Cslew-rate qontrol) to try to reduce the noise spikes mentioned above. The so-called slew rate refers to the maximum possible change in the output voltage phase in a circuit. It can also be referred to as the maximum change in output voltage. “W” volts per second. Traditionally, digital output that can control the slew rate ϊ = = ί is composed of a parallel transistor, and the voltage is reduced by the parallel connection! This also reduces the above point §, and by using a delay element (del ay Control the above-mentioned parallel electric sun and sun body, so as to achieve the operation function of the buffer. N The above-mentioned digital output buffer's high network (pUl h & etwork) can be arranged into a -network) like electricity and two bodies. Among them, the upper commandment ▲ and pull down the network (PuU-down is increased to +1, the heart low network ^ _ road can simulate the output of buffer II

Vss. In this way, the output level of the buffer can be lowered by raising the network C output level, so that the electric power can be changed. The replacement of Kushiro, and tuning technology, has many disadvantages. For example, "First, 1 is a crisis. However, when this kind of practice is conducted, the other network is often slow; = China-this network is slowly within the network. Before, resulting in a period of 9 σ 亇 v pass, and resulting in Vdd and '

479408 V. Description of the invention (3) Instantaneous short circuit and current) 〇 Therefore, how to slowly turn on the pull-up and reach the digital output and gate voltage designed by the integrated circuit, and also summarize the invention: The main purpose of the invention is to use the gate voltage of MOS, which has the purpose of flattening each load. The present invention also has a low-cut output buffer circuit. The present invention is to expose the pull-up and pull-down to fast discharge to generate a huge short-circuit current at the time of switching (cr0wbar designed a digital output buffer circuit so that the network can be slowly pulled down to achieve good switching rate control, And discharging to avoid causing huge short-circuit current during switching, which is a very important issue in the industry. In addition, if the buffer circuit is used, it can more easily control the wheel-out current. It has become a considerable challenge in the industry. To provide a digital output The snubber circuit, which uses a feedback pull-up circuit, can be used to drive the negative gate voltage waveform of the output terminal, so as to control the output terminal u bamboo-shaped reverse cattle [slew μ inch short-circuit current (crowbar current) number 4 Digital output buffer circuit network to achieve a good switching speed to avoid huge switching, not only can slow rate control, but also reach short-circuit current. 479408

5. Description of the invention (4) The digital output buffer circuit disclosed in the present invention & pulls down the network. In the bean, Lagu defeated the Lanan network and the "Lala network" through the switch-PM0S, and the terminal is connected to the output to increase the output voltage, so that wd through the switch- NM0S, so that the yss terminal output | | · > ι. The same way is the Lei Gan Gan Shi 柘 、, the output 钿 is turned on to pull down the output terminal, the second and pull down the network are all available- GVFpUL returns to GVFPHT and late f 4 I early-direction switch. Among them, taking the pull-down network as an example, the GVFPUL loop will be coupled to the NM0s element, and when the "frightening loop", the idle voltage of the NM0S element can be pulled up To near a predetermined value. After the gate voltage rises to a predetermined value, the GVFPUL circuit will immediately open:

In the delay device, it can respond to the current I and the enable signal 0EN, and delay the transmission of the f signal. In this way, the gate voltage can be maintained for a period of time near the predetermined value. In addition, the above-mentioned one-way switch is respectively adapted to the GVFPUL loop and the delay device, and can control the signal transmission direction to avoid signal competition between the GVFpuL loop and the delay device. Drawing number comparison table

1 2 input 1 6 output 2 0 pull down the network 2 4 first inverter 28 delay device 32 GVFPUL loop 36 contact 40th _NMOS

10 Digital output buffer circuit 14 Input terminal 1 8 High network 22 Reverse gate 26 Reverse gate 30 Unidirectional switch 34 Second inverter 38 MOS diode

Page 7 479408 V. Description of the invention (5)

42 Second NM0S 46 Fourth inverter 50 M0S capacitor 54 contact

58 First PM0S 6 2 Sixth inverter 68 Second PMOS 72 contact

134 Eighth Inverter 138 M0S Diode 142 Fifth PM0S 146 Tenth Inverter 1 50 M0S Capacitor 154 Contact 158 Sixth PMOS 162 Twelfth Inverter 168 Fifth NMOS 0 1 7 2 Contact Details Description 44 Third inverter 4 8 Fifth inverter 52 MOS capacitor 5 6 contacts

60 Third NMOS

6 4 Seventh inverter 70 Third PMOS

136 contact 1 40 fourth PMOS 144 ninth inverter 148 eleventh inverter 1 52 MOS capacitor 1 5 6 contact 160 fourth NMOS 164 thirteenth inverter 170 sixth NMOS The present invention discloses a kind of Digitally pull the network up and down to achieve a fast discharge to avoid causing buffer circuits, not only can slowly control the switching rate, but also achieve short-circuit current during switching. among them

479408 V. Description of the invention (6) 'By using the gate voltage feedback pull-up circuit, M0S which can be used to drive the output terminal has a smoother gate voltage waveform, so as to achieve the purpose of controlling the output and end load. The detailed description of the present invention is as follows. Please refer to the first figure, which shows a circuit diagram of a digital output buffer circuit provided by the present invention. The digital output buffer 10 includes two input terminals 12, 14, an output 咼 16, a pull-down network 18, and a pull-down network 20. In this integrated circuit, the 'current signal I and the enable signal 0EN are coupled to the pull-up network 18 and the pull-down \ 罔 circuit 20 via an inverse AND gate NAND 22 and an inverse OR gate N0R 26, respectively. Among them, the enable signal 0EN is coupled to the anti-gate NAND 22 via the first inverter 24, and the output of the anti-gate NAND 22 is coupled to the input terminal 12 of the pull-up network 18. On the other hand, the current signal t and the enable signal 0EN of the integrated circuit are coupled to a reverse OR gate N0R 26, and the output of this reverse OR gate NO 26 is coupled to the input terminal of the pull-down network 2 0. 4. The main components of the pull-down network 20 here include a delay device 28, a unidirectional switch 30, a gate voltage feedback pull-up loop (GVFPUL) 32, and a grounding level. (Vss) and the first NMOS 40 of the output terminal 16. Among them, the delay device 28 is coupled to the output terminal (contact 3 6) of the second inverter 34 and the unidirectional switch 30, and the input terminal of the first reverse state 34 is the entire pull-down. Input 20 of the network 20. As for the one-way switch 30, the input terminals 14 and contacts 36 located on both sides of the second inverter 34 are respectively coupled to receive signals from the reverse OR gate 26 and the second inverter 34 for operation. In addition, the GVFPUL circuit 32 is coupled to a unidirectional switch.

479408 V. Description of the invention (7)! Γ. 0 复 Ϊ—Face 5 4 °, the second _S42, the GVFPUL circuit 32 with the * second inverter 34, in addition to being lightly closed to the second through the MOS diode 38, and can respond to the first The two inverters 34 and the second NMOS 42 operate in order to control the on or off of the first NMOS 40. = In a preferred embodiment, the delay device ⑶ is composed of a plurality of competing worms and a capacitor coupled between the inverters. For example, you can make the inverter Γ times the third inverter and the fourth inverter. J: * The inversion is 48 and two MOS capacitors 50 and 52 are used to form a delay device =, the second inversion The input terminal of the converter 44 is connected to the contact 36, and the output terminal of the fifth in 28 is connected to the unidirectional switch 30. As for the two MOS power valleys 50, 52, they are bypassed respectively. Fang Shang = one hour, you can increase the ρ number field of the fine s capacitor of the inverter. And longer delay time In addition, the one-way switch 30 here is = 60. Among them, the first cut "8 And the third _ =: the pole and the drain are connected to each other, and are respectively connected to the 7 output of the fifth inverter 48 and the π1 of the M0S diode 38 to lose the seventh; 5 South cry to the goods as GVFPUL The loop 32 is connected by a σ sixth inverter 62, a second PM0S Θ8, and a third route: 80% of other connections. ★ Among them, the seventh inverse round-by-round warp of 11 64 ", the blade J is connected to the gate of the -NM0S 40 and the second NM0s 42 page 10 479408 5. The source of the invention description (8). On the one hand, the output of the sixth inverter 62 is connected to the gate of the second PM0S 68, which is used to control the second PM0S 68 to turn on and the current of vdd can flow through the second PM0S 68 and the third PM0S 70. Go to contact 72. As for the gate of the third PMOS 70, it is connected to contact 36 to receive the signal output by the second inverter 34. In this way, when the voltage of contact 7 2 is sufficient to open 40 , The Vss and the output terminal 16 can be turned on. When the enable signal OEN and the current I are set at the voltage levels of Vss and Vdd, respectively, they are transmitted to the second NMOS 42 through the output terminal (contact 36) of the second inverter 34. The current will have a high potential to turn on the second NMOS 42 and pull the potential of the contact 72 to Vss. At this time, the first NMOS 40 will be completely turned off. Then, the level of the current I can be reduced from the high potential To a low potential so that the current level at the output of the second inverter 34 can be reduced from a high potential to a low potential. In this way, it can be closed via the contact 36 The second NMOS 42 is turned on and the third PM0S 70 is turned on to start the GVFPUL circuit 32. In addition, since the second NMOS 42 is turned off, the Nissho 'contact 7 2 has a low potential, so that it can cry through the seventh reverse 64, the sixth reverse The commutator 62 keeps the gate of the second PM0S 68 at a low potential. At this time, both the second PM0S 68 and the third PM0S 70 are turned on, and the potential of the contact 72 is immediately raised. At the moment when the potential of 2 rises, the GVFPUL circuit 32 will open again, and the potential of the contact 72 will be maintained near a predetermined value. Since the current I drops to a low level, the output of the second inverter 34 ( The current at contact 36) also has a low level and can conduct the first pM0s μ.

479408 5. Description of the invention (9) " " " " " " Conversely, the current at the input terminal 14 has a high level and can conduct the third NM0S 60. In other words, when the current I is at a low level, it is unidirectionally opened; and the contact 72 and the output terminal of the fifth inverter 48 are lightly connected together. At the same time, the current passing through the contact 36 will also pass through the delay device 28, such as the third inverter 44, the MOS capacitor 50, the fourth inverter 46, and the MOS capacitor, to produce a delay effect. In this way, when the voltage level at the output terminal of the fifth inverter 48 fails to rise to Vdd-Vth (Vth is the starting voltage of the MOS diode 38) due to the signal delay, the power of the contact 72 = will be Maintained around this predetermined value for a period of time. Until the contact 56 receives a current from a high potential to a low potential and the current through the fifth inverter 48 rises from a low potential to a high potential (Vdd-Vth), the jjos diode 38 can be turned on and pulled The potential of the high contact 72 is Vdd-Vth. It should be particularly emphasized that the design of the one-way switch 30 here can effectively avoid the signai > competition between the GVFPUL circuit 32 and the delay device 28. As for the design of the MOS diode 38, it is ensured that the GVFPUL circuit 32 will only pull up the potential of the contact 72. Among them, when the signal is transmitted through the delay device 28, the output terminal of the fifth inverter 48 will be maintained at a low potential. Therefore, if the MOS diode 38 is not used, the pull-down current of the fifth inverter 48 will compete with the GVFPUL circuit 32 (via the first PM0s 68 and the third PM0S 70 to Vdd). Furthermore, since the M0s diode 38 is composed of an M 0 S element, the M0S diode will only be made when the level of the contact 72 is lower than Vth by the fifth inverter 48. The body 38 appears conductive. In other words, before the current signal passes through the delay device 28,

Page 12 479408 V. Description of the invention (10) All the bodies 38 will be cut-off, which effectively eliminates the current competition that may occur between the fifth inverter 48 and the GVFPUL circuit 32. Subsequently, when the level of the current I rises from a low potential to a high potential again, the contact 36 will also rise from a low potential to a high potential, and re-conduct the second NMOS 42 to instantly lower the potential of the contact 72 again to Vss. At this time, the NM0S 40 will be turned off immediately, and Vss and the output terminal 6 will be disconnected. For example, the voltage level of the output terminal 16 can be switched on time to avoid causing a crowbar current. At the same time, since the voltage at the input terminal 14 is reduced from a high potential to a low potential, the third NMOS 60 will be turned off, and the first PMOS 58 is also turned off due to the voltage level of the contact 36. In this way, the coupling relationship between the fifth inverter 48 and the contact 72 will form an open circuit again, and block all paths that may cause leakage current. Next, reference is made to the corresponding drawing network 18 in the first figure. Its main elements also include a delay device 128, a unidirectional switch 13 (), and a gate voltage feedback pull-up loop (gate voltage feedback pulup 100p,

GVFPUL) 132, and a fourth PMOS 14 for conducting vdd and output terminal 16. Among these, the delay device 128 is coupled to the output terminal (contact 136) of the eighth inverter 134 and the unidirectional switch 13 respectively. In addition, the input '' of this eighth inverter 34 is the input terminal M of the pull network M. As for the one-way switch 1 3 0, it is not coupled to the eighth inverter 1 3 4 · point " 6, so as to receive the signals from the inverse of the question 22 and the eighth inverter 134: 1.2 In addition, outside, The GVFPUL circuit 132 is coupled to the unidirectional switch 13 (), the fourth pM0s 479408, the fifth invention description (π) 140, the fifth PMOS 142, and the contact 136, respectively. Among them, the GVFPUL loop 132 is coupled to the unidirectional switch 130 through the MOS diode 138, and can operate in response to the eighth inverter 134 and the fifth PMOS 142 to control the fourth PMOS 140 to be turned on or off. Similar to the delay device 28 in the pull-down network 20, in a preferred embodiment, the delay device 128 can also use three serial inverters (ninth inverter 144, tenth inverter in turn). 146 and the eleventh inverter 148) and two MOS capacitors 150 and 152. Among them, the input terminal of the ninth inverter 144 is connected to the contact 1 36, and the output terminal of the eleventh inverter 148 is connected to the unidirectional switch 130. As for the two MOS capacitors 150 and 152, they are bypassed to the output terminal (contact 154) of the ninth inverter 144 and the output terminal (contact 156) of the tenth inverter 146, respectively. . Similarly, the number of inverters and MOS capacitors can be determined according to the length of the required delay time.

The unidirectional switch 130 here also includes a sixth PMOS 158 and a fourth NMOS 160 whose source and drain electrodes are connected to each other, and is connected to the output terminal of the eleventh inverter 148 and the MOS diode体 138. The GVFPUL circuit 132 is a circuit composed of a thirteenth inverter 164, a twelfth inverter 162, a fifth NMOS 168, and a sixth NMOS 170. The input terminal of the thirteenth inverter 164 is connected to the gate of the fourth pMOS 140 and the source of the fifth pMOS 142 via contacts 172, respectively. The output terminal of the twelfth inverter 16 2 is connected to the gate of the fifth n μs 168, which is used to control the fifth NMOS 168 to be turned on and the VSS terminal to pass through the fifth NMOS 168, sixth

479408 V. Description of the invention (12) NM0S 170 is connected to contact 172. The gate of the sixth NMOS 170 is connected to the contact 136 to receive the signal output from the eighth inverter 134. In this way, when the voltage of contact 1 72 is sufficient to turn on the fourth PMOS 1 40, Vdd and 16 can be turned on.

When the enable signal OEN and the current I are set at the voltage levels of Vss and Vdd, respectively, the signals of the inverse gate 22 and the eighth inverter 134 will cause the contact 136 to have a high potential and the fifth pm0S. 1 4 2 is off. At this time, the fourth PMOS 140 is in a conducting state, and Vdd is coupled to 16. Then 'the current I can be reduced from a high potential to a low potential, so that the GVFPUL circuit 32 in the pull-down network 20 will first pull the voltage level of the contact 72 to a predetermined value, and then by the delay device 28 The function of the contact 72 keeps the voltage of the contact 72 at this predetermined value for a period of time. Then, increase the voltage at contact 72 to vdd-vth. That is, by gradually increasing the gate voltage of the first NMOS 40, the purpose of slowly turning on the first NMOS 40 can be achieved, and Vss and the output terminal 16 can be gradually turned on to provide a better slew rate. ). In the same dry room, because the voltage of contact 1 3 6 drops from high potential to low potential,

Therefore, the fifth PMOS 142 is turned on so that the contact 172 has the potential of Vdd in an instant. At this time, the fourth PMOS 140 is immediately turned off, so that Vdd and the output terminal 16 are disconnected. After the heart ’, when the potential of the output terminal 16 is to be pulled to vdd again, the level of the current I may be raised from a low potential to a high potential. At this time, the contact 136 will also rise from a low potential to a high potential to turn off the fifth PM0s 142 and turn on the second

479408 V. Description of the invention (13)

The NMOS 170 activates the GVFPUL circuit 132. In addition, when the fifth PM0S 1 42 is closed, the contact 1 72 has a high potential, so that the gate of the fifth NMOS 168 can be passed through the thirteenth inverter 164 and the twelfth inverter 162. Also maintained at a high potential. At this time, both the fifth NMOS 168 and the sixth NMOS 170 are turned on, and the potential of the contact 172 is lowered. Since the current I has a high level, the current at the output terminal (contact 136) of the eighth inverter 134 also has a high level, and the fourth NMOS 160 can be turned on. In contrast, the current at the input terminal 12 has a low level and can turn on the sixth PMOS 158. In other words, when the current I is at a high level, the one-way switch 130 is turned on, and the contact 17 2 is coupled to the output terminal of the eleventh inverter 148. At the same time, the current passing through the contact 136 will also pass through the delay devices 128, such as the ninth inverter 144, the MOS capacitor 150, the tenth inverter 146, and the MOS capacitor 152, to produce a delay effect. In this way, when the voltage level at the output terminal of the eleventh inverter 148 has not fallen due to the signal delay, the potential of the contact n2 will be maintained near this predetermined value for a period of time. Until the contact 156 receives a current rising from a low potential to a high potential, and the current passing through the eleventh inverter 148 decreases from a high potential to a conductive MOS diode 138, the contact will be pulled down again 1 7 2 The potential. Similar to the above, the design of the unidirectional switch 315 here is also used to avoid signal competition between the GVFPUL loop 132 and the delay device 128. As for the design of the MOS diode 138, it is ensured that the GVFpUL circuit 132 can only lower the potential of the contact 172. Among them, as the signal is passed through the delay device ⑶, the output terminal of the eleventh inverter 148 will be maintained at a high potential.

Page 16 479408 V. Description of the invention (14) So if the M0S diode 138 is not used, the low current of the eleventh inverter 148 will be connected to the GVFPUL circuit 132 (via Fili 0S 168, sixth NM0S 170 to Vss)). Furthermore, since the MOS diode 1 38 is composed of a MOS element, it is only used when the level of the contact 72 is higher than Vth by the eleventh inverter 148. The diode 138 is turned on. In other words, before the current signal passes through the delay device 28, the MOS diodes 1 38 will be open, and the current competition between the eleventh inverter 148 and the GVFPUL circuit 132 can be effectively eliminated. Please refer to the second figure, which shows the case where the GVFPUL circuit 32 is used to control the first NMOS 40 gate voltage in the pull-down network 20 of the present invention. Among them, the horizontal axis represents the entire operating time of 10, and the vertical axis represents the gate voltage of the: NMOS 40, and the curve a in the figure is the gate voltage. Assuming that the output terminal 16 has a high potential of 3.3 V at an operating time of 30 ns, as described above, the current I can be raised from a low potential to a high potential. In this way, the GVFPUL circuit 32 will pull the voltage of the contact 72 to about 30.3 ns. In addition, the voltage of the contact 72 rises, so that the GVFpuL circuit 32 = circuit. At this time, '帛 -question 40 will slowly turn on the Vss and the voltage, and' f 'because the GVFPUL circuit 32 appears to be open circuit, and is maintained at ... about-by the electrical delay device 28 of the contact 72. The direct current was raised to two minutes before the output terminal level of the fifth inverter 48 was switched from a low potential to the one-way switch. The voltage of the contact 72 was used. Among them, 'Because the starting σ I of the MoS diode 38, 々 is 0.6V, so that the potential of the contact 72 can be pulled up to 479408. 5. Description of the invention (15) 3 · 3-0 · 6 = 2 · 7ν. At the same time, Vss and 16 are completely turned on. It should be particularly noted that in the embodiment provided by the present invention, whether in the pull-down network 20 or the pull-up network 18, only one GVFPUL loop 32 and 132 is used to control the first NMOS 40, the first Four PM0S 140 gate voltages to turn on the load at output 16. However, for those skilled in the art, it can be easily known that in order to further make the gate voltages of the first NMOS 40 and the fourth PMOS 140 have a smoother and slower waveform, the number of GVFPUL circuits can be increased. By using a plurality of GVFPUL circuits, the gate voltage can be increased step by step, and the load on the output terminal 6 can be gradually increased. In this way, the purpose of controlling the slew rate can be effectively achieved by adjusting the gate voltages of the first NMOS 40 and the fourth pMOS 140. In addition, as mentioned above, when the pull-down network 20 is gradually turned on, the pull-up network 18 will immediately open the fourth pM0s 14 to prevent a huge short-circuit current during switching. As the pull-up of the network 2 0 gradually turns on, the pull-down of the network 20 will also immediately turn off the first NMOS 40, so that the short-circuit current during switching can be effectively avoided. The above is to make the scope of the present invention with better practice, and it is well known to make slight changes and adjustments, without departing from the spirit and scope of the present invention. The examples illustrate the present invention in detail, and those who are not limited to this technique can also understand. Without losing the gist of the present invention,

Page 479408 Brief Description of the Drawings The above description and the many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, where: The first diagram is a component circuit diagram showing the components provided according to the present invention. The circuit diagram of the digital output buffer circuit; and the second diagram is the gate waveform diagram, which shows the gate voltage waveform of the MOS that can drive the load at the output terminal using the pull-down network disclosed in the present invention.

Page 19

Claims (1)

479408 6. Scope of patent application 1. A digital output buffer circuit, which includes a pull-up network and a pull-down network, and the pull-up network is used to pull up the output voltage of an output terminal, and the pull-up network The low network is used to pull down the output voltage of the output terminal. The low network includes at least: M0S element to turn on the ground voltage (Vss) and the output terminal; at least one gate voltage feedback pull-up (GVFpUL ) Circuit, coupled to the M0S element 'can adjust the gate voltage of the M0S element to a predetermined value to determine the conduction state of the M0S element; a delay device' coupled to the M0S element can delay the transmission signal for a period of time to So that the gate voltage can be maintained at about the predetermined value; and a unidirectional switch, which is coupled to the GVFPUL loop and the delay device, can control the flood transmission direction to avoid signal competition between the qVFPUL loop and the delay device. Above 2 · If the M0S element described in the first digit of the scope of the patent application is composed of the first NMOS < ... 3. If the digital output buffer circuit in the second scope of the patent application, the above mentioned network can be lowered, You are coupled to the current on the mountain / M, the input is coupled to the current (I), the signal at the toilet (0ΕΝ) 〇% ^, enable ^ If the digital output of the third scope of the patent application buffers the above input, It can be connected to the delay device via 筮 where J ,, Φ, and Φ are the first reverse behaviors. Τ Page 20 479408 6. Application for patent scope 5, such as the digital output buffer circuit of the patent application scope item 4, in which the above second inverter is connected to the gate of the second Radeon, which can conduct the / second NMOS And reduce the gate voltage of the first NMOS to the Vss level, so that the output terminal and the Vss terminal are disconnected. , 6: If the digital output buffer circuit of item 4 of the patent scope is declared, where t Ϊ two two-way & is connected to the one-way switch, the one-way switch can be controlled to be turned on or off. , :: If the digital output buffer circuit of item 4 of the patent claim is declared, wherein the first inversion ⑤ is connected to the GVFpUL circuit, it can conduct the circuit and control the gate voltage of the first NMOS. 8. The digital output buffer circuit of item 1 of the patent application range, wherein the delay device includes a plurality of inverters connected in series and a plurality of bypass (hPaSS) capacitors, and the capacitors can delay the signal. For example, the digital output buffer circuit of item 8 of the patent scope, wherein the bypass capacitor is composed of a MOS capacitor. ψ 丨 + 〇 The digital output buffer circuit of item 1 of the scope of patent application, its-1 ^ unidirectional switch is composed of PMOS element and NM0S element, and the PM0S element /, the source of the NM0S element Connected to the drain. Page 21 479408 VI. Application scope 1 — 11. If the digital output buffer circuit of item 1 of the scope of patent application, the above GVFPUL circuit is composed of a plurality of inverters and a plurality of Mos elements 0 12. As claimed The above-mentioned pull-up network PM0S element has at least one first PM0S element, and determines the second delay of the PM0S is delayed for a period of time, which is about the value; The digital output buffer circuit includes at least: ',' to turn on the voltage source (Vdd) and the output terminal; the two gate voltage feedback pull-up (GVFPUL) circuit, which is lightly adjusted to adjust the gate voltage of the PM0S element To a predetermined value, the conduction state of the device; the device, coupled to the PM0S device, can delay the transmission signal so that the gate voltage of the PM0S device can be maintained at the predetermined switch, coupled to the second GVFPUL circuit and the second The transmission direction of the alum signal is extended to avoid signal competition from the second GVFpUL loop device. 13. A digital round-out buffer circuit, comprising: a first buffer network and a first-end buffer network, wherein the first buffer network is combined with an output terminal, and the first buffer network A buffer circuit is used to pull the output voltage that the output is always on the mountain side, and the second buffer network is used to pull the output of the wheel box at the output terminal. Each of the buffer networks contains ... The second buffer network is listed in the recognition of the mountain *, ^ ^ £, the knife and the manuscript are combined into an output terminal, and the first buffer is used to pull the output of the output to the mountain. The flute stole a marriage _ element to provide the output load; Page 22 479408 6. The scope of the patent application is at least one gate voltage feedback pull-up (GVFPUL) circuit, which is coupled to the M0S element. When the GVFPUL circuit is turned on, the gate of the 8 element can be connected to a voltage source. And the gate voltage of the M0S element is pulled to a predetermined value 'and the GVFPUL circuit will immediately show an open circuit. Near the predetermined value, wherein when the signal passes through the delay device, the gate voltage can be increased from the predetermined value; and a unidirectional switch is engaged with the GVFPUL circuit and the delay device, which can be controlled Make the signal transmission direction to avoid signal competition between the GVFPUL loop and the delay device. 14. The digital output buffer circuit according to item 13 of the scope of patent application, wherein the buffer network can be coupled to the current (1) toilet enable signal (0ENE) through an input terminal. "15. If the digital output buffer circuit of item 14 of the patent application scope, wherein the above input terminal can be connected to the delay device through an inverter. 1 6 · If the digital output buffer circuit of item 15 of the patent scope is declared The above inverter can control the gate voltage of the Mos element. Page 23 479408 On or off. The digital wheel-out slow-balance circuit of item 15 of the middle and upper 3 patent scope, which < inverter is connected to the GVFPUL circuit, can conduct the GVFPUL circuit, and control the gate voltage of the Mos element . If the digital wheel-out slow-balance circuit of item 13 of the scope of patent application, the above-mentioned delay device includes a plurality of inverters connected in series and a plurality of bypass capacitors, and the capacitors can delay the signal . 20. The digital output buffer circuit according to item 19 of the patent application scope, wherein the bypass capacitor is composed of a MOS capacitor. 21 · If the digital output buffer circuit of item 13 of the patent application scope, wherein the unidirectional switch is composed of a PM0S element and a NMOS element, and a source and a drain of the pM0s element and the NMOS element Connected to each other. 22. The digital output buffer circuit according to item 13 of the scope of patent application, wherein the above-mentioned GVFPUL loop is composed of a plurality of inverters and a plurality of Mos elements. Page 24