WO2022204990A1 - 控制芯片的方法和集成电路系统 - Google Patents

控制芯片的方法和集成电路系统 Download PDF

Info

Publication number
WO2022204990A1
WO2022204990A1 PCT/CN2021/084110 CN2021084110W WO2022204990A1 WO 2022204990 A1 WO2022204990 A1 WO 2022204990A1 CN 2021084110 W CN2021084110 W CN 2021084110W WO 2022204990 A1 WO2022204990 A1 WO 2022204990A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
wake
sleep mode
circuit
circuits
Prior art date
Application number
PCT/CN2021/084110
Other languages
English (en)
French (fr)
Inventor
李南
张广宇
肖文才
刘荣国
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/084110 priority Critical patent/WO2022204990A1/zh
Priority to CN202180093544.5A priority patent/CN116868177A/zh
Publication of WO2022204990A1 publication Critical patent/WO2022204990A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer

Definitions

  • the present disclosure relates to the field of electronics, and more particularly to a method for controlling a chip, an integrated circuit system including the chip, and an electronic device.
  • the power consumption of the chip can be reduced by, for example, reducing the size of the devices in the chip.
  • the cost is correspondingly increased significantly.
  • the embodiments of the present disclosure aim to provide a solution for controlling a chip.
  • a method for controlling a first chip includes controlling the state of a plurality of first receivers and one or more wake-up circuits in the first chip.
  • the plurality of first receivers are disabled in the first sleep mode.
  • At least one of the one or more first wake-up circuits is enabled in the first sleep mode.
  • the one or more first wake-up circuits correspond to the plurality of first receivers.
  • the number of at least one first wake-up circuit is less than the number of the plurality of first receivers.
  • the method also includes enabling at least one first receiver of the plurality of first receivers in response to the at least one first wakeup circuit receiving a first wakeup signal.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the total power consumption of the first chip in the sleep mode is the product of the power consumption of the wake-up circuits and the number of all wake-up circuits.
  • the control method according to the first aspect enables fewer wake-up circuits by disabling a portion of the wake-up circuits, that is, the number of enabled wake-up circuits is reduced compared to the number of all wake-up circuits. Reduce the total power consumption of the first chip in sleep mode.
  • the integrated circuit chip according to the present disclosure does not involve reducing the size of the chip, the cost of the chip is not significantly increased, thereby solving the problem of significantly increasing the cost in the background art.
  • the at least one first wake-up circuit of the one or more first wake-up circuits being in an enabled state in the first sleep mode includes: only one first wake-up circuit of the one or more first wake-up circuits is enabled in the first sleep mode. By enabling only one wake-up circuit in sleep mode, the power consumption of the first chip in sleep mode can be greatly reduced, while still keeping the receiver able to wake up for normal operation.
  • the at least one first wake-up circuit of the one or more first wake-up circuits being enabled in the first sleep mode includes: only one first receiver of the plurality of first receivers The first wake-up circuit in is enabled. By enabling only one wake-up circuit in the first receiver in sleep mode, the power consumption of the first chip in sleep mode can be greatly reduced, while still keeping the receiver able to wake up for normal operation.
  • the wake-up circuit is located in the receiver, the physical transmission path of the signal is shorter, and in the case where the wake-up circuit directly triggers the wake-up receiver, the wake-up circuit does not need to transmit the wake-up signal to the controller first and does not need to wait for the controller to wake up in sequence receiver, so it can speed up the wake-up response.
  • the first chip and the second chip transmit data and/or commands according to a serializer/deserializer (Serializer-Deserializer, SerDes) protocol.
  • Serializer-Deserializer Serializer-Deserializer, SerDes
  • the method further includes enabling the first transmitter in the first chip to transmit the second wakeup signal to the second reception of the second chip in response to the at least one first wakeup circuit receiving the first wakeup signal device.
  • the second chip is different from the first chip.
  • the method further includes starting communication between the first transmitter and the second receiver in the second chip after the first transmitter of the first chip is enabled for a first predetermined period of time; and at least After one of the first receivers is enabled for a second predetermined period of time, the at least one first receiver begins to communicate with the second transmitter in the second chip.
  • the first predetermined period of time may be the same as or different from the second predetermined period of time.
  • the method further includes sending, by the first transmitter of the first chip, the first mode data to the second receiver of the second chip before entering the first sleep mode, the first mode data representing the first The first sleep mode supported by the chip; the plurality of first receivers of the first chip receive the second mode data from the second transmitter of the second chip, and the second mode data represents the first sleep mode supported by the second chip and determining a first sleep mode to be used by the first chip based on the supported first sleep mode and second mode data of the first chip.
  • the method further includes, before entering the first sleep mode, receiving, by the plurality of first receivers of the first chip, the wake-up circuit designation data from the plurality of second transmitters of the second chip, and the second chip different from the first chip; and determining at least one first wake-up circuit of the one or more first wake-up circuits to be enabled in the first sleep mode based on the wake-up circuit specification data.
  • a method for controlling a second chip includes controlling the state of a plurality of second receivers in the second chip and one or more second wake-up circuits in the second chip, wherein the plurality of second receivers and the one or more second wake-up circuits At least one second wake-up circuit is disabled in the second sleep mode, and the one or more second wake-up circuits correspond to the plurality of second receivers.
  • the method also includes, in response to entering the operating mode, sending a first wake-up signal to a first chip, the second chip being different from the first chip.
  • the method further includes enabling at least one second receiver of the plurality of second receivers of the second chip at a predetermined time after sending the wake-up signal.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the total power consumption of the first chip in the sleep mode is the product of the power consumption of the wake-up circuits and the number of all wake-up circuits.
  • the control method according to the second aspect can reduce the total power consumption of the second chip in the sleep mode by disabling all wake-up circuits, that is, the number of enabled wake-up circuits is actually zero.
  • the integrated circuit chip according to the present disclosure does not involve reducing the size of the chip, the cost of the chip is not significantly increased, thereby solving the problem of significantly increasing the cost in the background art.
  • the second chip operates as a master and the first chip operates as a slave.
  • the plurality of second receivers in the second chip and at least one second wake-up circuit of the one or more second wake-up circuits in the second chip are disabled in the second sleep mode This includes disabling all of the one or more second wake-up circuits. By disabling all wake-up circuits of the second chip, the sleep power consumption of the second chip in the second sleep mode can be greatly reduced.
  • a method for controlling a chip includes controlling the state of a plurality of first receivers and one or more first wake-up circuits in a first chip.
  • the plurality of first receivers are disabled in the first sleep mode.
  • At least one of the one or more first wake-up circuits is enabled in the first sleep mode.
  • the one or more first wake-up circuits correspond to the plurality of first receivers.
  • the number of the at least one first wake-up circuit is less than the number of the plurality of first receivers.
  • the method also includes controlling the state of the plurality of second receivers in the second chip.
  • the plurality of second receivers are disabled in a second sleep mode, and the second chip is different from the first chip.
  • the method further includes enabling at least one first receiver of the plurality of first receivers in response to the at least one first wakeup circuit receiving the first wakeup signal.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the total power consumption of the first chip in the sleep mode is the product of the power consumption of the wake-up circuits and the number of all wake-up circuits.
  • the control method according to the third aspect enables fewer wake-up circuits by disabling a portion of the wake-up circuits, that is, the number of enabled wake-up circuits is reduced compared to the number of all wake-up circuits.
  • the at least one of the one or more first wake-up circuits in the first chip being in an enabled state in the first sleep mode includes: only one of the one or more first wake-up circuits A first wake-up circuit is enabled in the first sleep mode.
  • the method further includes at least one of the one or more second wake-up circuits in the second chip being enabled in the second sleep mode.
  • the one or more second wake-up circuits correspond to the plurality of second receivers.
  • the number of the at least one second wake-up circuit is less than the number of the plurality of second receivers.
  • At least one of the one or more second wake-up circuits in the second chip being in an enabled state in the second sleep mode includes only one of the one or more second wake-up circuits
  • the second wake-up circuit is enabled in the second sleep mode.
  • the method further includes enabling the first transmitter in the first chip to transmit the second wakeup signal to the second reception of the second chip in response to the at least one first wakeup circuit receiving the first wakeup signal device.
  • the second chip is different from the first chip.
  • the method further includes disabling all of the second wake-up circuits in the second chip in the second sleep mode. By disabling all wake-up circuits of the second chip, the sleep power consumption of the second chip in the second sleep mode can be greatly reduced.
  • the method further includes sending, by the first transmitter of the first chip to the second receiver of the second chip, data in the first mode before entering the sleep mode, where the data in the first mode represents the data of the first chip. supported sleep modes; second mode data is sent by the transmitter of the second chip to the first receiver of the first chip, the second mode data representing the sleep modes supported by the second chip; and the first chip is based on the first The supported sleep mode and second mode data of the chip determines the sleep mode to be used by the first chip; and the second chip determines, based on the supported sleep mode and first mode data of the second chip, the sleep mode to be used by the second chip Sleep mode to use.
  • the method further includes receiving, by the plurality of first receivers of the first chip, the wake-up circuit designation data from the plurality of second transmitters of the second chip before entering the sleep mode; and based on the wake-up circuit
  • the specified data determines at least one first wake-up circuit in the first chip to be enabled in the first sleep mode.
  • a first chip includes a plurality of first receivers and one or more first wake-up circuits.
  • the plurality of first receivers are configured to be in a disabled state in the first sleep mode.
  • the one or more first wake-up circuits correspond to the plurality of first receivers.
  • At least one of the one or more first wake-up circuits is configured to be in an enabled state in the first sleep mode.
  • the number of the at least one first wake-up circuit is less than the number of the plurality of first receivers.
  • the at least one wake-up circuit is further configured to cause at least one first receiver of the plurality of first receivers to be enabled in response to receiving the first wake-up signal.
  • the power consumption of the first chip in sleep mode can be reduced.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the total power consumption of the first chip in the sleep mode is the product of the power consumption of the wake-up circuits and the number of all wake-up circuits.
  • the control method according to the first aspect enables fewer wake-up circuits by disabling a portion of the wake-up circuits, that is, the number of enabled wake-up circuits is reduced compared to the number of all wake-up circuits. Reduce the total power consumption of the first chip in sleep mode.
  • the integrated circuit chip according to the present disclosure does not involve reducing the size of the chip, the cost of the chip is not significantly increased, thereby solving the problem of significantly increasing the cost in the background art.
  • the at least one first wake-up circuit includes only one first wake-up circuit. By enabling only one wake-up circuit in sleep mode, the power consumption of the first chip in sleep mode can be greatly reduced, while still keeping the receiver able to wake up for normal operation.
  • only one first wake-up circuit is located in one first receiver of the plurality of first receivers.
  • the power consumption of the first chip in the sleep mode can be greatly reduced, while still keeping the receiver able to be woken up for normal operation, And it can also speed up the response speed of wake-up.
  • the power consumption of the first chip in sleep mode can be greatly reduced, while still keeping the receiver able to wake up for normal operation.
  • the wake-up circuit is located in the receiver, the physical transmission path of the signal is shorter, and in the case where the wake-up circuit directly triggers the wake-up receiver, the wake-up circuit does not need to transmit the wake-up signal to the controller first and does not need to wait for the controller to wake up in sequence receiver, so it can speed up the wake-up response.
  • the first chip is configured to enable the first transmitter in the first chip to transmit the second wake-up signal to the second wake-up signal in response to the at least one first wake-up circuit receiving the first wake-up signal chip's second receiver.
  • the second chip is different from the first chip.
  • the first chip is configured to initiate communication between the first transmitter and the second receiver in the second chip after the first transmitter of the first chip is enabled for a first predetermined period of time; and After the at least one first receiver is enabled for a second predetermined period of time, the at least one first receiver begins to communicate with the second transmitter in the second chip.
  • the first predetermined period of time may be the same as or different from the second predetermined period of time.
  • the first chip is configured to transmit the first mode data from the first transmitter of the first chip to the second receiver of the second chip before entering the first sleep mode, the first mode data representing The first sleep mode supported by the first chip; the plurality of first receivers of the first chip receive the second mode data from the second transmitter of the second chip, and the second mode data represents the first sleep mode supported by the second chip. a sleep mode; and determining a first sleep mode to be used by the first chip based on the supported first sleep mode and second mode data of the first chip.
  • the first chip is configured to receive wake-up circuit designation data from a plurality of first receivers of the first chip from a plurality of second transmitters of the second chip before entering the first sleep mode, the first The two chips are different from the first chip; and, based on the wake-up circuit specification data, determining at least one first wake-up circuit of the one or more first wake-up circuits to be enabled in the first sleep mode.
  • a second chip including a plurality of second receivers, one or more second wake-up circuits, and a plurality of second transmitters.
  • the plurality of second receivers are configured to be disabled in the second sleep mode.
  • the one or more second wake-up circuits correspond to the plurality of second receivers. At least one of the one or more second wake-up circuits is configured to be in a disabled state in the second sleep mode.
  • the plurality of second transmitters are configured to, in response to entering the operating mode, send a first wake-up signal to the first chip, the first chip being different from the second chip; and a predetermined time after sending the first wake-up signal, such that the plurality of first wake-up signals are At least one of the two receivers is enabled.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the total power consumption of the first chip in the sleep mode is the product of the power consumption of the wake-up circuits and the number of all wake-up circuits.
  • the control method according to the fifth aspect can reduce the total power consumption of the second chip in the sleep mode by disabling all wake-up circuits, that is, the number of enabled wake-up circuits is actually zero.
  • the integrated circuit chip according to the present disclosure does not involve reducing the size of the chip, the cost of the chip is not significantly increased, thereby solving the problem of significantly increasing the cost in the background art.
  • the second chip is configured as a master device and the first chip is configured as a slave device.
  • the one or more second wake-up circuits are configured to be all disabled in the second sleep mode. By disabling all wake-up circuits of the second chip, the sleep power consumption of the second chip in the second sleep mode can be greatly reduced.
  • an integrated circuit system includes a first chip and a second chip.
  • the first chip includes a plurality of first receivers and one or more first wake-up circuits.
  • the plurality of first receivers are configured to be in a disabled state in the first sleep mode.
  • the one or more first wake-up circuits correspond to the plurality of first receivers.
  • At least one of the one or more first wake-up circuits is configured to be in an enabled state in the first sleep mode.
  • the number of the at least one first wake-up circuit is less than the number of the plurality of first receivers.
  • the at least one wake-up circuit is further configured to cause at least one first receiver of the plurality of first receivers to be enabled in response to receiving the first wake-up signal.
  • the second chip includes a plurality of second receivers configured to be disabled in the second sleep mode.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the total power consumption of the first chip in the sleep mode is the product of the power consumption of the wake-up circuits and the number of all wake-up circuits.
  • the control method according to the sixth aspect enables less wake-up circuits by disabling a part of wake-up circuits, that is, the number of enabled wake-up circuits is reduced compared to the number of all wake-up circuits. Reduce the total power consumption of the first chip in sleep mode.
  • the at least one wake-up circuit since at least one wake-up circuit is still enabled in the sleep mode, it can be ensured that the receiver of the first chip is normally woken up.
  • the at least one first wake-up circuit includes only one first wake-up circuit. By enabling only one wake-up circuit in sleep mode, the power consumption of the first chip in sleep mode can be greatly reduced, while still keeping the receiver able to wake up for normal operation.
  • the integrated circuit chip according to the present disclosure does not involve reducing the size of the chip, the cost of the chip is not significantly increased, thereby solving the problem of significantly increasing the cost in the background art.
  • the second chip further includes one or more second wake-up circuits. At least one of the one or more second wake-up circuits is configured to be in an enabled state in the second sleep mode.
  • the power consumption of the second chip in the second sleep mode can be reduced.
  • the power consumption of the first chip in sleep mode can be greatly reduced, while still keeping the receiver able to wake up for normal operation.
  • the power consumption of the first chip in the sleep mode can be greatly reduced, while still keeping the receiver able to be woken up for normal operation, And it can also speed up the response speed of wake-up.
  • the first chip is configured to enable the first transmitter in the first chip to transmit the second wake-up signal to the second wake-up signal in response to the at least one first wake-up circuit receiving the first wake-up signal chip's second receiver.
  • the second chip is different from the first chip.
  • the second chip further includes one or more second wake-up circuits.
  • the one or more second wake-up circuits are configured to be all disabled in the second sleep mode. By disabling all wake-up circuits of the second chip, the sleep power consumption of the second chip in the second sleep mode can be greatly reduced.
  • the first chip is configured to transmit first mode data from the first transmitter of the first chip to the second receiver of the second chip before entering the sleep mode, the first mode data representing the first The supported sleep modes of the chip.
  • the second chip is configured to cause the transmitter of the second chip to transmit second mode data to the first receiver of the first chip, the second mode data representing a supported sleep mode of the second chip.
  • the first chip is configured to determine a sleep mode to be used by the first chip based on the sleep mode and second mode data supported by the first chip.
  • the second chip is configured to determine a sleep mode to be used by the second chip based on the sleep modes supported by the second chip and the first mode data.
  • the first chip is configured to receive, by the plurality of first receivers of the first chip, wake-up circuit specification data from the plurality of second transmitters of the second chip before entering the sleep mode; and based on The wake-up circuit designates data identifying at least one first wake-up circuit in the first chip to be enabled in the first sleep mode.
  • An electronic device includes a circuit board and an integrated circuit system according to the sixth aspect.
  • the integrated circuit system is arranged on the circuit board.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the total power consumption of the first chip in the sleep mode is the product of the power consumption of the wake-up circuits and the number of all wake-up circuits.
  • the control method according to the seventh aspect enables fewer wake-up circuits by disabling a portion of the wake-up circuits, that is, the number of enabled wake-up circuits is reduced compared to the number of all wake-up circuits. Reduce the total power consumption of the first chip in sleep mode. On the other hand, since at least one wake-up circuit is still enabled in the sleep mode, it can be ensured that the receiver of the first chip is normally woken up. In addition, since the integrated circuit chip according to the present disclosure does not involve reducing the size of the chip, the cost of the chip is not significantly increased, thereby solving the problem of significantly increasing the cost in the background art.
  • a method for controlling a first chip includes disabling the plurality of first receivers in the first chip in a first sleep mode.
  • the method also includes enabling at least one of the one or more first wake-up circuits in the first sleep mode.
  • the one or more first wake-up circuits correspond to the plurality of first receivers.
  • the number of the at least one first wake-up circuit is less than the number of the plurality of first receivers.
  • the method further includes enabling at least one first receiver of the plurality of first receivers in response to the at least one first wakeup circuit receiving the first wakeup signal.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the control method according to the eighth aspect enables less wake-up circuits by disabling a part of wake-up circuits, that is, the number of enabled wake-up circuits is reduced compared to the number of all wake-up circuits, and can Reduce the total power consumption of the first chip in sleep mode.
  • the control method according to the eighth aspect since at least one wake-up circuit is still enabled in the sleep mode, it can be ensured that the receiver of the first chip is normally woken up.
  • the integrated circuit chip according to the present disclosure does not involve reducing the size of the chip, the cost of the chip is not significantly increased, thereby solving the problem of significantly increasing the cost in the background art.
  • a method for controlling a second chip includes disabling a plurality of second receivers in the second chip and at least one of the one or more second wake-up circuits in the second chip in a disabled state in a second sleep mode, one or more The second wake-up circuits correspond to the plurality of second receivers.
  • the method also includes, in response to entering the operating mode, sending a first wake-up signal to a first chip, the second chip being different from the first chip.
  • the method further includes enabling at least one second receiver of the plurality of second receivers of the second chip at a predetermined time after sending the wake-up signal.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the total power consumption of the first chip in the sleep mode is the product of the power consumption of the wake-up circuits and the number of all wake-up circuits.
  • the control method according to the ninth aspect can reduce the total power consumption of the second chip in the sleep mode by disabling all wake-up circuits, that is, the number of enabled wake-up circuits is actually zero.
  • the integrated circuit chip according to the present disclosure does not involve reducing the size of the chip, the cost of the chip is not significantly increased, thereby solving the problem of significantly increasing the cost in the background art.
  • a method for controlling a chip includes disabling the plurality of first receivers in the first chip in a first sleep mode.
  • the method also includes disabling the plurality of second receivers in the second chip in a second sleep mode.
  • the second chip is different from the first chip.
  • the method further includes enabling at least one of the one or more first wake-up circuits in the first chip in an enabled state in the first sleep mode; and receiving the first wake-up in response to the at least one first wake-up circuit
  • the signal enables at least one first receiver of the plurality of first receivers.
  • the one or more first wake-up circuits correspond to the plurality of first receivers.
  • the number of the at least one first wake-up circuit is less than the number of the plurality of first receivers.
  • Each wake-up circuit that is enabled in sleep mode still needs to be powered up and consume power in order to keep receiving a wake-up signal at any time.
  • the total power consumption of the first chip in the sleep mode is the product of the power consumption of the wake-up circuits and the number of all wake-up circuits.
  • the control method according to the tenth aspect enables less wake-up circuits by disabling a part of wake-up circuits, that is, the number of enabled wake-up circuits is reduced compared to the number of all wake-up circuits. Reduce the total power consumption of the first chip in sleep mode.
  • the integrated circuit chip according to the present disclosure does not involve reducing the size of the chip, the cost of the chip is not significantly increased, thereby solving the problem of significantly increasing the cost in the background art.
  • Fig. 1 shows a schematic block diagram of a low power consumption system
  • FIG. 2 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure
  • FIG. 3 shows a simplified block diagram of a low power consumption system according to one embodiment of the present disclosure
  • FIG. 4 shows a schematic block diagram of a low power consumption system according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic block diagram of a low power consumption system according to another embodiment of the present disclosure
  • FIG. 6 shows a flowchart of an example process according to one embodiment of the present disclosure
  • FIG. 7 shows a flowchart of an example process according to another embodiment of the present disclosure.
  • Figure 8 shows a flowchart of an example method according to one embodiment of the present disclosure
  • FIG. 9 shows a flowchart of an example method according to another embodiment of the present disclosure.
  • FIG. 10 shows a flowchart of an example method according to another embodiment of the present disclosure.
  • FIG. 11 shows a circuit schematic diagram of a wake-up circuit according to one embodiment of the present disclosure.
  • the term “comprising” and the like should be understood as open-ended inclusion, ie, “including but not limited to”.
  • the term “based on” should be understood as “based at least in part on”.
  • the terms “one embodiment” or “the embodiment” should be understood to mean “at least one embodiment”.
  • the terms “first”, “second”, etc. may refer to different or the same objects.
  • the term “and/or” means at least one of the two items to which it is associated. For example "A and/or B" means A, B, or A and B. Other explicit and implicit definitions may also be included below.
  • the multiple chips communicate with each other to transfer data and commands.
  • the transmission of these data and commands consumes a lot of energy.
  • these chips don't transmit data all the time. Therefore, it is desirable to put these chips to sleep to reduce power consumption when they are not working.
  • the chip In order to be able to wake up from sleep mode, the chip usually has a wake-up circuit (squelch circuit) that keeps working in sleep mode.
  • the wake-up circuit can detect the wake-up signal transmitted from the outside in the sleep mode.
  • Each transceiver channel includes a receiver (RX) and a transmitter (TX).
  • RX receiver
  • TX transmitter
  • sleep mode the transmitter and/or receiver may be disabled, eg powered down, to reduce power consumption. But in sleep mode, the wake-up circuitry in each receiver remains active.
  • the wake-up circuit receives a wake-up signal from the outside, the receiver and the transmitter are returned from the sleep mode to the working mode.
  • the receiver and transmitter can thus operate normally to transmit data and/or commands.
  • FIG. 1 shows a schematic block diagram of a low power consumption system.
  • the low power consumption system operates according to some protocol or standard, for example.
  • the low power consumption system includes a first chip 10 and a second chip 20 that communicate with each other.
  • the first chip 10 is, for example, a hard disk controller
  • the second chip 20 is a processor.
  • the first chip 10 includes a first controller 110 , a first transceiving channel 111 , a second transceiving channel 112 and a third transceiving channel 113 .
  • the first controller 110 communicates with the first transceiving channel 111 , the second transceiving channel 112 and the third transceiving channel 113 respectively to transmit signals.
  • the first transceiver channel 111 includes a first transmitter TX11 and a first receiver RX11
  • the second transceiver channel 112 includes a first transmitter TX12 and a first receiver RX12
  • the third transceiver channel 113 includes a first transmitter TX13 and a first receiver. Receiver RX13.
  • the second chip 20 includes a second controller 210 , a first transceiving channel 211 , a second transceiving channel 212 and a third transceiving channel 213 .
  • the second controller 110 communicates with the first transceiving channel 211 , the second transceiving channel 212 and the third transceiving channel 213 respectively to transmit signals.
  • the first transceiver channel 211 includes a second transmitter TX21 and a second receiver RX21
  • the second transceiver channel 212 includes a second transmitter TX22 and a second receiver RX22
  • the third transceiver channel 213 includes a second transmitter TX23 and a second transceiver Receiver RX23.
  • the first transmitter TX11 of the first chip 10 transmits data to the second receiver RX21 of the second chip, and the first receiver RX11 of the first chip 10 receives data from the second transmitter TX21 of the second chip data, as indicated by the arrows in the figure.
  • the second transceiver channel 112 of the first chip 10 communicates with the second transceiver channel 212 of the second chip 20
  • the third transceiver channel 113 of the first chip 10 communicates with the third transceiver channel 213 of the second chip 20 , As shown by the arrow in the figure.
  • the physical layer (PHY) of the first chip 10 and the PHY of the second chip 20 communicate with each other, eg, to transmit data, eg, according to the SerDes protocol. It can be understood that the present disclosure may also be applicable to application scenarios according to other protocols.
  • the first receiver RX11 , the first receiver RX12 and the first receiver RX13 of the first chip 10 further include a first wake-up circuit S11 , a first wake-up circuit S12 and a first wake-up circuit S13 respectively.
  • the second receiver RX21 , the second receiver RX22 and the second receiver RX23 of the second chip 20 also include a second wake-up circuit S21 , a second wake-up circuit S22 and a second wake-up circuit S23 , respectively.
  • each chip has three transceiver channels, this is for illustration only and does not limit the scope of the present disclosure.
  • the first chip 10 and the second chip 20 may respectively have more or less transceiving channels, eg, 8 or 16 transceiving channels.
  • the second chip 20 may determine the transceiving between the first chip 10 and the second chip 20 Channels can enter sleep mode.
  • the second chip 20 may send a sleep request to the first chip 10 through any transceiver channel.
  • the first chip 10 may send confirmation information for confirming the sleep to the second chip 20 through any transceiver channel.
  • the first chip 10 enters a first sleep mode of the first chip 10 and disables the three receivers and/or transmitters while transmitting or at a first predetermined period of time after completing the transmission.
  • a circuit may be that the circuit is powered off or at least disables the function of the circuit.
  • disabling the receiver means that the receiver's circuit modules are powered down here, or even though the receiver is powered but its receive functional modules are here disabled to reduce power consumption.
  • an "enable” circuit means that the circuit is powered on to operate normally, or to restore its circuit functionality from an already powered state.
  • enabling the receiver means that the receiver's circuit block is powered here, or if the receiver is powered on (without receive capability), but it is enabled, it means that the receiver resumes receive functionality and is ready to receive data .
  • the receivers and transmitters in the three transceiver channels are kept disabled, eg powered off, but the wake-up circuits in the three receivers are kept enabled, eg powered, In order to receive a wake-up signal for waking up the first chip 10 in the first sleep mode.
  • the wake-up circuit even if the wake-up circuit is located in the receiver, when the receiver is disabled, it does not mean that the wake-up circuit in the receiver is disabled.
  • the receiver in the chip is disabled, even if the one or more wake-up circuits are located in the receiver, at least one of the one or more wake-up circuits remains enabled to wake up the receiver.
  • the second chip 20 enters the second sleep mode of the second chip 20 when receiving the confirmation information or at a second predetermined period after receiving the confirmation information.
  • the serial numbers in the first sleep mode and the second sleep mode are only used to distinguish that the sleep modes belong to different chips.
  • the first predetermined period of time and the second predetermined period of time may be the same or different.
  • the sleep mode may be further subdivided within each chip.
  • the receiver of the first chip 10 has the first receiver sleep mode
  • the transmitter of the first chip 10 has the first transmitter sleep mode. What sleep modes have in common is that a circuit can suspend the functioning of the circuit's functions while in sleep mode. For example, a transmitter in sleep mode will stop transmitting, whether or not the transmitter is powered in sleep mode.
  • the receivers and transmitters in all three transceiver channels remain disabled, eg, powered down, but the wake-up circuits in all three receivers remain enabled, eg Powered to receive a wake-up signal for waking up the second chip 20 in the second sleep mode.
  • the wake-up circuits in all three receivers remain enabled, eg Powered to receive a wake-up signal for waking up the second chip 20 in the second sleep mode.
  • the power consumed by the wake-up circuit in the sleep mode is much smaller than the power consumed by the receiver and the transmitter, so the power consumption of the first chip 10 and the second chip 20 can be significantly saved. Accordingly, the power consumption of a system including the first chip 10 and the second chip 20 (eg, the integrated circuit assembly 30 and the electronic device 100 ) can also be significantly saved.
  • the first chip 10 may disable all its circuits except the wake-up circuit in the first sleep mode to minimize the sleep power consumption.
  • the first chip 10 may keep some circuits disabled in the first sleep mode, for example, only keep the transceiver channel disabled, and keep other circuit parts (eg, other wake-up circuits that communicate with other chips or circuits) and transceivers. The wake-up circuit in the channel is enabled.
  • the second chip 20 can also disable all its circuits except the wake-up circuit, or disable some circuits including the transceiver channel.
  • the first chip 10 and the second chip 20 may not enter the sleep mode at the same time. For example, when the first chip 10 enters the sleep mode, the second chip 20 may remain in the working mode to perform other processing, and vice versa.
  • the first chip 10 and the second chip 20 may also have a low-speed mode and a high-speed mode. In the low-speed mode, only part of the transceiver channels between the first chip 10 and the second chip 20 are enabled. In the high speed mode, most or all of the transceiver channels of the first chip 10 and the second chip 20 are enabled. In other words, the first chip 10 and the second chip 20 can selectively enable transceiving channels according to service requirements in the working mode. In active mode, each wake-up circuit can be fully enabled, fully disabled, or selectively enabled. The embodiments of the present disclosure do not limit this. It can be seen that, in the exemplary embodiment of FIG. 1 , for N transceiver channels, the first chip 10 and the second chip 20 have 2N wake-up circuits enabled during the sleep mode, where N represents an integer greater than 0.
  • the power consumption of the chip can be significantly reduced by turning off or disabling the transceiver channels during sleep mode while leaving only the 2N wake-up circuits in the transceiver channels enabled, it is still desirable to further reduce the chip's power consumption for battery-operated electronic devices.
  • power consumption The power consumption of the wake-up circuit is much smaller than the power consumption of the receiver, so in electronic equipment powered by commercial power, the power consumption of the wake-up circuit is often negligible.
  • the receiver has a wake-up circuit, and each wake-up circuit needs to be enabled in the sleep mode. Therefore, in some solutions, designers often reduce the power consumption of the chip from the perspective of optimizing the design of each circuit of the chip. However, for some electronic devices, it is desirable to further reduce the power consumption of the chip, thereby reducing the overall power consumption of the electronic device.
  • a low-power consumption chip and a system including the low-power consumption chip are proposed.
  • the low-power chip further reduces the number of wake-up circuits in sleep mode, and wakes up one or more transceiver channels by using the reduced wake-up circuits.
  • the power consumption of the chip can be further reduced, and the power consumption of the system including the first chip and the second chip can be correspondingly reduced.
  • the integrated circuit chip according to the embodiments of the present disclosure does not need to reduce the size of the chip, the cost of the chip, such as design and manufacturing costs, is not significantly increased.
  • FIG. 2 shows a schematic diagram of an electronic device 200 according to one embodiment of the present disclosure.
  • the electronic device 200 is, for example, a smartphone.
  • Other electronic devices are also possible, such as computers, tablet computers or other smart terminal devices.
  • Electronic device 200 includes integrated circuit assembly 30 as well as other components not shown, such as other chips, sensors, and the like.
  • Integrated circuit assembly 30 may be formed as at least part of an integrated circuit system.
  • integrated circuit assembly 30 may include multiple packaged chips on a circuit board such as a printed circuit board (PCB) or flexible circuit board (FPC). One or more chips may be packaged inside each packaged chip.
  • the integrated circuit assembly 30 itself is a single chip, eg, a SiP chip with multiple chips integrated therein. The present disclosure does not make any limitation on the form of the integrated circuit assembly 30 herein.
  • the integrated circuit assembly 30 may be, for example, a SiP chip or a printed circuit board with integrated chips.
  • the integrated circuit assembly 30 may include a first chip 10 and a second chip 20 .
  • the integrated circuit assembly 30 may also include other chips or components not shown.
  • the first chip 10 may include N transceiver channels for communicating with the second chip 20 , where N represents a natural number greater than 0.
  • the second chip 20 may also include N transceiver channels for communicating with the first chip 10 . It can be understood that the first chip 10 and the second chip 20 may also respectively have other transceiver channels for communicating with other chips or components. This disclosure does not make any limitation in this regard.
  • FIG. 4 shows a schematic block diagram of a low power consumption system according to an embodiment of the present disclosure. Similar to FIG. 1 , in this exemplary embodiment, the low power consumption system includes a first chip 10 and a second chip 20 .
  • the hardware configuration of the low-power consumption system in FIG. 4 is the same as or similar to that of the low-power consumption system in FIG. 1 . Therefore, various aspects described in relation to FIG. 1 can be applied to the low-power consumption system in FIG. 4 , and details are not repeated here. .
  • the first chip 10 is, for example, a hard disk controller, and the second chip is a processor.
  • the first chip 10 includes a first controller 110 , a first transceiving channel 111 , a second transceiving channel 112 and a third transceiving channel 113 .
  • the first controller 110 communicates with the first transceiving channel 111 , the second transceiving channel 112 and the third transceiving channel 113 respectively to transmit signals.
  • the first transceiver channel 111 includes a first transmitter TX11 and a first receiver RX11
  • the second transceiver channel 112 includes a first transmitter TX12 and a first receiver RX12
  • the third transceiver channel 113 includes a first transmitter TX13 and a first receiver. Receiver RX13.
  • the second chip 20 includes a second controller 210 , a first transceiving channel 211 , a second transceiving channel 212 and a third transceiving channel 213 .
  • the second controller 110 communicates with the first transceiving channel 211 , the second transceiving channel 212 and the third transceiving channel 213 respectively to transmit signals.
  • the first transceiver channel 211 includes a second transmitter TX21 and a second receiver RX21
  • the second transceiver channel 212 includes a second transmitter TX22 and a second receiver RX22
  • the third transceiver channel 213 includes a second transmitter TX23 and a second transceiver Receiver RX23.
  • each chip has three transceiving channels, this is for illustration only and does not limit the scope of the present disclosure.
  • the first chip 10 and the second chip 20 may respectively have more or less transceiving channels, eg, 8 or 16 transceiving channels.
  • the first receiver RX11 , the first receiver RX12 and the first receiver RX13 of the first chip 10 further include a first wake-up circuit S11 , a first wake-up circuit S12 and a first wake-up circuit S13 , respectively.
  • the second receiver RX21 , the second receiver RX22 and the second receiver RX23 of the second chip 20 also include a second wake-up circuit S21 , a second wake-up circuit S22 and a second wake-up circuit S23 , respectively.
  • the second chip 20 when the second chip 20 detects that the transmission and reception channels of the second chip 20 and the first chip 10 do not transmit data and/or instructions to each other for a predetermined period of time, the second chip 20 determines that the second chip 20 can enter the sleep mode model.
  • the controller 210 of the second chip 20 sends a sleep request to the first receiver of the first chip 10 via the second transmitter of the second chip 20.
  • the controller 110 of the first chip 10 After receiving the sleep request, sends the sleep request via the first receiver
  • the first transmitter of the chip 10 replies with confirmation information to the second receiver of the second chip 20 .
  • the controller 110 of the first chip 10 then disables, eg, powers down, the transmitters and receivers in the respective transceiver channels of the first chip 10 to reduce power consumption.
  • the controller 110 of the first chip 10 also causes some wake-up circuits to be disabled in the first sleep mode.
  • the first wake-up circuit S11 in the first receiver RX11 is in an enabled state (shown with shading), the first wake-up circuit S12 and the first wake-up circuit S12 in the first receiver RX12 and the first receiver RX13 A wake-up circuit S13 is disabled (shown in blank).
  • the first wake-up circuit that is enabled in the sleep mode it may be enabled before entering the sleep mode, or when entering the sleep mode, or after entering the sleep mode. The present disclosure does not limit this. Compared with the example shown in FIG.
  • the The embodiment further reduces the power consumption of the first chip 10 in the first sleep mode, for example, the power consumption of the first wake-up circuit S12 and the first wake-up circuit S13 is saved. This is especially true for chips with multiple transceiver channels (eg, 16 channels, 16 wake-up circuits) and battery-powered electronic devices that include the chip. For example, the total power consumption of the N wake-up circuits during the first sleep mode is reduced to about 1/N, eg, 1/16.
  • at least one wake-up circuit is still enabled to receive a wake-up signal in the embodiment of FIG. 4, it may still be ensured that the first receiver and the first transmitter in the first chip can be woken up to enter normal operating state.
  • the number of wake-up circuits used in the first sleep mode of the first chip 10 may also be increased.
  • the first wake-up circuit S11 and the first wake-up circuit S12 may be set to an enabled state in the first sleep mode. In this way, it is possible to avoid the situation that each transceiver channel of the first chip 10 cannot be woken up due to the failure of a certain wake-up circuit due to various reasons.
  • a wake-up circuit for directly waking up the transceiver channel can also be set inside the transceiver channel to wake up the transceiver quickly, without the need for the controller to wake up the transceiver after receiving the wake-up circuit. After the wake-up signal, the transceiver channel is woken up indirectly.
  • the controller 210 of the second chip 20 After receiving the confirmation information, the controller 210 of the second chip 20 makes the receivers and transmitters in each transceiving channel in a disabled state, for example, power off them, so as to reduce power consumption.
  • the controller 210 of the second chip 20 also causes some wake-up circuits to be disabled in the second sleep mode. For example, in FIG. 4 , only the second wake-up circuit S21 in the second receiver RX21 is in an enabled state (shown with shading), the second wake-up circuit S22 in the second receiver RX22 and the second receiver RX23 and the first Two wake-up circuits S23 are disabled (shown in blank).
  • the second wake-up circuit that is enabled in the sleep mode it may be enabled before entering the sleep mode, or when entering the sleep mode or after entering the sleep mode.
  • the embodiment of FIG. 4 further reduces the power consumption of the second chip 20 in the second sleep mode, for example, the power consumption of the second wake-up circuit S22 and the second wake-up circuit S23 is saved. This is especially true for chips with multiple transceiver channels (eg, 16 transceiver channels, 16 wake-up circuits) and battery-powered electronic devices that include the chip.
  • the total power consumption of the N wake-up circuits during the second sleep mode is reduced to about 1/N, eg, 1/16.
  • the power consumption of the wake-up circuit of the integrated circuit system can be reduced from 2N*P to 2P , for example, from 32P of 16 transceiver channels to 2P.
  • the second chip 20 can also increase the number of wake-up circuits in the second sleep mode.
  • the second wake-up circuit S21 and the second wake-up circuit S22 may be in an enabled state in the second sleep mode.
  • both the first wake-up circuit and the second wake-up circuit are located within the receiver.
  • the power consumption of the first chip in sleep mode can be greatly reduced, while still keeping the receiver able to wake up for normal operation.
  • a wake-up circuit located within the receiver can directly trigger on a low dropout linear regulator (LDO) switch in the receiver without going through the controller to enable the receiver is enabled. In this way, the response speed of the receiver being woken up can be accelerated.
  • LDO low dropout linear regulator
  • each transceiver channel in the first chip 10 and the second chip 20 is disabled, for example, powered off. , while each chip leaves only one or more wake-up circuits enabled.
  • the first chip 10 and the second chip 20 may negotiate through communication which wake-up circuit or circuits to wake up in the upcoming first and second sleep modes. circuit is enabled. In this way, the flexibility of configuration can be increased, and other wake-up circuits can be used to operate normally when a certain wake-up circuit fails.
  • the first wake-up circuit S11 of the first chip 10 and the second wake-up circuit S21 of the second chip 20 may be the wake-up circuits used in the first sleep mode and the second sleep mode by default without negotiation. In this way, the communication cost and communication power consumption can be reduced, and the response speed of the system going into sleep can be increased.
  • the transceiver channel of the first chip 10 is dormant, while the transceiver channel of the second chip 20 is still in a working state.
  • some of the transceiver channels of the first chip 10 and the second chip 20 are dormant, while some of the transceiver channels are still in a normal working state.
  • the receiver and transmitter of the first chip 10 are disabled, while the receiver of the second chip 20 is disabled but at least one transmitter of the second chip 20 is enabled.
  • the controller 210 when the second chip 20 in the second sleep mode needs to wake up the first chip 10 , the controller 210 enables the second transmitter TX21 and causes the second transmitter TX21 to wake up the first chip 10
  • the circuit S11 sends a first wake-up signal. After the first wake-up circuit S11 in the enabled state in the first sleep mode receives the first wake-up signal, the first wake-up circuit S11 notifies the controller 110 .
  • the controller 110 then enables at least one receiver.
  • the controller 110 enables the first receiver RX11 and the first transmitter TX11 of the first transceiving channel 111 .
  • the controller 110 may also enable receivers and transmitters in the second transceiving channel 112 and the third transceiving channel 113 .
  • the controller 110 enables the first transmitter TX11 to transmit the second wake-up signal to the first receiver S21 of the second chip 20 .
  • the second wake-up circuit S21 notifies the controller 210 after the second wake-up signal is received by the second wake-up circuit S21 in the enabled state in the second sleep mode.
  • the controller 210 then enables at least one receiver.
  • the controller 210 enables the second receiver RX21 of the first transceiving channel 111 .
  • the controller 210 may also enable receivers and transmitters in the second transceiving channel 212 and the third transceiving channel 213 .
  • the first chip 10 may have a timer or a counter, such as in the controller 110, for timing. Alternatively, the first chip 10 may be clocked using a clock signal from the outside. After the first transmitter TX11 of the first chip 10 is enabled for a first predetermined period, both the first chip 10 and the second chip 20 are in the operating mode, and the first transmitter TX11 of the first chip 10 starts to communicate with the second chip of the second receiver RX21 to communicate. By setting the predetermined period of time, it can be ensured that the first chip can operate at the correct time and not operate incorrectly, such as losing data and/or commands, because the second chip is not yet ready.
  • first chip 10 and the second chip 20 may further determine to be in the first sleep mode and the second sleep mode based on data specified by the wake-up circuit. Which of the first wake-up circuits and the second wake-up circuit(s) are enabled.
  • any receiver of the first chip 10 before the first chip 10 enters the first sleep mode, can receive data specified by the wake-up circuit from the second chip 20, and the data indicates that the first chip 10 is in the first sleep mode.
  • the controller 110 of the first chip 10 can then reply with a confirmation message to the second chip 20 to confirm that the first wake-up circuit will be enabled.
  • the first chip 10 may not reply the confirmation information, but make the first wake-up circuit in the enabled state in the first sleep mode.
  • the first chip 10 may not reply the confirmation information, but make the first wake-up circuit in the enabled state in the first sleep mode.
  • chips typically have one wake-up circuit in each receiver, and each wake-up circuit is enabled in sleep mode. Therefore, due to hardware, software or protocol reasons, some chips may not be able to support low power sleep in sleep mode as described above with respect to FIG. 4 . To this end, in some embodiments, before the chips enter the sleep mode, the two chips may communicate with the sleep scheme supported by the two chips, so as to determine the sleep mode to be used.
  • the first chip 10 and the second chip 20 enter the first sleep mode and the second sleep mode respectively for description.
  • the first chip 10 sends the first mode data indicating the sleep scheme supported by the first chip 10 to the second chip 20.
  • the second chip 20 may determine the sleep mode to be used by the second chip 20 based on the second sleep mode supported by the second chip 20 and the first mode data.
  • the pattern data may be characterized by data bits reserved in predetermined fields of the data set sent by the first chip 10 to the second chip 20 . Such predetermined data bits may be specified in the data transmission protocol.
  • the sleep modes include three sleep schemes
  • three bits of data may be used to characterize the supported sleep modes. For example, "001" means only the first scheme is supported, "010” means only the second scheme is supported, "100” means only the third scheme is supported, and "111" means all three schemes are supported. It can be understood that there may be other representations of pattern data, such as introducing more data bits or data patterns to represent more sleep schemes.
  • the mode data can also be negotiated before sleep, for example, by sending a request and replying a confirmation message to confirm the sleep mode used.
  • the second chip 20 sends the second mode data to the first chip 10 indicating the second sleep mode supported by the second chip 20 .
  • the first chip 10 may then determine the sleep mode to be used by the first chip 10 based on the first sleep mode and second mode data supported by the first chip 10 . Subsequently, the first chip 10 and the second chip 20 may enter the sleep mode as described above, respectively.
  • the first mode data and the second mode data may be encrypted.
  • the sleep request, confirmation information, and wake-up circuit designation data described above may also be encrypted. After receiving the encrypted data, the receiver can decrypt it to obtain the original data. It will be appreciated that encryption and decryption are not required in some embodiments of the present disclosure.
  • the above-mentioned communication process of the sleep mode supported by the first chip 10 and the second chip 20 may be performed when the system is powered on.
  • the communication process of the above supported sleep mode may be performed before sending the sleep request, or at the same time as sending the sleep request and replying confirmation information, or after replying to confirm the rest but before entering the sleep mode. The present disclosure does not limit this.
  • the sleep mode supported by the chip includes a first scheme, a second scheme and a third scheme.
  • each wake-up circuit of the chip is enabled in the sleep mode.
  • the second scheme only one wake-up circuit in each chip is enabled in sleep mode, and the remaining wake-up circuits are disabled in sleep mode.
  • one of the first and second chips operates as a master and the other operates as a slave, and only one wake-up circuit of the slave is enabled in sleep mode, while the master operates All wake-up circuits of the device and other wake-up circuits of the slave device are disabled.
  • the third solution will be specifically described below with reference to FIG. 5 .
  • the first chip and the second chip can sleep in a suitable sleep scheme, and it can be ensured that the transceiver channels in the chips can be woken up correctly. It will be appreciated that other schemes are also supported, such as each chip having two wake-up circuits enabled in sleep mode, while other wake-up circuits are disabled.
  • FIG. 5 shows a schematic block diagram of a low power consumption system according to another embodiment of the present disclosure.
  • the low power consumption system of FIG. 5 has a similar configuration to the low power consumption system of FIG. 4 , so the same or similarities are not repeated here, and various aspects described above with respect to FIG. 4 can be applied to the system of FIG. 5 .
  • the difference between FIG. 5 and FIG. 4 is that the first chip 11 has only one first wake-up circuit S13, and the second chip 21 also has only one second wake-up circuit S23.
  • the first wake-up circuit S13 is independent of the first receiver, and the second wake-up circuit S23 is independent of the second receiver. In other words, the first wake-up circuit S13 corresponds to and is actually shared by the three first receivers.
  • the second wake-up circuit S23 also corresponds to and is actually shared by the three second receivers.
  • the first wake-up circuit S13 and the second wake-up circuit S23 are shown in FIG. 5 as being located outside the receiver, the first and second wake-up circuits S13 and S23 may also be located within the receiver in some embodiments.
  • the first wake-up circuit S13 is located in the first receiver RX13, and the first wake-up circuit S13 is connected to the first receivers RX11 and RX12 through signal wires to wake them up.
  • the second wake-up circuit S23 is located in the second receiver RX23, and the second wake-up circuit S23 is connected to the second receivers RX21 and RX22 through signal wiring to wake them up.
  • the second chip 21 operates as a master device, and the first chip 22 operates as a slave device.
  • the third hibernation scheme mentioned above is described below.
  • the second chip 21 may send a sleep request to the first chip 11 .
  • the first chip 11 sends confirmation information to the second chip 21 .
  • the first chip 11 enters the first sleep mode, and in the first sleep mode, the first receivers RX11 , RX12 and RX13 and the first transmitters TX11 , TX12 and TX13 are in a disabled state.
  • the first chip enables the first wake-up circuit S13 in the first sleep mode.
  • the second wake-up circuit S23 of the second chip 21 may be in a disabled state in the second sleep mode because it does not need to receive a wake-up signal from the first chip 11 . In this way, in the sleep mode of the first chip 11 and the second chip 21 , only one wake-up circuit of the two chips in the integrated circuit system is in an enabled state.
  • the second chip 21 enables at least one second receiver among the plurality of second receivers of the second chip 21 at a predetermined time after sending the wake-up signal. Additionally, the second chip 21 may also enable all receivers and transmitters in the plurality of transceiving channels for normal operation. By setting the predetermined time, it can be determined that the first chip 11 is in a normal operating state at this time, without receiving a wake-up signal from the first chip to determine that the first chip will be in a normal operating state. Compared with the embodiment of FIG. 4 , the power consumption of the wake-up circuit in the sleep mode can be further reduced by half. Compared with the example of FIG. 1 , the total power consumption of the wake-up circuit in the sleep mode is actually only about 1/2N, eg, 1/32.
  • the power consumption in the sleep mode of the chip can be greatly reduced.
  • the first chip 11 and the second chip 21 may negotiate a sleep scheme to be used in the sleep mode, for example, use a third sleep scheme, before entering the respective sleep modes.
  • FIG. 6 shows a flowchart of an example process 600 according to one embodiment of the present disclosure. It will be appreciated that various aspects described above with respect to FIGS. 1 , 4 and 5 may be selectively applied to process 600 .
  • the second chip 20 sends second hibernation data to the first die 10 to inform the first chip 10 of the second mode data representing the hibernation scheme supported by the second chip 20 .
  • the first chip 10 determines a sleep mode to be used based on the second mode data and the sleep modes supported by the first chip.
  • the first chip 10 sends the second chip 20 first mode data representing the sleep scheme supported by the first chip 10 to the second chip 20 .
  • the second chip 20 determines a sleep mode to be used based on the first mode data and the sleep modes supported by the second chip 20 at 625 .
  • 610, 613, 620 and 625 may be omitted, eg the chip may default to a certain sleep mode without negotiation.
  • the second chip 20 sends a sleep request to the first chip 10 .
  • the wake-up circuit specification data may also be sent together with other possible sleep-related data, such as the selection of a sleep scheme.
  • the first chip 10 replies with a confirmation message to the second chip.
  • wake-up circuit designation data and other possible sleep-related data may also be sent together.
  • the first chip 10 may selectively disable the first receiver and the first transmitter in the transceiving channel and the first wake-up circuit corresponding to the first receiver at 643 , as described above.
  • the second chip 20 After receiving the confirmation information, the second chip 20 selectively disables the second receiver and the second transmitter in the transceiving channel and the second wake-up circuit corresponding to the receiver at 645 . Thereafter, the first chip 10 enters the first sleep mode, and the second chip 20 enters the second sleep mode. In another embodiment, the second chip 20 may not enter the second sleep mode, but continue to work normally.
  • the second chip 20 sends a first wake-up signal to the wake-up circuit of the first chip 10 .
  • the first chip 10 selectively wakes up at least one of the first receiver and the first transmitter in the transceiving channel at 653 .
  • the first wake-up circuit may first inform the controller of the first chip 10, and the controller then enables at least one of the first receiver and the first transmitter.
  • the first wake-up circuit may enable the first receiver and the first transmitter corresponding thereto or related thereto by direct triggering.
  • the first chip 10 sends a second wake-up signal to the wake-up circuit of the second chip 20 .
  • the first chip 10 selectively wakes up at 665 at least one second receiver in the transceiving channel.
  • the second wake-up circuit may first inform the controller of the second chip 20, and the controller then enables the at least one second receiver.
  • the second wake-up circuit may enable a second receiver corresponding to or associated with it by direct triggering. Additionally, the second transmitter may also be enabled based on the second wake-up signal.
  • FIG. 7 shows a flowchart of an example process 700 according to another embodiment of the present disclosure. It will be appreciated that various aspects described above with respect to FIGS. 1 , 4 , and 5 may be selectively applied to process 700 .
  • the second chip 20 operates as a master and the first chip 10 operates as a slave.
  • the second chip 20 sends a sleep request to the first chip 10 .
  • wake-up circuit specific data and other possible sleep-related data may also be sent together.
  • the first chip 10 replies with a confirmation message to the second chip.
  • wake-up circuit specific data and other possible sleep-related data may also be sent together.
  • the first chip 10 may selectively disable the first receiver and the first transmitter in the transceiving channel and the first wake-up circuit corresponding to the first receiver at 643, as described above.
  • the second chip 20 selectively disables the second receiver and the second transmitter in the transceiving channel and the second wake-up circuit corresponding to the receiver at 645 .
  • the first chip 10 enters the first sleep mode
  • the second chip 20 enters the second sleep mode.
  • the second chip 20 may not enter the second sleep mode, but continue to work normally.
  • the second chip 20 sends a first wake-up signal to the wake-up circuit of the first chip 10 .
  • the first chip 10 After the first wake-up circuit of the first chip 10 receives the first wake-up signal, the first chip 10 selectively wakes up at least one of the first receiver and the first transmitter in the transceiving channel at 653 .
  • the second chip 20 determines to enable at least one second receiver of the plurality of second receivers of the second chip 20 at a predetermined time after sending the first wake-up signal. Additionally, the second transmitter may also be activated at a predetermined time.
  • FIG. 8 shows a flowchart of an example method 800 according to one embodiment of the present disclosure. It will be appreciated that various aspects described above with respect to FIGS. 4-7 may be selectively applied to method 800 .
  • at 804 in response to the at least one first wake-up circuit receiving the first wake-up signal, at least one first receiver of the plurality of first receivers is enabled.
  • FIG. 9 shows a flowchart of an example method 900 according to another embodiment of the present disclosure. It will be appreciated that various aspects described above with respect to FIGS. 4-7 may be selectively applied to method 900 .
  • the circuits are disabled in the second sleep mode, and the one or more second wake-up circuits correspond to the plurality of second receivers.
  • a first wake-up signal is sent to a first chip, the second chip being different from the first chip.
  • at least one second receiver of the plurality of second receivers of the second chip is enabled at a predetermined time after the wake-up signal is sent.
  • control states of a plurality of first receivers and one or more first wake-up circuits in a first chip wherein the plurality of first receivers are in a disabled state in a first sleep mode, the one or more first At least one of the wake-up circuits is enabled in the first sleep mode, the one or more first wake-up circuits correspond to the plurality of first receivers, wherein the number of the at least one first wake-up circuit is less than the plurality The number of first receivers.
  • a state of a plurality of second receivers in a second chip, wherein the plurality of second receivers are in a disabled state in a second sleep mode, is controlled, and the second chip is different from the first chip.
  • at least one first wake-up circuit receiving the first wake-up signal at least one first receiver of the plurality of first receivers is enabled.
  • FIG. 11 shows a schematic circuit diagram of a wake-up circuit S0 according to an embodiment of the present disclosure.
  • the wake-up circuit S0 can be adapted to the block diagrams shown in FIGS. 4-5 . It will be appreciated that various aspects of the wake-up circuit described above with respect to FIGS. 4-7 may be selectively applied to the wake-up circuit S0.
  • the wake-up circuit S0 has a first input VIN and a second input VIP for receiving a wake-up signal from the counterpart chip. In one embodiment, the first input VIN and the second input VIP may be pin inputs of the chip.
  • the wake-up circuit S0 also has a first reference voltage input VREFP and a second reference voltage input VREFN.
  • the first reference voltage input VREFP and the second reference voltage input VREFN are configured to receive an adjustable input voltage inside the chip.
  • the wake-up circuit S0 also includes an output terminal VOUT.
  • the voltage output by the output terminal VOUT can be represented by the following formula:
  • VOUT (VREFN-VREFP)-(VIN-VIP)
  • the output voltage of the output terminal VOUT when in the sleep mode, the output voltage of the output terminal VOUT is zero.
  • the wake-up circuit S0 receives the wake-up signal from the first input VIN and the second input VIP, the output voltage of the output terminal VOUT is 1 to wake up the receiver and/or the transmitter in the chip.
  • the voltage output by the output terminal VOUT may also have other patterns to represent more information.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

本公开涉及一种芯片和控制芯片的方法。该方法包括在休眠模式中将芯片中的多个接收器禁用，并且在休眠模式中将多个唤醒电路禁用，而仅保留一个唤醒电路启用以用于接收唤醒信号。相比于在休眠模式下使得全部唤醒电路启用以接收唤醒信号，该方法可以在休眠模式中节约原本被启用的多个唤醒电路所消耗的电能。这样，使得芯片在休眠模式中可以降低功耗并且延长包括该芯片的电子设备的休眠待机时间。

Description

控制芯片的方法和集成电路系统 技术领域
本公开涉及电子领域，更具体而言涉及用于控制芯片的方法、包含芯片的集成电路系统和电子设备。
背景技术
随着集成电路的发展，诸如无线通信装置之类的电子设备集成了越来越多的芯片(die)或内部封装有一个或多个芯片的封装芯片(packaged chip)，以实现各种各样的功能。随着电子设备内部的芯片的增多，例如系统级封装(system in package,SiP)和片上系统(system on a chip,SoC)内部集成了多个芯片，芯片本身和彼此之间的交互消耗了大量能量，导致电子设备的功耗需求也越来越大。因此，芯片的功耗问题，尤其诸如由电池供电并且包括众多芯片的移动终端的功耗问题，也越来越引起重视。
在一些常规方案中，可以通过诸如缩小芯片中的器件尺寸来降低芯片的功耗。然而，这些设计虽然收益较大，但是成本也相应地显著增加。
发明内容
鉴于上述问题，本公开的实施例旨在提供一种用于控制芯片的方案。
根据本公开的第一方面，提供一种用于控制第一芯片的方法。该方法包括控制所述第一芯片中的多个第一接收器和一个或多个唤醒电路的状态。多个第一接收器在第一休眠模式中处于禁用状态。一个或多个第一唤醒电路中的至少一个第一唤醒电路在第一休眠模式中处于启用状态。一个或多个第一唤醒电路与多个第一接收器对应。至少一个第一唤醒电路的数目少于所述多个第一接收器的数目。该方法还包括响应于所述至少一个第一唤醒电路接收到第一唤醒信号，启用多个第一接收器中的至少一个第一接收器。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第一方面的控制方法通过禁用一部分唤醒电路以启用更少的唤醒电路，即，被启用的唤醒电路的数目相比于全部唤醒电路的数目减小，可以降低第一芯片在休眠模式下的总功耗。另一方面，由于仍然有至少一个唤醒电路在休眠模式下被启用，因此能够确保第一芯片的接收器被正常唤醒。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
在一些可能实现方式中，一个或多个第一唤醒电路中的至少一个第一唤醒电路在第一休眠模式中处于启用状态包括：一个或多个第一唤醒电路中的仅一个第一唤醒电路在第一休眠模式中处于启用状态。通过在休眠模式下仅启用仅一个唤醒电路，可以极大程度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作。
在一些可能实现方式中，一个或多个第一唤醒电路中的至少一个第一唤醒电路在第一休眠模式中处于启用状态包括：仅一个位于多个第一接收器中的一个第一接收器中的第一唤醒电路处于启用状态。通过在休眠模式下仅启用第一接收器中的仅一个唤醒电路，可以极大程 度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作。此外，由于唤醒电路位于接收器中，信号的物理传输路径更短，并且在唤醒电路直接触发唤醒接收器的情形下，唤醒电路无需先传输唤醒信号至控制器并且无需等待控制器按序操作唤醒接收器，因此可以加快唤醒的响应速度。
在一些可能实现方式中，第一芯片和第二芯片根据串行器/解串化器(Serializer-Deserializer,SerDes)协议传输数据和/或命令。
在一些可能实现方式中，该方法还包括响应于至少一个第一唤醒电路接收到第一唤醒信号，启用第一芯片中的第一发送器以发送第二唤醒信号至第二芯片的第二接收器。第二芯片不同于第一芯片。通过启用发送器以唤醒第二芯片的接收器，可以确保第一芯片能够在正常模式下将数据和/或命令正确地发送至第二芯片。
在一些可能实现方式中，该方法还包括在第一芯片的第一发送器被启用达第一预定时段之后，第一发送器与第二芯片中的第二接收器开始进行通信；以及在至少一个第一接收器被启用达第二预定时段之后，至少一个第一接收器与第二芯片中的第二发送器开始进行通信。第一预定时段可以与第二预定时段相同或不同。通过设置预定时段，可以确保第一芯片能够在正确的时间进行操作，而不会因第二芯片尚未准备好而错误操作，例如丢失数据和/或命令。
在一些可能实现方式中，该方法还包括在进入第一休眠模式之前，由第一芯片的第一发送器发送第一模式数据至第二芯片的第二接收器，第一模式数据表示第一芯片的所支持的第一休眠模式；第一芯片的多个第一接收器接收来自第二芯片的第二发送器的第二模式数据，第二模式数据表示第二芯片所支持的第一休眠模式；以及基于第一芯片的所支持的第一休眠模式和第二模式数据，确定待由第一芯片使用的第一休眠模式。通过在休眠之前协商休眠模式，可以确保第一芯片和第二芯片能够以合适的休眠方案进行休眠，并且能够确保芯片中的收发通道能够被正确唤醒。
在一些可能实现方式中，该方法还包括在进入第一休眠模式之前，由第一芯片的多个第一接收器从第二芯片的多个第二发送器接收唤醒电路指定数据，第二芯片不同于第一芯片；以及基于唤醒电路指定数据，确定一个或多个第一唤醒电路的、待在第一休眠模式中被启用的至少一个第一唤醒电路。通过指定在休眠模式下那个或哪些个唤醒电路被启用，可以更为灵活地休眠和唤醒。此外，还可以增加唤醒的可靠性以及增加唤醒时的响应速度。
根据本公开的第二方面，提供一种用于控制第二芯片的方法。该方法包括控制第二芯片中的多个第二接收器以及第二芯片中的一个或多个第二唤醒电路的状态，其中多个第二接收器和一个或多个第二唤醒电路中的至少一个第二唤醒电路在第二休眠模式中处于禁用状态，一个或多个第二唤醒电路与多个第二接收器对应。该方法还包括响应于进入工作模式，向第一芯片发送第一唤醒信号，第二芯片不同于第一芯片。该方法进一步包括在发送唤醒信号之后的预定时间，启用第二芯片的多个第二接收器中的至少一个第二接收器。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第二方面的控制方法通过禁用全部的唤醒电路，即被启用的唤醒电路的数目实际上为零，可以降低第二芯片在休眠模式下的总功耗。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
在一些可能实现方式中，第二芯片作为主设备进行操作，并且第一芯片作为从设备进行 操作。
在一些可能实现方式中，使第二芯片中的多个第二接收器以及第二芯片中的一个或多个第二唤醒电路中的至少一个第二唤醒电路在第二休眠模式中处于禁用状态包括使一个或多个第二唤醒电路中的全部第二唤醒电路处于禁用状态。通过将第二芯片的全部唤醒电路禁用，可以极大地降低第二芯片在第二休眠模式下的休眠功耗。
根据本公开的第三方面，提供一种用于控制芯片的方法。该方法包括控制第一芯片中的多个第一接收器和一个或多个第一唤醒电路的状态。多个第一接收器在第一休眠模式中处于禁用状态。一个或多个第一唤醒电路中的至少一个第一唤醒电路在第一休眠模式中处于启用状态。一个或多个第一唤醒电路与多个第一接收器对应。至少一个第一唤醒电路的数目少于多个第一接收器的数目。该方法还包括控制第二芯片中的多个第二接收器的状态。多个第二接收器在第二休眠模式中处于禁用状态，第二芯片不同于第一芯片。该方法进一步包括响应于至少一个第一唤醒电路接收到第一唤醒信号，启用多个第一接收器中的至少一个第一接收器。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第三方面的控制方法通过禁用一部分唤醒电路以启用更少的唤醒电路，即，被启用的唤醒电路的数目相比于全部唤醒电路的数目减小，可以降低第一芯片在休眠模式下的总功耗。另一方面，由于仍然有至少一个唤醒电路在休眠模式下被启用，因此能够确保第一芯片的接收器被正常唤醒。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
在一些可能实现方式中，第一芯片中的一个或多个第一唤醒电路中的至少一个第一唤醒电路在第一休眠模式中处于启用状态包括：一个或多个第一唤醒电路中的仅一个第一唤醒电路在第一休眠模式中处于启用状态。通过在休眠模式下仅启用仅一个唤醒电路，可以极大程度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作。
在一些可能实现方式中，该方法还包括第二芯片中的一个或多个第二唤醒电路中的至少一个第二唤醒电路在第二休眠模式中处于启用状态。一个或多个第二唤醒电路与多个第二接收器对应。至少一个第二唤醒电路的数目少于多个第二接收器的数目。通过在休眠模式下禁用接收器以及多个第二唤醒电路，可以降低第二芯片在第二休眠模式下的功耗。
在一些可能实现方式中，第二芯片中的一个或多个第二唤醒电路中的至少一个第二唤醒电路在第二休眠模式中处于启用状态包括一个或多个第二唤醒电路中的仅一个第二唤醒电路在第二休眠模式中处于启用状态。通过在休眠模式下仅启用第二接收器中的仅一个唤醒电路，可以极大程度地降低第二芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作，并且还能加快唤醒的响应速度。
在一些可能实现方式中，该方法还包括响应于至少一个第一唤醒电路接收到第一唤醒信号，启用第一芯片中的第一发送器以发送第二唤醒信号至第二芯片的第二接收器。第二芯片不同于第一芯片。通过启用发送器以唤醒第二芯片的接收器，可以确保第一芯片能够在正常模式下将数据和/或命令正确地发送至第二芯片。
在一些可能实现方式中，该方法还包括第二芯片中的全部的第二唤醒电路在第二休眠模式中处于禁用状态。通过将第二芯片的全部唤醒电路禁用，可以极大地降低第二芯片在第二休眠模式下的休眠功耗。
在一些可能实现方式中，该方法还包括在进入休眠模式之前，由第一芯片的第一发送器发送第一模式数据至第二芯片的第二接收器，第一模式数据表示第一芯片的所支持的休眠模式；由第二芯片的发送器发送第二模式数据至第一芯片的第一接收器，第二模式数据表示第二芯片的所支持的休眠模式；以及第一芯片基于第一芯片的所支持的休眠模式和第二模式数据，确定待由第一芯片使用的休眠模式；以及第二芯片基于第二芯片的所支持的休眠模式和第一模式数据，确定待由第二芯片使用的休眠模式。通过在休眠之前协商休眠模式，可以确保第一芯片和第二芯片能够以合适的休眠方案进行休眠，并且能够确保芯片中的收发通道能够被正确唤醒。
在一些可能实现方式中，该方法还包括在进入休眠模式之前，由第一芯片的多个第一接收器接收来自第二芯片的多个第二发送器的唤醒电路指定数据；以及基于唤醒电路指定数据，确定第一芯片中的、待在第一休眠模式中被启用的至少一个第一唤醒电路。通过指定在休眠模式下那个或哪些个唤醒电路被启用，可以更为灵活地休眠和唤醒。此外，还可以增加唤醒的可靠性以及增加唤醒时的响应速度。
根据本公开的第四方面，提供一种第一芯片。第一芯片包括多个第一接收器和一个或多个第一唤醒电路。多个第一接收器被配置为在第一休眠模式中处于禁用状态。一个或多个第一唤醒电路与多个第一接收器对应。一个或多个第一唤醒电路中的至少一个第一唤醒电路被配置为在第一休眠模式中处于启用状态。至少一个第一唤醒电路的数目少于多个第一接收器的数目。至少一个唤醒电路被进一步配置为响应于接收到第一唤醒信号，使得多个第一接收器中的至少一个第一接收器被启用。通过仅启用更少的唤醒电路，可以降低第一芯片在休眠模式下的功耗。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第一方面的控制方法通过禁用一部分唤醒电路以启用更少的唤醒电路，即，被启用的唤醒电路的数目相比于全部唤醒电路的数目减小，可以降低第一芯片在休眠模式下的总功耗。另一方面，由于仍然有至少一个唤醒电路在休眠模式下被启用，因此能够确保第一芯片的接收器被正常唤醒。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
在一些可能实现方式中，至少一个第一唤醒电路包括仅一个第一唤醒电路。过在休眠模式下仅启用仅一个唤醒电路，可以极大程度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作。
在一些可能实现方式中，仅一个第一唤醒电路位于多个第一接收器中的一个第一接收器中。通过在休眠模式下仅启用第一接收器中的仅一个唤醒电路，可以极大程度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作，并且还能加快唤醒的响应速度。通过在休眠模式下仅启用第一接收器中的仅一个唤醒电路，可以极大程度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作。此外，由于唤醒电路位于接收器中，信号的物理传输路径更短，并且在唤醒电路直接触发唤醒接收器的情形下，唤醒电路无需先传输唤醒信号至控制器并且无需等待控制器按序操作唤醒接收器，因此可以加快唤醒的响应速度。
在一些可能实现方式中，第一芯片被配置为响应于至少一个第一唤醒电路接收到第一唤醒信号，使第一芯片中的第一发送器处于启用状态以发送第二唤醒信号至第二芯片的第二接 收器。第二芯片不同于第一芯片。通过启用发送器以唤醒第二芯片的接收器，可以确保第一芯片能够在正常模式下将数据和/或命令正确地发送至第二芯片。
在一些可能实现方式中，第一芯片被配置为在第一芯片的第一发送器被启用达第一预定时段之后，第一发送器与第二芯片中的第二接收器开始进行通信；以及在至少一个第一接收器被启用达第二预定时段之后，至少一个第一接收器与第二芯片中的第二发送器开始进行通信。第一预定时段可以与第二预定时段相同或不同。通过设置预定时段，可以确保第一芯片能够在正确的时间进行操作，而不会因第二芯片尚未准备好而错误操作，例如丢失数据和/或命令。
在一些可能实现方式中，第一芯片被配置为在进入第一休眠模式之前，由第一芯片的第一发送器发送第一模式数据至第二芯片的第二接收器，第一模式数据表示第一芯片的所支持的第一休眠模式；第一芯片的多个第一接收器接收来自第二芯片的第二发送器的第二模式数据，第二模式数据表示第二芯片所支持的第一休眠模式；以及基于第一芯片的所支持的第一休眠模式和第二模式数据，确定待由第一芯片使用的第一休眠模式。通过在休眠之前协商休眠模式，可以确保第一芯片和第二芯片能够以合适的休眠方案进行休眠，并且能够确保芯片中的收发通道能够被正确唤醒。
在一些可能实现方式中，第一芯片被配置为在进入第一休眠模式之前，由第一芯片的多个第一接收器从第二芯片的多个第二发送器接收唤醒电路指定数据，第二芯片不同于第一芯片；以及基于唤醒电路指定数据，确定一个或多个第一唤醒电路的、待在第一休眠模式中被启用的至少一个第一唤醒电路。通过指定在休眠模式下那个或哪些个唤醒电路被启用，可以更为灵活地休眠和唤醒。此外，还可以增加唤醒的可靠性以及增加唤醒时的响应速度。
根据本公开的第五方面，提供一种第二芯片，包括多个第二接收器、一个或多个第二唤醒电路和多个第二发送器。多个第二接收器被配置为在第二休眠模式中处于禁用状态。一个或多个第二唤醒电路与多个第二接收器对应。一个或多个第二唤醒电路中的至少一个第二唤醒电路被配置为在第二休眠模式中处于禁用状态。多个第二发送器被配置为响应于进入工作模式，向第一芯片发送第一唤醒信号，第一芯片不同于第二芯片；以及在发送第一唤醒信号之后的预定时间，使得多个第二接收器中的至少一个第二接收器被启用。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第五方面的控制方法通过禁用全部的唤醒电路，即被启用的唤醒电路的数目实际上为零，可以降低第二芯片在休眠模式下的总功耗。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
在一些可能实现方式中，第二芯片被配置为主设备，并且第一芯片被配置为从设备。
在一些可能实现方式中，一个或多个第二唤醒电路被配置为在第二休眠模式中全部被禁用。通过将第二芯片的全部唤醒电路禁用，可以极大地降低第二芯片在第二休眠模式下的休眠功耗。
根据本公开的第六方面，提供一种集成电路系统。该集成电路系统包括第一芯片和第二芯片。第一芯片包括多个第一接收器和一个或多个第一唤醒电路。多个第一接收器被配置为在第一休眠模式中处于禁用状态。一个或多个第一唤醒电路与多个第一接收器对应。一个或多个第一唤醒电路中的至少一个第一唤醒电路被配置为在第一休眠模式中处于启用状态。至 少一个第一唤醒电路的数目少于多个第一接收器的数目。至少一个唤醒电路被进一步配置为响应于接收到第一唤醒信号，使得多个第一接收器中的至少一个第一接收器被启用。第二芯片包括被配置为在第二休眠模式中被禁用的多个第二接收器。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第六方面的控制方法通过禁用一部分唤醒电路以启用更少的唤醒电路，即，被启用的唤醒电路的数目相比于全部唤醒电路的数目减小，可以降低第一芯片在休眠模式下的总功耗。另一方面，由于仍然有至少一个唤醒电路在休眠模式下被启用，因此能够确保第一芯片的接收器被正常唤醒。在一些可能实现方式中，至少一个第一唤醒电路包括仅一个第一唤醒电路。通过在休眠模式下仅启用仅一个唤醒电路，可以极大程度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
在一些可能实现方式中，第二芯片还包括一个或多个第二唤醒电路。一个或多个第二唤醒电路中的至少一个第二唤醒电路被配置为在第二休眠模式中处于启用状态。通过在休眠模式下禁用接收器以及多个第二唤醒电路，可以降低第二芯片在第二休眠模式下的功耗。通过在休眠模式下仅启用仅一个唤醒电路，可以极大程度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作。通过在休眠模式下仅启用第一接收器中的仅一个唤醒电路，可以极大程度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作，并且还能加快唤醒的响应速度。
在一些可能实现方式中，第一芯片被配置为响应于至少一个第一唤醒电路接收到第一唤醒信号，使第一芯片中的第一发送器处于启用状态以发送第二唤醒信号至第二芯片的第二接收器。第二芯片不同于第一芯片。通过启用发送器以唤醒第二芯片的接收器，可以确保第一芯片能够在正常模式下将数据和/或命令正确地发送至第二芯片。
在一些可能实现方式中，第二芯片还包括一个或多个第二唤醒电路。一个或多个第二唤醒电路被配置为在第二休眠模式中全部处于禁用状态。通过将第二芯片的全部唤醒电路禁用，可以极大地降低第二芯片在第二休眠模式下的休眠功耗。
在一些可能实现方式中，第一芯片被配置为在进入休眠模式之前，由第一芯片的第一发送器发送第一模式数据至第二芯片的第二接收器，第一模式数据表示第一芯片的所支持的休眠模式。第二芯片被配置为使第二芯片的发送器发送第二模式数据至第一芯片的第一接收器，第二模式数据表示第二芯片的所支持的休眠模式。第一芯片被配置为基于第一芯片的所支持的休眠模式和第二模式数据，确定待由第一芯片使用的休眠模式。第二芯片被配置为基于第二芯片的所支持的休眠模式和第一模式数据，确定待由第二芯片使用的休眠模式。通过在休眠之前协商休眠模式，可以确保第一芯片和第二芯片能够以合适的休眠方案进行休眠，并且能够确保芯片中的收发通道能够被正确唤醒。
在一些可能实现方式中，第一芯片被配置为在进入休眠模式之前，由第一芯片的多个第一接收器接收来自第二芯片的多个第二发送器的唤醒电路指定数据；以及基于唤醒电路指定数据，确定第一芯片中的、待在第一休眠模式中被启用的至少一个第一唤醒电路。通过指定在休眠模式下那个或哪些个唤醒电路被启用，可以更为灵活地休眠和唤醒。此外，还可以增加唤醒的可靠性以及增加唤醒时的响应速度。
根据本公开的第七方面，提供一种电子设备。电子设备包括电路板和根据第六方面的集成电路系统。集成电路系统被设置在电路板上。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第七方面的控制方法通过禁用一部分唤醒电路以启用更少的唤醒电路，即，被启用的唤醒电路的数目相比于全部唤醒电路的数目减小，可以降低第一芯片在休眠模式下的总功耗。另一方面，由于仍然有至少一个唤醒电路在休眠模式下被启用，因此能够确保第一芯片的接收器被正常唤醒。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
根据本公开的第八方面，提供一种用于控制第一芯片的方法。该方法包括使第一芯片中的多个第一接收器在第一休眠模式中处于禁用状态。该方法还包括使一个或多个第一唤醒电路中的至少一个第一唤醒电路在第一休眠模式中处于启用状态。一个或多个第一唤醒电路与多个第一接收器对应。至少一个第一唤醒电路的数目少于多个第一接收器的数目。该方法进一步包括响应于至少一个第一唤醒电路接收到第一唤醒信号，启用多个第一接收器中的至少一个第一接收器。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第八方面的控制方法通过禁用一部分唤醒电路以启用更少的唤醒电路，即，被启用的唤醒电路的数目相比于全部唤醒电路的数目减小，可以降低第一芯片在休眠模式下的总功耗。另一方面，由于仍然有至少一个唤醒电路在休眠模式下被启用，因此能够确保第一芯片的接收器被正常唤醒。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
根据本公开的第九方面，提供一种用于控制第二芯片的方法。该方法包括使第二芯片中的多个第二接收器以及第二芯片中的一个或多个第二唤醒电路中的至少一个第二唤醒电路在第二休眠模式中处于禁用状态，一个或多个第二唤醒电路与多个第二接收器对应。该方法还包括响应于进入工作模式，向第一芯片发送第一唤醒信号，第二芯片不同于第一芯片。该方法进一步包括在发送唤醒信号之后的预定时间，启用第二芯片的多个第二接收器中的至少一个第二接收器。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第九方面的控制方法通过禁用全部的唤醒电路，即被启用的唤醒电路的数目实际上为零，可以降低第二芯片在休眠模式下的总功耗。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
根据本公开的第十方面，提供一种用于控制芯片的方法。该方法包括使第一芯片中的多个第一接收器在第一休眠模式中处于禁用状态。该方法还包括使第二芯片中的多个第二接收器在第二休眠模式中处于禁用状态。第二芯片不同于第一芯片。该方法进一步包括使第一芯片中的一个或多个第一唤醒电路中的至少一个第一唤醒电路在第一休眠模式中处于启用状态；以及响应于至少一个第一唤醒电路接收到第一唤醒信号，启用多个第一接收器中的至少 一个第一接收器。一个或多个第一唤醒电路与多个第一接收器对应。至少一个第一唤醒电路的数目少于多个第一接收器的数目。每个在休眠模式下被启用的唤醒电路为了保持能够随时接收到唤醒信号，仍需上电操作并且消耗功耗。在启用全部的唤醒电路的情形下，第一芯片在休眠模式下的总功耗为唤醒电路的功耗与全部唤醒电路的数目的乘积。相比于启用全部的唤醒电路，根据第十方面的控制方法通过禁用一部分唤醒电路以启用更少的唤醒电路，即，被启用的唤醒电路的数目相比于全部唤醒电路的数目减小，可以降低第一芯片在休眠模式下的总功耗。另一方面，由于仍然有至少一个唤醒电路在休眠模式下被启用，因此能够确保第一芯片的接收器被正常唤醒。此外，由于根据本公开的集成电路芯片并不涉及对芯片的尺寸进行缩减，因此未显著增加芯片的成本，由此可以解决背景技术里的显著增加成本的问题。
应当理解，发明内容部分中所描述的内容并非旨在限定本公开的实施例的关键或重要特征，亦非用于限制本公开的范围。本公开的其它特征将通过以下的描述变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了一种低功耗系统的示意框图；
图2示出了根据本公开的一个实施例的电子设备的示意图；
图3示出了根据本公开的一个实施例的低功耗系统的简化框图；
图4示出了根据本公开的一个实施例的低功耗系统的示意框图；
图5示出了根据本公开的另一实施例的低功耗系统的示意框图；
图6示出了根据本公开的一个实施例的示例过程的流程图；
图7示出了根据本公开的另一实施例的示例过程的流程图；
图8示出了根据本公开的一个实施例的示例方法的流程图；
图9示出了根据本公开的另一实施例的示例方法的流程图；
图10示出了根据本公开的另一实施例的示例方法的流程图；以及
图11示出了根据本公开的一个实施例的唤醒电路的电路示意图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。例如“A和/或B”表示A、B、或者A和B。下文还可能包括其他明确的和隐含的定义。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
如上所述，包含多个芯片的电子设备的功耗问题日益引起重视。虽然已经通过缩小器件 尺寸来降低功耗。然而，这仍然不够理想。随着芯片性能的提升和功能的增强，仍然需要进一步降低功耗的方案。
在一些情形下，在包括多个芯片的封装芯片中，多个芯片彼此之间进行通信以传输数据和命令。此外，在分别包括一个或多个芯片的不同封装芯片之间，通常也有大量数据和命令的传输。这些数据和命令的传输消耗了大量能量。然而，这些芯片并非时刻传输数据。因此，期望能够在其不工作时，使得这些芯片休眠来降低功耗。
为了能够从休眠模式中被唤醒，芯片通常具有在休眠模式下保持工作的唤醒电路(squelch circuit)。唤醒电路能够在休眠模式下检测到外部传输过来的唤醒信号。例如，在芯片中可以具有多个收发通道(lane)。每个收发通道包括一个接收器(RX)和一个发送器(TX)。每个接收器中具有一个唤醒电路。在休眠模式中，发送器和/或接收器可以被禁用，例如断电，以降低功耗。但是在休眠模式中，每个接收器中的唤醒电路仍然保持工作。当唤醒电路从外界接收到唤醒信号时，使得接收器和发送器从休眠模式返回至工作模式。接收器和发送器由此可以正常操作来传输数据和/或命令。
图1示出了一种低功耗系统的示意框图。该低功耗系统例如根据一些协议或标准操作。该低功耗系统包括彼此互相通信的第一芯片10和第二芯片20。在一个实施例中，第一芯片10例如是硬盘控制器，第二芯片20是处理器。第一芯片10包括第一控制器110、第一收发通道111、第二收发通道112和第三收发通道113。第一控制器110与第一收发通道111、第二收发通道112和第三收发通道113分别通信以传输信号。第一收发通道111包括第一发送器TX11和第一接收器RX11，第二收发通道112包括第一发送器TX12和第一接收器RX12，第三收发通道113包括第一发送器TX13和第一接收器RX13。
对应地，第二芯片20包括第二控制器210、第一收发通道211、第二收发通道212和第三收发通道213。第二控制器110与第一收发通道211、第二收发通道212和第三收发通道213分别通信以传输信号。第一收发通道211包括第二发送器TX21和第二接收器RX21，第二收发通道212包括第二发送器TX22和第二接收器RX22，第三收发通道213包括第二发送器TX23和第二接收器RX23。
在工作模式下，第一芯片10的第一发送器TX11向第二芯片的第二接收器RX21传输数据，并且第一芯片10的第一接收器RX11从第二芯片的第二发送器TX21接收数据，如图中箭头所示。类似地，第一芯片10的第二收发通道112与第二芯片20的第二收发通道212通信，并且第一芯片10的第三收发通道113与第二芯片20的第三收发通道213通信，如图中箭头具体示出。在一个实施例中，第一芯片10的物理层(PHY)和第二芯片20的PHY例如根据SerDes协议来彼此互相通信以例如传输数据。可以理解，本公开也可以适用于根据其它协议的应用场景。
在图1中，第一芯片10的第一接收器RX11、第一接收器RX12和第一接收器RX13还分别包括第一唤醒电路S11、第一唤醒电路S12和第一唤醒电路S13。类似地，第二芯片20的第二接收器RX21、第二接收器RX22和第二接收器RX23也分别包括第二唤醒电路S21、第二唤醒电路S22和第二唤醒电路S23。虽然在图1中示出了每个芯片具有三个收发通道，但是这仅是示意而非对本公开的范围进行限制。第一芯片10和第二芯片20可以分别具有更多或更少的收发通道，例如8个或16个收发通道。
在一个实施例中，如果第二芯片20检测到第二芯片20和第一芯片10已经未传输数据/命令达预定时段，则第二芯片20可以确定第一芯片10和第二芯片20的收发通道可以进入休 眠模式。第二芯片20可以通过任一收发通道向第一芯片10发送休眠请求。第一芯片10在接收到休眠请求之后，可以通过任一收发通道向第二芯片20发送用于确认休眠的确认信息。第一芯片10在发送同时或是在完成发送之后的第一预定时段，进入第一芯片10的第一休眠模式并且禁用三个接收器和/或发送器。
此外，在第一休眠模式中，还可以根据需要进一步禁用(disable)三个发送器。“禁用”电路可以是电路被断电(powered off)或者至少停用电路的功能。例如，禁用接收器表示接收器的电路模块在此被断电，或者即使接收器被供电但是其接收功能模块在此被停用以降低功耗。相对而言，“启用”(enable)电路则表示电路被供电(powered on)以正常操作，或是从原本就已供电的状态恢复其电路功能。例如，启用接收器表示接收器的电路模块在此被供电，或者如果接收器原本就处于供电状态(不具备接收功能)，但是其被启用则意味着接收器重新恢复接收功能以准备好接收数据。
在第一芯片10的第一休眠模式下，三个收发通道中的接收器和发送器均保持禁用，例如被断电，但三个接收器中的唤醒电路均保持被启用，例如被供电，以便于在第一休眠模式中接收唤醒信号以用于唤醒第一芯片10。在本文中，即使唤醒电路位于接收器中，当接收器被禁用时，这也不意味着接收器中的唤醒电路被禁用。相反，通过下文的具体描述，可以理解当芯片中的接收器被禁用时，即使一个或多个唤醒电路位于接收器中，一个或多个唤醒电路中的至少一个唤醒电路仍保持被启用的状态以用于唤醒接收器。
第二芯片20在接收到该确认信息时或是在接收到该确认信息之后的第二预定时段，进入第二芯片20的第二休眠模式。第一休眠模式和第二休眠模式中的序号仅是用于区分该休眠模式隶属于不同的芯片。第一预定时段和第二预定时段可以相同或不同。在一些实施例中，在每个芯片内部还可以进一步细分休眠模式。例如，第一芯片10的接收器具有第一接收器休眠模式，第一芯片10的发送器具有第一发送器休眠模式。休眠模式的共同之处在于，电路在休眠模式下可以暂停该电路的功能的运行。例如，发送器在休眠模式下会停止发送，无论发送器在休眠模式下是否被供电。
类似地，在第二芯片20的第二休眠模式下，三个收发通道中的接收器和发送器均保持禁用，例如被断电，但三个接收器中的唤醒电路均保持被启用，例如被供电，以便于在第二休眠模式中接收唤醒信号以用于唤醒第二芯片20。这样，在第二休眠模式下，仅6个唤醒电路被启用。相比于接收器和发送器，唤醒电路在休眠模式下所消耗的功率远远小于接收器和发送器所消耗的功率，因此可以显著节省第一芯片10和第二芯片20的功耗。相应地，也可以显著节省包括第一芯片10和第二芯片20的系统(例如集成电路组件30和电子设备100)的功耗。
在一个示例中，第一芯片10在第一休眠模式下可以将其除了唤醒电路之外的全部电路禁用，以最大程度地降低休眠功耗。备选地，第一芯片10在第一休眠模式下也可以保持部分电路被禁用，例如仅保持收发通道被禁用，而保持其它电路部分(例如与其它芯片或电路通信的其它唤醒电路)和收发通道中的唤醒电路被启用。类似地，第二芯片20在第二休眠模式下也可以将其除了唤醒电路之外的全部电路禁用，或是将包括收发通道在内的部分电路禁用。在另一实施例中，第一芯片10和第二芯片20可以不同时进入休眠模式。例如，第一芯片10进入休眠模式的情形下，第二芯片20可以仍保持在工作模式以执行其它处理，反之亦然。
此外，第一芯片10和第二芯片20还可以有低速模式和高速模式。在低速模式下，第一芯片10和第二芯片20彼此之间仅部分收发通道被启用。在高速模式下，第一芯片10和第二 芯片20的大部分收发通道或所有收发通道被启用。换言之，第一芯片10和第二芯片20可以在工作模式下根据业务需求选择性地启用收发通道。在工作模式下，各个唤醒电路可以被全部启用、全部禁用或是被选择性地启用。本公开的实施例对此不进行限制。由此可见，在图1的示例性实施例中，针对N个收发通道，第一芯片10和第二芯片20在休眠模式期间有2N个唤醒电路被启用，其中N表示大于0的整数。
虽然通过在休眠模式期间关闭或禁用收发通道而仅保留收发通道中的2N个唤醒电路被启用来显著降低芯片的功耗，但是对于使用电池供电的电子设备而言，仍然期望能够进一步降低芯片的功耗。唤醒电路的功耗远远小于接收器的功耗，因此在使用市电电源供电的电子设备中，唤醒电路的功耗往往可以忽略不计。此外，在一些情形下，受限于收发信道所遵守的标准或协议，接收器均具有一个唤醒电路，并且每个唤醒电路在休眠模式下均需要处于启用状态。因此在一些方案中，因此，设计人员往往从优化芯片的各个电路的设计角度来降低芯片功耗。然而，对于一些电子设备而言，期望能够进一步降低芯片的功耗，从而降低电子设备的整体功耗。
在本公开的实施例中，提出了一种低功耗芯片以及包括低功耗芯片的系统。该低功耗芯片在休眠模式下进一步减少唤醒电路的数目，并且通过使用经减少的唤醒电路来唤醒一个或多个收发器通道。这样，可以进一步降低芯片的功耗，并且相应地降低包括第一芯片和第二芯片的系统的功耗。另一方面，由于根据本公开的实施例的集成电路芯片并不需要对芯片的尺寸进行缩减，因此也未显著增加芯片的成本，例如设计和制造成本。
图2示出了根据本公开的一个实施例的电子设备200的示意图。在一个实施例中，电子设备200例如是智能手机。其它电子设备也是可能的，例如计算机、平板电脑或者其他智能终端设备。电子设备200包括集成电路组件30以及其它未示出的部件，诸如其它芯片、传感器等。集成电路组件30可以被形成为集成电路系统的至少一部分。在一个实施例中，集成电路组件30可以包括在诸如印刷电路板(PCB)或柔性电路板(FPC)之类的电路板上的多个封装芯片。每个封装芯片内部可以封装有一个或多个芯片。在另一实施例中，集成电路组件30本身就是单个芯片，例如，内部集成了多个芯片的SiP芯片。本公开在此不对集成电路组件30的形式做任何限制。
图3示出了根据本公开的一个实施例的低功耗系统的简化框图。在一个实施例中，集成电路组件30例如可以是SiP芯片或是集成了芯片的印刷电路板。集成电路组件30可以包括第一芯片10和第二芯片20。集成电路组件30还可以包括其它未被示出的芯片或部件。第一芯片10可以包括N个与第二芯片20进行通信的收发通道，其中N表示大于0的自然数。相应地，第二芯片20也可以包括N个与第一芯片10进行通信的收发通道。可以理解，第一芯片10和第二芯片20还可以分别具有与其它芯片或部件通信的其它收发通道。本公开对此不做任何限制。
图4示出了根据本公开的一个实施例的低功耗系统的示意框图。与图1类似地，在该示例性实施例中，低功耗系统包括第一芯片10和第二芯片20。图4的低功耗系统的硬件配置与图1的低功耗系统的硬件配置相同或相似，因此关于图1所描述的各个方面可以适用于图4的低功耗系统，在此不再赘述。
在一个实施例中，第一芯片10例如是硬盘控制器，第二芯片是处理器。第一芯片10包括第一控制器110、第一收发通道111、第二收发通道112和第三收发通道113。第一控制器110与第一收发通道111、第二收发通道112和第三收发通道113分别通信以传输信号。第一 收发通道111包括第一发送器TX11和第一接收器RX11，第二收发通道112包括第一发送器TX12和第一接收器RX12，第三收发通道113包括第一发送器TX13和第一接收器RX13。
对应地，第二芯片20包括第二控制器210、第一收发通道211、第二收发通道212和第三收发通道213。第二控制器110与第一收发通道211、第二收发通道212和第三收发通道213分别通信以传输信号。第一收发通道211包括第二发送器TX21和第二接收器RX21，第二收发通道212包括第二发送器TX22和第二接收器RX22，第三收发通道213包括第二发送器TX23和第二接收器RX23。虽然在图4中示出了每个芯片具有三个收发通道，但是这仅是示意而非对本公开的范围进行限制。第一芯片10和第二芯片20可以分别具有更多或更少的收发通道，例如8个或16个收发通道。
第一芯片10的第一接收器RX11、第一接收器RX12和第一接收器RX13还分别包括第一唤醒电路S11、第一唤醒电路S12和第一唤醒电路S13。类似地，第二芯片20的第二接收器RX21、第二接收器RX22和第二接收器RX23也分别包括第二唤醒电路S21、第二唤醒电路S22和第二唤醒电路S23。
在一个实施例中，当第二芯片20检测到第二芯片20和第一芯片10的收发通道相互之间未进行数据和/或指令的传输达预定时段时，第二芯片20确定可以进入休眠模式。第二芯片20的控制器210经由第二芯片20的第二发送器向第一芯片10的第一接收器发送休眠请求，第一芯片10的控制器110在接收到休眠请求后，经由第一芯片10的第一发送器向第二芯片20的第二接收器回复确认信息。第一芯片10的控制器110随后使得第一芯片10的各个收发通道中的发送器和接收器禁用，例如对其断电，以降低功耗。
此外，第一芯片10的控制器110还使得一些唤醒电路在第一休眠模式中处于禁用状态。例如，在图4中，仅第一接收器RX11中的第一唤醒电路S11处于启用状态(以阴影示出)，第一接收器RX12和第一接收器RX13中的第一唤醒电路S12和第一唤醒电路S13被禁用(以空白示出)。在一个实施例中，对于在休眠模式中处于启用状态的第一唤醒电路而言，其可以在进入休眠模式之前就被启用，或者在进入休眠模式时，或在进入休眠模式后被启用。本公开对此不进行限制。相比于图1所示的例子，由于在第一休眠模式中除了禁用第一发送器和第一接收器之外还进一步禁用了第一唤醒电路S12和第一唤醒电路S13，因此图4的实施例在第一休眠模式中进一步降低了第一芯片10的功耗，例如节省了第一唤醒电路S12和第一唤醒电路S13的功耗。这对于多收发通道(例如16通道，16个唤醒电路)的芯片和使用电池供电并且包含该芯片的电子设备而言，功耗优势尤为明显。例如，将N个唤醒电路在第一休眠模式期间的总功耗降低至约1/N，例如1/16。另一方面，由于在图4的实施例中仍然有至少一个唤醒电路处于启用状态以接收唤醒信号，因此可以仍然能够确保第一芯片中的第一接收器和第一发送器能够被唤醒以进入正常操作状态。
备选地，也可以增加在第一芯片10的第一休眠模式中使用的唤醒电路的数目。例如，可以在第一休眠模式中将第一唤醒电路S11和第一唤醒电路S12设置为启用状态。这样，可以避免出于各种原因导致的某个唤醒电路的失效所引起的无法唤醒第一芯片10的各个收发通道的情形。此外，对于需要快速响应的某些收发通道而言，也可以在该收发通道内部设置用于直接唤醒该收发通道的唤醒电路来快速唤醒该收发器，而无需由控制器在收到唤醒电路的唤醒信号之后间接唤醒收发通道。
第二芯片20的控制器210在接收到确认信息之后，使得各个收发信道中的接收器和发送器处于禁用状态，例如对其断电，以降低功耗。此外，第二芯片20的控制器210还使得一些 唤醒电路在第二休眠模式中处于禁用状态。例如，在图4中，仅第二接收器RX21中的第二唤醒电路S21处于启用状态(以阴影示出)，第二接收器RX22和第二接收器RX23中的第二唤醒电路S22和第二唤醒电路S23被禁用(以空白示出)。在一个实施例中，对于在休眠模式中处于启用状态的第二唤醒电路而言，其可以在进入休眠模式之前就被启用，或者在进入休眠模式时或在进入休眠模式后被启用。本公开对此不进行限制。相比于图1所示的例子，图4的实施例在第二休眠模式中进一步降低了第二芯片20的功耗，例如节省了第二唤醒电路S22和第二唤醒电路S23的功耗。这对于多收发通道(例如16路收发通道，16个唤醒电路)的芯片和使用电池供电并且包含该芯片的电子设备而言，功耗优势尤为明显。例如，将N个唤醒电路在第二休眠模式期间的总功耗降低至约1/N，例如1/16。对于包括第一芯片10和第二芯片20的集成电路系统而言，假设每个唤醒电路在休眠期间的功耗为P，则集成电路系统的唤醒电路的功耗可以从2N*P降低至2P，例如从16路收发通道的32P降低至2P。
与第一芯片10相似，第二芯片20也可以在第二休眠模式中增加唤醒电路的数目。例如，第二唤醒电路S21和第二唤醒电路S22可以在第二休眠模式中处于启用状态。在图1中，第一唤醒电路和第二唤醒电路均位于接收器内。通过在休眠模式下启用接收器中的仅一个唤醒电路，可以极大程度地降低第一芯片在休眠模式下的功耗，同时仍能保持接收器能够被唤醒以用于正常工作。此外，相比于唤醒电路经由控制器来启用接收器，位于接收器内的唤醒电路可以无需经由控制器而直接触发导通接收器中的低压差线性稳压器(LDO)开关，以使得接收器被启用。这样，可以加快接收器被唤醒的响应速度。
在一个实施例中，当第一芯片10和第二芯片20分别进入第一休眠模式和第二休眠模式之后，第一芯片10和第二芯片20中的各个收发通道被禁用，例如被断电，而每个芯片仅保留一个或多个唤醒电路处于启用状态。可以在进入第一休眠模式和第二休眠模式前，第一芯片10和第二芯片20可以通过通信协商在即将到来的第一休眠模式和第二休眠模式中使哪个唤醒电路或哪几个唤醒电路被启用。这样，可以增加配置的灵活性，也可以在某个唤醒电路故障时，采用其它唤醒电路来正常操作。备选地，也可以默认第一芯片10的第一唤醒电路S11和第二芯片20的第二唤醒电路S21是在第一休眠模式和第二休眠模式中使用的唤醒电路，而无需协商。这样，可以减少通信成本和通信功耗，增加系统进入休眠的响应速度。
虽然在上面描述了第一芯片10和第二芯片20的收发通道均被休眠的情形，但这仅是示意而非对本公开的范围进行限制。其它情形是可能的，例如第一芯片10的收发通道被休眠，而第二芯片20的收发通道仍处于工作状态。再例如，第一芯片10和第二芯片20的部分收发通道被休眠，而部分收发通道仍处于正常工作状态。在另一些情形中，第一芯片10的接收器和发送器被禁用，而第二芯片20的接收器被禁用但是第二芯片20的至少一个发送器处于启用状态。
在一个实施例中，处于第二休眠模式的第二芯片20在需要唤醒第一芯片10时，控制器210启用第二发送器TX21并且使第二发送器TX21向第一芯片10的第一唤醒电路S11发送第一唤醒信号。在第一休眠模式中处于启用状态的第一唤醒电路S11在接收到第一唤醒信号之后，第一唤醒电路S11通知控制器110。控制器110继而启用至少一个接收器。在一个实施例中，控制器110启用第一收发通道111的第一接收器RX11和第一发送器TX11。备选地或附加地，控制器110还可以启用第二收发通道112和第三收发通道113中的接收器和发送器。控制器110例如使第一发送器TX11发送第二唤醒信号至第二芯片20的第一接收器S21。在第二休眠模式中处于启用状态的第二唤醒电路S21在接收到第二唤醒信号之后，第二唤醒 电路S21通知控制器210。控制器210继而启用至少一个接收器。在一个实施例中，控制器210启用第一收发通道111的第二接收器RX21。备选地或附加地，控制器210还可以启用第二收发通道212和第三收发通道213中的接收器和发送器。
第一芯片10可以具有计时器或是计数器，例如位于控制器110内，以用于计时。备选地，第一芯片10可以使用来自外部的时钟信号进行计时。在第一芯片10的第一发送器TX11被启用达第一预定时段之后，第一芯片10和第二芯片20均处于工作模式，并且第一芯片10的第一发送器TX11开始与第二芯片的第二接收器RX21进行通信。通过设置预定时段，可以确保第一芯片能够在正确的时间进行操作，而不会因第二芯片尚未准备好而错误操作，例如丢失数据和/或命令。
在一个实施例中，第一芯片10和第二芯片20在分别进入第一休眠模式和第二休眠模式之前，还可以基于唤醒电路指定数据来确定待在第一休眠模式和第二休眠模式中哪个或哪些个第一唤醒电路和第二唤醒电路处于启用状态。以第一芯片10为例，第一芯片10在进入第一休眠模式之前，第一芯片10的任一接收器可以从第二芯片20接收唤醒电路指定数据，该数据指示了待在第一休眠模式中使用的第一唤醒电路。第一芯片10的控制器110继而可以向第二芯片20回复确认信息以确认该第一唤醒电路将被启用。备选地，第一芯片10也可以不回复确认信息，而是使该第一唤醒电路在第一休眠模式下处于启用状态。通过指定在休眠模式下那个或哪些个唤醒电路被启用，可以更为灵活地休眠和唤醒。此外，还可以增加唤醒的可靠性以及增加唤醒时的响应速度。
此外，基于协议要求，芯片通常在每个接收器中具有一个唤醒电路，并且在休眠模式下使得各个唤醒电路均处于启用状态。因此，由于硬件、软件或协议的原因，一些芯片可能存在不能支持如上针对图4所描述的在休眠模式下的低功耗休眠的情形。为此，在一些实施例中，可以芯片在进入休眠模式之前，双方芯片进行所支持的休眠方案通信，以确定将使用的休眠模式。
仍以第一芯片10和第二芯片20分别进入第一休眠模式和第二休眠模式为进行说明。在在一个实施例中，第一芯片10和第二芯片20分别进入第一休眠模式和第二休眠模式之前，第一芯片10将表示其所支持的休眠方案的第一模式数据发送给第二芯片20。第二芯片20在接收到第一模式数据之后，可以基于第二芯片20所支持的第二休眠模式和第一模式数据确定第二芯片20将使用的休眠模式。在一个实施例中，模式数据可以由在第一芯片10发送给第二芯片20的数据组的预定字段中预留的数据位来表征。这种预定的数据位可以是在数据传输协议中规定。在一个实施例中，例如假设休眠模式包括三种休眠方案，则可以使用三位数据表征所支持的休眠模式。例如，“001”表示仅支持第一方案，“010”表示仅支持第二方案，“100”表示仅支持第三方案，而“111”则表示这三种方案都支持。可以理解，还可以有其它的模式数据的表示方式，例如引入更多的数据位或数据图案来表征更多的休眠方案。备选地，模式数据也可以在休眠之前约定协商，例如通过发送请求和回复确认信息来确认所使用的休眠模式。
第二芯片20将表示其所支持的第二休眠模式的第二模式数据发送至第一芯片10。第一芯片10继而可以基于第一芯片10所支持的第一休眠模式和第二模式数据确定第一芯片10将使用的休眠模式。随后，第一芯片10和第二芯片20可以分别前文所述地进入休眠模式。在一些实施例中，第一模式数据和第二模式数据可以被加密。此外，上文所述的休眠请求、确认信息和唤醒电路指定数据也可以被加密。接收端在接收到加密数据之后可以对其进行解密 以获得原始数据。可以理解，在本公开的一些实施例中，加密和解密并非必需。
在一个实施例中，第一芯片10和第二芯片20的上述所支持的休眠模式的通信过程可以在系统上电之时就执行。在另一实施例中，上述所支持的休眠模式的通信过程可以在发送休眠请求之前、或与发送休眠请求和回复确认信息的同时、或在回复确认休息之后但在进入休眠模式之前执行。本公开对此不进行限制。
在本公开的一些实施例中，芯片所支持的休眠模式包括第一方案、第二方案和第三方案。在第一方案中，芯片的各个唤醒电路在休眠模式中均处于启用状态。在第二方案中，每个芯片中仅一个唤醒电路在休眠模式中处于启用状态，而剩余唤醒电路在休眠模式中处于禁用状态。在第三方案中，第一芯片和第二芯片中的一个芯片作为主设备操作，而另一芯片作为从设备操作，并且仅从设备的一个唤醒电路在休眠模式中处于启用状态，而主设备的所有唤醒电路和从设备的其他唤醒电路均处于禁用状态。下面将结合图5具体描述第三方案。
通过在休眠之前协商休眠模式，可以确保第一芯片和第二芯片能够以合适的休眠方案进行休眠，并且能够确保芯片中的收发通道能够被正确唤醒。可以理解，还可以有所支持的其他方案，例如每个芯片具有两个唤醒电路在休眠模式下处于启用状态，而其它唤醒电路处于禁用状态。
图5示出了根据本公开的另一实施例的低功耗系统的示意框图。图5的低功耗系统具有与图4的低功耗系统相似的配置，因此相同或相似之处在此不再赘述，上面针对图4描述的各个方面可以应用于图5的系统。图5与图4的不同之处在于第一芯片11仅具有一个第一唤醒电路S13，并且第二芯片21也仅具有一个第二唤醒电路S23。第一唤醒电路S13独立于第一接收器，并且第二唤醒电路S23独立于第二接收器。换言之，第一唤醒电路S13对应于三个第一接收器并且实际上被三个第一接收器共享。类似地，第二唤醒电路S23也对应于三个第二接收器并且实际上被三个第二接收器共享。虽然在图5中示出第一唤醒电路S13和第二唤醒电路S23位于接收器之外，但是第一唤醒电路S13和第二唤醒电路S23在一些实施例中也可以位于接收器内。例如，第一唤醒电路S13位于第一接收器RX13内，并且第一唤醒电路S13通过信号连线与第一接收器RX11和RX12连接以对其进行唤醒。类似地，第二唤醒电路S23位于第二接收器RX23内，并且第二唤醒电路S23通过信号连线与第二接收器RX21和RX22连接以对其进行唤醒。
在图5的低功耗系统中，第二芯片21作为主设备进行操作，并且第一芯片22作为从设备进行操作。下面介绍上文提及的第三休眠方案。第二芯片21可以向第一芯片11发送休眠请求。第一芯片11在接收到休眠请求之后，向第二芯片21发送确认信息。在此之后，第一芯片11进入第一休眠模式，并且在第一休眠模式中使得第一接收器RX11、RX12和RX13和第一发送器TX11、TX12和TX13处于禁用状态。第一芯片在第一休眠模式下使第一唤醒电路S13处于启用状态。由于第二芯片21和第一芯片11属于主从关系，因此只能由第二芯片21唤醒第一芯片11。在此情形下，第二芯片21的第二唤醒电路S23在第二休眠模式下可以处于禁用状态，因为其无需从第一芯片11接收唤醒信号。这样，在第一芯片11和第二芯片21的休眠模式下，集成电路系统中的两个芯片总共只有一个唤醒电路处于启用状态。
第二芯片21在发送唤醒信号之后的预定时间，启用第二芯片21的多个第二接收器中的至少一个第二接收器。附加地，第二芯片21还可以启用多个收发通道中的所有的接收器和发送器以用于正常操作。通过设置该预定时间，可以确定第一芯片11此时出于正常操作状态，而无需从第一芯片接收唤醒信号来确定第一芯片将处于正常工作状态。相比于图4的实施例 中，可以将休眠模式下的唤醒电路的功耗进一步降低一半。相比于图1的例子，休眠模式下的唤醒电路的总功耗实际上仅约为1/2N，例如1/32。由此可见，在图4的实施例中，可以极大程度地降低芯片休眠模式下的功耗。此外，在一个实施例中，第一芯片11和第二芯片21在进入各自的休眠模式之前，可以协商确定待在休眠模式中使用的休眠方案，例如使用第三休眠方案。
图6示出了根据本公开的一个实施例的示例过程600的流程图。可以理解，上面针对图1、图4和图5所描述的各个方面可以选择性地应用于过程600。在610，第二芯片20向第一管芯10发送第二休眠数据以将表示第二芯片20所支持的休眠方案的第二模式数据告知第一芯片10。第一芯片10在接收到第二模式数据之后，在613，第一芯片10基于第二模式数据和第一芯片所支持的休眠模式确定待使用的休眠模式。在620，第一芯片10向第二芯片20发送表示第一芯片10所支持的休眠方案的第一模式数据给第二芯片20。第二芯片20在625基于第一模式数据和第二芯片20所支持的休眠模式来确定待使用的休眠模式。在一个实施例中，可以省略610、613、620和625，例如芯片可以默认某种休眠模式而无需协商。
在630，第二芯片20向第一芯片10发送休眠请求。此外，在一些实施例中，还可以一起发送唤醒电路指定数据和与休眠相关的其它可能数据，例如休眠方案的选择。在640，第一芯片10向第二芯片回复确认信息。此外，在一些实施例中，还可以一起发送唤醒电路指定数据和与休眠相关的其它可能数据。在此之后，第一芯片10在643可以选择性地使收发通道中的第一接收器和第一发送器以及与第一接收器对应的第一唤醒电路处于禁用状态，如上文所述。第二芯片20在接收到确认信息之后，在645选择性地使收发通道中的第二接收器和第二发送器以及与接收器对应的第二唤醒电路处于禁用状态。此后，第一芯片10进入第一休眠模式，并且第二芯片20进入第二休眠模式。在另一实施例中，第二芯片20可以不进入第二休眠模式，而是继续正常工作。
在650，第二芯片20向第一芯片10的唤醒电路发送第一唤醒信号。第一芯片10的第一唤醒电路在接收到第一唤醒信号之后，第一芯片10在653选择性地唤醒收发通道中的至少一个第一接收器和第一发送器。在一个实施例中，第一唤醒电路可以先告知第一芯片10的控制器，并且控制器继而启用至少一个第一接收器和第一发送器。在另一实施例中，第一唤醒电路可以通过直接触发启用与其对应或相关的第一接收器和第一发送器。
在660，第一芯片10向第二芯片20的唤醒电路发送第二唤醒信号。第一芯片10在665选择性地唤醒收发通道中的至少一个第二接收器。在一个实施例中，第二唤醒电路可以先告知第二芯片20的控制器，并且控制器继而启用至少一个第二接收器。在另一实施例中，第二唤醒电路可以通过直接触发启用与其对应或相关的第二接收器。附加地，还可以基于第二唤醒信号启用第二发送器。通过使用如图6的流程，可以显著减少唤醒电路在休眠模式中的功耗，从而降低第一芯片10和第二芯片20的功耗以及包括第一芯片10和第二芯片20的集成电路系统和电子设备的总体功耗。
图7示出了根据本公开的另一实施例的示例过程700的流程图。可以理解，上面针对图1、图4和图5所描述的各个方面可以选择性地应用于过程700。在图7的实施例中，第二芯片20作为主设备操作，并且第一芯片10作为从设备操作。
在630，第二芯片20向第一芯片10发送休眠请求。此外，还可以一起发送唤醒电路指定数据和与休眠相关的其它可能数据。在640，第一芯片10向第二芯片回复确认信息。此外，还可以一起发送唤醒电路指定数据和与休眠相关的其它可能数据。在此之后，第一芯片10在 643可以选择性地使收发通道中的第一接收器和第一发送器以及与第一接收器对应的第一唤醒电路处于禁用状态，如上文所述。第二芯片20在接收到确认信息之后，在645选择性地使收发通道中的第二接收器和第二发送器以及与接收器对应的第二唤醒电路处于禁用状态。此后，第一芯片10进入第一休眠模式，并且第二芯片20进入第二休眠模式。在另一实施例中，第二芯片20可以不进入第二休眠模式，而是继续正常工作。
在650，第二芯片20向第一芯片10的唤醒电路发送第一唤醒信号。第一芯片10的第一唤醒电路在接收到第一唤醒信号之后，第一芯片10在653选择性地唤醒收发通道中的至少一个第一接收器和第一发送器。在755，第二芯片20确定在发送第一唤醒信号之后的预定时间，启用第二芯片20的多个第二接收器中的至少一个第二接收器。附加地，还可以在预定时间启用第二发送器。通过使用如图7的流程，可以显著减少唤醒电路在休眠模式中的功耗，从而降低第一芯片10和第二芯片20的功耗以及包括第一芯片10和第二芯片20的集成电路系统和电子设备的总体功耗。
图8示出了根据本公开的一个实施例的示例方法800的流程图。可以理解，上面针对图4-图7所描述的各个方面可以选择性地应用于方法800。在802，控制第一芯片中的多个第一接收器和一个或多个唤醒电路的状态，其中多个第一接收器在第一休眠模式中处于禁用状态，一个或多个第一唤醒电路中的至少一个第一唤醒电路在第一休眠模式中处于启用状态，一个或多个第一唤醒电路与多个第一接收器对应，至少一个第一唤醒电路的数目少于多个第一接收器的数目。在804，响应于至少一个第一唤醒电路接收到第一唤醒信号，启用多个第一接收器中的至少一个第一接收器。
图9示出了根据本公开的另一实施例的示例方法900的流程图。可以理解，上面针对图4-图7所描述的各个方面可以选择性地应用于方法900。在902，控制第二芯片中的多个第二接收器和一个或多个第二唤醒电路的状态，其中多个第二接收器和一个或多个第二唤醒电路中的至少一个第二唤醒电路在第二休眠模式中处于禁用状态，一个或多个第二唤醒电路与多个第二接收器对应。在904，响应于进入工作模式，向第一芯片发送第一唤醒信号，第二芯片不同于第一芯片。在906，在发送唤醒信号之后的预定时间，启用第二芯片的多个第二接收器中的至少一个第二接收器。
图10示出了根据本公开的另一实施例的示例方法1000的流程图。可以理解，上面针对图4-图7所描述的各个方面可以选择性地应用于方法1000。在1002，控制第一芯片中的多个第一接收器和一个或多个第一唤醒电路的状态，其中多个第一接收器在第一休眠模式中处于禁用状态，一个或多个第一唤醒电路中的至少一个第一唤醒电路在第一休眠模式中处于启用状态，一个或多个第一唤醒电路与多个第一接收器对应，其中至少一个第一唤醒电路的数目少于多个第一接收器的数目。在1004，控制第二芯片中的多个第二接收器的状态，其中多个第二接收器在第二休眠模式中处于禁用状态，第二芯片不同于第一芯片。在1006，响应于至少一个第一唤醒电路接收到第一唤醒信号，启用多个第一接收器中的至少一个第一接收器。
图11示出了根据本公开的一个实施例的唤醒电路S0的电路示意图。唤醒电路S0可以适用于图4-图5中所示的框图。可以理解，上面针对图4-图7所描述的关于唤醒电路的各个方面可以选择性地应用于唤醒电路S0。唤醒电路S0具有第一输入VIN和第二输入VIP以用于接收来自对方芯片的唤醒信号。在一个实施例中，第一输入VIN和第二输入VIP可以是芯片的管脚输入。唤醒电路S0还具有第一参考电压输入VREFP和第二参考电压输入VREFN。在一个实施例中，第一参考电压输入VREFP和第二参考电压输入VREFN被配置用于接收芯 片内部的可调节输入电压。唤醒电路S0还包括输出端子VOUT。在一个实施例中，输出端子VOUT输出的电压可以由下式表示：
VOUT＝(VREFN-VREFP)-(VIN-VIP)
在一个实施例中，当在休眠模式下，输出端子VOUT的输出电压为0。当唤醒电路S0从第一输入VIN和第二输入VIP接收到唤醒信号时，输出端子VOUT的输出电压为1以用于唤醒芯片中的接收器和/或发送器。虽然在图11中具体示出了唤醒电路的一种实现方式，但是可以理解，还可以有其它实现方式。此外，输出端子VOUT输出的电压也可以具有其它图案(pattern)以表征更多的信息。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (28)

  1. 一种用于控制第一芯片的方法，包括：
    控制所述第一芯片中的多个第一接收器和一个或多个唤醒电路的状态，其中所述多个第一接收器在第一休眠模式中处于禁用状态，所述一个或多个第一唤醒电路中的至少一个第一唤醒电路在所述第一休眠模式中处于启用状态，所述一个或多个第一唤醒电路与所述多个第一接收器对应，所述至少一个第一唤醒电路的数目少于所述多个第一接收器的数目；以及
    响应于所述至少一个第一唤醒电路接收到第一唤醒信号，启用所述多个第一接收器中的至少一个第一接收器。
  2. 根据权利要求1所述的方法，其中所述一个或多个第一唤醒电路中的至少一个第一唤醒电路在所述第一休眠模式中处于启用状态包括：所述一个或多个第一唤醒电路中的仅一个第一唤醒电路在所述第一休眠模式中处于所述启用状态。
  3. 根据权利要求2所述的方法，其中所述一个或多个第一唤醒电路中的至少一个第一唤醒电路在所述第一休眠模式中处于启用状态包括：所述一个或多个第一唤醒电路中的仅一个位于所述多个第一接收器中的一个第一接收器中的第一唤醒电路处于所述启用状态。
  4. 根据权利要求1-3中任一项所述的方法，还包括：
    响应于所述至少一个第一唤醒电路接收到第一唤醒信号，启用所述第一芯片中的第一发送器以发送第二唤醒信号至第二芯片的第二接收器，所述第二芯片不同于所述第一芯片。
  5. 根据权利要求4所述的方法，还包括：
    在所述第一芯片的第一发送器被启用达第一预定时段之后，所述第一发送器与所述第二芯片中的第二接收器开始进行通信；以及
    在所述至少一个第一接收器被启用达第二预定时段之后，所述至少一个第一接收器与所述第二芯片中的第二发送器开始进行通信。
  6. 根据权利要求1-5中任一项所述的方法，还包括：
    在进入所述第一休眠模式之前，由所述第一芯片的第一发送器发送第一模式数据至第二芯片的第二接收器，所述第一模式数据表示所述第一芯片的所支持的第一休眠模式；
    所述第一芯片的所述第一接收器接收来自所述第二芯片的第二发送器的第二模式数据，所述第二模式数据表示所述第二芯片所支持的第二休眠模式；以及
    基于所述第一芯片的所支持的第一休眠模式和所述第二模式数据，确定待由所述第一芯片使用的所述第一休眠模式。
  7. 根据权利要求1-6中任一项所述的方法，还包括：
    在进入所述第一休眠模式之前，由所述第一芯片的多个第一接收器从第二芯片的多个第二发送器接收唤醒电路指定数据，所述第二芯片不同于所述第一芯片；以及
    基于所述唤醒电路指定数据，确定所述一个或多个第一唤醒电路的、待在所述第一休眠模式中被启用的所述至少一个第一唤醒电路。
  8. 一种用于控制第二芯片的方法，包括：
    控制所述第二芯片中的多个第二接收器和一个或多个第二唤醒电路的状态，其中所述多个第二接收器和所述一个或多个第二唤醒电路中的至少一个第二唤醒电路在第二休眠模式中处于禁用状态，所述一个或多个第二唤醒电路与所述多个第二接收器对应；
    响应于进入工作模式，向第一芯片发送第一唤醒信号，所述第二芯片不同于所述第一芯 片；以及
    在发送所述唤醒信号之后的预定时间，启用所述第二芯片的所述多个第二接收器中的至少一个第二接收器。
  9. 根据权利要求8所述的方法，其中所述第二芯片作为主设备进行操作，并且所述第一芯片作为从设备进行操作。
  10. 根据权利要求8或9所述的方法，其中所述多个第二接收器和所述一个或多个第二唤醒电路中的至少一个第二唤醒电路在第二休眠模式中处于禁用状态包括：
    所述一个或多个第二唤醒电路中的全部第二唤醒电路在所述第二休眠模式中处于所述禁用状态。
  11. 一种用于控制芯片的方法，包括：
    控制第一芯片中的多个第一接收器和一个或多个第一唤醒电路的状态，其中所述多个第一接收器在第一休眠模式中处于禁用状态，所述一个或多个第一唤醒电路中的至少一个第一唤醒电路在所述第一休眠模式中处于启用状态，所述一个或多个第一唤醒电路与所述多个第一接收器对应，其中所述至少一个第一唤醒电路的数目少于所述多个第一接收器的数目；
    控制第二芯片中的多个第二接收器的状态，其中所述多个第二接收器在第二休眠模式中处于禁用状态，所述第二芯片不同于所述第一芯片；以及
    响应于所述至少一个第一唤醒电路接收到第一唤醒信号，启用所述多个第一接收器中的至少一个第一接收器。
  12. 根据权利要求11所述的方法，其中所述一个或多个第一唤醒电路中的至少一个第一唤醒电路在所述第一休眠模式中处于启用状态包括：所述一个或多个第一唤醒电路中的仅一个第一唤醒电路在所述第一休眠模式中处于启用状态。
  13. 根据权利要求11或12所述的方法，其中
    所述第二芯片中的一个或多个第二唤醒电路中的至少一个第二唤醒电路在所述第二休眠模式中处于启用状态，所述一个或多个第二唤醒电路与所述多个第二接收器对应，其中所述至少一个第二唤醒电路的数目少于所述多个第二接收器的数目。
  14. 根据权利要求13所述的方法，其中所述第二芯片中的一个或多个第二唤醒电路中的至少一个第二唤醒电路在所述第二休眠模式中处于启用状态包括：
    所述一个或多个第二唤醒电路中的仅一个第二唤醒电路在所述第二休眠模式中处于启用状态。
  15. 根据权利要求11或12所述的方法，还包括：
    第二芯片中的全部的第二唤醒电路在所述第二休眠模式中处于禁用状态。
  16. 根据权利要求11-15中任一项所述的方法，还包括：
    在进入所述休眠模式之前，由所述第一芯片的第一发送器发送第一模式数据至所述第二芯片的第二接收器，所述第一模式数据表示所述第一芯片的所支持的休眠模式；
    由所述第二芯片的发送器发送第二模式数据至所述第一芯片的第一接收器，所述第二模式数据表示所述第二芯片的所支持的休眠模式；以及
    所述第一芯片基于所述第一芯片的所支持的休眠模式和所述第二模式数据，确定待由所述第一芯片使用的休眠模式；以及
    所述第二芯片基于所述第二芯片的所支持的休眠模式和所述第一模式数据，确定待由所述第二芯片使用的休眠模式。
  17. 根据权利要求11-16中任一项所述的方法，还包括：
    在进入所述休眠模式之前，由所述第一芯片的多个第一接收器接收来自所述第二芯片的多个第二发送器的唤醒电路指定数据；以及
    基于所述唤醒电路指定数据，确定所述第一芯片中的、待在所述第一休眠模式中被启用的所述至少一个第一唤醒电路。
  18. 一种第一芯片，包括：
    多个第一接收器，被配置为在第一休眠模式中处于禁用状态；以及
    一个或多个第一唤醒电路，与所述多个第一接收器对应，所述一个或多个第一唤醒电路中的至少一个第一唤醒电路被配置为在所述第一休眠模式中处于启用状态，其中所述至少一个第一唤醒电路的数目少于所述多个第一接收器的数目；
    其中所述至少一个唤醒电路被进一步配置为响应于接收到第一唤醒信号，使得所述多个第一接收器中的至少一个第一接收器被启用。
  19. 根据权利要求18所述的第一芯片，其中所述至少一个第一唤醒电路包括仅一个第一唤醒电路。
  20. 根据权利要求19所述的第一芯片，其中所述仅一个第一唤醒电路位于所述多个第一接收器中的一个第一接收器中。
  21. 一种第二芯片，包括：
    多个第二接收器，被配置为在第二休眠模式中处于禁用状态；
    一个或多个第二唤醒电路，与所述多个第二接收器对应，所述一个或多个第二唤醒电路中的至少一个第二唤醒电路被配置为在所述第二休眠模式中处于禁用状态；
    多个第二发送器，被配置为：
    响应于进入工作模式，向第一芯片发送第一唤醒信号，所述第一芯片不同于所述第二芯片；以及
    在发送所述第一唤醒信号之后的预定时间，使得所述多个第二接收器中的至少一个第二接收器被启用。
  22. 根据权利要求21所述的第二芯片，其中所述第二芯片被配置为主设备，并且所述第一芯片被配置为从设备。
  23. 根据权利要求21或22所述的第二芯片，其中所述一个或多个第二唤醒电路被配置为在所述第二休眠模式中全部被禁用。
  24. 一种集成电路系统，包括：
    第一芯片，包括：
    多个第一接收器，被配置为在第一休眠模式中处于禁用状态；以及
    一个或多个第一唤醒电路，与所述多个第一接收器对应，所述一个或多个第一唤醒电路中的至少一个第一唤醒电路被配置为在所述第一休眠模式中处于启用状态，其中所述至少一个第一唤醒电路的数目少于所述多个第一接收器的数目；
    其中所述至少一个唤醒电路被进一步配置为响应于接收到第一唤醒信号，使得所述多个第一接收器中的至少一个第一接收器被启用；以及
    第二芯片，包括：
    多个第二接收器，被配置为在第二休眠模式中处于禁用状态。
  25. 根据权利要求24所述的集成电路系统，其中所述至少一个第一唤醒电路包括仅一个 第一唤醒电路。
  26. 根据权利要求24或25所述的集成电路系统，其中所述第二芯片还包括：
    一个或多个第二唤醒电路，所述一个或多个第二唤醒电路中的至少一个第二唤醒电路被配置为在所述第二休眠模式中处于启用状态。
  27. 根据权利要求24或25所述的集成电路系统，其中所述第二芯片还包括：
    一个或多个第二唤醒电路，所述一个或多个第二唤醒电路被配置为在所述第二休眠模式中全部处于禁用状态。
  28. 一种电子设备，包括：
    电路板；以及
    根据权利要求24-27中任一项所述集成电路系统，被设置在所述电路板上。
PCT/CN2021/084110 2021-03-30 2021-03-30 控制芯片的方法和集成电路系统 WO2022204990A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2021/084110 WO2022204990A1 (zh) 2021-03-30 2021-03-30 控制芯片的方法和集成电路系统
CN202180093544.5A CN116868177A (zh) 2021-03-30 2021-03-30 控制芯片的方法和集成电路系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/084110 WO2022204990A1 (zh) 2021-03-30 2021-03-30 控制芯片的方法和集成电路系统

Publications (1)

Publication Number Publication Date
WO2022204990A1 true WO2022204990A1 (zh) 2022-10-06

Family

ID=83455407

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/084110 WO2022204990A1 (zh) 2021-03-30 2021-03-30 控制芯片的方法和集成电路系统

Country Status (2)

Country Link
CN (1) CN116868177A (zh)
WO (1) WO2022204990A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115985021A (zh) * 2023-03-21 2023-04-18 深圳鼎智通讯有限公司 双芯片pos机的唤醒方法
CN116414212A (zh) * 2023-04-13 2023-07-11 海光信息技术股份有限公司 芯粒以及芯粒的控制方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1893696A (zh) * 2005-07-04 2007-01-10 中兴通讯股份有限公司 一种双模终端及其内部芯片间控制和通信的方法
CN101872995A (zh) * 2010-05-17 2010-10-27 深圳市金溢科技有限公司 电子自动收费车载单元
CN102547935A (zh) * 2011-12-23 2012-07-04 华为终端有限公司 一种控制便携式路由器低功耗工作的方法及便携式路由器
US20130290572A1 (en) * 2011-03-09 2013-10-31 Apple Inc. Client device configuration based on information stored by host device
CN106796563A (zh) * 2014-07-18 2017-05-31 高通股份有限公司 用于芯片到芯片通信的系统和方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1893696A (zh) * 2005-07-04 2007-01-10 中兴通讯股份有限公司 一种双模终端及其内部芯片间控制和通信的方法
CN101872995A (zh) * 2010-05-17 2010-10-27 深圳市金溢科技有限公司 电子自动收费车载单元
US20130290572A1 (en) * 2011-03-09 2013-10-31 Apple Inc. Client device configuration based on information stored by host device
CN102547935A (zh) * 2011-12-23 2012-07-04 华为终端有限公司 一种控制便携式路由器低功耗工作的方法及便携式路由器
CN106796563A (zh) * 2014-07-18 2017-05-31 高通股份有限公司 用于芯片到芯片通信的系统和方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115985021A (zh) * 2023-03-21 2023-04-18 深圳鼎智通讯有限公司 双芯片pos机的唤醒方法
CN116414212A (zh) * 2023-04-13 2023-07-11 海光信息技术股份有限公司 芯粒以及芯粒的控制方法
CN116414212B (zh) * 2023-04-13 2024-02-13 海光信息技术股份有限公司 芯粒以及芯粒的控制方法

Also Published As

Publication number Publication date
CN116868177A (zh) 2023-10-10

Similar Documents

Publication Publication Date Title
US9886993B2 (en) Protocol for memory power-mode control
US8683091B2 (en) Device disconnect detection
US9239810B2 (en) Low power universal serial bus
JP5335919B2 (ja) Ｕｓｂリモートウェイクアップ
CN102959487B (zh) 提供用于将电子设备从低功率模式唤醒的唤醒逻辑
WO2019104947A1 (zh) 系统级芯片、通用串行总线主设备、系统及唤醒方法
WO2022204990A1 (zh) 控制芯片的方法和集成电路系统
US8683097B2 (en) Device connect detection
JP2005018729A (ja) 即時スリープ解除機能付き無線信号受信装置及び無線信号受信装置の即時スリープ解除方法
US9588562B2 (en) Method for waking up a distant device from a local device without waking up a physical layer unit in the distant device
US8837468B1 (en) Network device and method for powering a media access controller
US11048315B2 (en) Remote wake-up of mobile devices
KR20130113203A (ko) 전자 장치 및 전자 장치의 파워 관리 방법
TWI654516B (zh) 使用兩線串列介面之串列傳輸方法及包括兩線串列介面之系統及積體電路裝置
JP2008186462A (ja) Ｓａｔａインターフェースでのパワーセービング・モード制御方法
US7912989B2 (en) Network interface for decreasing power consumption
KR20070020952A (ko) 호스트 웨이크업 기능을 갖는 와이파이(Ｗｉ－Ｆｉ) 모듈및 그 와이파이 모듈에서의 호스트 웨이크업 방법
US20240111354A1 (en) Power management for peripheral component interconnect
KR100403371B1 (ko) 범용 직렬 버스를 이용한 무선 단말기의 전원 공급 장치및 방법
KR20170088750A (ko) 반도체 장치, 반도체 시스템 및 반도체 장치의 동작 방법
JP6827991B2 (ja) 通信装置、転送速度変更方法およびプログラム

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21933671

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180093544.5

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21933671

Country of ref document: EP

Kind code of ref document: A1