WO2022201814A1 - 半導体装置、撮像装置 - Google Patents
半導体装置、撮像装置 Download PDFInfo
- Publication number
- WO2022201814A1 WO2022201814A1 PCT/JP2022/002109 JP2022002109W WO2022201814A1 WO 2022201814 A1 WO2022201814 A1 WO 2022201814A1 JP 2022002109 W JP2022002109 W JP 2022002109W WO 2022201814 A1 WO2022201814 A1 WO 2022201814A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- wiring
- substrate
- rewiring
- region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 165
- 238000003384 imaging method Methods 0.000 title claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 42
- 239000010410 layer Substances 0.000 description 27
- 238000001514 detection method Methods 0.000 description 23
- 238000012545 processing Methods 0.000 description 23
- 238000005516 engineering process Methods 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 19
- 239000010949 copper Substances 0.000 description 19
- 238000004891 communication Methods 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 230000004888 barrier function Effects 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 230000003287 optical effect Effects 0.000 description 13
- 238000002674 endoscopic surgery Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 238000001356 surgical procedure Methods 0.000 description 5
- 230000005284 excitation Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 208000005646 Pneumoperitoneum Diseases 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000010336 energy treatment Methods 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 210000004204 blood vessel Anatomy 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- MOFVSTNWEDAEEK-UHFFFAOYSA-M indocyanine green Chemical compound [Na+].[O-]S(=O)(=O)CCCCN1C2=CC=C3C=CC=CC3=C2C(C)(C)C1=CC=CC=CC=CC1=[N+](CCCCS([O-])(=O)=O)C2=CC=C(C=CC=C3)C3=C2C1(C)C MOFVSTNWEDAEEK-UHFFFAOYSA-M 0.000 description 2
- 229960004657 indocyanine green Drugs 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000002194 synthesizing effect Effects 0.000 description 2
- 240000004050 Pentaglottis sempervirens Species 0.000 description 1
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000000740 bleeding effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002073 fluorescence micrograph Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
Definitions
- the present technology relates to a semiconductor device and an imaging device, and for example, to a semiconductor device and an imaging device in which wirings formed on a substrate surface are adjusted to have a uniform film thickness.
- back-illuminated solid-state imaging devices that use the back side of the semiconductor substrate as the light incident surface are widespread.
- Such a back-illuminated solid-state imaging device is joined such that the wiring layers of the first semiconductor device that performs signal processing and the wiring layers of the second semiconductor device that is the back-illuminated solid-state imaging device face each other. , is proposed to be integrated into one chip (see, for example, Patent Document 1).
- wiring for extracting signals from wiring layers to the outside is formed, for example, by electrolytic plating on the substrate of the first semiconductor element. Due to, for example, restrictions on the layout of the wiring, there is a possibility that regions of dense wiring and regions of sparse wiring may coexist. If there is a difference in density between wirings, there will be a difference in density of electric lines of force during plating.
- This technology was developed in view of this situation, and is designed to prevent differences in wiring height.
- a semiconductor device includes a substrate, a wiring layer on a first surface of the substrate, and a first wiring layer provided on a second surface of the substrate facing the first surface. and a through electrode that connects the second wiring and the first wiring in the wiring layer and penetrates the substrate, and a part of the first wiring has an uneven region. It is a device.
- An imaging device includes a first chip on which a solid-state imaging element is formed, and a second chip that processes a signal from the first chip, the second chip comprising: a substrate, a wiring layer on a first surface of the substrate, a first wiring provided on a second surface of the substrate facing the first surface, and a second wiring in the wiring layer and a through electrode penetrating through the substrate, wherein a part of the first wiring has an uneven region.
- a through electrode that connects the second wiring and the first wiring in the wiring layer and penetrates the substrate, and a part of the first wiring has an uneven region.
- An imaging device includes a first chip on which a solid-state imaging element is formed, and a second chip that processes signals from the first chip.
- the second chip is configured to include the semiconductor device.
- the imaging device may be an independent device, or may be an internal block that constitutes one device.
- FIG. 1 is a diagram illustrating a configuration example of an embodiment of a semiconductor device to which the present technology is applied;
- FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment;
- FIG. FIG. 4 is a diagram for explaining determination of wiring density; It is a figure for demonstrating manufacture of a semiconductor device. It is a figure for demonstrating manufacture of a semiconductor device.
- FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device according to a second embodiment; It is a figure for demonstrating manufacture of a semiconductor device. It is a figure for demonstrating manufacture of a semiconductor device.
- FIG. 11 is a cross-sectional view showing a configuration example of a semiconductor device according to a third embodiment; FIG.
- FIG. 14 is a cross-sectional view showing a configuration example of a semiconductor device according to a fourth embodiment
- FIG. 11 is a cross-sectional view showing a configuration example of a semiconductor device according to a fifth embodiment
- FIG. 21 is a cross-sectional view showing a configuration example of a semiconductor device according to a sixth embodiment
- FIG. 21 is a cross-sectional view showing a configuration example of a semiconductor device according to a seventh embodiment; It is a figure for demonstrating manufacture of a semiconductor device. It is a figure for demonstrating manufacture of a semiconductor device.
- FIG. 21 is a cross-sectional view showing a configuration example of a semiconductor device according to an eighth embodiment;
- FIG. 21 is a cross-sectional view showing a configuration example of a semiconductor device according to a ninth embodiment;
- FIG. 21 is a cross-sectional view showing a configuration example of a semiconductor device according to a tenth embodiment;
- FIG. 21 is a cross-sectional view showing a configuration example of a semiconductor device according to an eleventh embodiment; It is a figure for demonstrating manufacture of a semiconductor device. It is a figure which shows an example of an electronic device.
- 1 is a diagram showing an example of a schematic configuration of an endoscopic surgery system;
- FIG. 3 is a block diagram showing an example of functional configurations of a camera head and a CCU;
- FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system;
- FIG. FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;
- a semiconductor device including an imaging device chip such as a CCD (Charged-Coupled Device) or a CMOS (Complementary Metal-Oxide Semiconductor).
- Light-receiving elements such as PD (Photo Diode), MEMS (Micro Electro Mechanical Systems) elements such as optical switches and mirror devices, Laser Diodes (LDs) and LEDs (Light Emitting Diodes), Vertical cavity surface emitting lasers ( It can also be applied to a semiconductor device including a chip of an optical element such as a light emitting element such as a vertical cavity surface emitting laser (VCSEL).
- PD Photo Diode
- MEMS Micro Electro Mechanical Systems
- LDs Laser Diodes
- LEDs Light Emitting Diodes
- VCSEL vertical cavity surface emitting laser
- FIG. 1 is a plan view showing a configuration example of a semiconductor device 11a according to the first embodiment.
- FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device 11a taken along line segment A-A' in the upper diagram of FIG.
- the semiconductor device 11a has a silicon substrate 32 on a wiring layer 31, and an insulating film 33 is formed on the silicon substrate 32.
- a rewiring 22 - 7 is provided on the insulating film 33 .
- the rewiring 22-7 is formed on the surface on which the insulating film 33 is formed (hereinafter referred to as the upper surface).
- FIG. 1 is a diagram showing a configuration example of part of the upper surface of the semiconductor device 11a, and rewirings 22-1 to 22-9 are formed in part of the semiconductor device 11a.
- the rewirings 22-1 to 22-5 are formed in the left region in the drawing
- the rewirings 22-6 and 22-7 are formed in the upper right region in the drawing
- the rewirings 22-8 and 22-9 are formed in the upper right region. , are formed in the lower right region in the figure.
- the rewirings 22-1 to 22-9 will simply be referred to as the rewirings 22 when there is no need to distinguish them individually. Other parts are similarly described.
- One end of the rewiring 22 is connected to the through-electrode 21, and the other end is provided with an uneven formation region 23.
- one end of the rewiring 22-1 is connected to the through electrode 21-1, and the other end thereof is provided with the irregularity forming region 23-1.
- a through electrode 21-7 is connected to one end of the rewiring 22-7, and as shown in FIG. 36 is connected. Other through electrodes 21 are similarly electrically connected to the wiring layer 31 .
- the rewiring 22 is made of Cu (copper), for example.
- the through electrode 21-7 is formed on the insulating film 33, the barrier metal film 34, and the seed film 35 laminated on the side surface of the through hole.
- the through electrode 21-7 is formed integrally with the rewiring 22-7.
- Inorganic films such as SiO2, SiN, SiON, and low-k films can be used as the material of the insulating film 33 .
- As materials for the barrier metal film 34 tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), and their nitride films and carbide films can be used.
- An uneven formation region 23-7 is formed in the rewiring 22-7.
- a non-through hole 41 having the same configuration as the through electrode 21-7 is formed in the irregularity forming region 23-7.
- One non-through hole 41 is formed in the example shown in FIG. The non-through hole 41 is provided to reduce the influence of the wiring density difference of the rewiring 22 .
- the rewiring 22 includes the through electrode 21 and the irregularity formation region 23 (the non-through holes 41 formed in the irregularity formation region 23). I will continue to explain.
- the rewiring 22 arranged on the upper surface of the semiconductor device 11a has layout restrictions, and there are cases where the rewiring 22 cannot be arranged on the entire upper surface.
- the upper surface of the semiconductor device 11a has a region where the rewiring 22 is formed and a region where the rewiring 22 is not formed.
- the rewiring 22 is formed by electrolytic plating, for example. Therefore, if there is a difference in the density of the rewiring 22, a difference in the density of the lines of electric force will occur, and as a result, the height (thickness) of the rewiring 22 may vary from place to place. Specifically, since the electric field concentrates on the rewiring 22 in a region where the density of the rewiring 22 is low, the height of the rewiring 22 increases (the film thickness increases). On the other hand, since the electric field is dispersed in the rewiring 22 in the region where the density of the rewiring 22 is high, the height of the rewiring 22 is lowered (thickness is reduced).
- the rewiring lines 22 formed in the semiconductor device 11a are formed in the uneven formation region 23 as shown in FIG. A non-through hole 41 is formed.
- the non-through holes 41 in the rewiring 22 that may be thickened, the extra material of the rewiring 22 is absorbed by the non-through holes 41, and the film thickness of the rewiring 22 is increased. can be prevented.
- FIG. 2 shows the case where one non-through hole 41 is formed in the irregularity forming region 23, a plurality of non-through holes 41 may be formed (described later as a second embodiment).
- the depth and width (size) of the non-through holes 41 may be set according to the degree of sparseness of the rewirings 22 .
- the area to be plated on the upper surface of the semiconductor device 11 (the area where the rewiring 22 including the through electrode 21 is formed) is uniform over the entire upper surface, so that adjustment can be made in the irregularity forming area 23. It is configured.
- the area to be plated around the rewiring 22 can be adjusted by changing the number, depth, diameter, etc. of the non-through holes 41 provided in the concave-convex forming region 23 . . That is, the shape of the non-through hole 41 can be designed according to the degree of density difference of the rewirings 22, and the height variation of the rewirings 22 can be eliminated.
- the depth of the non-through holes 41 may be increased, or the size (diameter) of the opening may be increased.
- the depth of the non-through hole 41 may be provided to a position that does not contact the wiring layer 31 , in other words, to a position that does not penetrate the silicon substrate 32 .
- the rewiring 22 tends to be low (film thickness is thin) in the vicinity of the through electrode 21, if the non-through hole 41 is formed near the through electrode 21, the rewiring 22 near the through electrode 21 will be reduced. height may be lower.
- the positions of the non-through holes 41 can be set so that the through electrodes 21 and the non-through holes 41 are separated from each other to such an extent that there is no effect on the film thickness.
- the through electrode 21 and the non-through hole 41 can be set apart from each other by 200 ⁇ m or more.
- the depth of the non-through hole 41 and the diameter of the opening can be made about 70% or less of the depth of the through electrode 21 and the diameter of the opening. By making it 70% or less, the through electrode 21 and the non-through hole 41 can be processed in the same process during manufacturing. In addition, when the insulating film 33 is etched back, the wiring 36 under the through electrode 21 can be exposed without opening the bottom portion of the through electrode 21, and the unevenness forming region 23 can be exposed without increasing the number of steps. A through hole 41 can be formed.
- the non-through hole 41 shown in FIG. 2 shows a case where the inside of the non-through hole 41 is hollow. is also good (described later as a fourth embodiment). If Cu is buried inside the non-through hole 41, the wiring cross-sectional area increases, so that the resistance value can be reduced, the EM (Electro Migration) resistance can be improved, and the rewiring 22 and the insulating film 33 can be connected. It is possible to improve the adhesion of the interface with.
- the rewiring 22 having a higher height is provided with the uneven formation region 23 .
- One or a plurality of non-penetrating vias are formed in the irregularity forming region 23 for adjusting the film thickness.
- the surface of the semiconductor device 11a on which the rewiring 22 is formed is virtually divided into grids of a predetermined size, and the drawing area density within each division is calculated.
- the numerical values shown in each section in the left diagram of FIG. 3 indicate the drawing area density.
- the drawing area density can be the ratio of the resist applied to areas other than the portion where the wiring is formed when the rewiring 22 is formed by plating.
- the drawing area density can also be said to be the area other than the area where the wiring in the section is formed. Therefore, areas where the drawing area density is high have a high ratio of resist and are areas where wiring is formed are small.
- the drawing area density of section 101-1 is 55%, the drawing area density of section 101-2 is 100%, and the drawing area density of section 101-3 is 100%.
- the drawing area density of the section 101-4 is 30%, the drawing area density of the section 101-5 is 60%, and the drawing area density of the section 101-6 is 65%.
- the drawing area density of the section 101-7 is 100%, the drawing area density of the section 101-8 is 100%, and the drawing area density of the section 101-9 is 65%.
- the drawing area density of the sections surrounding the section 101-5 is also used instead of the drawing area density of the section 101-5. judgment is made.
- the average value of the drawing area densities of the sections 101-1 to 101-9 is calculated, and it is determined whether or not the average value is equal to or greater than a predetermined threshold value, thereby determining whether or not the area is sparse. An example in which determination is made will be described.
- the threshold is set to 70% and is set to be determined as sparse when 70% or more, the section 101-5 is determined to be a sparse area.
- the shape and size of the concave-convex forming region 23 of the rewiring 22 may be set based on the average value of the drawing area density.
- the sparseness and density of a predetermined section is determined only by the drawing area density of the section.
- the rewirings 22-1 to 22-5 shown in FIG. 1 are arranged at regular intervals and formed to have approximately the same length.
- the drawing area density is likely to be the same, there is a high possibility that the same determination as sparse or dense is made.
- the rewiring 22-1 and the rewiring 22-2 are arranged on both sides of the rewiring 22-2. Therefore, considering the rewiring 22-2 and its surroundings, it is determined that the rewiring 22-2 is dense.
- the rewiring 22-1 when focusing on the rewiring 22-1, the rewiring 22-1 has the rewiring 22-2 on the right side, but the rewiring 22 is not arranged on the left side. Therefore, considering the rewiring 22-1 and its surroundings, it is determined that the rewiring 22-1 is sparse.
- the degree of provision of the irregularity forming region 23, specifically, the size, depth, etc. of the irregularity forming region 23 is set.
- the rewiring 22 determined to be sparse
- the concave-convex formed region 23-1 of -1 is formed larger than the concave-convex formed region 23-2 of the rewiring 22-2 determined to be dense.
- the size and shape of the concave-convex forming region 23 may be set according to the average value of the drawing area density calculated for the rewiring 22 .
- the method of determining the sparseness and denseness given here is an example, and does not represent a limitation, and the determination may be made by another determination method. Further, the shape, size, etc. of the concave-convex forming region 23 may be set according to the determination result (numerical value).
- the size, depth, etc. of the unevenness forming region 23 are set so that the area to be plated per unit area of the upper surface of the semiconductor device 11 is uniform over the entire upper surface.
- non-through holes 41 are formed in the silicon substrate 32 on the wiring layer 31 .
- through holes are formed at positions where the through electrodes 21 will be formed.
- step S11 and step S12 can be performed simultaneously, and non-through hole 41 and through electrode 21 (through holes) can be formed at the same time with the same mask.
- the non-through hole 41 and the through electrode 21 can be formed by lithography and dry etching.
- the insulating film 33 is formed by a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like.
- the insulating film 33 is etched back by dry etching to expose the wiring 36 in the wiring layer 31 connected to the through electrode 21 .
- the diameter and depth of the non-through hole 41 are set to about 70% or less of the diameter and depth of the through electrode 21, so that the insulating film 33 at the bottom of the non-through hole 41 is left open even after etching back. can prevent you from doing it.
- the insulating film 33 in the field portion (upper portion of the through electrode 21) is thicker than the insulating film 33 in the bottom portion of the through electrode 21. Therefore, the insulating film 33 is etched back. Also, the insulating film in the field portion does not disappear.
- a barrier metal film 34 is formed and a seed film 35 is formed by a PVD (Physical Vapor Deposition) method, a CVD method, an ALD method, or the like.
- Ta, TaN, Ti, or the like can be used for the barrier metal film 34 and Cu can be used for the seed film 35 .
- step S16 the portion other than the portion where the rewiring 22 is formed by lithography is covered with a resist 121, and in step S17, a Cu film, that is, the rewiring 22, is formed by Cu plating by a semi-additive method. be.
- the ratio of the area covered with the resist 121 can be used as the drawing area density described above.
- step S18 the resist 121 is removed by wet etching, and in step S19, the seed film 35 and the barrier metal film 34 under the resist 121 are removed in order.
- the rewiring 22 is formed, and the uneven formation region 23 (non-through hole 41) is formed.
- the manufacturing process shown here is an example, and is not a description showing limitation.
- the semiconductor device 11a as shown in FIG. 2 may be manufactured by other manufacturing processes.
- the upper diagram in FIG. 6 is a cross-sectional view showing a configuration example of a semiconductor device 11b according to the second embodiment, and the lower diagram in FIG. 6 corresponds to a cross-sectional configuration example taken along line segment AA' of the semiconductor device 11a of FIG. 7 are described as a through electrode 21, a rewiring 22, and an uneven formation region 23, respectively.
- the same parts as those of the semiconductor device 11a (FIG. 2) according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
- the semiconductor device 11b according to the second embodiment differs from the semiconductor device 11a according to the first embodiment in that a plurality of non-through holes 201-1 to 201-3 are formed in the irregularity formation region 23b. , otherwise the same.
- Non-through holes 201-1 to 201-3 are formed in the unevenness formation region 23b of the semiconductor device 11b. These non-through holes 201-1 to 201-3 are designed to have a small diameter and a shallow depth. By setting the diameter and depth of each of the non-through holes 201-1 to 203-3 to values that are approximately 30% smaller than the diameter and depth of the through electrode 21, the through electrodes 21 and the non-through holes 201-1 to 201-3 can be formed simultaneously with the same mask.
- the number is not limited to three and may be any number.
- the number, diameter, depth, etc. of the non-through holes 201 formed in the irregularity forming region 23 b are set according to the degree of sparseness of the rewiring lines 22 .
- step S31 through electrodes 21 and non-through holes 201 are formed in the silicon substrate 32 on the wiring layer 31. If the diameter and depth of the non-through holes 201 are designed to be approximately 30% smaller than the diameter and depth of the through electrodes 21, in step S31, the through electrodes 21 and the non-through holes 201 are simultaneously formed using the same mask. can be formed.
- step S32 the insulating film 33 is formed by the CVD method, the ALD method, or the like.
- step S ⁇ b>33 the insulating film 33 is etched back by dry etching to expose the wiring 36 in the wiring layer 31 connected to the through electrode 21 .
- step S34 a barrier metal film 34 is formed and a seed film 35 is formed by PVD, CVD, ALD, or the like.
- step S35 the portion other than the portion where the rewiring 22 is formed by lithography is covered with a resist 121, and in step S36, a Cu film, that is, the rewiring 22 is formed by Cu plating by a semi-additive method. be.
- step S37 the resist 121 is removed by wet etching, and in step S38, the seed film 35 and the barrier metal film 34 under the resist 121 are removed in order.
- the rewiring 22 is formed, and the uneven formation region 23 (non-through hole 201) is formed.
- FIG. 9 is a cross-sectional view showing a configuration example of a semiconductor device 11c according to the third embodiment, and the lower diagram in FIG.
- portions similar to those of the semiconductor device 11a (FIG. 2) according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
- the semiconductor device 11c according to the third embodiment differs from the semiconductor device 11a according to the first embodiment in that a plurality of non-through holes 221-1 to 221-3 are formed in the irregularity forming region 23c. , otherwise the same.
- the non-through holes 221-1 to 221-3 are configured to have different depths.
- the non-through hole 221-2 is deeper than the non-through hole 221-1, and the non-through hole 221-3 is deeper than the non-through hole 221-2.
- the diameters of the non-through holes 221-1 to 222-3 are also configured to have different sizes.
- the non-through hole 221-2 is larger in diameter than the non-through hole 221-1, and the non-through hole 221-3 is larger in diameter than the non-through hole 221-2. .
- the distances between the non-through holes 221 may be equal or different.
- the non-through hole 221 arranged on the side closer to the through electrode 21 is formed smaller, and the side farther from the through electrode 21 is formed.
- the non-through holes 221 arranged in are formed large.
- each of the non-through holes 221-1 to 221-3 formed in the rugged region 23c, the distance between the non-through holes 221, and the like are set according to the degree of sparseness of the rewiring lines 22. .
- a plurality of non-through holes 221 having different depths, diameters, and distances from the non-through holes 221-1 to 221-3 formed in the unevenness forming region 23c are formed in the film of the rewiring 22.
- a configuration in which the thickness is adjusted can also be used. Note that only one of the depth and diameter of the non-through holes 221-1 to 221-3 may be different.
- FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device 11d according to the fourth embodiment, and the lower diagram in FIG.
- the same parts as those of the semiconductor device 11a (FIG. 2) of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.
- a plurality of non-through holes 241-1 to 241-3 are formed in the irregularity formation region 23d of the semiconductor device 11d according to the fourth embodiment, and Cu (copper) is embedded in the non-through holes 241.
- the semiconductor device 11a in the first embodiment is different from the semiconductor device 11a in that the second embodiment is the same as the semiconductor device 11a of the first embodiment.
- Cu is present in the non-through holes 201-1 to 201-3 of the semiconductor device 11b of the second embodiment. It is good also as an embedded structure.
- Cu is present in the non-through holes 221-1 to 221-3 of the semiconductor device 11c of the third embodiment. It is good also as an embedded structure.
- the wiring cross-sectional area increases, so that the resistance value can be reduced, the EM (Electro Migration) resistance can be improved, and rewiring can be performed.
- the adhesiveness of the interface between 22 and the insulating film 33 can be improved.
- FIG. 11 is a cross-sectional view showing a configuration example of a semiconductor device 11e according to the fifth embodiment, and the lower diagram in FIG.
- portions similar to those of the semiconductor device 11a (FIG. 2) according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
- the semiconductor device 11e according to the fifth embodiment differs from the semiconductor device 11a according to the first embodiment in that non-through holes 261 are formed in a grid shape in the irregularity formation region 23e of the semiconductor device 11e. It is the same.
- Non-through holes 261 are formed in a lattice shape in plan view as shown in the lower diagram of FIG. As shown in the upper diagram of FIG. 11, in a cross-sectional view, a plurality of non-through holes 261 are formed in the concave-convex forming region 23e.
- a grid shape is a shape composed of at least one line and lines that intersect with that line.
- the lower diagram of FIG. 11 shows an example in which a lattice shape is formed from two horizontal lines and three vertical lines perpendicularly intersecting the two horizontal lines.
- the number, arrangement, thickness, depth, etc. of the lines forming the grid-shaped non-through holes 261 are set according to the degree of sparseness of the rewiring lines 22 .
- the non-through holes 261 formed in the irregularity forming region 23e into a lattice shape, the area to be plated can be increased, and the film thickness can be more easily adjusted.
- the semiconductor device 11e having the lattice-shaped non-through holes 261 can be basically manufactured in the same process as the manufacturing process of the semiconductor device 11a described with reference to FIGS. By using a grid-shaped mask for forming the non-through holes 41 in step S11, the semiconductor device 11e having the grid-shaped non-through holes 261 can be manufactured.
- FIG. 12 is a cross-sectional view showing a configuration example of a semiconductor device 11f according to the sixth embodiment, and the lower diagram in FIG.
- portions similar to those of the semiconductor device 11e (FIG. 11) according to the fifth embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
- the semiconductor device 11f of the sixth embodiment is similar to the semiconductor device 11e of the fifth embodiment in that grid-shaped non-through holes 281 are formed in the irregularity forming region 23f.
- the semiconductor device 11f according to the sixth embodiment differs from the semiconductor device 11e according to the fifth embodiment in that the non-through holes 281 of the concave-convex formed region 23f are filled with Cu (copper).
- the wiring cross-sectional area increases, so that the resistance value can be reduced, the EM (Electro Migration) resistance can be improved, and rewiring can be performed.
- the adhesiveness of the interface between 22 and the insulating film 33 can be improved.
- FIG. 13 is a cross-sectional view showing a configuration example of a semiconductor device 11g according to the seventh embodiment, and the lower diagram in FIG.
- the same parts as those of the semiconductor device 11a (FIG. 2) of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.
- the semiconductor device 11g according to the seventh embodiment differs from the semiconductor device 11a according to the first embodiment in that slit-shaped non-through holes 301 are formed in the irregularity forming region 23g. It is the same.
- non-through hole 301 is formed in a rectangular shape with a width smaller than the width of the rewiring 22 and a predetermined length in plan view. As shown in the upper diagram of FIG. 13 , non-through hole 301 is formed to have a predetermined depth, which is shallower than the depth of through electrode 21 in a cross-sectional view.
- the size and depth of the slit-shaped non-through holes 301 are set according to the degree of sparseness of the rewirings 22, and are adjusted so that the film thickness of the rewirings 22 is uniform.
- the depth of the non-through hole 301 is set to be approximately 50% less than the depth of the through electrode 21, the through electrode 21 and the through electrode 21 can be simultaneously formed using the same mask during manufacturing.
- step S51 through electrodes 21 and non-through holes 301 are formed in the silicon substrate 32 on the wiring layer 31.
- the depth of the non-through hole 301 is set to be approximately 50% less than the depth of the through electrode 21, the through electrode 21 and the non-through hole 301 can be simultaneously formed using the same mask in step S51.
- step S52 the insulating film 33 is formed by the CVD method, the ALD method, or the like.
- step S ⁇ b>53 the insulating film 33 is etched back by dry etching to expose the wiring 36 in the wiring layer 31 connected to the through electrode 21 .
- step S54 the barrier metal film 34 and the seed film 35 are formed by PVD, CVD, ALD, or the like.
- step S55 the portion other than the portion where the rewiring 22 is formed by lithography is covered with a resist 121, and in step S56, a Cu film, that is, the rewiring 22, is formed by Cu plating by a semi-additive method. be.
- step S57 the resist 121 is removed by wet etching, and in step S58, the seed film 35 and the barrier metal film 34 under the resist 121 are removed in order.
- the rewiring 22 is formed, and the uneven formation region 23 (non-through hole 301) is formed.
- FIG. 16 is a cross-sectional view showing a configuration example of a semiconductor device 11h according to the eighth embodiment, and the lower diagram in FIG.
- portions similar to those of the semiconductor device 11a (FIG. 2) according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.
- the rewiring 22 of the semiconductor device 11h according to the eighth embodiment is different from the semiconductor device 11a according to the first embodiment in that it is formed in a stepped shape, and is otherwise the same.
- the unevenness forming area 23h (assumed to be the low land portion 321) is formed at a position lower than the reference height.
- the low-lying portion 321 is formed in a rectangular shape with a width approximately equal to the width of the rewiring 22 and a predetermined length in plan view.
- the unevenness forming region 23h (lower portion 321) of the rewiring 22 is formed at a position lower than the rewiring 22 other than the unevenness forming region 23h.
- the rewiring 22 is formed in a stepped shape.
- the silicon substrate 32 in the region where the height of the rewiring is assumed to be high can be formed thin in advance to prevent an increase in wiring capacitance and reduce the height of the wiring.
- the size (area) of the uneven formation region 23h is set according to the degree of sparseness of the rewirings 22, and is adjusted so that the film thickness of the rewirings 22 is uniform. Also in this case, an increase in capacitance in the rewiring 22 can be suppressed.
- FIG. 17 is a cross-sectional view showing a configuration example of a semiconductor device 11i according to the ninth embodiment, and the lower diagram in FIG.
- the same parts as those of the semiconductor device 11a (FIG. 2) of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.
- the surface of the silicon substrate 32 is provided with ruggedness, and the rewiring 22 and the like are also formed in accordance with the ruggedness.
- the semiconductor device 11a is the same in other respects.
- the surface of the silicon substrate 32 on which the rewiring 22 is formed and the area on which the irregularity forming region 23i is formed are made uneven.
- the irregularity forming region 23i has a convex shape with respect to the reference plane.
- Two protrusions 341 are formed on the silicon substrate 32 .
- the barrier metal film 34 and the seed film 35 also have a convex shape in the region where the convex portion 341 of the silicon substrate 32 is formed. Looking at the unevenness forming region 23i of the rewiring 22 formed on the seed film 35, the silicon substrate 32 side of the unevenness forming region 23i of the rewiring 22 has an uneven shape.
- step S11 (FIG. 4)
- step S12 (FIG. 4)
- step S12 the processes from step S12 on the silicon substrate 32 on which the convex portion 341 is formed.
- FIG. 18 is a cross-sectional view showing a configuration example of a semiconductor device 11j according to the tenth embodiment, and the lower diagram in FIG.
- the same parts as those of the semiconductor device 11i (FIG. 17) according to the ninth embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.
- the unevenness forming region 23j of the semiconductor device 11j in the tenth embodiment has unevenness on the surface of the insulating film 33, and the rewiring 22 and the like are also formed in accordance with the unevenness. It is different from the semiconductor device 11i in form, and is the same in other respects.
- the surface of the insulating film 33 on which the rewiring 22 is formed and the area of the insulating film 33 on which the uneven forming region 23j is formed are made uneven.
- the unevenness forming region 23j has a concave shape with respect to the reference plane.
- Four recesses 361 are formed in the insulating film 33 .
- the barrier metal film 34 and the seed film 35 are also recessed.
- the insulating film 33 side of the irregularity forming region 23j of the rewiring 22 has an irregular shape.
- step S71 through electrodes 21 are formed on the silicon substrate 32 on the wiring layer 31 by lithography and dry etching.
- the insulating film 33 is formed by the CVD method, the ALD method, or the like. Since the maximum depth of the concave shape is determined by the thickness of the insulating film 33, the film thickness is set so that the insulating film 33 is thicker than the desired depth of the concave shape.
- step S73 a resist 141 is formed on the portion other than the portion where the concave shape is to be formed by lithography.
- step S ⁇ b>73 the portion of the through electrode 21 is tented with the resist 141 and controlled so that the resist 141 does not enter the through electrode 21 .
- step S73 light dry etching is performed using the resist 141 as a mask to form a concave shape in the insulating film 33.
- step S73 if the insulating film 33 is made too thin, the insulating film 33 may disappear when the insulating film 33 is etched back in a subsequent step. be.
- step S74 the resist 141 is removed. A concave shape is formed on the insulating film 33 by removing the resist 141 .
- the barrier metal film 34 and the seed film 35 are formed in the same steps as those after step S53 shown in FIGS. be done.
- the rewiring 22 is formed in which the insulating film 33 in the irregularity forming region 23 has a concave shape.
- FIG. 20 is a cross-sectional view showing a configuration example of a semiconductor device 11k according to the eleventh embodiment, and the lower diagram in FIG.
- the same parts as those of the semiconductor device 11a (FIG. 2) of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.
- the semiconductor device 11k according to the eleventh embodiment differs from the semiconductor device 11a according to the first embodiment in that the concave-convex formed region 23k is not connected to the rewiring 22, and is otherwise the same. .
- a non-through hole 381 is formed in the irregularity forming region 23k of the semiconductor device 11k in the eleventh embodiment shown in FIG.
- the concave-convex forming region 23 k is formed with a predetermined gap from the rewiring 22 .
- Non-through hole 381 is formed in a floating state.
- the irregularity forming region 23 k is formed as a floating dummy electrode around the rewiring 22 . Since it is a dummy electrode, the irregularity forming region 23 k (non-through hole 381 ) is formed in a state of not being connected to the wiring layer 31 .
- the irregularity forming region 23k is formed in a floating state, it is possible to suppress variations in the height of the rewiring 22 without increasing the wiring capacitance.
- step S16 the resist 121 is also provided between the region that will become the rewiring 22 and the region that will become the non-through hole 381.
- step S16 the resist 121 is also provided between the region that will become the rewiring 22 and the region that will become the non-through hole 381.
- step S16 the resist 121 is also provided between the region that will become the rewiring 22 and the region that will become the non-through hole 381.
- step S16 FIG. 5
- Cu plating is not performed between the region where the resist 121 is provided and which becomes the rewiring 22 and the region which becomes the non-through hole 381
- a state in which the rewiring 22 and the non-through hole 381 are not connected can be created. can be done.
- the semiconductor device 11k manufactured until the rewiring 22 and the non-through hole 381 are not connected is subjected to the processes from step S17 onward, thereby manufacturing the semiconductor device 11k.
- the eleventh embodiment can be combined with any of the uneven formation regions 23b to 23j in the second to tenth embodiments. That is, the rewiring 22 and the concave-convex forming regions 23a to 23j in the first to tenth embodiments can be arranged with a predetermined interval.
- the concave-convex forming region 23 is formed in a part of the rewiring 22, variations in the height of the rewiring 22 can be reduced without being subject to restrictions on the wiring layout.
- the unevenness forming region 23 can be formed in the same process using the same mask as the through electrode 21. Therefore, the unevenness forming region 23 can be formed without increasing the number of steps. .
- the semiconductor device 11 of the first to eleventh embodiments can be applied to an imaging device.
- the semiconductor device 11 described above may be used as a chip of an imaging element.
- the chip stacked on the semiconductor device 11 described above may be a chip on which a solid-state imaging element is formed, and the semiconductor device 11 may be a chip having a processing section for processing signals from the solid-state imaging element.
- the image pickup device may be, for example, an image pickup device such as a digital still camera or a digital video camera, a mobile phone with an image pickup function, or other equipment with an image pickup function. can be applied to electronic equipment.
- FIG. 21 is a block diagram showing a configuration example of an imaging device as an electronic device.
- An image pickup apparatus 1001 shown in FIG. 21 includes an optical system 1002, a shutter device 1003, an image sensor 1004, a drive circuit 1005, a signal processing circuit 1006, a monitor 1007, and a memory 1008, and picks up still images and moving images. It is possible.
- the optical system 1002 is configured with one or more lenses, guides the light (incident light) from the subject to the imaging element 1004, and forms an image on the light receiving surface of the imaging element 1004.
- a shutter device 1003 is arranged between the optical system 1002 and the imaging element 1004 and controls the light irradiation period and the light shielding period for the imaging element 1004 according to the control of the driving circuit 1005 .
- the imaging element 1004 is configured by a package including the imaging element described above.
- the imaging device 1004 accumulates signal charges for a certain period of time according to the light imaged on the light receiving surface via the optical system 1002 and the shutter device 1003 .
- the signal charges accumulated in the image sensor 1004 are transferred according to a drive signal (timing signal) supplied from the drive circuit 1005 .
- a drive circuit 1005 drives the image sensor 1004 and the shutter device 1003 by outputting drive signals for controlling the transfer operation of the image sensor 1004 and the shutter operation of the shutter device 1003 .
- a signal processing circuit 1006 performs various signal processing on the signal charges output from the image sensor 1004 .
- An image (image data) obtained by the signal processing performed by the signal processing circuit 1006 is supplied to the monitor 1007 to be displayed, or supplied to the memory 1008 to be stored (recorded).
- an imaging device configured to include any of the semiconductor devices 11a to 11j described above can be applied to the imaging device 1004.
- FIG. 1 is a diagrammatic representation of the imaging device 1001 configured in this manner.
- the technology (the present technology) according to the present disclosure can be applied to various products.
- the technology according to the present disclosure may be applied to an endoscopic surgery system.
- FIG. 22 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (this technology) can be applied.
- FIG. 22 illustrates a state in which an operator (doctor) 11131 is performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000 .
- an endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, and a support arm device 11120 for supporting the endoscope 11100. , and a cart 11200 loaded with various devices for endoscopic surgery.
- An endoscope 11100 is composed of a lens barrel 11101 whose distal end is inserted into the body cavity of a patient 11132 and a camera head 11102 connected to the proximal end of the lens barrel 11101 .
- an endoscope 11100 configured as a so-called rigid scope having a rigid lens barrel 11101 is illustrated, but the endoscope 11100 may be configured as a so-called flexible scope having a flexible lens barrel. good.
- the tip of the lens barrel 11101 is provided with an opening into which the objective lens is fitted.
- a light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel 11101 by a light guide extending inside the lens barrel 11101, where it reaches the objective. Through the lens, the light is irradiated toward the observation object inside the body cavity of the patient 11132 .
- the endoscope 11100 may be a straight scope, a perspective scope, or a side scope.
- An optical system and an imaging element are provided inside the camera head 11102, and the reflected light (observation light) from the observation target is focused on the imaging element by the optical system.
- the imaging element photoelectrically converts the observation light to generate an electric signal corresponding to the observation light, that is, an image signal corresponding to the observation image.
- the image signal is transmitted to a camera control unit (CCU: Camera Control Unit) 11201 as RAW data.
- CCU Camera Control Unit
- the CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and controls the operations of the endoscope 11100 and the display device 11202 in an integrated manner. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing such as development processing (demosaicing) for displaying an image based on the image signal.
- CPU Central Processing Unit
- GPU Graphics Processing Unit
- the display device 11202 displays an image based on an image signal subjected to image processing by the CCU 11201 under the control of the CCU 11201 .
- the light source device 11203 is composed of a light source such as an LED (light emitting diode), for example, and supplies the endoscope 11100 with irradiation light for imaging a surgical site or the like.
- a light source such as an LED (light emitting diode)
- LED light emitting diode
- the input device 11204 is an input interface for the endoscopic surgery system 11000.
- the user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204 .
- the user inputs an instruction or the like to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) by the endoscope 11100 .
- the treatment instrument control device 11205 controls driving of the energy treatment instrument 11112 for tissue cauterization, incision, blood vessel sealing, or the like.
- the pneumoperitoneum device 11206 inflates the body cavity of the patient 11132 for the purpose of securing the visual field of the endoscope 11100 and securing the operator's working space, and injects gas into the body cavity through the pneumoperitoneum tube 11111. send in.
- the recorder 11207 is a device capable of recording various types of information regarding surgery.
- the printer 11208 is a device capable of printing various types of information regarding surgery in various formats such as text, images, and graphs.
- the light source device 11203 that supplies the endoscope 11100 with irradiation light for photographing the surgical site can be composed of, for example, a white light source composed of an LED, a laser light source, or a combination thereof.
- a white light source is configured by a combination of RGB laser light sources
- the output intensity and output timing of each color (each wavelength) can be controlled with high accuracy. It can be carried out.
- the observation target is irradiated with laser light from each of the RGB laser light sources in a time-division manner, and by controlling the drive of the imaging element of the camera head 11102 in synchronization with the irradiation timing, each of RGB can be handled. It is also possible to pick up images by time division. According to this method, a color image can be obtained without providing a color filter in the imaging device.
- the driving of the light source device 11203 may be controlled so as to change the intensity of the output light every predetermined time.
- the drive of the imaging device of the camera head 11102 in synchronism with the timing of the change in the intensity of the light to obtain an image in a time-division manner and synthesizing the images, a high dynamic A range of images can be generated.
- the light source device 11203 may be configured to be able to supply light in a predetermined wavelength band corresponding to special light observation.
- special light observation for example, the wavelength dependence of light absorption in body tissues is used to irradiate a narrower band of light than the irradiation light (i.e., white light) used during normal observation, thereby observing the mucosal surface layer.
- irradiation light i.e., white light
- Narrow Band Imaging in which a predetermined tissue such as a blood vessel is imaged with high contrast, is performed.
- fluorescence observation may be performed in which an image is obtained from fluorescence generated by irradiation with excitation light.
- the body tissue is irradiated with excitation light and the fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and the body tissue is examined.
- a fluorescence image can be obtained by irradiating excitation light corresponding to the fluorescence wavelength of the reagent.
- the light source device 11203 can be configured to be able to supply narrowband light and/or excitation light corresponding to such special light observation.
- FIG. 23 is a block diagram showing an example of functional configurations of the camera head 11102 and CCU 11201 shown in FIG.
- the camera head 11102 has a lens unit 11401, an imaging section 11402, a drive section 11403, a communication section 11404, and a camera head control section 11405.
- the CCU 11201 has a communication section 11411 , an image processing section 11412 and a control section 11413 .
- the camera head 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400 .
- a lens unit 11401 is an optical system provided at a connection with the lens barrel 11101 . Observation light captured from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401 .
- a lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.
- the number of imaging elements constituting the imaging unit 11402 may be one (so-called single-plate type) or plural (so-called multi-plate type).
- image signals corresponding to RGB may be generated by each image pickup element, and a color image may be obtained by synthesizing the image signals.
- the imaging unit 11402 may be configured to have a pair of imaging elements for respectively acquiring right-eye and left-eye image signals corresponding to 3D (dimensional) display.
- the 3D display enables the operator 11131 to more accurately grasp the depth of the living tissue in the surgical site.
- a plurality of systems of lens units 11401 may be provided corresponding to each imaging element.
- the imaging unit 11402 does not necessarily have to be provided in the camera head 11102 .
- the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.
- the drive unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under control from the camera head control unit 11405 . Thereby, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.
- the communication unit 11404 is composed of a communication device for transmitting and receiving various information to and from the CCU 11201.
- the communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400 .
- the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies it to the camera head control unit 11405 .
- the control signal includes, for example, information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and/or information to specify the magnification and focus of the captured image. Contains information about conditions.
- the imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately designated by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. good.
- the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.
- the camera head control unit 11405 controls driving of the camera head 11102 based on the control signal from the CCU 11201 received via the communication unit 11404.
- the communication unit 11411 is composed of a communication device for transmitting and receiving various information to and from the camera head 11102 .
- the communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400 .
- the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102 .
- Image signals and control signals can be transmitted by electric communication, optical communication, or the like.
- the image processing unit 11412 performs various types of image processing on the image signal, which is RAW data transmitted from the camera head 11102 .
- the control unit 11413 performs various controls related to imaging of the surgical site and the like by the endoscope 11100 and display of the captured image obtained by imaging the surgical site and the like. For example, the control unit 11413 generates control signals for controlling driving of the camera head 11102 .
- control unit 11413 causes the display device 11202 to display a captured image showing the surgical site and the like based on the image signal that has undergone image processing by the image processing unit 11412 .
- the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 detects the shape, color, and the like of the edges of objects included in the captured image, thereby detecting surgical instruments such as forceps, specific body parts, bleeding, mist during use of the energy treatment instrument 11112, and the like. can recognize.
- the control unit 11413 may use the recognition result to display various types of surgical assistance information superimposed on the image of the surgical site. By superimposing and presenting the surgery support information to the operator 11131, the burden on the operator 11131 can be reduced and the operator 11131 can proceed with the surgery reliably.
- a transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable of these.
- wired communication is performed using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.
- the technology (the present technology) according to the present disclosure can be applied to various products.
- the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
- FIG. 24 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
- a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
- the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050.
- a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.
- the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
- the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
- the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
- the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
- the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
- the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
- the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
- the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
- the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
- the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
- the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
- the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
- the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
- the in-vehicle information detection unit 12040 detects in-vehicle information.
- the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
- the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
- the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
- a control command can be output to 12010 .
- the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of vehicles, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving
- the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
- the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
- the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
- the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
- an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
- the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
- FIG. 25 is a diagram showing an example of the installation position of the imaging unit 12031.
- the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
- the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example.
- An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
- Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
- An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
- the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
- FIG. 25 shows an example of the imaging range of the imaging units 12101 to 12104.
- the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
- the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
- the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
- At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
- at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
- the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
- automatic brake control including following stop control
- automatic acceleration control including following start control
- the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
- At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
- the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
- recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
- the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
- the system represents an entire device composed of multiple devices.
- the present technology can also take the following configuration.
- a substrate a wiring layer on the first surface of the substrate; a first wiring provided on a second surface facing the first surface of the substrate; a through electrode that connects the second wiring and the first wiring in the wiring layer and penetrates the substrate,
- a semiconductor device wherein a part of the first wiring has an uneven region.
- the semiconductor device according to (1) wherein the uneven shape is a non-through hole that does not penetrate the substrate.
- the semiconductor device according to (2) wherein a plurality of the non-through holes are provided.
- the semiconductor device according to (2) comprising a plurality of non-through holes having different depths with respect to the substrate.
- the semiconductor device according to (2), wherein the non-through hole has a lattice shape.
- the semiconductor device according to (1), wherein a region of the substrate corresponding to the uneven region of the second surface of the substrate has a convex portion.
- the semiconductor device according to (1) wherein a region of the insulating film corresponding to the uneven region on the second surface of the substrate has a recessed portion.
- the semiconductor device according to (1) wherein the first wiring and the uneven region are arranged with a predetermined gap therebetween.
- (12) The semiconductor device according to (2), wherein the size of the non-through hole is 70% or less of the size of the through electrode.
- the slit-shaped non-through hole has a depth from the second surface that is 50% or less of the depth from the second surface of the through electrode. Device.
- a first chip on which a solid-state imaging device is formed a second chip that processes signals from the first chip; the second chip, a substrate; a wiring layer on the first surface of the substrate; a first wiring provided on a second surface facing the first surface of the substrate; a through electrode that connects the second wiring and the first wiring in the wiring layer and penetrates the substrate, A part of said 1st wiring has an uneven
- 11 semiconductor device 21 through electrode, 22 rewiring, 23 irregularity formation region, 31 wiring layer, 32 silicon substrate, 33 insulating film, 34 barrier metal film, 35 seed film, 36 wiring, 41 non-through hole, 101 section, 121, 141 resist, 201, 221, 241, 261, 281, 301 non-through holes, 321 low-lying portion, 341 convex portion, 361 concave portion, 381 non-through hole
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
以下に説明する本技術は、CCD(Charged-Coupled Device)やCMOS(Complementary Metal-Oxide Semiconductor)等の撮像素子のチップを含む半導体装置に適用できる。PD(Photo Diode)等の受光素子、光スイッチやミラーデバイス等のMEMS(Micro Electro Mechanical Systems)素子、レーザーダイオード(LD;Laser Diode)やLED(Light Emitting Diode)、垂直共振器型面発光レーザ(VCSEL:vertical cavity surface emitting laser)等の発光素子のような光学素子のチップを含む半導体装置にも適用できる。
図6の上図は、第2の実施の形態における半導体装置11bの構成例を示す断面図であり、図6の下図は、再配線22の構成を示す図である。なお、図6は、図1の半導体装置11aの線分A-A’における断面構成例に該当するが、以下の説明では、貫通電極21-7、再配線22-7、凹凸形成領域23-7をそれぞれ貫通電極21、再配線22、凹凸形成領域23として説明する。
図9の上図は、第3の実施の形態における半導体装置11cの構成例を示す断面図であり、図9の下図は、再配線22の構成を示す図である。第3の実施の形態における半導体装置11cにおいて、第1の実施の形態における半導体装置11a(図2)と同様の部分には同様の符号を付し、その説明は適宜省略する。
図10の上図は、第4の実施の形態における半導体装置11dの構成例を示す断面図であり、図10の下図は、再配線22の構成を示す図である。第4の実施の形態における半導体装置11dにおいて、第1の実施の形態における半導体装置11a(図2)と同様の部分には同様の符号を付し、その説明は適宜省略する。
図11の上図は、第5の実施の形態における半導体装置11eの構成例を示す断面図であり、図11の下図は、再配線22の構成を示す図である。第5の実施の形態における半導体装置11eにおいて、第1の実施の形態における半導体装置11a(図2)と同様の部分には同様の符号を付し、その説明は適宜省略する。
図12の上図は、第6の実施の形態における半導体装置11fの構成例を示す断面図であり、図12の下図は、再配線22の構成を示す図である。第6の実施の形態における半導体装置11fにおいて、第5の実施の形態における半導体装置11e(図11)と同様の部分には同様の符号を付し、その説明は適宜省略する。
図13の上図は、第7の実施の形態における半導体装置11gの構成例を示す断面図であり、図13の下図は、再配線22の構成を示す図である。第7の実施の形態における半導体装置11gにおいて、第1の実施の形態における半導体装置11a(図2)と同様の部分には同様の符号を付し、その説明は適宜省略する。
図16の上図は、第8の実施の形態における半導体装置11hの構成例を示す断面図であり、図16の下図は、再配線22の構成を示す図である。第8の実施の形態における半導体装置11hにおいて、第1の実施の形態における半導体装置11a(図2)と同様の部分には同様の符号を付し、その説明は適宜省略する。
図17の上図は、第9の実施の形態における半導体装置11iの構成例を示す断面図であり、図17の下図は、再配線22の構成を示す図である。第9の実施の形態における半導体装置11iにおいて、第1の実施の形態における半導体装置11a(図2)と同様の部分には同様の符号を付し、その説明は適宜省略する。
図18の上図は、第10の実施の形態における半導体装置11jの構成例を示す断面図であり、図18の下図は、再配線22の構成を示す図である。第10の実施の形態における半導体装置11jにおいて、第9の実施の形態における半導体装置11i(図17)と同様の部分には同様の符号を付し、その説明は適宜省略する。
図20の上図は、第11の実施の形態における半導体装置11kの構成例を示す断面図であり、図20の下図は、再配線22の構成を示す図である。第11の実施の形態における半導体装置11kにおいて、第1の実施の形態における半導体装置11a(図2)と同様の部分には同様の符号を付し、その説明は適宜省略する。
第1乃至第11の実施の形態の半導体装置11を撮像素子に適用することができる。上述した半導体装置11を撮像素子のチップとしても良い。上述した半導体装置11に積層されるチップを固体撮像素子が形成されたチップとし、半導体装置11は、固体撮像素子からの信号を処理する処理部を有するチップとしても良い。
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、内視鏡手術システムに適用されてもよい。
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。
(1)
基板と、
前記基板の第1の面上にある配線層と、
前記基板の前記第1の面と対向する第2の面に設けられている第1の配線と、
前記配線層内の第2の配線と前記第1の配線を接続し、前記基板を貫通する貫通電極と
を備え、
前記第1の配線の一部は、凹凸形状の領域を有する
半導体装置。
(2)
前記凹凸形状は、前記基板を貫通しない非貫通孔である
前記(1)に記載の半導体装置。
(3)
前記非貫通孔は、複数設けられている
前記(2)に記載の半導体装置。
(4)
前記基板に対する深さが異なる複数の非貫通孔を備える
前記(2)に記載の半導体装置。
(5)
前記非貫通孔は、格子形状である
前記(2)に記載の半導体装置。
(6)
前記非貫通孔は、前記第1の配線と同一の材料で埋められている
前記(2)乃至(5)のいずれかに記載の半導体装置。
(7)
前記非貫通孔は、スリット形状である
前記(2)に記載の半導体装置。
(8)
前記第1の配線は、段差を有する形状に形成されている
前記(1)に記載の半導体装置。
(9)
前記基板の前記第2の面の前記凹凸形状の領域に該当する前記基板の領域は、凸形状の凸部を有する
前記(1)に記載の半導体装置。
(10)
前記基板と前記第1の配線との間に絶縁膜をさらに備え、
前記絶縁膜のうち、前記基板の前記第2の面の前記凹凸形状の領域に該当する領域は、凹形状の凹部を有する
前記(1)に記載の半導体装置。
(11)
前記第1の配線と前記凹凸形状の領域は、所定の間隔を有して配置されている
前記(1)に記載の半導体装置。
(12)
前記非貫通孔の大きさは、前記貫通電極の大きさの70%以下の大きさである
前記(2)に記載の半導体装置。
(13)
前記スリット形状の前記非貫通孔の前記第2の面からの深さは、前記貫通電極の前記第2の面からの深さの50%以下の深さである
前記(7)に記載の半導体装置。
(14)
前記第1の配線が配置される領域全体において、前記凹凸形状は、単位面積あたりの被めっき面積が均一になるような大きさで形成されている
前記(1)乃至(13)のいずれかに記載の半導体装置。
(15)
前記凹凸形状の領域は、膜厚が厚くなる前記第1の配線に設けられている
前記(1)乃至(14)のいずれかに記載の半導体装置。
(16)
固体撮像素子が形成されている第1のチップと、
前記第1のチップからの信号を処理する第2のチップと
を備え、
前記第2のチップは、
基板と、
前記基板の第1の面上にある配線層と、
前記基板の前記第1の面と対向する第2の面に設けられている第1の配線と、
前記配線層内の第2の配線と前記第1の配線を接続し、前記基板を貫通する貫通電極と
を備え、
前記第1の配線の一部は、凹凸形状の領域を有する
撮像装置。
Claims (16)
- 基板と、
前記基板の第1の面上にある配線層と、
前記基板の前記第1の面と対向する第2の面に設けられている第1の配線と、
前記配線層内の第2の配線と前記第1の配線を接続し、前記基板を貫通する貫通電極と
を備え、
前記第1の配線の一部は、凹凸形状の領域を有する
半導体装置。 - 前記凹凸形状は、前記基板を貫通しない非貫通孔である
請求項1に記載の半導体装置。 - 前記非貫通孔は、複数設けられている
請求項2に記載の半導体装置。 - 前記基板に対する深さが異なる複数の非貫通孔を備える
請求項2に記載の半導体装置。 - 前記非貫通孔は、格子形状である
請求項2に記載の半導体装置。 - 前記非貫通孔は、前記第1の配線と同一の材料で埋められている
請求項2に記載の半導体装置。 - 前記非貫通孔は、スリット形状である
請求項2に記載の半導体装置。 - 前記第1の配線は、段差を有する形状に形成されている
請求項1に記載の半導体装置。 - 前記基板の前記第2の面の前記凹凸形状の領域に該当する前記基板の領域は、凸形状の凸部を有する
請求項1に記載の半導体装置。 - 前記基板と前記第1の配線との間に絶縁膜をさらに備え、
前記絶縁膜のうち、前記基板の前記第2の面の前記凹凸形状の領域に該当する領域は、凹形状の凹部を有する
請求項1に記載の半導体装置。 - 前記第1の配線と前記凹凸形状の領域は、所定の間隔を有して配置されている
請求項1に記載の半導体装置。 - 前記非貫通孔の大きさは、前記貫通電極の大きさの70%以下の大きさである
請求項2に記載の半導体装置。 - 前記スリット形状の前記非貫通孔の前記第2の面からの深さは、前記貫通電極の前記第2の面からの深さの50%以下の深さである
請求項7に記載の半導体装置。 - 前記第1の配線が配置される領域全体において、前記凹凸形状は、単位面積あたりの被めっき面積が均一になるような大きさで形成されている
請求項1に記載の半導体装置。 - 前記凹凸形状の領域は、膜厚が厚くなる前記第1の配線に設けられている
請求項1に記載の半導体装置。 - 固体撮像素子が形成されている第1のチップと、
前記第1のチップからの信号を処理する第2のチップと
を備え、
前記第2のチップは、
基板と、
前記基板の第1の面上にある配線層と、
前記基板の前記第1の面と対向する第2の面に設けられている第1の配線と、
前記配線層内の第2の配線と前記第1の配線を接続し、前記基板を貫通する貫通電極と
を備え、
前記第1の配線の一部は、凹凸形状の領域を有する
撮像装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2023508700A JPWO2022201814A1 (ja) | 2021-03-24 | 2022-01-21 | |
CN202280022090.7A CN116998012A (zh) | 2021-03-24 | 2022-01-21 | 半导体器件和成像装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021-049544 | 2021-03-24 | ||
JP2021049544 | 2021-03-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022201814A1 true WO2022201814A1 (ja) | 2022-09-29 |
Family
ID=83395413
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2022/002109 WO2022201814A1 (ja) | 2021-03-24 | 2022-01-21 | 半導体装置、撮像装置 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPWO2022201814A1 (ja) |
CN (1) | CN116998012A (ja) |
WO (1) | WO2022201814A1 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05235194A (ja) * | 1991-11-29 | 1993-09-10 | Nec Corp | マイクロ波モノリシック集積回路 |
JP2008288309A (ja) * | 2007-05-16 | 2008-11-27 | Sony Corp | 半導体装置及びその製造方法 |
JP2009206496A (ja) * | 2008-01-30 | 2009-09-10 | Panasonic Corp | 半導体チップ及び半導体装置 |
JP2013243348A (ja) * | 2012-05-22 | 2013-12-05 | Samsung Electronics Co Ltd | ビアパッドインレイを有するtsv半導体素子 |
JP2019161046A (ja) * | 2018-03-14 | 2019-09-19 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、撮像装置、および電子機器 |
-
2022
- 2022-01-21 WO PCT/JP2022/002109 patent/WO2022201814A1/ja active Application Filing
- 2022-01-21 CN CN202280022090.7A patent/CN116998012A/zh active Pending
- 2022-01-21 JP JP2023508700A patent/JPWO2022201814A1/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05235194A (ja) * | 1991-11-29 | 1993-09-10 | Nec Corp | マイクロ波モノリシック集積回路 |
JP2008288309A (ja) * | 2007-05-16 | 2008-11-27 | Sony Corp | 半導体装置及びその製造方法 |
JP2009206496A (ja) * | 2008-01-30 | 2009-09-10 | Panasonic Corp | 半導体チップ及び半導体装置 |
JP2013243348A (ja) * | 2012-05-22 | 2013-12-05 | Samsung Electronics Co Ltd | ビアパッドインレイを有するtsv半導体素子 |
JP2019161046A (ja) * | 2018-03-14 | 2019-09-19 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置、撮像装置、および電子機器 |
Also Published As
Publication number | Publication date |
---|---|
CN116998012A (zh) | 2023-11-03 |
JPWO2022201814A1 (ja) | 2022-09-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2018074250A1 (ja) | 半導体装置、製造方法、および電子機器 | |
JP6951866B2 (ja) | 撮像素子 | |
US11784147B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
WO2020137285A1 (ja) | 撮像素子および撮像素子の製造方法 | |
WO2021044716A1 (ja) | 固体撮像装置及び電子機器 | |
JP2019192802A (ja) | 撮像素子および撮像素子の製造方法 | |
US11798965B2 (en) | Solid-state imaging device and method for manufacturing the same | |
WO2020246323A1 (ja) | 撮像装置 | |
US20220005853A1 (en) | Semiconductor device, solid-state imaging device, and electronic equipment | |
WO2022172711A1 (ja) | 光電変換素子および電子機器 | |
WO2022201814A1 (ja) | 半導体装置、撮像装置 | |
WO2022102278A1 (ja) | 固体撮像装置及び電子機器 | |
US11362123B2 (en) | Imaging device, camera module, and electronic apparatus to enhance sensitivity to light | |
EP4307373A1 (en) | Semiconductor device and imaging device | |
US11355421B2 (en) | Semiconductor device, manufacturing method for semiconductor, and imaging unit | |
WO2022130987A1 (ja) | 固体撮像装置およびその製造方法 | |
US11735615B2 (en) | Imaging device with protective resin layer and stress relaxation region | |
US20240096919A1 (en) | Semiconductor device, imaging device, and manufacturing method | |
WO2020235148A1 (ja) | 半導体装置及び電子機器 | |
US20240038807A1 (en) | Solid-state imaging device | |
JP2023083675A (ja) | 固体撮像装置 | |
TW202220228A (zh) | 半導體裝置及其製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 22774616 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2023508700 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 202280022090.7 Country of ref document: CN |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 22774616 Country of ref document: EP Kind code of ref document: A1 |