WO2022199310A1 - 硅-氮化镓复合衬底、复合器件及制备方法 - Google Patents

硅-氮化镓复合衬底、复合器件及制备方法 Download PDF

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WO2022199310A1
WO2022199310A1 PCT/CN2022/077459 CN2022077459W WO2022199310A1 WO 2022199310 A1 WO2022199310 A1 WO 2022199310A1 CN 2022077459 W CN2022077459 W CN 2022077459W WO 2022199310 A1 WO2022199310 A1 WO 2022199310A1
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silicon
layer
shallow trench
gallium nitride
trench isolation
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English (en)
French (fr)
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陈龙
程静云
商延卫
马旺
陈祖尧
袁理
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聚能晶源(青岛)半导体材料有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides

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  • the invention belongs to the technical field of semiconductors, and relates to a silicon-gallium nitride composite substrate, a composite device and a preparation method.
  • gallium nitride As a representative of the third-generation semiconductor materials, gallium nitride (GaN) has many excellent properties such as wide band gap, superior radiation noise resistance, high avalanche breakdown electric field, good thermal conductivity, and high electron drift rate under strong field. It is widely used in fields such as laser, LED, microwave, and radio frequency.
  • GaN semiconductors have a wide band gap, excellent thermal stability, high breakdown voltage, high electron saturation drift speed and excellent radiation resistance performance, and compared with silicon power semiconductors, GaN power semiconductors. There are also low temperature resistance characteristics, so that GaN power semiconductors can reduce power conversion losses caused by power semiconductors, and achieve the advantages of minimizing power system and power loss.
  • GaN devices are mainly discrete devices, and GaN integrated circuits have obvious advantages.
  • GaN materials cannot arbitrarily define p-type or n-type regions by ion implantation or diffusion, the development of GaN integrated circuits is limited.
  • the mainstream is to use the method of device cascading, that is, to interconnect silicon-based metal oxide field effect transistor devices (Si MOSFETs) and GaN devices through external wire bonding or flip chip interconnection. method, which will introduce additional parasitics, reduce the performance of the entire integrated device, and increase the system integration area.
  • Si MOSFETs silicon-based metal oxide field effect transistor devices
  • the purpose of the present invention is to provide a silicon-gallium nitride composite substrate, a composite device and a preparation method, which are used to solve the problem that it is difficult to prepare a GaN integrated circuit in the prior art.
  • the present invention provides a preparation method of a silicon-gallium nitride composite substrate, comprising the following steps:
  • III-N epitaxial structure on the surface of the first silicon layer, the III-N epitaxial structure including a GaN channel layer and an AlGaN barrier layer;
  • first hard mask layer covering the III-N epitaxial structure, and patterning the first hard mask layer
  • isolation spacers in the grooves, the isolation spacers covering the sidewalls of the III-N epitaxial structure
  • the shallow trench isolation structure fills the shallow trench, and the shallow trench isolation structure penetrates the first silicon layer;
  • the second hard mask layer is exposed.
  • the surface of the second silicon layer is made flush with the surface of the shallow trench isolation structure.
  • the silicon substrate includes an SOI substrate or a silicon substrate formed by a bonding method with the first silicon layer on the surface; the first silicon layer is a Si(111) layer; the second silicon layer is Si (111) Layer.
  • the III-N epitaxial structure further includes a buffer layer located between the first silicon layer and the GaN channel layer, and a buffer layer located between the AlGaN barrier layer and the first hard mask layer One or a combination of capping layers in between.
  • the first hard mask layer includes one or a combination of a silicon nitride layer and a silicon oxide layer
  • the second hard mask layer includes one or a combination of a silicon nitride layer and a silicon oxide layer.
  • the shallow trench isolation structure includes one or a combination of a silicon nitride layer and a silicon oxide layer.
  • the present invention also provides a silicon-gallium nitride composite substrate, the silicon-gallium nitride composite substrate comprising:
  • the silicon substrate including a first silicon layer
  • the shallow trench isolation structure is located on the silicon substrate, and the shallow trench isolation structure penetrates the first silicon layer;
  • III-N epitaxial structure the III-N epitaxial structure is located on the surface of the first silicon layer, the III-N epitaxial structure includes a GaN channel layer and an AlGaN barrier layer, and the III-N a family epitaxial structure is located outside the shallow trench isolation structure;
  • a second silicon layer, the second silicon layer is located on the surface of the first silicon layer, and the second silicon layer is located inside the shallow trench isolation structure.
  • the surface of the second silicon layer is flush with the surface of the shallow trench isolation structure.
  • the silicon substrate includes an SOI substrate; the first silicon layer is a Si(111) layer; the second silicon layer is a Si(111) layer; the shallow trench isolation structure includes a silicon nitride layer and one or a combination of the silicon oxide layer.
  • the present invention also provides a method for preparing a silicon-gallium nitride composite device, including preparing the silicon-gallium nitride composite device by using any of the above-mentioned preparation methods for a silicon-gallium nitride composite substrate.
  • the present invention also provides a silicon-gallium nitride composite device, wherein the silicon-gallium nitride composite device includes any one of the above-mentioned silicon-gallium nitride composite substrates.
  • the silicon-gallium nitride composite substrate, the composite device and the preparation method of the present invention can prepare a silicon-based and a gallium-nitride-based composite substrate integrated on the same plane, and further can prepare a coplanar integrated silicon-nitride Gallium composite devices, so as to realize coplanar and small-pitch on-chip interconnection of silicon devices and gallium nitride devices in the wafer manufacturing stage, solve the problem of parasitic effects of device interconnection of different materials, and save board area, improve integration, and improve integrated devices. performance.
  • FIG. 1 is a schematic diagram showing the process flow of preparing a silicon-gallium nitride composite substrate in the present invention.
  • FIG. 2a is a schematic structural diagram of a silicon substrate in the present invention.
  • FIG. 2b is a schematic structural diagram of another silicon substrate of the present invention.
  • FIG. 3 is a schematic view of the structure after the III-N epitaxial structure is formed in the present invention.
  • FIG. 4 is a schematic view of the structure after forming the isolation sidewall in the present invention.
  • FIG. 5 is a schematic view of the structure after forming the second silicon layer in the present invention.
  • FIG. 6 is a schematic view of the structure after forming the second hard mask layer in the present invention.
  • FIG. 7 is a schematic diagram of the structure after forming the shallow trench in the present invention.
  • FIG. 8 is a schematic diagram of the structure after forming the shallow trench isolation structure in the present invention.
  • spatially relative terms such as “below,” “below,” “below,” “below,” “above,” “on,” etc. may be used herein to describe an element shown in the figures or The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures.
  • a layer when referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between” means including both endpoints.
  • references where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include further features formed over the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.
  • this embodiment provides a method for preparing a silicon-gallium nitride composite substrate, which includes the following steps:
  • III-N epitaxial structure on the surface of the first silicon layer, the III-N epitaxial structure including a GaN channel layer and an AlGaN barrier layer;
  • first hard mask layer covering the III-N epitaxial structure, and patterning the first hard mask layer
  • isolation spacers in the grooves, the isolation spacers covering the sidewalls of the III-N epitaxial structure
  • the shallow trench isolation structure fills the shallow trench, and the shallow trench isolation structure penetrates the first silicon layer;
  • the second hard mask layer is exposed.
  • This embodiment can prepare a composite substrate that integrates silicon-based and gallium-nitride-based on the same plane, and can further be used to integrate a co-planar silicon-gallium nitride composite device, so as to realize silicon device and gallium nitride device in the wafer manufacturing stage
  • Coplanar, small-pitch on-chip interconnection solves the problem of parasitic effects of interconnection of devices with different materials, and can save board area, improve integration, and improve the performance of integrated devices.
  • FIGS. 2 a to 8 schematic diagrams of the structures presented when the silicon-gallium nitride composite substrate is prepared in this embodiment are shown.
  • a silicon substrate 100 is provided first, and the silicon substrate 100 includes a first silicon layer 101 .
  • silicon-on-insulator is used as the silicon substrate 100 , that is, the silicon substrate 100 includes a first silicon layer 101 , an intermediate silicon oxide insulating layer 102 and a silicon substrate 103 .
  • the type and structure of the silicon substrate 100 are not limited to this.
  • the silicon substrate 100 can also be a silicon substrate with the first silicon layer 101 on the surface.
  • the upper layer is the first silicon layer 101
  • the lower layer is A silicon substrate 103 or a silicon substrate of a silicon carbide layer
  • the first silicon layer 101 is a Si(111) layer, so as to facilitate epitaxial growth of the GaN layer.
  • the silicon substrate 100 can be directly purchased or prepared by bonding and peeling methods, and the material, structure and size of the silicon substrate 100 can be selected according to specific needs, which are not excessively limited here.
  • a III-N epitaxial structure 200 is formed on the surface of the first silicon layer 101 , and the III-N epitaxial structure 200 includes a GaN channel layer and an AlGaN barrier layer.
  • the III-N epitaxial structure 200 may further include a buffer layer between the first silicon layer 101 and the GaN channel layer, and the buffer layer 200 is preferably a buffer stack structure.
  • the GaN channel layer is heteroepitaxially grown on the first silicon layer 101
  • the first silicon layer 101 and the GaN material have problems of lattice mismatch and thermal expansion coefficient mismatch, so when the buffer layer is introduced between the first silicon layer 101 and the GaN channel layer, the buffer layer can be used to adjust the stress, and then the GaN channel can be epitaxially formed on the punch layer in sequence. channel layer and AlGaN barrier layer, etc.
  • the buffer layer may be an AlxGa1 - xN buffer stack, where 0 ⁇ x ⁇ 1, that is, the buffer layer may include AlN layers stacked sequentially from bottom to top and Alx with graded composition
  • the Ga 1-x N layer such as the Al 0.3 Ga 0.7 N layer, the Al 0.5 Ga 0.5 N layer, etc., can be specifically selected according to needs, and is not excessively limited here.
  • the group III-N epitaxial structure can be provided with relevant functional layers as required, so as to facilitate the subsequent preparation and integration of silicon-gallium nitride composite devices with different functions. Therefore, the group III-N epitaxial structure 200 Not limited to the above examples.
  • a first hard mask layer 301 covering the III-N epitaxial structure 200 is formed, and the first hard mask layer 301 is patterned.
  • a capping layer may be included between the AlGaN barrier layer and the first hard mask layer 301 , wherein the capping layer may include a p-GaN capping layer, but is not limited thereto, and may be specific as required Make settings and selections.
  • the first hard mask layer 301 includes one or a combination of a silicon nitride layer and a silicon oxide layer.
  • the etching window of the groove 400 can be formed by patterning the first hard mask layer 301, so that the III- The N group epitaxial structure 200 is protected.
  • the first hard mask layer 301 is a silicon nitride layer, but it is not limited to this.
  • a stack of a silicon oxide layer and a silicon nitride layer or only a silicon oxide layer can be used here. Do not impose excessive restrictions.
  • the III-N epitaxial structure 200 is etched to form the groove 400 exposing the first silicon layer 101 ; and an isolation spacer 500 is formed in the groove 400 , and the isolation spacer 500 is formed. The sidewalls of the III-N epitaxial structure 200 are covered.
  • the material of the isolation spacer 500 includes one or a combination of a silicon nitride layer and a silicon oxide layer.
  • the exposed III-N epitaxial structure 200 can be protected by the isolation sidewall 500 , and the isolation sidewall 500 can play a supporting role, and the isolation sidewall 500 is formed to be shallow in subsequent steps.
  • the shallow trench 600 can be prepared based on the isolation spacer 500 , thereby reducing damage to the III-N epitaxial structure 200 and the first silicon layer 101 .
  • a second silicon layer 111 is formed, and the second silicon layer 111 fills the groove 400 .
  • the material of the second silicon layer 111 is preferably the same as that of the first silicon layer 101 , that is, the second silicon layer 111 is a Si(111) layer.
  • the method for preparing the second silicon layer 111 includes selective epitaxy, but it is not limited thereto, and the material and preparation method of the second silicon layer 111 can be selected according to specific needs.
  • a planarization process step is included to expose the first hard mask layer 301 to obtain a flat surface, which is convenient for subsequent process preparation.
  • the first hard mask layer 301 is removed, a second hard mask layer 302 is formed, and the second hard mask layer 302 is patterned.
  • the second hard mask layer 302 includes one or a combination of a silicon nitride layer and a silicon oxide layer.
  • the etching window of the shallow trench 600 can be formed by patterning the second hard mask layer 302, so that the second hard mask layer 302 can be used to perform the etching process in the subsequent etching process.
  • the III-N epitaxial structure 200 is protected.
  • the second hard mask layer 302 is a silicon nitride layer, but it is not limited to this.
  • a stack of a silicon oxide layer and a silicon nitride layer or only a silicon oxide layer can be used here. Do not impose excessive restrictions.
  • the isolation spacers 500 are removed to form the shallow trenches 600 .
  • the isolation spacer 500 is removed, the first silicon layer 101 is continuously etched until the first silicon layer 101 is penetrated, so that after the shallow trench isolation structure 700 is subsequently formed,
  • the silicon-based device region and the GaN device region can be divided by the shallow trench isolation structure 700 , and devices with different functions can be completely isolated by the shallow trench isolation structure 700 to avoid crosstalk and improve the performance of the integrated device.
  • the shallow trench isolation structure 700 is formed, the shallow trench isolation structure 700 fills the shallow trench 600 , and the shallow trench isolation structure 700 penetrates the first silicon layer 101 .
  • the shallow trench isolation structure 700 includes one or a combination of a silicon nitride layer and a silicon oxide layer.
  • the size and specific type of the shallow trench isolation structure 700 can be selected according to requirements, which are not excessively limited here.
  • the shallow trench isolation structure 700 is formed by depositing a silicon oxide material with high concentration plasma (HDP) to fill the shallow trench 600 to form the high quality shallow trench isolation structure 700 .
  • HDP high concentration plasma
  • a planarization process step is included to expose the second hard mask layer 302 to obtain a flat surface, which is convenient for subsequent process preparation.
  • CMP chemical mechanical polishing
  • the surface of the second silicon layer 111 is flush with the surface of the shallow trench isolation structure 700 , sufficient base space can be provided for subsequent fabrication of silicon-based devices, and the surface of the second silicon layer 111 Being flush with the surface of the shallow trench isolation structure 700 can also reduce the height difference between the silicon-based device and the GaN device to be subsequently fabricated during interconnection, so as to reduce extra parasitics and improve the performance of the integrated device.
  • this embodiment also provides a silicon-gallium nitride composite substrate.
  • the silicon-gallium nitride composite substrate can be prepared by the above-mentioned preparation process, but is not limited to this.
  • the above-mentioned preparation method prepares the silicon-gallium nitride composite substrate. Therefore, for the material, structure, preparation process and beneficial effects of the silicon-gallium nitride composite substrate, reference can be made to the above-mentioned embodiments.
  • the silicon-gallium nitride composite substrate includes a silicon substrate 100 , a shallow trench isolation structure 700 , a III-N group epitaxial structure 200 and a second silicon layer 111 .
  • the silicon substrate 100 includes a first silicon layer 101; the shallow trench isolation structure 700 is located on the silicon substrate 100, and the shallow trench isolation structure 700 penetrates the first silicon layer 101;
  • the The III-N epitaxial structure 200 is located on the surface of the first silicon layer 101 , the III-N epitaxial structure 200 includes a GaN channel layer and an AlGaN barrier layer, and the III-N epitaxial structure 200 is located on the surface of the first silicon layer 101 .
  • the outer side of the shallow trench isolation structure 700 ; the second silicon layer 111 is located on the surface of the first silicon layer 101 , and the second silicon layer 111 is located at the inner side of the shallow trench isolation structure 700 .
  • the surface of the second silicon layer 111 is flush with the surface of the shallow trench isolation structure 700 .
  • the difference between the silicon-based device and the GaN device to be prepared subsequently can be reduced.
  • the height difference when interconnecting is made to reduce additional parasitics and improve the performance of integrated devices.
  • the silicon substrate 100 includes an SOI substrate; the first silicon layer is a Si(111) layer; the second silicon layer is a Si(111) layer; the shallow trench isolation structure 700 includes silicon nitride one or a combination of layers and silicon oxide layers.
  • This embodiment also provides a method for preparing a silicon-gallium nitride composite device, and the method for preparing a silicon-gallium nitride composite device includes preparing the silicon-gallium nitride composite substrate using the above-mentioned method for preparing a silicon-gallium nitride composite substrate. GaN composite devices. The preparation method, structure and material of the silicon-gallium nitride composite substrate will not be repeated here.
  • the silicon-gallium nitride composite substrate is prepared and formed, sources, gates and drains, as well as interconnection structures can be prepared as required to form integrated GaN HEMT devices and Si MOS devices.
  • the composite device but not limited to this, the formed silicon-gallium nitride composite device may also include composite devices such as integrated GaN lasers and Si MOS devices or composite devices of integrated GaN LED devices and Si MOS devices, etc., according to The type of integrated device required only needs to be adaptively selected and replaced with the III-N epitaxial structure 200
  • This embodiment also provides a silicon-gallium nitride composite device, and the silicon-gallium nitride composite device includes the above-mentioned silicon-gallium nitride composite substrate.
  • the preparation method, structure and material of the silicon-gallium nitride composite substrate will not be repeated here.
  • the silicon-gallium nitride composite device may include a composite device integrating a GaN HEMT device and a Si MOS device, the composite device can achieve higher efficiency, and the composite device is similar to the packaged interconnected cascode structure gallium nitride device. ratio, the parasitic capacitance can be reduced by 20%.
  • the silicon-gallium nitride composite device is not limited to this, and the silicon-gallium nitride composite device may also include a composite device integrating a GaN laser and a Si MOS device or a composite device integrating a GaN LED device and a Si MOS device etc., according to the type of integrated device required, it is only necessary to select and replace the III-N epitaxial structure 200 adaptively.
  • the silicon-gallium nitride composite substrate, composite device and preparation method of the present invention can prepare a silicon-based and gallium-nitride-based composite substrate integrated on the same plane, and further can prepare a coplanar integrated silicon-nitrogen GaN composite devices, so as to realize coplanar and small-pitch on-chip interconnection of silicon devices and GaN devices in the wafer manufacturing stage, solve the parasitic effect of interconnection between devices of different materials, save board area, improve integration, and can Shorten interconnect paths and improve the performance of integrated devices.

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Abstract

本发明提供一种硅-氮化镓复合衬底、复合器件及制备方法，硅-氮化镓复合衬底包括硅基底、浅沟槽隔离结构、III-N族外延结构及第二硅层；硅基底包括第一硅层；浅沟槽隔离结构位于硅基底上且贯穿第一硅层；III-N族外延结构位于第一硅层的表面包括GaN沟道层及AlGaN势垒层且位于浅沟槽隔离结构的外侧；第二硅层位于第一硅层的表面且位于浅沟槽隔离结构的内侧。本发明可在同一平面集成硅基及氮化镓基的复合衬底，进一步可制备共平面集成硅-氮化镓复合器件，从而在晶圆制造阶段实现硅器件和氮化镓器件共平面、小间距片上互联，解决不同材料器件互联的寄生效应问题，且可节省占板面积，提高集成度及集成器件的性能。

Description

硅-氮化镓复合衬底、复合器件及制备方法 技术领域
本发明属于半导体技术领域，涉及一种硅-氮化镓复合衬底、复合器件及制备方法。
背景技术
作为第三代半导体材料的代表，氮化镓(GaN)具有如宽带隙、优越的抗辐噪性、高雪崩击穿电场、良好的热传导率以及强场下高电子漂移速率等众多优良特性，被广泛应用于如激光、LED、微波、射频等领域中。
现有电力半导体市场以硅的功率器件为主，在过去的20年里，硅功率器件每隔10年提高5～6倍的电力密度，但是其电力密度已经接近理论极限，很难再进一步的提高性能。相比硅或砷化镓，GaN半导体由于其带隙宽、优良的热稳定性、高击穿电压、高电子饱和漂移速度及优良的抗辐射性能，以及相比于硅电力半导体，GaN电力半导体还有低温抵抗特性，从而GaN电力半导体可以减少电力半导体引起的电力转换损失，做到电力系统、电力损耗最少化等优点。
目前GaN器件主要以分立器件为主，GaN集成电路具有明显优势，但由于GaN材料不可以通过离子注入或者扩散的方式随意的定义p型区域或n型区域，因而限制了GaN集成电路的发展。目前主流是采用器件级联的方法，即通过外接打线互联或倒装植球互联的方式将硅基金属氧化物场效应晶体管器件(Si MOSFET)与GaN器件进行互连，但这种封装互联的方法，会引入额外寄生，降低整个集成器件的性能，还增加系统集成面积。
因此，提供一种硅-氮化镓复合衬底、复合器件及制备方法，尤其是在高频、高速GaN集成电路领域，实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种硅-氮化镓复合衬底、复合器件及制备方法，用于解决现有技术中难以制备GaN集成电路的问题。
为实现上述目的及其他相关目的，本发明提供一种硅-氮化镓复合衬底的制备方法，包括以下步骤：
提供硅基底，所述硅基底包括第一硅层；
于所述第一硅层的表面形成III-N族外延结构，所述III-N族外延结构包括GaN沟道层及AlGaN势垒层；
形成覆盖所述III-N族外延结构的第一硬掩膜层，并图形化所述第一硬掩膜层；
刻蚀所述III-N族外延结构，形成显露所述第一硅层的凹槽；
于所述凹槽中形成隔离侧墙，所述隔离侧墙覆盖所述III-N族外延结构的侧壁；
形成第二硅层，所述第二硅层填充所述凹槽；
显露所述第一硬掩膜层；
去除所述第一硬掩膜层，形成第二硬掩膜层，并图形化所述第二硬掩膜层；
去除所述隔离侧墙，形成浅沟槽；
形成浅沟槽隔离结构，所述浅沟槽隔离结构填充所述浅沟槽，且所述浅沟槽隔离结构贯穿所述第一硅层；
显露所述第二硬掩膜层。
可选地，通过CMP工艺，使得所述第二硅层的表面与所述浅沟槽隔离结构的表面齐平。
可选地，所述硅基底包括SOI基底或通过键合法形成的表面具有所述第一硅层的硅基底；所述第一硅层为Si(111)层；所述第二硅层为Si(111)层。
可选地，所述III-N族外延结构还包括位于所述第一硅层与所述GaN沟道层之间的缓冲层及位于所述AlGaN势垒层与所述第一硬掩膜层之间的盖帽层中的一种或组合。
可选地，所述第一硬掩膜层包括氮化硅层及氧化硅层中的一种或组合；所述第二硬掩膜层包括氮化硅层及氧化硅层中的一种或组合；所述浅沟槽隔离结构包括氮化硅层及氧化硅层中的一种或组合。
本发明还提供一种硅-氮化镓复合衬底，所述硅-氮化镓复合衬底包括：
硅基底，所述硅基底包括第一硅层；
浅沟槽隔离结构，所述浅沟槽隔离结构位于所述硅基底上，且所述浅沟槽隔离结构贯穿所述第一硅层；
III-N族外延结构，所述III-N族外延结构位于所述第一硅层的表面，所述III-N族外延结构包括GaN沟道层及AlGaN势垒层，且所述III-N族外延结构位于所述浅沟槽隔离结构的外侧；
第二硅层，所述第二硅层位于所述第一硅层的表面，且所述第二硅层位于所述浅沟槽隔离结构的内侧。
可选地，所述第二硅层的表面与所述浅沟槽隔离结构的表面齐平。
可选地，所述硅基底包括SOI基底；所述第一硅层为Si(111)层；所述第二硅层为Si(111)层；所述浅沟槽隔离结构包括氮化硅层及氧化硅层中的一种或组合。
本发明还提供一种硅-氮化镓复合器件的制备方法，包括采用上述任一硅-氮化镓复合衬底的制备方法制备所述硅-氮化镓复合器件。
本发明还提供一种硅-氮化镓复合器件，所述硅-氮化镓复合器件包括上述任一所述硅-氮化镓复合衬底。
如上所述，本发明的硅-氮化镓复合衬底、复合器件及制备方法，可制备在同一平面集成硅基及氮化镓基的复合衬底，进一步可制备共平面集成硅-氮化镓复合器件，从而在晶圆制造阶段实现硅器件和氮化镓器件共平面、小间距片上互联，解决不同材料器件互联的寄生效应问题，且可节省占板面积，提高集成度，提高集成器件的性能。
附图说明
图1显示为本发明中制备硅-氮化镓复合衬底的工艺流程示意图。
图2a显示为本发明中一种硅基底的结构示意图。
图2b显示为本发明另一种硅基底的结构示意图。
图3显示为本发明中形成III-N族外延结构后的结构示意图。
图4显示为本发明中形成隔离侧墙后的结构示意图。
图5显示为本发明中形成第二硅层后的结构示意图。
图6显示为本发明中形成第二硬掩膜层后的结构示意图。
图7显示为本发明中形成浅沟槽后的结构示意图。
图8显示为本发明中形成浅沟槽隔离结构后的结构示意图。
元件标号说明
100                    硅基底
101                    第一硅层
111                    第二硅层
102                    氧化硅绝缘层
103                    硅衬底
200                    III-N族外延结构
301                    第一硬掩膜层
302                    第二硬掩膜层
400                    凹槽
500                    隔离侧墙
600                    浅沟槽
700                    浅沟槽隔离结构
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
如在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。本文使用的“介于……之间”表示包括两端点值。
在本申请的上下文中，所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，其组件布局型态也可能更为复杂。
如图1所示，本实施例提供一种硅-氮化镓复合衬底的制备方法，包括以下步骤：
提供硅基底，所述硅基底包括第一硅层；
于所述第一硅层的表面形成III-N族外延结构，所述III-N族外延结构包括GaN沟道层及AlGaN势垒层；
形成覆盖所述III-N族外延结构的第一硬掩膜层，并图形化所述第一硬掩膜层；
刻蚀所述III-N族外延结构，形成显露所述第一硅层的凹槽；
于所述凹槽中形成隔离侧墙，所述隔离侧墙覆盖所述III-N族外延结构的侧壁；
形成第二硅层，所述第二硅层填充所述凹槽；
显露所述第一硬掩膜层；
去除所述第一硬掩膜层，形成第二硬掩膜层，并图形化所述第二硬掩膜层；
去除所述隔离侧墙，形成浅沟槽；
形成浅沟槽隔离结构，所述浅沟槽隔离结构填充所述浅沟槽，且所述浅沟槽隔离结构贯穿所述第一硅层；
显露所述第二硬掩膜层。
本实施例可制备在同一平面集成硅基及氮化镓基的复合衬底，进一步可用以集成制备共平面硅-氮化镓复合器件，从而在晶圆制造阶段实现硅器件和氮化镓器件共平面、小间距片上互联，解决不同材料器件互联的寄生效应问题，且可节省占板面积，提高集成度，提高集成器件的性能。
具体的，参阅图2a～图8，显示为本实施例中制备所述硅-氮化镓复合衬底时所呈现的结构示意图。
参阅图2a及图2b，首先提供硅基底100，所述硅基底100包括第一硅层101。
具体的，本实施例中，以绝缘体上硅(SOI)作为所述硅基底100，即所述硅基底100包括第一硅层101、中间氧化硅绝缘层102及硅衬底103，但所述硅基底100的种类及结构并非局限于此，如图2b，所述硅基底100还可采用表面具有所述第一硅层101的硅基底，如上层为所述第一硅层101，下层为硅衬底103或碳化硅层的硅基底，且所述第一硅层101为Si(111)层，以便于外延生长所述GaN层。其中，所述硅基底100可直接采购或通过键合与剥离的方法进行制备，且所述硅基底100的材质、结构及尺寸等，具体可根据需要进行选择，此处不作过分限制。
接着，参阅图3，于所述第一硅层101的表面形成III-N族外延结构200，所述III-N族外延结构200包括GaN沟道层及AlGaN势垒层。
作为示例，所述III-N族外延结构200还可包括位于所述第一硅层101与所述GaN沟道层之间的缓冲层，且所述缓冲层200优选为缓冲叠层结构。
具体的，当在所述第一硅层101上异质外延所述GaN沟道层时，所述第一硅层101与GaN材料存在晶格不匹配以及热膨胀系数不匹配的问题，从而当在所述第一硅层101与所述GaN沟道层之间引入所述缓冲层后，可通过所述缓冲层用以进行应力的调节，而后再在所述冲层上依次外延所述GaN沟道层及AlGaN势垒层等。其中，所述缓冲层可为Al xGa 1-xN缓冲叠层，其中0≤x≤1，即所述缓冲层可包括自下而上依次叠置的AlN层及组分渐变的Al xGa 1-xN层，如Al 0.3Ga 0.7N层、Al 0.5Ga 0.5N层等，具体可根据需要进行选择，此处不作过分限制。需 要说明的是所述III-N族外延结构可根据需要进行相关功能层的设置，以便于后续制备集成具有不同功能的硅-氮化镓复合器件，因此，所述III-N族外延结构200并非局限于上述示例。
接着，参阅图4，形成覆盖所述III-N族外延结构200的第一硬掩膜层301，并图形化所述第一硬掩膜层301。
作为示例，所述AlGaN势垒层与所述第一硬掩膜层301之间可包括盖帽层，其中，所述盖帽层可包括p-GaN盖帽层，但并非局限于此，具体可根据需要进行设置及选择。
作为示例，所述第一硬掩膜层301包括氮化硅层及氧化硅层中的一种或组合。
具体的，通过图形化所述第一硬掩膜层301可形成凹槽400的刻蚀窗口，从而在进行后续的刻蚀工艺中通过所述第一硬掩膜层301可对所述III-N族外延结构200进行保护。本实施例中，所述第一硬掩膜层301采用氮化硅层，但并非局限于此，如也可采用氧化硅层及氮化硅层的叠层或仅采用氧化硅层，此处不作过分限制。
接着，刻蚀所述III-N族外延结构200，形成显露所述第一硅层101的所述凹槽400；并于所述凹槽400中形成隔离侧墙500，所述隔离侧墙500覆盖所述III-N族外延结构200的侧壁。
作为示例，所述隔离侧墙500的材质包括氮化硅层及氧化硅层中的一种或组合。
具体的，通过所述隔离侧墙500可对显露的所述III-N族外延结构200进行保护，且所述隔离侧墙500可起到支撑作用，且所述隔离侧墙500在后续形成浅沟槽隔离结构700时，可基于所述隔离侧墙500进行浅沟槽600的制备，从而可降低对所述III-N族外延结构200及所述第一硅层101的损伤。
接着，参阅图5，形成第二硅层111，所述第二硅层111填充所述凹槽400。
作为示例，所述第二硅层111的材质优选为与所述第一硅层101相同，即所述第二硅层111为Si(111)层。
具体的，制备所述第二硅层111的方法包括选择性外延，但并非局限于此，所述第二硅层111的材质、制备方法可以根据具体需要进行选择。其中，在形成所述第二硅层111之后，包括进行平坦化的工艺步骤，以显露所述第一硬掩膜层301，获得平整的表面，便于后续的工艺制备。
接着，参阅图6，去除所述第一硬掩膜层301，形成第二硬掩膜层302，并图形化所述第二硬掩膜层302。
作为示例，所述第二硬掩膜层302包括氮化硅层及氧化硅层中的一种或组合。
具体的，通过图形化所述第二硬掩膜层302可形成所述浅沟槽600的刻蚀窗口，从而在 进行后续的刻蚀工艺中通过所述第二硬掩膜层302可对所述III-N族外延结构200进行保护。本实施例中，所述第二硬掩膜层302采用氮化硅层，但并非局限于此，如也可采用氧化硅层及氮化硅层的叠层或仅采用氧化硅层，此处不作过分限制。
接着，如图7，去除所述隔离侧墙500，形成所述浅沟槽600。
具体的，在去除所述隔离侧墙500之后，继续对所述第一硅层101进行刻蚀，直至贯穿所述第一硅层101，从而在后续形成所述浅沟槽隔离结构700后，可通过所述浅沟槽隔离结构700划分出硅基器件区域及GaN器件区域，且通过所述浅沟槽隔离结构700可将具有不同功能的器件完全隔离，避免串扰，提高集成器件的性能。
接着，如图8，形成所述浅沟槽隔离结构700，所述浅沟槽隔离结构700填充所述浅沟槽600，且所述浅沟槽隔离结构700贯穿所述第一硅层101。
作为示例，所述浅沟槽隔离结构700包括氮化硅层及氧化硅层中的一种或组合。
具体的，所述浅沟槽隔离结构700的尺寸、具体种类等可根据需要进行选择，此处不作过分限制。本实施例中，优选所述浅沟槽隔离结构700采用高浓度等离子流(HDP)淀积氧化硅材料以填充所述浅沟槽600形成高质量的所述浅沟槽隔离结构700。在填充所述浅沟槽600之后，包括进行平坦化的工艺步骤，以显露所述第二硬掩膜层302，获得平整的表面，便于后续的工艺制备。
作为示例，优选采用化学机械研磨法(CMP)进行所述浅沟槽隔离结构700的平坦化工艺，以获得表面粗糙度较小的平整表面，使得所述第二硅层111的表面与所述浅沟槽隔离结构700的表面齐平。
具体的，当所述第二硅层111的表面与所述浅沟槽隔离结构700的表面齐平时，可为后续制备硅基器件提供足够的基底空间，且所述第二硅层111的表面与所述浅沟槽隔离结构700的表面齐平还可降低后续制备的硅基器件与GaN器件在进行互连时的高度差，以降低额外寄生，提高集成器件的性能。
如图8，本实施例还提供一种硅-氮化镓复合衬底，所述硅-氮化镓复合衬底可采用上述制备工艺制备，但并非局限于此，本实施例中，直接采用上述制备方法制备所述硅-氮化镓复合衬底，因此，有关所述硅-氮化镓复合衬底的材质、结构、制备工艺及有益效果等均可参阅上述实施例。
具体的，所述硅-氮化镓复合衬底包括硅基底100、浅沟槽隔离结构700、III-N族外延结构200及第二硅层111。其中，所述硅基底100包括第一硅层101；所述浅沟槽隔离结构700位于所述硅基底100上，且所述浅沟槽隔离结构700贯穿所述第一硅层101；所述III-N族外 延结构200位于所述第一硅层101的表面，所述III-N族外延结构200包括GaN沟道层及AlGaN势垒层，且所述III-N族外延结构200位于所述浅沟槽隔离结构700的外侧；所述第二硅层111位于所述第一硅层101的表面，且所述第二硅层111位于所述浅沟槽隔离结构700的内侧。
作为示例，所述第二硅层111的表面与所述浅沟槽隔离结构700的表面齐平。以便于后续为制备硅基器件提供足够的基底空间，且所述第二硅层111的表面与所述浅沟槽隔离结构700的表面齐平还可降低后续制备的硅基器件与GaN器件在进行互连时的高度差，以降低额外寄生，提高集成器件的性能。
作为示例，所述硅基底100包括SOI基底；所述第一硅层为Si(111)层；所述第二硅层为Si(111)层；所述浅沟槽隔离结构700包括氮化硅层及氧化硅层中的一种或组合。
本实施例中还提供一种硅-氮化镓复合器件的制备方法，所述硅-氮化镓复合器件的制备方法包括采用上述硅-氮化镓复合衬底的制备方法制备所述硅-氮化镓复合器件。有关所述硅-氮化镓复合衬底的制备方法、结构、材质等此处不作赘述。
具体的，在制备形成所述硅-氮化镓复合衬底之后，可根据需要制备如源极、栅极及漏极以及互连结构的制备等，以形成如集成GaN HEMT器件及Si MOS器件的复合器件，但并非局限于此，形成的所述硅-氮化镓复合器件还可包括如集成GaN激光器及Si MOS器件的复合器件或集成GaN LED器件及Si MOS器件的复合器件等，根据所需的集成器件的种类，仅需对所述III-N族外延结构200进行适应性的选择及替换即可
本实施例中还提供一种硅-氮化镓复合器件，所述硅-氮化镓复合器件包括上述硅-氮化镓复合衬底。有关所述硅-氮化镓复合衬底的制备方法、结构、材质等此处不作赘述。
具体的，所述硅-氮化镓复合器件可包括集成GaN HEMT器件及Si MOS器件的复合器件，该复合器件可实现更高的效率，该复合器件与封装互联的cascode结构氮化镓器件相比，寄生电容可减小20％。但所述硅-氮化镓复合器件并非局限于此，所述硅-氮化镓复合器件还可包括如集成GaN激光器及Si MOS器件的复合器件或集成GaN LED器件及Si MOS器件的复合器件等，根据所需的集成器件的种类，仅需对所述III-N族外延结构200进行适应性的选择及替换即可。
综上所述，本发明的硅-氮化镓复合衬底、复合器件及制备方法，可制备在同一平面集成硅基及氮化镓基的复合衬底，进一步可制备共平面集成硅-氮化镓复合器件，从而在晶圆制造阶段实现硅器件和氮化镓器件共平面、小间距片上互联，解决不同材料器件互联的寄生效应问题，且可节省占板面积，提高集成度，且可缩短互连路径，提高集成器件的性能。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种硅-氮化镓复合衬底的制备方法，其特征在于，包括以下步骤：
    提供硅基底，所述硅基底包括第一硅层；
    于所述第一硅层的表面形成III-N族外延结构，所述III-N族外延结构包括GaN沟道层及AlGaN势垒层；
    形成覆盖所述III-N族外延结构的第一硬掩膜层，并图形化所述第一硬掩膜层；
    刻蚀所述III-N族外延结构，形成显露所述第一硅层的凹槽；
    于所述凹槽中形成隔离侧墙，所述隔离侧墙覆盖所述III-N族外延结构的侧壁；
    形成第二硅层，所述第二硅层填充所述凹槽；
    显露所述第一硬掩膜层；
    去除所述第一硬掩膜层，形成第二硬掩膜层，并图形化所述第二硬掩膜层；
    去除所述隔离侧墙，形成浅沟槽；
    形成浅沟槽隔离结构，所述浅沟槽隔离结构填充所述浅沟槽，且所述浅沟槽隔离结构贯穿所述第一硅层；
    显露所述第二硬掩膜层。
  2. 根据权利要求1所述的硅-氮化镓复合衬底的制备方法，其特征在于：通过CMP工艺，使得所述第二硅层的表面与所述浅沟槽隔离结构的表面齐平。
  3. 根据权利要求1所述的硅-氮化镓复合衬底的制备方法，其特征在于：所述硅基底包括SOI基底或通过键合法形成的表面具有所述第一硅层的硅基底；所述第一硅层为Si(111)层；所述第二硅层为Si(111)层。
  4. 根据权利要求1所述的硅-氮化镓复合衬底的制备方法，其特征在于：所述III-N族外延结构还包括位于所述第一硅层与所述GaN沟道层之间的缓冲层及位于所述AlGaN势垒层与所述第一硬掩膜层之间的盖帽层中的一种或组合。
  5. 根据权利要求1所述的硅-氮化镓复合衬底的制备方法，其特征在于：所述第一硬掩膜层包括氮化硅层及氧化硅层中的一种或组合；所述第二硬掩膜层包括氮化硅层及氧化硅层中的一种或组合；所述浅沟槽隔离结构包括氮化硅层及氧化硅层中的一种或组合。
  6. 一种硅-氮化镓复合衬底，其特征在于，所述硅-氮化镓复合衬底包括：
    硅基底，所述硅基底包括第一硅层；
    浅沟槽隔离结构，所述浅沟槽隔离结构位于所述硅基底上，且所述浅沟槽隔离结构贯穿所述第一硅层；
    III-N族外延结构，所述III-N族外延结构位于所述第一硅层的表面，所述III-N族外延结构包括GaN沟道层及AlGaN势垒层，且所述III-N族外延结构位于所述浅沟槽隔离结构的外侧；
    第二硅层，所述第二硅层位于所述第一硅层的表面，且所述第二硅层位于所述浅沟槽隔离结构的内侧。
  7. 根据权利要求6所述的硅-氮化镓复合衬底，其特征在于：所述第二硅层的表面与所述浅沟槽隔离结构的表面齐平。
  8. 根据权利要求6所述的硅-氮化镓复合衬底，其特征在于：所述硅基底包括SOI基底；所述第一硅层为Si(111)层；所述第二硅层为Si(111)层；所述浅沟槽隔离结构包括氮化硅层及氧化硅层中的一种或组合。
  9. 一种硅-氮化镓复合器件的制备方法，其特征在于：包括采用权利要求1～5中任一所述硅-氮化镓复合衬底的制备方法制备所述硅-氮化镓复合器件。
  10. 一种硅-氮化镓复合器件，其特征在于：所述硅-氮化镓复合器件包括权利要求6～8中任一所述硅-氮化镓复合衬底。
PCT/CN2022/077459 2021-03-24 2022-02-23 硅-氮化镓复合衬底、复合器件及制备方法 WO2022199310A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN113130297A (zh) * 2021-03-24 2021-07-16 聚能晶源(青岛)半导体材料有限公司 硅-氮化镓复合衬底、复合器件及制备方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060289876A1 (en) * 2005-06-14 2006-12-28 Mike Briere Methods of combining silicon and III-Nitride material on a single wafer
US20110140176A1 (en) * 2009-12-10 2011-06-16 International Rectifier Corporation Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same
CN103021927A (zh) * 2012-12-26 2013-04-03 中国科学院上海微系统与信息技术研究所 混合共平面soi衬底结构及其制备方法
CN103311244A (zh) * 2012-03-06 2013-09-18 英飞凌科技奥地利有限公司 半导体器件及用于制造半导体器件的方法
CN105448845A (zh) * 2015-12-17 2016-03-30 中航（重庆）微电子有限公司 三层混合晶向绝缘体上半导体结构及其制作方法
CN107342215A (zh) * 2016-04-29 2017-11-10 上海芯晨科技有限公司 一种iii族氮化物和硅异质集成衬底及其制造方法
US9935175B1 (en) * 2017-04-17 2018-04-03 International Business Machines Corporation Sidewall spacer for integration of group III nitride with patterned silicon substrate
US20200295045A1 (en) * 2019-03-15 2020-09-17 International Business Machines Corporation ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GaN DEVICES
CN113130297A (zh) * 2021-03-24 2021-07-16 聚能晶源(青岛)半导体材料有限公司 硅-氮化镓复合衬底、复合器件及制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8242510B2 (en) * 2010-01-28 2012-08-14 Intersil Americas Inc. Monolithic integration of gallium nitride and silicon devices and circuits, structure and method
US9245760B2 (en) * 2010-09-30 2016-01-26 Infineon Technologies Ag Methods of forming epitaxial layers on a porous semiconductor layer
CN103021815B (zh) * 2012-12-26 2015-06-24 中国科学院上海微系统与信息技术研究所 混合共平面衬底结构及其制备方法
DE112015006854T5 (de) * 2015-08-28 2018-05-17 Intel Corporation Verfahren und Vorrichtungen zum Integrieren von III-N-Transistorschaltungen mit SI-Transistorschaltungen
WO2017222513A1 (en) * 2016-06-22 2017-12-28 Intel Corporation Techniques for monolithic co-integration of silicon and iii-n semiconductor transistors
US20200135766A1 (en) * 2018-10-30 2020-04-30 Qualcomm Incorporated Monolithic integration of gan hemt and si cmos

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060289876A1 (en) * 2005-06-14 2006-12-28 Mike Briere Methods of combining silicon and III-Nitride material on a single wafer
US20110140176A1 (en) * 2009-12-10 2011-06-16 International Rectifier Corporation Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same
CN103311244A (zh) * 2012-03-06 2013-09-18 英飞凌科技奥地利有限公司 半导体器件及用于制造半导体器件的方法
CN103021927A (zh) * 2012-12-26 2013-04-03 中国科学院上海微系统与信息技术研究所 混合共平面soi衬底结构及其制备方法
CN105448845A (zh) * 2015-12-17 2016-03-30 中航（重庆）微电子有限公司 三层混合晶向绝缘体上半导体结构及其制作方法
CN107342215A (zh) * 2016-04-29 2017-11-10 上海芯晨科技有限公司 一种iii族氮化物和硅异质集成衬底及其制造方法
US9935175B1 (en) * 2017-04-17 2018-04-03 International Business Machines Corporation Sidewall spacer for integration of group III nitride with patterned silicon substrate
US20200295045A1 (en) * 2019-03-15 2020-09-17 International Business Machines Corporation ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GaN DEVICES
CN113130297A (zh) * 2021-03-24 2021-07-16 聚能晶源(青岛)半导体材料有限公司 硅-氮化镓复合衬底、复合器件及制备方法

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