WO2022198880A1 - 一种任意字节读写用户侧逻辑控制器 - Google Patents

一种任意字节读写用户侧逻辑控制器 Download PDF

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Publication number
WO2022198880A1
WO2022198880A1 PCT/CN2021/111645 CN2021111645W WO2022198880A1 WO 2022198880 A1 WO2022198880 A1 WO 2022198880A1 CN 2021111645 W CN2021111645 W CN 2021111645W WO 2022198880 A1 WO2022198880 A1 WO 2022198880A1
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module
iic
data
user
side logic
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PCT/CN2021/111645
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French (fr)
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牛广
李顺斌
王利强
张兴明
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之江实验室
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Priority to JP2022572268A priority Critical patent/JP2023518326A/ja
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21113—Bus interface has multiplexer, control register, data shift register
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the invention relates to the field of control, in particular to an arbitrary byte read and write user side logic controller.
  • IIC Inter-Integrated Circuit, the full name of the integrated circuit bus
  • IIC is mainly used to connect the overall circuit.
  • IIC is a multi-directional control bus, which means that multiple chips can be connected to the same bus structure, and each chip can be connected to the same bus structure. It can be used as a control source for real-time data transmission.
  • the IIC protocol is used as a common transmission protocol to complete the complex timing requirements in the data process, and to monitor the status in the production process in real time.
  • the requirements for IIC are getting higher and higher, and new functions are also put forward.
  • the current IIC controller mainly uses the form of single byte to read and write the logic on the user side, and the usage scenarios have limitations; as the amount of data transmitted increases, there is greater flexibility in the number of transmitted bytes requirements.
  • the present invention proposes a user-side logic controller and method for reading and writing arbitrary bytes, and the specific technical solutions are as follows.
  • An arbitrary byte read-write user side logic controller comprising: a main control bus IIC MASTER module, a slave control bus IIC SLAVE module, a clock reset module and a user side logic module
  • the main control bus IIC MASTER module converts the user's The data is converted into the format of the IIC message and sent to the slave control bus IIC SLAVE module
  • the slave control bus IIC SLAVE module receives the data in the IIC message format
  • the user side logic module is connected with the slave control bus IIC SLAVE.
  • the modules are connected, and the clock reset module controls the connection from the control bus IIC SLAVE module to the user side logic module.
  • the format of the IIC message is the read and write message format configured by the IIC.
  • the field segment of the IIC write message format has 8 bytes, the first two bytes are the address field segment, and the last 6 bytes are.
  • the byte is the data field segment, that is, the 48-bit data composed of DATA0 ⁇ DATA5 is written into the 16-bit address register composed of ADDR0 and ADDR1;
  • the field segment of the IIC read message format has 2 bytes, both of which are address fields. segment, that is, read out the BLOCK RAM corresponding to the address composed of ADDR0 and ADDR1.
  • the state machine jump from the control bus IIC SLAVE module has a total of 8, including: IDLE, START, ID_RECV, ACK_ID_RECV, DATA_SEND, ACK_DATA_SEND, DATA_RECV, ACK_DATA_RECV, the IDLE state is the system default state, when detected When the SCL rises, the system jumps to the START state, the system enters the ID_RECV state, and starts to receive the ID number of the IIC message.
  • the DATA_SEND and ACK_DATA_SEND are: when When starting to send data, the first two bytes are the address field segment, and the last 6 bytes are the data field segment; the DATA_RECV and ACK_DATA_RECV are: when data starts to be received, the read address is two bytes.
  • the user side logic module includes: a register module unit, a distributed RAM module unit and a BLOCK RAM module unit connected with the slave control bus IIC SLAVE module.
  • the distributed RAM module unit includes: reverse mapping RAM, writing parameter RAM, reading parameter RAM, command RAM, PLC type RAM, and mapping RAM, which are used to store the startup and operation program of the central processing unit CPU and the user side. Configuration parameters for the logic module.
  • the described BLOCK RAM module unit configures 8 port port data of port0 ⁇ port7 of the user side logic module, and the BLOCK RAM configured by each port port is an address RAM.
  • the address range of the register module unit is: 0X0 ⁇ 0X1000, the number of bytes to be read and written is 2, and the 8 port port data of port0 ⁇ port7 of the user side logic module is configured, and each port port
  • the configured registers include protocol parameters, the role of the port, serial port parameters, and edge computing parameters.
  • the clock reset module includes: a clock synchronization module and a reset module, the clock synchronization module uses the 50M clock of the backplane to generate a 125Mhz clock through PLL frequency multiplication, and provides a clock source for the controller, so that the system is in a unified 125Mhz clock.
  • the reset module makes the system high reset, when the clock synchronization module generates a stable 125Mhz clock signal, the locked signal of the clock synchronization module is pulled high, and the lock signal of the clock synchronization module is used to count, When the count reaches 3F, the system is reset high.
  • the controller of the present invention adopts the traditional IIC interface to realize independent reading and writing of multiple address segments and data reading and writing of any byte, supports deterministic data transmission, reduces the delay and jitter of data transmission, and realizes multi-user data transmission.
  • Data upload and data release; among them, the traditional IIC interface is used to ensure the compatibility and unity of the traditional controller, and to ensure the accuracy, real-time and reliability of data transmission.
  • FIG. 1 is a schematic structural diagram of an arbitrary byte read-write user-side logic controller module of the present invention
  • Fig. 2 is the schematic diagram of the read and write message format of IIC configuration
  • Fig. 3 is the flow chart of IIC read-write state machine
  • Fig. 4 is the distributed RAM form schematic diagram of the distributed RAM module unit to the port0 ⁇ port7 of the user side;
  • FIG. 5 is a schematic diagram of the register form of port0 to port7 on the user side by the register module unit.
  • the controller supporting multi-user and multi-byte transmission of the present invention includes: main control bus IIC MASTER module, slave control bus IIC SLAVE module, clock reset module and user side logic module;
  • the described master control bus IIC MASTER module converts the user's data into the format of the IIC message and sends it to the slave control bus IIC SLAVE module to realize communication, logic control and data processing.
  • the IIC SLAVE module from the control bus receives the data in the IIC message format, parses and encapsulates time-sensitive data, provides a unified external Ethernet interface, and is compatible with traditional switches and time-sensitive network switches.
  • the read and write message format configured by IIC is shown in Figure 2.
  • the SLAVE ID of IIC is 0X54
  • the field segment of the IIC write message format has 8 bytes. The first two bytes are the address field segment, and the last 6 bytes are the address field segment.
  • Each byte is the data field segment, that is, the 48-bit data composed of DATA0 to DATA5 is written into the 16-bit address register composed of ADDR0 and ADDR1.
  • the field segment of the IIC read message format has 2 bytes, both of which are address field segments, that is, read the BLOCK RAM corresponding to the address composed of ADDR0 and ADDR1.
  • the IIC ID number of this device is 0X54. When the correct IIC ID number is received, it will jump to the ACK_ID_RECV state;
  • DATA_SEND When starting to send data, the first two bytes are the address field segment, and the last 6 bytes are the data field segment.
  • DATA_RECV When starting to receive data, the read address is two bytes.
  • the user side logic module includes: a register module unit, a distributed RAM module unit and a BLOCK RAM module unit connected with the slave control bus IIC SLAVE module.
  • the distributed RAM module unit includes: reverse mapping RAM, writing parameter RAM, reading parameter RAM, command RAM, PLC type RAM, and mapping RAM, which are used to store the startup operation program of the central processing unit CPU. and the configuration parameters of the user-side logic module, specifically:
  • the IIC address of the distributed RAM module unit 0X1000 ⁇ 0X2000, and the number of bytes read and written is 3.
  • the distributed RAM module unit configures the distributed RAM in the 8 ports of port 0 to port 7 on the user side.
  • the distributed RAM configured on each port is inversely mapped distributed RAM, write parameter distributed RAM, and read parameter distributed RAM.
  • portn_ivsmapform Inverse mapping distributed RAM corresponding to the port
  • portn_ivsmap2paraform_w Distributed RAM corresponding to the write parameters of the port port
  • portn_ivsmap2paraform_r The read parameter distributed RAM corresponding to the port is located;
  • portn_cmdform Command distributed RAM corresponding to the port port
  • portn_plctypeform plc type distributed RAM corresponding to the port
  • portn_mapform the mapped distributed RAM corresponding to the port
  • Described BLOCK RAM module unit comprises: address RAM, is used for storing the configuration parameter of the startup running program of central processing unit CPU and user side logic module, concrete:
  • the read and write addresses of BLOCK RAM are: 0X2000 ⁇ 0X3000, and the number of bytes read and written is 4;
  • the main function of the BLOCK RAM module is to configure the data of the 8 port ports of port0 ⁇ port7 on the user side, and the BLOCK RAM configured for each port port is the address RAM;
  • port0_addrform Convert the address of the source protocol to the address of the target protocol BLOCK RAM corresponding to the port port.
  • the register module unit is used to configure the registers used by the user-side logic module.
  • the address range of the register module is 0X0 ⁇ 0X1000, and the number of bytes to read and write is 2. More specifically: for the user Configure the data of the eight port ports of port0 to port7 on the side.
  • the registers configured for each port port include protocol parameters, the role of the port port, serial port parameters, and edge computing parameters.
  • the 7Z045FPGA inside the gateway device is used as the MASTER of the IIC, and the 7PFPGA is used as the SLAVE of the IIC, that is, the main control bus IIC MASTER module uses the 7Z045FPGA to convert the user's data into the format of the IIC message, and then transmits it through the internal channel between the 7P FPGA and the 7Z045.
  • the 7P FPGA is responsible for receiving the data in the IIC message format and converting it into register interface data, passing it to the user-side logic module, and then configuring the registers, distributed RAM and BLOCK RAM in the protocol conversion module, adding Registers in the decryption module and registers in the network module.
  • clock reset module control is connected from control bus IIC SLAVE module and user side logic module, the logic on 7P FPGA uses unified clock domain and the same reset control, clock reset module includes clock synchronization module and reset module.
  • the clock synchronization module uses the 50M clock of the backplane to generate a 125Mhz clock through PLL frequency multiplication, provides a clock source for the controller, makes the overall system in the 125M clock domain, provides a unified clock domain for the overall logic system, and is the IIC.
  • the efficient transmission of data provides a reference source.
  • the reset module makes the whole system reset at high level.
  • the clock synchronization module When the clock synchronization module generates a stable 125Mhz clock signal, the locked signal of the clock synchronization module will be pulled high, and the lock signal of the clock synchronization module is used for counting.
  • the count reaches 3F, the overall system is reset to high, which provides power for the normal operation of the controller and the normal operation of the FPGA chip to provide millisecond-level power-on and power-off sequence requirements.
  • the present invention can perform hierarchical transmission according to the importance of the data, so as to ensure the real-time, reliability and accuracy of the high-priority data.

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Abstract

本发明涉及控制领域，具体涉及一种任意字节读写用户侧逻辑控制器，包括：主控制总线IIC MASTER模块、从控制总线IIC SLAVE模块、时钟复位模块和用户侧逻辑模块，其特征在于，所述的主控制总线IIC MASTER模块将用户的数据转化为IIC报文的格式下发给从控制总线IIC SLAVE模块，所述的从控制总线IIC SLAVE模块接收所述IIC报文格式的数据，所述用户侧逻辑模块与与从控制总线IIC SLAVE模块相连接，所述时钟复位模块控制连接从控制总线IIC SLAVE模块与用户侧逻辑模块。本发明的控制器采用传统的IIC接口，保证了数据传输的准确性、实时性和可靠性，实现对多个地址段的进行独立读写和任意字节的数据读写，支持确定性数据传输，降低数据传输的延时和抖动，实现多用户的数据上送和数据下发。

Description

一种任意字节读写用户侧逻辑控制器 技术领域
本发明涉及控制领域，具体涉及一种任意字节读写用户侧逻辑控制器。
背景技术
IIC协议(Inter-Integrated Circuit，全称为集成电路总线)主要是用来连接整体电路，IIC是一种多向控制总线，也就是说多个芯片可以连接到同一总线结构下，同时每个芯片都可以作为实时数据传输的控制源。
在传统的数据传输中，IIC协议作为常用的传输协议来完成数据过程中的复杂时序要求，对生产过程中的状态进行实时监控。随着工业互联网技术的发展，对IIC的要求也越来越高，功能也提出了新的需求。
目前的IIC控制器主要通过使用单字节的形式对用户侧逻辑进行读写，使用的场景存在局限性；随着数据传输的数据量越来越大，对传输字节数灵活性存在较大的要求。
发明内容
为了解决现有的IIC数据传输存在传输字节固定不灵活和兼容性差的问题，本发明提出一种任意字节读写用户侧逻辑控制器和方法，其具体技术方案如下。
一种任意字节读写用户侧逻辑控制器，包括：主控制总线IIC MASTER模块、从控制总线IIC SLAVE模块、时钟复位模块和用户侧逻辑模块，所述的主控制总线IIC MASTER模块将用户的数据转化为IIC报文的格式下发给从控制总线IIC SLAVE模块，所述的从控制总线IIC SLAVE模块接收所述IIC报文格式的数据，所述用户侧逻辑模块与与从控制总线IIC SLAVE模块相连接，所述时钟复位模块控制连接从控制总线IIC SLAVE模块与用户侧逻辑模块。
进一步的，所述IIC报文的格式，即是IIC配置的读写报文格式，IIC的写报文格式的域段有8个字节，前两个字节为地址域段，后6个字节为数据域段，即将DATA0～DATA5拼成的48bit数据，写入到由ADDR0、ADDR1拼成的16bit地址寄存器中；IIC读报文格式的域段有2个字节，都为地址域段，即读出由ADDR0和ADDR1拼成的地址所对应的BLOCK RAM。
进一步的，所述从控制总线IIC SLAVE模块的状态机跳转共有8个，包括： IDLE、START、ID_RECV、ACK_ID_RECV、DATA_SEND、ACK_DATA_SEND、DATA_RECV、ACK_DATA_RECV，所述IDLE状态为系统默认状态，当检测到SCL上升沿时系统跳转到START状态，系统进入ID_RECV状态，开始接收IIC报文的ID号，当接收到正确的IIC ID号时，则跳转到ACK_ID_RECV状态；所述DATA_SEND、ACK_DATA_SEND为：当开始发送数据时，前两个字节为地址域段，后6个字节为数据域段；所述DATA_RECV、ACK_DATA_RECV为：当开始接收数据时，读地址为两个字节。
进一步的，所述的用户侧逻辑模块，包括：与从控制总线IIC SLAVE模块相连接的寄存器模块单元、分布式RAM模块单元和BLOCK RAM模块单元。
进一步的，所述的分布式RAM模块单元，包括：逆映射RAM、写参数RAM、读参数RAM、命令RAM、PLC类型RAM、映射RAM，用于存储中央处理器CPU的启动运行程序和用户侧逻辑模块的配置参数。
进一步的，所述的BLOCK RAM模块单元对用户侧逻辑模块的port0～port7的8个port口数据进行配置，每个port口配置的BLOCK RAM为地址RAM。
进一步的，所述的寄存器模块单元的地址范围为：0X0～0X1000，读写的字节数为2个，对用户侧逻辑模块的port0～port7的8个port口数据进行配置，每个port口配置的寄存器包括协议参数、该port口所处角色、串口参数以及边缘计算参数。
进一步的，所述时钟复位模块，包括：时钟同步模块和复位模块，所述时钟同步模块使用底板的50M时钟通过PLL倍频产生125Mhz的时钟，为控制器提供时钟源，使系统处于125Mhz的统一时钟域下；所述的复位模块，使系统为高复位，当时钟同步模块产生一个稳定的125Mhz的时钟信号时，时钟同步模块的locked信号拉高，并利用时钟同步模块的lock信号进行计数，当计数到3F时，则系统高复位。
本发明的控制器采用传统的IIC接口能够实现对多个地址段的进行独立读写和任意字节的数据读写，支持确定性数据传输，降低数据传输的延时和抖动，实现多用户的数据上送和数据下发；其中，采用传统IIC接口，保证了传统控制器兼容性、统一性，保证数据传输的准确性、实时性和可靠性。
附图说明
图1为本发明的任意字节读写用户侧逻辑控制器模块结构示意图；
图2是IIC配置的读写报文格式示意图；
图3是IIC读写状态机流程图；
图4是分布式RAM模块单元对用户侧的port0～port7的分布式RAM表单示意图；
图5是寄存器模块单元对用户侧的port0～port7的寄存器表单示意图。
具体实施方式
为了使本发明的目的、技术方案和技术效果更加清楚明白，以下结合说明附图和优选实施例，对本发明作进一步详细说明，应当理解，此处所描述的具体实施方式仅用以解释本发明，并不用于限定本发明。
如图1所示，本发明的支持多用户和多字节传输的控制器，包括：主控制总线IIC MASTER模块、从控制总线IIC SLAVE模块、时钟复位模块和用户侧逻辑模块；
所述的主控制总线IIC MASTER模块将用户的数据转化为IIC报文的格式下发给从控制总线IIC SLAVE模块，实现通信、逻辑控制和数据处理。
所述的从控制总线IIC SLAVE模块接收所述IIC报文格式的数据，解析和封装时间敏感数据，提供统一的对外以太网接口，兼容传统的交换机和时间敏感网络交换机。
其中，IIC配置的读写报文格式如图2所示，IIC的SLAVE ID为0X54，IIC的写报文格式的域段有8个字节，前两个字节为地址域段，后6个字节为数据域段，即将DATA0～DATA5拼成的48bit数据，写入到由ADDR0、ADDR1拼成的16bit地址寄存器中。
IIC读报文格式的域段有2个字节，都为地址域段，即读出由ADDR0和ADDR1拼成的地址所对应的BLOCK RAM。
如图3所示，从控制总线IIC SLAVE模块的状态机跳转共有8个，分别是：IDLE、START、ID_RECV、ACK_ID_RECV、DATA_SEND、ACK_DATA_SEND、DATA_RECV、ACK_DATA_RECV。系统默认状态为IDLE状态，当检测到SC上升沿时系统跳转到START状态，系统开始接收IIC报文的ID号；
ID_RECV、ACK_ID_RECV：本设备的IIC ID号为0X54，当接收到正确的IIC ID 号时，则跳转到ACK_ID_RECV状态；
DATA_SEND、ACK_DATA_SEND：当开始发送数据时，前两个字节为地址域段，后6个字节为数据域段。
DATA_RECV、ACK_DATA_RECV：当开始接收数据时，读地址为两个字节。
所述的用户侧逻辑模块，包括：与从控制总线IIC SLAVE模块相连接的寄存器模块单元、分布式RAM模块单元和BLOCK RAM模块单元。
如图4所示，所述的分布式RAM模块单元，包括：逆映射RAM、写参数RAM、读参数RAM、命令RAM、PLC类型RAM、映射RAM，用于存储中央处理器CPU的启动运行程序和用户侧逻辑模块的配置参数，具体的：
分布式RAM模块单元的IIC地址：0X1000～0X2000，读写的字节数为3个。
分布式RAM模块单元对用户侧的port0～port7的8个port口中的分布式RAM进行配置，每个port口配置的分布式RAM，逆映射分布式RAM、写参数分布式RAM、读参数分布式RAM、命令分布式RAM、plc类型分布式RAM、映射分布式RAM；
portn_ivsmapform：对应port口的逆映射分布式RAM；
portn_ivsmap2paraform_w：对应port口的写参数分布式RAM；
portn_ivsmap2paraform_r：对应port口所处的读参数分布式RAM；
portn_cmdform：对应port口的命令分布式RAM；
portn_plctypeform：对应port口的plc类型分布式RAM；
portn_mapform：对应port口的映射分布式RAM；
所述的BLOCK RAM模块单元，包括：地址RAM，用于存储中央处理器CPU的启动运行程序和用户侧逻辑模块的的配置参数，具体的：
BLOCK RAM的读写地址为：0X2000～0X3000，读写的字节数为4个；
BLOCK RAM模块的主要功能是对用户侧的port0～port7的8个port口数据进行配置，每个port口配置的BLOCK RAM为地址RAM；
port0_addrform：对应port口的将源协议的地址转化为目标协议的地址BLOCK RAM。
如图5所示，所述的寄存器模块单元，用于配置用户侧逻辑模块所用的寄存器，寄存器模块的地址范围：0X0～0X1000，读写的字节数为2个，更具体的：对用户侧的port0～port7的8个port口数据进行配置，每个port口配置的寄存器 包括协议参数、该port口所处角色、串口参数以及边缘计算参数。
在网关设备内部的7Z045FPGA作为IIC的MASTER，7PFPGA作为IIC的SLAVE，即主控制总线IIC MASTER模块采用7Z045FPGA将用户的数据转化为IIC报文的格式，再通过7P FPGA和7Z045之间的内部通路传递给7P FPGA，7P FPGA负责接收所述IIC报文格式的数据并转化为寄存器接口数据，传递给用户侧逻辑模块，然后进行配置，配置协议转换模块中的寄存器、分布式RAM和BLOCK RAM，加解密模块中的寄存器和网络模块中的寄存器。
所述时钟复位模块，控制连接从控制总线IIC SLAVE模块与用户侧逻辑模块，在7P FPGA上的逻辑使用统一的时钟域和同一个复位所控制，时钟复位模块包括时钟同步模块和复位模块。
所述的时钟同步模块使用底板的50M时钟通过PLL倍频去产生一个125Mhz的时钟，为控制器提供时钟源，使得整体系统处于125M时钟域下，为整体逻辑系统提供统一的时钟域，为IIC的数据有效传输提供基准源。
所述的复位模块，使得整个系统为高复位，当时钟同步模块产生一个稳定的125Mhz的时钟信号时，时钟同步模块的locked信号便会拉高，并利用时钟同步模块的lock信号进行计数，当计数到3F时，则整体系统高复位，为控制器的正常运行提供电源及FPGA芯片的正常运行提供毫秒级的上下电时序要求。
本发明在数据通信的过程中能够根据数据的重要性进行分级传输，保证高优先级的数据的实时性、可靠性和准确性。
本领域普通技术人员可以理解，以上所述仅为发明的优选实例而已，并不用于限制发明，尽管参照前述实例对发明进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述各实例记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。凡在发明的精神和原则之内，所做的修改、等同替换等均应包含在发明的保护范围之内。

Claims (7)

  1. 一种任意字节读写用户侧逻辑控制器，包括：主控制总线IIC MASTER模块、从控制总线IIC SLAVE模块、时钟复位模块和用户侧逻辑模块，所述的主控制总线IIC MASTER模块将用户的数据转化为IIC报文的格式下发给从控制总线IIC SLAVE模块，所述的从控制总线IIC SLAVE模块接收所述IIC报文格式的数据，所述用户侧逻辑模块与与从控制总线IIC SLAVE模块相连接，所述时钟复位模块控制连接从控制总线IIC SLAVE模块与用户侧逻辑模块；
    其特征在于，所述从控制总线IIC SLAVE模块的状态机跳转共有8个，包括：IDLE、START、ID_RECV、ACK_ID_RECV、DATA_SEND、ACK_DATA_SEND、DATA_RECV、ACK_DATA_RECV，所述IDLE状态为系统默认状态，当检测到SCL上升沿时系统跳转到START状态，系统进入ID_RECV状态，开始接收IIC报文的ID号，当接收到正确的IIC ID号时，则跳转到ACK_ID_RECV状态；所述DATA_SEND、ACK_DATA_SEND为：当开始发送数据时，前两个字节为地址域段，后6个字节为数据域段；所述DATA_RECV、ACK_DATA_RECV为：当开始接收数据时，读地址为两个字节。
  2. 如权利要求1所述的一种任意字节读写用户侧逻辑控制器，其特征在于，所述IIC报文的格式，即是IIC配置的读写报文格式，IIC的写报文格式的域段有8个字节，前两个字节为地址域段，后6个字节为数据域段，即将DATA0～DATA5拼成的48bit数据，写入到由ADDR0、ADDR1拼成的16bit地址寄存器中；IIC读报文格式的域段有2个字节，都为地址域段，即读出由ADDR0和ADDR1拼成的地址所对应的BLOCK RAM。
  3. 如权利要求1所述的一种任意字节读写用户侧逻辑控制器，其特征在于，所述的用户侧逻辑模块，包括：与从控制总线IIC SLAVE模块相连接的寄存器模块单元、分布式RAM模块单元和BLOCK RAM模块单元。
  4. 如权利要求3所述的一种任意字节读写用户侧逻辑控制器，其特征在于，所述的分布式RAM模块单元，包括：逆映射RAM、写参数RAM、读参数RAM、命令RAM、PLC类型RAM、映射RAM，用于存储中央处理器CPU的启动运行程序和用户侧逻辑模块的配置参数。
  5. 如权利要求3所述的一种任意字节读写用户侧逻辑控制器，其特征在于，所述的BLOCK RAM模块单元对用户侧逻辑模块的port0～port7的8个port口数据进行配置，每个port口配置的BLOCK RAM为地址RAM。
  6. 如权利要求3所述的一种任意字节读写用户侧逻辑控制器，其特征在于，所述的寄存器模块单元的地址范围为：0X0～0X1000，读写的字节数为2个，对用户侧逻辑模块的port0～port7的8个port口数据进行配置，每个port口配置的寄存器包括协议参数、该port口所处角色、串口参数以及边缘计算参数。
  7. 如权利要求1所述的一种任意字节读写用户侧逻辑控制器，其特征在于，所述时钟复位模块，包括：时钟同步模块和复位模块，所述时钟同步模块使用底板的50M时钟通过PLL倍频产生125Mhz的时钟，为控制器提供时钟源，使系统处于125Mhz的统一时钟域下；所述的复位模块，使系统为高复位，当时钟同步模块产生一个稳定的125Mhz的时钟信号时，时钟同步模块的locked信号拉高，并利用时钟同步模块的lock信号进行计数，当计数到3F时，则系统高复位。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070112990A1 (en) * 2005-11-15 2007-05-17 Matsushita Electric Industrial Co., Ltd. Iic bus communication system, slave device, and method for controlling iic bus communication
CN106168934A (zh) * 2016-06-29 2016-11-30 锐捷网络股份有限公司 一种数据传输方法及装置
CN108292286A (zh) * 2015-11-24 2018-07-17 高通股份有限公司 用于等待时间敏感的掩蔽写入的全掩码部分比特字段（fm-pbf）技术
CN112269749A (zh) * 2020-10-30 2021-01-26 厦门紫光展锐科技有限公司 I2c通信系统
CN112698614A (zh) * 2021-03-25 2021-04-23 之江实验室 一种任意字节读写用户侧逻辑控制器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4879765B2 (ja) * 2007-01-29 2012-02-22 パナソニック株式会社 Ｉ２ｃバス制御回路
CN102193889B (zh) * 2011-06-08 2014-01-22 杭州国芯科技股份有限公司 一种i2c总线转发器及其读写方法
CN110597745A (zh) * 2019-09-20 2019-12-20 苏州浪潮智能科技有限公司 一种交换机系统多主多从i2c通信实现方法和装置
CN111078606B (zh) * 2019-11-18 2021-05-11 上海灵动微电子股份有限公司 一种模拟i2c从机及其实现方法、终端设备和存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070112990A1 (en) * 2005-11-15 2007-05-17 Matsushita Electric Industrial Co., Ltd. Iic bus communication system, slave device, and method for controlling iic bus communication
CN108292286A (zh) * 2015-11-24 2018-07-17 高通股份有限公司 用于等待时间敏感的掩蔽写入的全掩码部分比特字段（fm-pbf）技术
CN106168934A (zh) * 2016-06-29 2016-11-30 锐捷网络股份有限公司 一种数据传输方法及装置
CN112269749A (zh) * 2020-10-30 2021-01-26 厦门紫光展锐科技有限公司 I2c通信系统
CN112698614A (zh) * 2021-03-25 2021-04-23 之江实验室 一种任意字节读写用户侧逻辑控制器

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