WO2022193471A1 - 存储器件修复方法及系统 - Google Patents

存储器件修复方法及系统 Download PDF

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Publication number
WO2022193471A1
WO2022193471A1 PCT/CN2021/103481 CN2021103481W WO2022193471A1 WO 2022193471 A1 WO2022193471 A1 WO 2022193471A1 CN 2021103481 W CN2021103481 W CN 2021103481W WO 2022193471 A1 WO2022193471 A1 WO 2022193471A1
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WIPO (PCT)
Prior art keywords
repair
unit
row address
row
module
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PCT/CN2021/103481
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English (en)
French (fr)
Inventor
张良
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21772941.7A priority Critical patent/EP4084005B1/en
Priority to US17/404,119 priority patent/US20220300388A1/en
Publication of WO2022193471A1 publication Critical patent/WO2022193471A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/835—Masking faults in memories by using spares or by reconfiguring using programmable devices with roll call arrangements for redundant substitutions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/804—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout to prevent clustered faults
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/81—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a hierarchical redundancy scheme

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a method and system for repairing a memory device.
  • the stored several error units are repaired uniformly. In this way, when repairing, several faulty units can be repaired at one time, thereby improving the repair efficiency.
  • a first aspect of the present application provides a method for repairing a memory device, comprising:
  • the unit address includes a row address
  • a second aspect of the present application provides a storage device repair system, which includes:
  • a detection module configured to perform error detection on a storage unit of the storage device, and output a unit address of the error unit, where the error unit is a damaged storage unit;
  • a register module electrically connected to the detection module, includes a number of registers not less than a first preset number, each of the registers is used to receive the unit address of the error unit, and output the row address of the error unit, one of the registers The error unit occupies one of the registers, and the unit address includes a row address;
  • control module electrically connected to each of the registers, for selecting a target register in sequence in each of the registers when the number of error units detected by the detection module reaches a first preset number
  • a first judging module electrically connected to the reference storage module and the register module, for receiving the row address output by the target register and the row address output by the reference storage module, and judging the row address in the target register Whether it exists in the reference storage module, and outputs the judgment result;
  • the repairing module is electrically connected to the first judging module, and is used for repairing the erroneous unit that has not undergone row address repairing according to the judging result.
  • the unit addresses of multiple error units are repaired uniformly, the unit addresses of each error unit are first stored in different registers, and then it is judged whether the addresses in each register are stored in the reference storage module, Further, it can be judged whether the error unit corresponding to each register has been repaired by the row address, so that only the error unit that has not been repaired by the row address can be repaired.
  • FIG. 1 is a flowchart of a method for repairing a memory device provided in an embodiment
  • FIG. 2 is a flowchart of a method for repairing a memory device provided in another embodiment
  • FIG. 3 is a flowchart of a method for repairing a memory device provided in yet another embodiment
  • FIG. 4 is a schematic structural diagram of a module of a memory device repair system provided in an embodiment.
  • the first judging module becomes the second judging module, and similarly, the second judging module can be called the first judging module; the first judging module and the second judging module are different judging modules.
  • connection in the following embodiments should be understood as “electrical connection”, “communication connection” and the like if there is transmission of electrical signals or data between the objects to be connected.
  • the inventor's research found that one of the reasons for the failure of repair is that when different faulty cells appear on the same word line in the same memory area (bank) at the same time, this word line will be damaged. Repeat the repair several times, causing the entire repair to fail. For example, if it is detected that two faulty cells appear on the same word line, if we do not identify it, the row address A of the word line will be stored in the two row repair fuses, corresponding to two redundant words. Wire. Then when we read and write, if the read and write address is A, two redundant word lines will be turned on at the same time, so the read and write will go wrong.
  • the present application provides a method and system for repairing a storage device.
  • the storage device repairing method and storage device repairing system provided by the present application can be applied to repairing a storage device in which at least two faulty cells appear on the same word line.
  • a method for repairing a memory device including the following steps:
  • Step S100 performing error detection on the storage unit of the storage device
  • Step S200 temporarily store the unit address of the detected error unit in the register, until the number of the detected error unit reaches the first preset number, the error unit is a damaged storage unit, one error unit occupies one register, and the unit address including the row address;
  • Step S300 selecting a target register in turn in each register
  • Step S400 judging whether the row address in the target register exists in the reference storage module, and the reference storage module stores the row address that has been repaired or the row address that has not been repaired;
  • Step S500 according to the judgment result, repair the error cell that has not been repaired by the row address.
  • the memory device includes a plurality of memory cells arranged in rows and columns. Meanwhile, the memory device includes a plurality of word lines. Each word line provides a gate voltage for a plurality of memory cells in the same row to control the reading and writing of data to the memory cells.
  • Each memory cell can store data 0 or 1. When the storage unit is damaged, it cannot perform normal reading and writing.
  • Error detection is performed on the memory cells of the memory device, that is, to detect whether each memory cell of the memory device is damaged.
  • step S200 each time an error unit is detected, the unit address of the error unit is temporarily stored in a register.
  • the unit address of an error unit occupies one register, and the unit addresses of different error units are temporarily stored in different registers.
  • the detection is suspended.
  • the first preset number can be set according to actual requirements, and can be set to be the same as the number of registers in the repair system used for repair.
  • step S300 in each register, a target register is selected.
  • the target register is a register that stores the unit address of the memory unit to be repaired currently.
  • the row address in the destination register is the current row address to be repaired.
  • step S400 the reference storage module stores the row address that has been repaired, or the reference storage module stores the row address that has not been repaired.
  • the row address that has been repaired is the row address of the memory cell that has been repaired for the row address.
  • the row address that has not been repaired is the row address of the memory cell that has not been repaired.
  • step S500 if the reference storage module stores the row address that has been repaired, then when the judgment result is that the row address in the target register exists in the reference storage module, the error unit corresponding to the target register is not repaired; When the row address in the target register does not exist in the reference storage module, the error unit corresponding to the target register is repaired.
  • the reference storage module stores an unrepaired row address
  • the error unit corresponding to the target register is repaired;
  • the error unit corresponding to the target register is not repaired.
  • the unit addresses of each error unit are first stored in different registers, and then it is judged whether the addresses in each register are stored in the reference storage module, and then it can be It is judged whether the error unit corresponding to each register has been repaired by the row address, so that only the error unit that has not been repaired by the row address can be repaired.
  • the row address of the reference memory module is gradually changed during the repair process. If the repaired row address is stored in the reference storage module, after the row address of an erroneous unit is repaired, its row address is stored in the reference storage module. If an unrepaired row address is stored in the reference memory module, after the row address of an erroneous unit is repaired, its row address is removed from the reference memory module.
  • the reference memory module stores row addresses that have been repaired. At this time, before repairing, the reference storage module may not be stored. During the repairing process, the row addresses stored in the reference storage module gradually increase, thereby effectively reducing the system memory and improving the repairing efficiency.
  • step S500 includes:
  • Step S510 if the row address in the target register exists in the reference storage module, skip repairing the error unit corresponding to the target register.
  • the repair of the error unit corresponding to the target register is skipped, that is, the current target register is skipped, and the selection and judgment of the next target register are automatically performed.
  • step S500 also includes:
  • Step S520 if the row address in the target register does not exist in the reference storage module, repair the error unit corresponding to the target register.
  • the memory device includes a row repair unit.
  • the row repair unit that is, a circuit unit for performing row address repair on an erroneous unit, includes a second preset number of row repair fuses.
  • the second preset number can be set according to actual needs.
  • the row repair fuse is used to receive and store the row address of the erroneous cell.
  • One row repair fuse corresponds to one redundant row address.
  • One redundant row address corresponds to one redundant word line.
  • the redundant word line WF1 is turned on, and the word line W1 is turned off.
  • step S520 includes: step S522, storing the row address in the target register to a blank row repair fuse of the row repair unit.
  • the row address in the target register is the row address of the error unit corresponding to the register, and is stored in a blank row repair fuse of the row repair unit, that is, the row address repair of the error unit corresponding to the register can be completed.
  • blade row repair fuses are row repair fuses that do not store row addresses of memory cells.
  • the reference storage module includes a row repair unit.
  • the row repair unit is used to perform row address repair on the erroneous unit on the one hand, and on the other hand, it is also used to determine whether the row address repair has been performed on the erroneous unit to be repaired, so that the row address can be effectively used. line repair unit, while saving system storage space.
  • step S522 before step S522, it further includes:
  • Step S521 it is judged whether there is a blank row repair fuse in the row repair unit.
  • step S522 is performed to store the row address in the target register to a blank row repair fuse of the row repair unit.
  • the cell addresses stored in the registers may also include column addresses.
  • step S523 may be performed to perform column address repair on the error unit corresponding to the target register.
  • Column address repair can be implemented through column repair fuses, similar to the foregoing (step S522 ), row address repair can be implemented through row repair fuses.
  • step S500 it further includes:
  • Step S600 clearing the target register.
  • the target register is cleared. After all registers are selected as target registers in turn and processed accordingly, all registers are cleared. So when a repair is done, all registers are cleared so that they can be used again for the next repair.
  • the present embodiment can effectively improve the utilization rate of the register.
  • the register is cleared.
  • the present application is not limited by this.
  • step S500 it further includes:
  • step S700 after the row addresses in all the registers are repaired, all the registers are cleared.
  • the row address in a register has not been repaired by the row address, the row address is repaired, thereby completing the repair of the row address in the register.
  • each register in a repair process, after all registers are applied, all registers are cleared uniformly. At this time, each register can also be used for the next repair again, so that the utilization of the register can be effectively improved.
  • steps in the flowchart of FIG. 1 are shown in sequence according to the arrows, these steps are not necessarily executed in the sequence shown by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 1 may include multiple steps or multiple stages, these steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution sequence of these steps or stages is also It does not have to be performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages within the other steps.
  • a storage device repair system including a detection module 100 , a register module 200 , a control module 300 , a reference storage module 400 , a first judgment module 500 and a repair module 600 .
  • the detection module 100 is configured to perform error detection on the memory cells of the storage device, and output the cell address of the error cell.
  • the wrong cell is a damaged memory cell.
  • the register module 200 is electrically connected to the detection module 100, and includes a number of registers 210 not less than the first preset number. Specifically, the number of registers 210 may be the same as the first preset number, thereby improving register utilization.
  • Each register 210 is used to receive and temporarily store the unit address of the erroneous unit, and output the row address in the unit address of the erroneous unit.
  • An error cell occupies one register, and the cell address includes the row address.
  • the control module 300 is electrically connected to each of the registers 210, and is configured to select a target register in sequence from each of the registers when the number of error units detected by the detection module 100 reaches a first preset number.
  • the storage module 400 it is used for storing and outputting the row address that has been repaired or the row address that has not been repaired.
  • the first judgment module 500 is electrically connected to the reference storage module 400 and the register module 200, and is used for receiving the row address output by the target register 210 and the row address output by the reference storage module 400, and judging whether the row address in the target register exists in the reference storage. module, and output the judgment result.
  • control module 300 may include the same number of switch units 310 as the registers 210 in the register module 200 .
  • the first judging module 500 may be electrically connected to each register 210 correspondingly through each switch unit 310 of the control module 300 . When the corresponding switch unit in the control module 300 is turned on, the first judgment module 500 is connected to the target register.
  • the control module 300 may include a first control unit 320 and n switch units 310 , each switch unit 310 corresponds to a register 210 , and n is a positive integer greater than 1.
  • the first control unit 320 inputs control signals S1 to Sn to the n switch units 310 , respectively.
  • the control signal input by the first control unit 320 to the k-th switch unit 310 is Sk, 1 ⁇ k ⁇ n.
  • the remaining control signals are low-level signals.
  • the first control unit 320 controls S1 to Sn to become high-level signals in sequence, and then turns on the first to nth switch units in sequence. , and then make the registers corresponding to the first switch unit to the nth switch unit become target registers in sequence, and are connected to the first judgment module 500 .
  • the switching unit 310 may include a transmission gate 311 and an inverter 312 .
  • the transmission gate 311 may be composed of a PMOS transistor and an NMOS transistor in parallel.
  • the gate terminal of the NMOS transistor and the input terminal of the inverter 312 can be connected to the control signal of the first control unit 320, and at the same time, the output terminal of the inverter 312 can be connected to the gate terminal of the PMOS transistor.
  • the manner in which the first control unit 320 controls the kth switch unit 310 to be turned on may be:
  • the control signal Sk input by the first control unit 320 to the k-th switch unit 310 is a high-level signal, and the NMOS transistor receives the high-level signal.
  • the inverter 312 receives the high-level signal, converts the high-level signal into a low-level signal, and outputs it to the PMOS transistor. Therefore, at this time, at least one of the NMOS transistor or the PMOS transistor is turned on, so that the switch unit 310 is turned on.
  • the NMOS transistor When the control signal Sk input by the first control unit 320 to the k-th switch unit 310 is a low-level signal, the NMOS transistor receives the low-level signal. At the same time, the inverter 312 receives the low-level signal, converts the low-level signal into a high-level signal, and outputs it to the PMOS transistor. Therefore, at this time, both the NMOS transistor and the PMOS transistor are disconnected, so that the switch unit 310 is disconnected.
  • the repairing module 600 is electrically connected to the first judging module 500, and is configured to repair the erroneous cells that have not undergone row address repairing according to the judging result.
  • the first judgment module 500 sequentially judges whether the row addresses of the error cells to be repaired stored in each register 210 are stored in the reference memory module 400, and then can judge whether each register corresponds to Whether the erroneous unit has been repaired by row address, so that only the erroneous unit that has not been repaired by row address can be repaired.
  • the reference storage module 400 is used to store row addresses that have been repaired.
  • the repair module 600 is further configured to skip repairing the error unit corresponding to the target register when the row address in the target register exists in the reference storage module 400 .
  • the first judgment module 500 includes a comparator 510, and the comparator 510 is configured to receive the row address output by the target register 210 and the row address output by the reference storage module 400, and for the target The row address output by the register 210 is compared with the row address output by the reference storage module 400, and when the row address output by the target register is inconsistent with the row address output by the reference storage module, a preset level signal is output to the repair module 600 to turn on Repair module 600.
  • the preset level signal may be a high level signal.
  • the comparator 510 outputs a high-level signal, and the repair module 600 is turned on, so that the error unit corresponding to the target register can be repaired.
  • the comparator 510 can output a low-level signal, so that the repair module 600 is not turned on.
  • the comparator 510 sequentially compares whether the row addresses output by the target register 210 are consistent with the row addresses stored in the reference storage module 400 .
  • the repair module 600 includes a row repair unit 610 and a second control unit 620 .
  • the row repair unit 610 is electrically connected to each register 210, and is used for performing row address repair on the error unit corresponding to the target register.
  • the second control unit 620 is electrically connected to the comparator 510 and the row repair unit 610, and is used for switching the row repair unit according to the high-level signal or the low-level signal output by the comparator 510.
  • the second control unit 620 may include switching devices such as switching transistors.
  • a switching device such as a switching transistor is turned on to turn on the row repair unit 610, so as to perform row address repair on the erroneous unit corresponding to the target register.
  • the switching device such as the switch transistor is turned off to turn off the row repair unit, skip the repair of the error unit corresponding to the target register, or terminate the current repair.
  • the repairing module 600 may, together with the first judging module 500 , electrically connect each register 210 correspondingly through each switch unit 310 of the control module 300 .
  • control module 300 may include a first control unit 320 and n switch units 310 , each switch unit 310 corresponds to a register 210 , and n is a positive integer greater than 1.
  • the first control unit 320 inputs control signals S1 to Sn to the n switch units 310 , respectively.
  • the control signal input by the first control unit 320 to the k-th switch unit 310 is Sk, 1 ⁇ k ⁇ n.
  • the remaining control signals are low-level signals.
  • the first control unit 320 controls S1 to Sn to become high-level signals in sequence, and then turns on the first to nth switch units in sequence. , and then make the registers corresponding to the first switch unit to the nth switch unit become target registers in sequence.
  • the corresponding switch unit 310 is turned on. Therefore, the row address in the target register can be transmitted to the first judgment module 500 and the repair module 600 .
  • the comparator 510 of the first judgment module 500 can directly obtain the row address in the target register, compare it with the row address output by the reference storage module 400, and output a level signal according to the comparison result.
  • the row repair unit 610 receives and stores the row address in the target register, so that the row address in the target register can be stored to Repair is performed in the row repair unit 610 .
  • the row repair unit 610 includes a second preset number of row repair fuses, and one row repair fuse corresponds to one redundant row address.
  • the row repair unit 610 is used for storing the row address in the target register to a blank row repair fuse of the row repair unit.
  • the reference storage module 400 includes a row repair unit 610 .
  • the memory device repairing system may further include a second judging module (not shown), and the second judging module is used for judging whether the row repairing unit 610 has a blank row repairing fuse.
  • the second control unit 620 may turn on the row repair unit when the row address in the target register does not exist in the reference memory module 400 and the row repair unit 610 has a blank row repair fuse.
  • the cell address may also include a column address.
  • the repair module 600 further includes a column repair unit (not shown), and the column repair unit is configured to perform column address repair on the error unit corresponding to the target register.
  • the second control unit may turn on the column repair unit when the row address in the target register does not exist in the reference memory module, but the row repair unit does not have a blank row repair fuse.
  • Each module in the above-mentioned storage device repairing system may be implemented in whole or in part by software, hardware and combinations thereof.
  • the above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.
  • the division of modules in the embodiments of the present application is schematic, and is only a logical function division, and there may be other division manners in actual implementation.

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Abstract

本申请涉及一种存储器件修复方法及系统。其中，存储器件修复方法，包括：对存储器件的存储单元进行错误检测；将检测到的错误单元的单元地址暂存至寄存器，直至检测到的错误单元的数量达到第一预设数量，错误单元为已损坏的存储单元，一个错误单元占用一个寄存器，单元地址包括行地址；在各个寄存器中依次选择目标寄存器；判断目标寄存器中的行地址是否存在于参考存储模块中，参考存储模块中存储有已经修复过的行地址或者未被修复过的行地址；根据判断结果，对未经过行地址修复的错误单元进行修复。本申请可以有效防止不同的错误单元同时出现在同一个存储区域的同一根字线上而导致的修复失败。

Description

存储器件修复方法及系统
本申请要求于2021年3月19日提交中国专利局，申请号为2021102954052，申请名称为“存储器件修复方法及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，特别是涉及一种存储器件修复方法及系统。
背景技术
在存储器件的修复中，为了提高检测效率，往往会在存储几个错误单元的单元地址之后，对存储的几个错误单元统一进行修复。这样，在进行修复的时候，可以一次性修复几个错误单元，进而提高了维修效率。
但是，在实际修复过程中，运用该种修复方式会存在修复失败现象。
发明内容
本申请的第一方面提供一种存储器件修复方法，其包括：
对所述存储器件的存储单元进行错误检测；
将检测到的错误单元的单元地址暂存至寄存器，直至检测到的错误单元的数量达到第一预设数量，所述错误单元为已损坏的存储单元，一个所述错误单元占用一个所述寄存器，所述单元地址包括行地址；
在各个所述寄存器中依次选择目标寄存器；
判断所述目标寄存器中的行地址是否存在于参考存储模块中，所述参考存储模块中存储有已经修复过的行地址或者未被修复过的行地址；
根据所述判断结果，对未经过行地址修复的所述错误单元进行修复。
本申请的第二方面提供一种存储器件修复系统，其包括：
检测模块，用于对所述存储器件的存储单元进行错误检测，且输出所述错误单元的单元地址，所述错误单元为已损坏的存储单元；
寄存模块，电连接所述检测模块，包括数量不少于第一预设数量的寄存器，各所述寄存器用于接收所述错误单元的单元地址，且输出所述错误单元的行地址，一个所述错误单 元占用一个所述寄存器，所述单元地址包括行地址；
控制模块，电连接各个所述寄存器，用于当所述检测模块检测到的错误单元的数量达到第一预设数量时，在各个所述寄存器中依次选择目标寄存器；
参考存储模块，用于存储以及输出已经修复过的行地址或者未被修复过的行地址；
第一判断模块，电连接所述参考存储模块与所述寄存模块，用于接收所述目标寄存器输出的行地址以及所述参考存储模块输出的行地址，且判断所述目标寄存器中的行地址是否存在于所述参考存储模块中，并输出判断结果；
修复模块，电连接所述第一判断模块，用于根据所述判断结果，对未经过行地址修复的所述错误单元进行修复。
上述存储器件修复方法及系统，在多个错误单元的单元地址统一进行修复时，首先将各个错误单元的单元地址存储至不同的寄存器，然后判断各个寄存器中的地址是否存储在于参考存储模块中，进而可以判断各个寄存器对应的错误单元是否进行过行地址修复，从而可以只对未经过行地址修复的错误单元进行修复。
因此，即便同一次修复过程中的各个错误单元中，有不同的错误单元同时出现在同一个存储区域(bank)的同一根字线上，该字线也不会被重复修复，从而可以有效防止修复失败。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的存储器件修复方法的流程图；
图2为另一实施例中提供的存储器件修复方法的流程图；
图3为又一实施例中提供的存储器件修复方法的流程图；
图4为一实施例中提供的存储器件修复系统的模块结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描 述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一判断模块成为第二判断模块，且类似地，可以将第二判断模块成为第一判断模块；第一判断模块与第二判断模块为不同的判断模块。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
需要说明的是，当一个元件被认为是“连接”另一个元件时，它可以是直接连接到另一个元件，或者通过居中元件连接另一个元件。此外，以下实施例中的“连接”，如果被连接的对象之间具有电信号或数据的传递，则应理解为“电连接”、“通信连接”等。
正如背景技术所述，在存储器件的修复中，为了提高检测效率，往往会在存储几个错误单元的单元地址之后，对存储的几个错误单元统一进行修复。这样，在进行修复的时候，可以一次性修复几个错误单元，进而提高了维修效率。但是，在实际修复过程中，运用该种修复方式会存在修复失败现象。
经发明人研究发现，导致修复失败现象的其中一种原因为：当有不同的错误单元同时出现在同一个存储区域(bank)的同一根字线上时，这样这一根字线就会被重复修几次，导致整个修复失败。例如，检测到两个错误单元都出现在同一个字线上面，如果我们不加 以识别，就会把该字线的行地址A存入两个行修复熔丝中，对应两根冗余的字线。那么我们在读写的时候，如果读写地址是A，就会同时开启两根冗余的字线，那么读写就会出错。
基于以上原因，本申请提供了一种存储器件修复方法及系统。本申请提供的存储器件修复方法以及存储器件修复系统可以应用于对至少两个错误单元出现在同一个字线上的存储器件进行修复。
在一个实施中，请参阅图1，提供一种存储器件修复方法，包括如下步骤：
步骤S100，对存储器件的存储单元进行错误检测；
步骤S200，将检测到的错误单元的单元地址暂存至寄存器，直至检测到的错误单元的数量达到第一预设数量，错误单元为已损坏的存储单元，一个错误单元占用一个寄存器，单元地址包括行地址；
步骤S300，在各个寄存器中依次选择目标寄存器；
步骤S400，判断目标寄存器中的行地址是否存在于参考存储模块中，参考存储模块中存储有已经修复过的行地址或者未被修复过的行地址；
步骤S500，根据判断结果，对未经过行地址修复的错误单元进行修复。
在步骤S100中，存储器件包括多个呈多行多列排布的存储单元。同时，存储器件包括多条字线。每条字线为位于同一行的多个存储单元提供栅极电压，以控制对存储单元进行数据的读写。
每个存储单元可以存储数据0或1。当存储单元损坏时，其不能进行正常读写。
对存储器件的存储单元进行错误检测，即检测存储器件的各个存储单元是否损坏。
在步骤S200中，每检测到一个错误单元，即将该错误单元的单元地址暂存至一个寄存器。一个错误单元的单元地址占用一个寄存器，不同的错误单元的单元地址暂存至不同的寄存器。当检测到的错误单元的数量达到第一预设数量时，暂停检测。
第一预设数量可以根据实际需求进行设定，其可以设置成与修复所使用的修复系统中的寄存器的数量相同。
在步骤S300中，在各个寄存器中，进行目标寄存器的选取。目标寄存器即存储有当前即将要修复的存储单元的单元地址的寄存器。目标寄存器中的行地址为当前即将要修复的行地址。
在步骤S400中，参考存储模块存储有已经修复过的行地址，或者参考存储模块存储有未被修复过的行地址。
已经修复过的行地址即已经进行过行地址修复的存储单元的行地址。未被修复过的行 地址即未进行过行地址修复的存储单元的行地址。
判断目标寄存器中的行地址是否存在于参考存储模块中，即可获取目标寄存器对应的错误单元是否进行过行地址修复。
在步骤S500中，如果参考存储模块存储有已经修复过的行地址，则当判断结果为目标寄存器中的行地址存在于参考存储模块中时，不对目标寄存器对应的错误单元进行修复；当判断结果为目标寄存器中的行地址未存在于参考存储模块中时，则对目标寄存器对应的错误单元进行修复。
如果参考存储模块存储有未被修复过的行地址，则当判断结果为目标寄存器中的行地址存在于参考存储模块中时，对目标寄存器对应的错误单元进行修复；当判断结果为目标寄存器中的行地址未存在于参考存储模块中时，则不对目标寄存器对应的错误单元进行修复。
在本实施例中，在多个错误单元的单元地址统一进行修复时，首先将各个错误单元的单元地址存储至不同的寄存器，然后判断各个寄存器中的地址是否存储在于参考存储模块中，进而可以判断各个寄存器对应的错误单元是否进行过行地址修复，从而可以只对未经过行地址修复的错误单元进行修复。
因此，即便同一次修复过程中的各个错误单元中，有不同的错误单元同时出现在同一个存储区域(bank)的同一根字线上，该字线也不会被重复修复，从而可以有效防止修复失败。
可以理解的是，参考存储模块中的存储的行地址在修复过程中是逐渐变化的。若参考存储模块中存储有已经修复过的行地址，则当一个错误单元进行过行地址修复后，其行地址即被存储至参考存储模块中。若参考存储模块中存储有未修复过的行地址，则当一个错误单元进行过行地址修复后，其行地址即被从参考存储模块中去除。
在一个实施例中，参考存储模块中存储有已经修复过的行地址。此时，在修复前，参考存储模块中可以不进行存储。在修复过程中，参考存储模块中的存储的行地址逐渐增多，进而可以有效减少系统内存，提高修复效率。
此时，步骤S500包括：
步骤S510，如果目标寄存器中的行地址存在于参考存储模块中，则跳过对目标寄存器对应的错误单元的修复。
跳过对目标寄存器对应的错误单元的修复，即跳过当前目标寄存器，而自动进行下一个目标寄存器的选取以及判断等。
进一步地，步骤S500还包括：
步骤S520，如果目标寄存器中的行地址未存在于参考存储模块中，则对目标寄存器对应的错误单元进行修复。
在一个实施例中，存储器件包括行修复单元。行修复单元，即对错误单元进行行地址修复的电路单元，其包括第二预设数量的行修复熔丝。第二预设数量可以根据实际需求进行设置。
行修复熔丝用于接收并存储错误单元的行地址。一个行修复熔丝对应一个冗余行地址。一个冗余行地址对应一条冗余字线。
当一个错误单元C1的行地址A1被存储至一个行修复熔丝F1后，该错误单元C1所对应的字线W1将被该行修复熔丝F1对应的冗余字线WF1取代，从而完成对错误单元C1的行地址修复。
此后，在对存储器件进行读写的时候，如果读写的存储单元的行地址为A1，则开启冗余字线WF1，而字线W1关闭。
此时，步骤S520包括：步骤S522，将目标寄存器中的行地址存储至行修复单元的一个空白行修复熔丝。
目标寄存器中的行地址即该寄存器对应的错误单元的行地址，将其存储至行修复单元的一个空白行修复熔丝，即可以完成对该寄存器对应的错误单元的行地址修复。
可以理解的是，“空白行修复熔丝”为未存储有存储单元的行地址的行修复熔丝。
在一个实施例中，参考存储模块包括行修复单元。由于行修复单元进行修复的过程中，对错误单元的行地址进行存储。因此，参考存储模块包括行修复单元，使得行修复单元一方面用于对错误单元进行行地址修复，另一方面还用于判断待修复的错误单元是否已经进行过行地址修复，从而可以有效利用行修复单元，而节省系统存储空间。
并且，此时不需要对错误单元的行地址进行另行存储，从而可以有效提高修复效率。
此外，在一些实施例中，步骤S522之前还包括：
步骤S521，判断行修复单元中是否具有空白行修复熔丝。
如果行修复单元中具有空白行修复熔丝，则进行步骤S522，将目标寄存器中的行地址存储至行修复单元的一个空白行修复熔丝。
此外，寄存器中存储的单元地址还可以包括列地址。
此时，如果行修复单元中不具有空白行修复熔丝，则可以进行步骤S523，对目标寄存器对应的错误单元进行列地址修复。
列地址修复可以通过列修复熔丝实现，类似于前述(步骤S522)行地址修复可以通过行修复熔丝实现。
在一个实施例中，步骤S500之后，还包括：
步骤S600，清空目标寄存器。
即完成对一个目标寄存器的相关处理后，即清空该目标寄存器。当所有寄存器都依次被选作为目标寄存器并进行相关处理之后，所有寄存器均清空。所以当一次修复完成之后，所有寄存器均清空，从而使其可以再次被用作下一次修复。
因此，本实施例可以有效提高寄存器的利用率。
在本实施例中，应用完一个寄存器，即清空该寄存器。当然，本申请并不以此为限制。
在另一个实施例中，步骤S500之后，还包括：
步骤S700，当所有寄存器中的行地址均完成修复之后，清空所有寄存器。
具体地，当一个寄存器中的行地址未经过行地址修复时，则对该行地址进行修复，从而完成对该寄存器中的行地址的修复。
而当一个寄存器中的行地址已经经过行地址修复时，则已经完成了对该寄存器中的行地址的修复，而不再次对其进行修复。
本实施例在一个修复过程中，当所有寄存器都应用完之后，统一清空所有寄存器。此时，各个寄存器也可以再次被用作下一次修复，从而可以有效提高寄存器的利用率。
应该理解的是，虽然图1的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在一个实施例中，还提供一种存储器件修复系统，包括检测模块100、寄存模块200、控制模块300、参考存储模块400、第一判断模块500以及修复模块600。
检测模块100用于对存储器件的存储单元进行错误检测，且输出错误单元的单元地址。错误单元为已损坏的存储单元。
寄存模块200电连接检测模块100，包括数量不少于第一预设数量的寄存器210。具体地，寄存器210的数量可以与第一预设数量相同，进而提高寄存器利用率。
各寄存器210用于接收并暂存错误单元的单元地址，且输出错误单元的单元地址中的 行地址。一个错误单元占用一个寄存器，单元地址包括行地址。
控制模块300电连接各个寄存器210，用于当检测模块100检测到的错误单元的数量达到第一预设数量时，在各个寄存器中依次选择目标寄存器。
参考存储模块400，用于存储以及输出已经修复过的行地址或者未被修复过的行地址。
第一判断模块500，电连接参考存储模块400和寄存模块200，用于接收目标寄存器210输出的行地址以及参考存储模块400输出的行地址，且判断目标寄存器中的行地址是否存在于参考存储模块中，并输出判断结果。
作为示例，控制模块300中可以包括与寄存模块200中的寄存器210等数量的开关单元310。第一判断模块500可以通过控制模块300的各个开关单元310对应电连接各个寄存器210。控制模块300中的相应开关单元导通时，第一判断模块500与目标寄存器相连接。
具体地，请参阅图4，控制模块300中可以包括第一控制单元320以及n个开关单元310，每个开关单元310对应一个寄存器210，n为大于1的正整数。
第一控制单元320对n个开关单元310分别输入控制信号S1至Sn。其中，第一控制单元320对第k个开关单元310输入的控制信号为Sk，1≤k≤n。并且，S1至Sn中任意一个为高电平信号时，其余控制信号为低电平信号。
当检测模块100检测到的错误单元的数量达到第一预设数量时，第一控制单元320控制S1至Sn依次成为高电平信号，进而打开顺序打开第一个开关单元至第n个开关单元，进而使得第一个开关单元至第n个开关单元对应的寄存器顺序成为目标寄存器，而与第一判断模块500相连。
更具体地，作为示例，开关单元310可以包括传输门311以及反相器312。传输门311可以由一个PMOS管和一个NMOS管并联构成。NMOS管的栅极端以及反相器312的输入端可以接入第一控制单元320的控制信号，同时，反相器312的输出端可以与PMOS管的栅极端连接。
第一控制单元320控制第k个开关单元310打开的方式可以为：
第一控制单元320对第k个开关单元310输入的控制信号Sk为高电平信号，NMOS管接收该高电平信号。同时，反相器312接收高电平信号，并将高电平信号转化为低电平信号而输出至PMOS管。因此，此时NMOS管或者PMOS管中的至少一个会导通，从而使得该开关单元310打开。
而当第一控制单元320对第k个开关单元310输入的控制信号Sk为低电平信号时， NMOS管接收该低电平信号。同时，反相器312接收低电平信号，并将低电平信号转化为高电平信号而输出至PMOS管。因此，此时NMOS管与PMOS管均断开，从而使得该开关单元310断开。
修复模块600电连接第一判断模块500，用于根据判断结果，对未经过行地址修复的错误单元进行修复。
本实施例在控制模块300的控制下，通过第一判断模块500依次对各个寄存器210中存储的待修复的错误单元的行地址是否存储在于参考存储模块400中进行判断，进而可以判断各个寄存器对应的错误单元是否进行过行地址修复，从而可以只对未经过行地址修复的错误单元进行修复。
因此，即便同一次修复过程中的各个错误单元中，有不同的错误单元同时出现在同一个存储区域(bank)的同一根字线上，该字线也不会被重复修复，从而可以有效防止修复失败。
在一个实施例中，参考存储模块400用于存储已经修复过的行地址。修复模块600还用于当目标寄存器中的行地址存在于参考存储模块400中时，跳过对目标寄存器对应的错误单元的修复。
在一个实施例中，在上述实施例的基础上，第一判断模块500包括比较器510，比较器510用于接收目标寄存器210输出的行地址以及参考存储模块400输出的行地址，且对目标寄存器210输出的行地址和参考存储模块400输出的行地址进行比较，且当目标寄存器输出的行地址和参考存储模块输出的行地址不一致时，向修复模块600输出预设电平信号，以开启修复模块600。
作为示例，预设电平信号可以为高电平信号。
若目标寄存器输出的行地址和参考存储模块400输出的行地址不一致，说明目标寄存器210对应的错误单元未进行过行地址修复。此时比较器510输出高电平信号，开启修复模块600，可以对目标寄存器对应的错误单元进行修复。
而二者一致时，说明目标寄存器210对应的错误单元已经进行过行地址修复。此时比较器510可以输出低电平信号，进而不开启修复模块600。
可以理解的是，参考存储模块400存储的行地址为多个时，比较器510依次比较目标寄存器210输出的行地址与参考存储模块400存储的各个行地址是否一致。
在一个实施例中，修复模块600包括行修复单元610与第二控制单元620。行修复单元610电连接各个寄存器210，用于对目标寄存器对应的错误单元进行行地址修复。第二 控制单元620电连接比较器510以及行修复单元610，用于根据比较器510输出的高电平信号或者低电平信号，开关行修复单元。
作为示例，第二控制单元620可以包括开关晶体管等开关器件。当接收到比较器510输出的高电平信号的时候，开关晶体管等开关器件打开以开启行修复单元610，从而对目标寄存器对应的错误单元进行行地址修复。当接收到到比较器510输出的低电平信号的时候，开关晶体管等开关器件断开以关闭行修复单元，跳过对目标寄存器对应的错误单元的修复或者终止本次修复。
具体地，修复模块600可以与第一判断模块500一起，通过控制模块300的各个开关单元310对应电连接各个寄存器210。
作为示例，如前述说明，控制模块300中可以包括第一控制单元320以及n个开关单元310，每个开关单元310对应一个寄存器210，n为大于1的正整数。
第一控制单元320对n个开关单元310分别输入控制信号S1至Sn。其中，第一控制单元320对第k个开关单元310输入的控制信号为Sk，1≤k≤n。并且，S1至Sn中任意一个为高电平信号时，其余控制信号为低电平信号。
当检测模块100检测到的错误单元的数量达到第一预设数量时，第一控制单元320控制S1至Sn依次成为高电平信号，进而打开顺序打开第一个开关单元至第n个开关单元，进而使得第一个开关单元至第n个开关单元对应的寄存器顺序成为目标寄存器。
对于目标寄存器，其成为目标寄存器时，相应的开关单元310是打开的。因此，目标寄存器内的行地址可以传输至第一判断模块500以及修复模块600。
此时，第一判断模块500的比较器510可以直接获取目标寄存器中的行地址，并将其与参考存储模块400输出的行地址进行比较，并根据比较结果而输出电平信号。
当比较器510输出的电平信号为预设电平信号而使得第二控制单元620打开时，行修复单元610接收并存储目标寄存器中的行地址，进而使得目标寄存器中的行地址可以存储至行修复单元610中而进行修复。
在一个实施例中，行修复单元610包括第二预设数量的行修复熔丝，一个行修复熔丝对应一个冗余行地址。行修复单元610用于将目标寄存器中的行地址存储至行修复单元的一个空白行修复熔丝。
进一步地，此时，参考存储模块400包括行修复单元610。
此外，在一些实施例中，存储器件修复系统还可以包括第二判断模块(未图示)，第二判断模块用于判断行修复单元610中是否具有空白行修复熔丝。
此时，第二控制单元620可以在目标寄存器中的行地址未存在于参考存储模块400中，且行修复单元610中具有空白行修复熔丝时，开启行修复单元。
同时，单元地址还可以包括列地址。修复模块600还包括列修复单元(未图示)，列修复单元用于对目标寄存器对应的错误单元进行列地址修复。
第二控制单元可以在目标寄存器中的行地址未存在于参考存储模块中，但行修复单元中不具有空白行修复熔丝时，开启列修复单元。
关于存储器件修复系统的具体限定可以参见上文中对于存储器件修复方法的限定，在此不再赘述。上述存储器件修复系统中的各个模块可全部或部分通过软件、硬件及其组合来实现。上述各模块可以硬件形式内嵌于或独立于计算机设备中的处理器中，也可以以软件形式存储于计算机设备中的存储器中，以便于处理器调用执行以上各个模块对应的操作。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种存储器件修复方法，包括：
    对所述存储器件的存储单元进行错误检测；
    将检测到的错误单元的单元地址暂存至寄存器，直至检测到的所述错误单元的数量达到第一预设数量，所述错误单元为已损坏的存储单元，一个所述错误单元占用一个所述寄存器，所述单元地址包括行地址；
    在各个所述寄存器中依次选择目标寄存器；
    判断所述目标寄存器中的行地址是否存在于参考存储模块中，所述参考存储模块中存储有已经修复过的行地址或者未被修复过的行地址；
    根据所述判断结果，对未经过行地址修复的所述错误单元进行修复。
  2. 根据权利要求1所述的存储器件修复方法，其中，所述参考存储模块中存储有已经修复过的行地址，所述根据所述判断结果，对未经过行地址修复的所述错误单元进行修复，包括：
    如果所述目标寄存器中的行地址存在于所述参考存储模块中，则跳过对所述目标寄存器对应的所述错误单元的修复。
  3. 根据权利要求2所述的存储器件修复方法，其中，所述根据所述判断结果，对未经过行地址修复的所述错误单元进行修复，还包括：
    如果目标寄存器中的行地址未存在于所述参考存储模块中，则对所述目标寄存器对应的所述错误单元进行修复。
  4. 根据权利要求3所述的存储器件修复方法，其中，
    所述存储器件包括行修复单元，所述行修复单元包括第二预设数量的行修复熔丝，一个所述行修复熔丝对应一个冗余行地址；
    所述如果目标寄存器中的行地址未存在于所述参考存储模块中，则对所述目标寄存器对应的所述错误单元进行修复，包括：
    将所述目标寄存器中的行地址存储至所述行修复单元的一个空白行修复熔丝。
  5. 根据权利要求4所述的存储器件修复方法，其中，所述参考存储模块包括所述行修复单元。
  6. 根据权利要求1所述的存储器件修复方法，还包括：在所述根据所述判断结果，对未经过行地址修复的所述错误单元进行修复之后，
    清空所述目标寄存器。
  7. 根据权利要求1所述的存储器件修复方法，还包括：在所述根据所述判断结果，对未经过行地址修复的所述错误单元进行修复之后，
    当所有寄存器中的行地址均完成修复之后，清空所有寄存器。
  8. 根据权利要求1所述的存储器件修复方法，其中，所述存储器件修复方法应用于对至少两个所述错误单元出现在同一个字线上的存储器件进行修复。
  9. 一种存储器件修复系统，包括：
    检测模块，用于对所述存储器件的存储单元进行错误检测，且输出所述错误单元的单元地址，所述错误单元为已损坏的存储单元；
    寄存模块，电连接所述检测模块，包括数量不少于第一预设数量的寄存器，各所述寄存器用于接收所述错误单元的单元地址，且输出所述错误单元的行地址，一个所述错误单元占用一个所述寄存器，所述单元地址包括行地址；
    控制模块，电连接各个所述寄存器，用于当所述检测模块检测到的错误单元的数量达到第一预设数量时，在各个所述寄存器中依次选择目标寄存器；
    参考存储模块，用于存储以及输出已经修复过的行地址或者未被修复过的行地址；
    第一判断模块，电连接所述参考存储模块与所述寄存模块，用于接收所述目标寄存器输出的行地址以及所述参考存储模块输出的行地址，且判断所述目标寄存器中的行地址是否存在于所述参考存储模块中，并输出判断结果；
    修复模块，电连接所述第一判断模块，用于根据所述判断结果，对未经过行地址修复的所述错误单元进行修复。
  10. 根据权利要求9所述的存储器件修复系统，其中，
    所述控制模块包括第一控制单元以及n个开关单元，每个所述开关单元对应一个所述寄存器，n为大于1的正整数；
    所述第一控制单元对n个所述开关单元分别输入控制信号S1至Sn，其中，所述第一控制单元对第k个所述开关单元输入的控制信号为Sk，1≤k≤n，并且，S1至Sn中任意一个为高电平信号时，其余控制信号为低电平信号；
    当检测模块检测到的错误单元的数量达到第一预设数量时，所述第一控制单元控制S1至Sn依次成为高电平信号，进而顺序打开第一个开关单元至第n个开关单元，进而使得第一个开关单元至第n个开关单元对应的所述寄存器顺序成为目标寄存器，进而与所述第一判断模块相连。
  11. 根据权利要求9所述的存储器件修复系统，其中，所述参考存储模块用于存储已经 修复过的行地址，所述修复模块还用于当所述目标寄存器中的行地址存在于所述参考存储模块中时，跳过对所述目标寄存器对应的所述错误单元的修复。
  12. 根据权利要求11所述的存储器件修复系统，其中，所述第一判断模块包括比较器，所述比较器用于接收所述目标寄存器输出的行地址以及所述参考存储模块输出的行地址，且对所述目标寄存器输出的行地址和所述参考存储模块输出的行地址进行比较，且当所述目标寄存器输出的行地址和所述参考存储模块输出的行地址不一致时，向所述修复模块输出预设电平信号，以开启所述修复模块。
  13. 根据权利要求12所述的存储器件修复系统，其中，所述预设电平信号为高电平信号。
  14. 根据权利要求12所述的存储器件修复系统，其中，
    所述修复模块包括行修复单元与第二控制单元，所述行修复单元电连接所述各个所述寄存器，用于对所述目标寄存器对应的所述错误单元进行行地址修复；
    所述第二控制单元电连接所述比较器与所述行修复单元，用于根据所述比较器输出的高电平信号或者低电平信号，开关所述行修复单元。
  15. 根据权利要求14所述的存储器件修复系统，其中，所述行修复单元包括第二预设数量的行修复熔丝，一个所述行修复熔丝对应一个冗余行地址，所述行修复单元用于将所述目标寄存器中的行地址存储至所述行修复单元的一个空白行修复熔丝。
  16. 根据权利要求15所述的存储器件修复系统，其中，所述参考存储模块包括所述行修复单元。
  17. 根据权利要求9所述的存储器件修复系统，其中，所述存储器件修复系统应用于对至少两个所述错误单元出现在同一个字线上的存储器件进行修复。
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