WO2021056804A1 - 存储器及其寻址方法 - Google Patents

存储器及其寻址方法 Download PDF

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Publication number
WO2021056804A1
WO2021056804A1 PCT/CN2019/121162 CN2019121162W WO2021056804A1 WO 2021056804 A1 WO2021056804 A1 WO 2021056804A1 CN 2019121162 W CN2019121162 W CN 2019121162W WO 2021056804 A1 WO2021056804 A1 WO 2021056804A1
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Prior art keywords
decoding
address
unit
input
coupled
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PCT/CN2019/121162
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English (en)
French (fr)
Inventor
尚为兵
张良
王佳
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/257,532 priority Critical patent/US11423999B2/en
Priority to EP19947164.0A priority patent/EP3896693B1/en
Publication of WO2021056804A1 publication Critical patent/WO2021056804A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1802—Address decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Definitions

  • the present invention relates to the technical field of memory, in particular to a memory and an addressing method thereof.
  • redundant cells are generally added internally to repair defective row storage locations and column storage locations at normal storage locations during the manufacturing process.
  • FIG. 1 is a schematic diagram of the layout position of normal and redundant storage of a DRAM memory in the prior art of the present invention.
  • WL word lines
  • BL bit lines
  • 16 rows of redundant storage are set every 1024 horizontal word lines WLs, corresponding to 16 redundant word lines RedWLs, and every 512 vertical bits
  • Line BL sets 16 columns of redundant storage, corresponding to 16 redundant bit lines RedBLs.
  • the normal storage unit and the redundant storage unit are tested separately to access the corresponding address through different paths and timing controls. During the test, it is necessary to frequently switch between the two tests, which increases the test time; and, because The difference in test path and timing will also easily introduce human test errors, which will result in a decrease in test accuracy.
  • the technical problem to be solved by the present invention is to provide a memory and an addressing method thereof to improve the test efficiency of the memory.
  • the present invention provides a memory including: an input module for receiving an address/command input signal including at least an access address, a command, and a decoding selection instruction, the access address includes a block address, a row address, and a column address.
  • each storage block includes multiple storage units arranged in the array;
  • control module including multiple storage block local control units, each storage block local control unit is connected to each storage block, Used to decode the address/command input signal with the corresponding block address to select the storage unit corresponding to the access address, the storage block local control unit includes: at least one decoding unit, the decoding unit is configured to Perform redundant decoding or normal decoding on the address/command input signal, the input end of the decoding unit is coupled to the input module, and the output end of the decoding unit is coupled to the storage unit; a selection module, The input terminal is coupled to the input module, and the output terminal of the selection module is coupled to the decoding unit, and is configured to output a first enable signal to the decoding unit according to a decoding selection instruction in the address/command input signal To control the decoding unit to perform redundant decoding or normal decoding corresponding to the decoding selection instruction on the address/command input signal.
  • the decoding unit includes a redundant pre-decoding unit, a normal pre-decoding unit, and a secondary decoding unit; the output end of the selection module is coupled to the enable end of the redundant pre-decoding unit and the normal pre-decoding unit.
  • the enabling end of the decoding unit; the output ends of the redundant pre-decoding unit and the normal pre-decoding unit are both coupled to the input end of the secondary decoding unit.
  • the storage block local control unit further includes an address comparison unit, an input end of the address comparison unit is coupled to the input module, an output end of the address comparison unit is coupled to the decoding unit, and the address comparison unit is The unit is used to store defective address information, and compare the access address in the address/command input signal with the defective address information, and according to the comparison result, output a second enable signal for controlling the decoding unit to The address/command input signal performs redundant decoding or normal decoding.
  • the input module includes: an input interface, a buffer unit coupled to the input interface, a logic control unit coupled to an output terminal of the buffer unit, and a normal address latch unit coupled to an output terminal of the logic control unit.
  • the storage block local control unit further includes: a first local latch unit, and an input end of the first local latch unit is coupled to an output end of a normal address latch unit of the input module.
  • the input interface includes multiple input pins
  • the address/command input signal includes multiple sets of digital signals
  • each set of digital signals includes multiple levels input through the multiple input pins.
  • the decoding selection instruction is a level signal input from a pin in a group of digital signals, and the decoding selection instruction corresponds to a decoding manner of the address/command input signal.
  • the selection module includes: a multiplexer, the first input of the multiplexer is coupled to the input module, the second input is connected to a reference level, and the control end is connected to a test control Signal, the test control signal is used to control the multiplexer to output a signal corresponding to the first input terminal or the second input terminal.
  • the selection module further includes: a test enable latch unit, and an input end of the test enable latch unit is coupled to an output end of the multiplexer.
  • the decoding unit further includes: a second local latch unit, and an input end of the second local latch unit is coupled to an output end of a test enable latch unit of the selection module.
  • the storage block local control unit includes two decoding units for respectively decoding the row address and the column address in the access address.
  • the technical solution of the present invention also provides a memory addressing method, including: receiving an address/command input signal including at least an access address, a command, and a decoding selection instruction, the access address including a block address, a row address, and a column address;
  • the decoding selection instruction in the address/command input signal is used to perform redundant decoding or normal decoding on the address/command input signal corresponding to the decoding selection instruction;
  • the storage unit corresponding to the address.
  • the redundant decoding includes redundant pre-decoding and secondary decoding
  • the normal decoding includes normal pre-decoding and secondary decoding
  • the method further includes: in the normal use of the memory, comparing the access address in the address/command input signal with the defect address information, and according to the comparison result, comparing the address/command input signal Perform redundant decoding or normal decoding.
  • the address/command input signal is received through multiple input pins
  • the address/command input signal includes multiple sets of digital signals
  • each set of digital signals includes input through the multiple input pins
  • the decoding selection instruction is a level signal input from a pin in a group of digital signals
  • the decoding selection instruction corresponds to a decoding manner of the address/command input signal.
  • the above method is used to decode the row address and column address in the address/command input signal respectively.
  • the memory of the present invention can control the corresponding redundant decoding or normal decoding of the address/command input signal by setting the decoding selection instruction, so that the test process is more flexible, and there is no need to switch the signal input interface.
  • the path and timing of the address signal input are consistent with the generation path and timing of the first enable signal, which can reduce man-made test errors, thereby improving the accuracy of the test and the convenience of the test.
  • FIG. 1 is a schematic structural diagram of a storage array of a prior art memory according to the present invention
  • FIG. 2 is a schematic structural diagram of a memory according to a specific embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a memory according to a specific embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a memory according to a specific embodiment of the present invention.
  • FIG. 5 is an addressing method of a memory according to a specific embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a memory according to a specific embodiment of the present invention.
  • the memory 200 includes: an input module 201, a storage array 202, a control module 203, and a selection module 204.
  • the memory array 202 may include multiple memory blocks (Banks), such as Bank1 to Bankn. Each bank may include a plurality of memory cells distributed in an array, and each memory cell has a row address and a column address. Therefore, each memory cell in the memory array 202 has a block address, a row address, and a column address, respectively.
  • Each storage block includes normal storage units and redundant storage units arranged in an array. The address decoding of the normal storage unit and the address decoding of the redundant storage unit need to adopt different decoding methods respectively.
  • the input module 201 is configured to receive an address/command input signal including at least an access address, a command, and a decoding selection instruction, and the access address includes a block address, a row address, and a column address.
  • the decoding selection instruction corresponds to the address decoding mode, and is used to indicate redundant decoding or normal decoding of the address.
  • the control module 203 includes a plurality of storage block local control units, for example, storage block local control unit 1 to storage block local control unit n, respectively connected to the corresponding storage block Bank1 to storage block Bankn, and is used for pairing with corresponding block addresses.
  • the address/command input signal is decoded to select the storage unit corresponding to the access address.
  • the input module 201 is connected to the control module 203. After the address/command input signal received by the input module 201 is processed, it is input to the storage block local control unit corresponding to the block address in the control module 203 for processing. decoding.
  • the storage block local control unit includes: at least one decoding unit, the decoding unit is configured to perform redundant decoding or normal decoding on the address/command input signal, the input of the decoding unit is coupled to the input module, the The output terminal of the decoding unit is coupled to the storage block.
  • each storage block local control unit includes two decoding units, which are a row decoding unit, which is used for row address decoding, and a column decoding unit, which is used for column address decoding.
  • the input terminal of the selection module 204 is coupled to the input module 201, and the output terminal of the selection module 204 is coupled to the decoding unit in the storage block local control unit, and is configured to input signals according to the address/command.
  • the decoding selection instruction outputs the first enable signal to the decoding unit in the local control unit of the corresponding storage block to control the decoding unit to perform redundant decoding or normal decoding on the address/command input signal.
  • FIG. 3 is a schematic structural diagram of the memory according to a specific embodiment of the present invention.
  • the input module 303 includes: an input interface, a buffer unit 3031 coupled to the input interface, a logic control unit 3032 coupled to the output of the buffer unit 3031, and a normal address latch unit coupled to the output of the logic control unit 3032 3033.
  • the input interface includes 6 pins, respectively pins CA0 ⁇ CA5, which are respectively used to input high and low level signals to form a set of digital signals as the address/command input signal CA ⁇ 5 :0>.
  • a complete address/command input signal can be input through one or multiple inputs.
  • the address/command input signal includes information such as block address, column address, row address, and command.
  • the command can be row address decoding or column address decoding. Operation instructions such as address decoding, read operation, write operation or refresh.
  • the address/command input signal CA ⁇ 5:0> also includes a decoding selection instruction, and the decoding selection instruction is used to select redundant decoding or normal decoding of the address/command input signal.
  • the pin when one of the pins of the input interface is not used as a valid address/command input pin at a certain clock edge, the pin is used to input the decoding selection command at the clock edge, thereby There is no need to add additional pins for the decoding selection instruction, and there is no need to change the timing and path of the address/command input signal, and the selection of the decoding mode can be realized flexibly and efficiently.
  • the address/command input signal CA ⁇ 5:0> is buffered by the buffer unit 3031 and after a certain logic process is performed by the logic control unit 3032, then it is sent to the normal address latch unit 3033.
  • the required column address signal ColAdr0 ⁇ 9:4> is latched, and then the column address signal ColAdr0 ⁇ 9:4> is sent to the local control unit 301 of the storage block corresponding to the block address in the address/command input signal to perform Column address decoding.
  • the specific structure of the input module 303 can be applied to various technical solutions known to those of ordinary skill in the art, and will not be described in detail here.
  • the storage block local control unit 301 includes a column decoding unit, and the storage block 302 is coupled to the output terminal of the column secondary decoding unit 3013, according to the decoding output from the column secondary decoding unit 3013. After the access address, the storage unit corresponding to the access address is selected.
  • the column decoding unit further includes a column normal pre-decoding unit 3011, a column redundant pre-decoding unit 3012, and a column secondary decoding unit 3013; the output terminals of the column redundant pre-decoding unit 3012 and the column normal pre-decoding unit 3011 Both are coupled to the input end of the column secondary decoding unit 3012.
  • the address/command input signal enters the column secondary decoding unit 3013 for secondary decoding to obtain the final column Address information.
  • the column address of the normal storage unit is obtained after decoding by the column normal pre-decoding unit 3011 and the column secondary decoding unit 3013, so that a column of storage units in the storage block 302 corresponding to the column address can be selected.
  • the column address of the redundant memory cell is obtained after decoding by the column redundancy pre-decoding unit 3012 and the column secondary decoding unit 3013, so that a column of redundant memory cells in the memory block 302 corresponding to the column address can be selected.
  • the storage block local control unit 301 further includes a first local latch unit 3015, and the input end of the first local latch unit 3015 is coupled to the output end of the normal address latch unit 3033, The output terminal of the first local latch unit 3015 is coupled to the input terminals of the column redundant pre-decoding unit 3012 and the column normal pre-decoding unit 3011.
  • the memory further includes a selection module 304, and an output terminal of the selection module 304 is coupled to the enable terminal of the column redundancy pre-decoding unit 3012 and the enable terminal of the column normal pre-decoding unit 3011.
  • the input end of the selection module 304 is coupled to the input module 303, and is used to receive the decoding selection instruction in the address/command input signal at the corresponding clock edge, and control the station according to the decoding selection instruction in the address/command input signal.
  • the column redundancy pre-decoding unit 3012 enables or controls the column normal pre-decoding unit 3011 to be enabled.
  • the selection module 304 includes: a multiplexer MUX.
  • the first input of the multiplexer MUX is coupled to the input module 303, and the second input is connected to a reference level.
  • the reference level is low level 0.
  • the control terminal of the selection module 304 is connected to a test control signal Cm0_ts_RedTest, and the test control signal Cm0_ts_RedTest is used to control the multiplexer MUX to output a signal corresponding to the first input terminal or the second input terminal.
  • the selection module 304 further includes a test enable latch unit 3041, and the input terminal of the test enable latch unit 3041 is coupled to the output terminal of the multiplexer MUX.
  • the storage block local control unit 301 also includes a second local latch unit 3016.
  • the input terminal of the second local latch unit 3016 is coupled to the output terminal of the selection module 304 for latching the first enable Signal RedColEn0; the output end of the second local latch unit 3016 is coupled to the enable end of the column redundant pre-decoding unit 3012 and the column normal pre-decoding unit 3011.
  • the normal address memory 3033 latches the required address information ColAdr ⁇ 9:4>; at the same time, the selection module 304 According to the obtained decoding selection instruction in the address/command input signal, the first enable signal RedColEn0 is output, and the column address signal ColAdr ⁇ 9:4> and the first enable signal RedColEn0 reach the storage block local control unit 301 respectively , And then are respectively latched by the first local latch unit 3015 and the second local latch unit 3016.
  • the storage block local control unit 301 can be controlled to perform corresponding redundant decoding or normal decoding by setting the decoding selection instruction, thereby making the testing process more flexible. No need to switch the signal input interface.
  • each latch unit is controlled by the same clock signal CLK.
  • CLK clock signal
  • the local storage block control unit 3014 further includes a column address comparison unit 3014, the input end of the column address comparison unit 3014 is coupled to the input module 303, and the output end of the column address comparison unit 3014 It is coupled to the enable end of the column normal pre-decoding unit 3011 and the column redundant pre-decoding unit 3011.
  • the column normal pre-decoding unit 3011 performs column normal pre-decoding 3011 on the input signal to obtain the column address of the normal storage unit.
  • FIG. 4 is a schematic structural diagram of a memory according to another specific embodiment of the present invention.
  • FIG. 4 only shows a schematic diagram of the circuit structure related to column decoding.
  • the input module 303 includes: an input interface, a buffer unit 3031 coupled to the input interface, a logic control unit 3032 coupled to the output of the buffer unit 3031, and a normal address latch unit coupled to the output of the logic control unit 3032 4033.
  • the address/command input signal CA ⁇ 5:0> is buffered by the buffer unit 3031 and processed by the logic control unit 3032, it is sent to the normal address latch unit 3033 to latch the row address signal RowAdr. ⁇ 15:0>, and then send the row address signal RowAdr0 ⁇ 15:0> into the row decoding unit in the local control unit 301 of the storage block corresponding to the block address in the address/command input signal to decode the row address .
  • the row decoding unit in the storage block local control unit 301 includes: a row normal pre-decoding unit 4011, a row redundant pre-decoding unit 4012, and a row secondary decoding unit 4013; the row redundant pre-decoding unit 4012, the row
  • the output ends of the normal pre-decoding unit 4011 are all coupled to the input ends of the row secondary decoding unit 4012, and the address/command input signal enters the row secondary decoding unit 4012 after row redundant decoding or row normal pre-decoding. Decode twice to obtain the final row address information.
  • the storage block local control unit 301 further includes a first local latch unit 4015, which is used to locally latch the row address signal RowAdr0 ⁇ 15:0>.
  • the input terminal of the first local latch unit 4015 is coupled to the output terminal of the normal address latch unit 3033, and the output terminal of the first local latch unit 4015 is coupled to the row redundancy pre-decoding unit 4012.
  • the storage block local control unit 301 also includes a second local latch unit 4016.
  • the input terminal of the second local latch unit 4016 is coupled to the output terminal of the selection module 304 and is used to latch the first enable Signal RedRowEn0; the output end of the second local latch unit 4016 is coupled to the enable end of the row redundant pre-decoding unit 4012 and the row normal pre-decoding unit 4011.
  • the local storage block control unit 301 further includes a row address comparison unit 4014, the input end of the row address comparison unit 4014 is coupled to the input module 303, and the output end of the row address comparison unit 4014 It is coupled to the enable end of the line normal pre-decoding unit 4011 and the line redundant pre-decoding unit 4011.
  • the row normal pre-decoding unit 4011 performs row normal pre-decoding 4011 on the input signal to obtain the row address of the normal storage unit.
  • the specific embodiment of the present invention also provides a memory addressing method.
  • Step S501 Receive an address/command input signal containing at least an access address, a command, and a decoding selection instruction, where the access address includes a block address, a row address, and a column address.
  • the address/command input signal may be received through a plurality of input pins.
  • the address/command input signal includes a plurality of sets of digital signals, and each set of digital signals includes a plurality of sets of digital signals input through the plurality of input pins.
  • a level signal wherein the decoding selection instruction is a level signal input from a pin in a group of digital signals, and the decoding selection instruction corresponds to a decoding manner of the address/command input signal.
  • Step S502 According to the decoding selection instruction in the address/command input signal, perform redundant decoding or normal decoding corresponding to the decoding selection instruction on the address/command input signal.
  • the redundant decoding includes redundant pre-decoding and secondary decoding
  • the normal decoding includes normal pre-decoding and secondary decoding
  • the corresponding decoding method for the address/command input signal can be selected by setting the decoding selection instruction. For example, when the decoding selection instruction is 1, normal decoding is performed; when the decoding selection instruction is 0, redundant decoding is performed.
  • Step S503 According to the address obtained after decoding, a storage unit corresponding to the access address is selected.
  • the access to the redundant storage unit and the normal storage unit can be switched, which is more flexible in the test process, and the control sequence is consistent, which can avoid human test errors and improve the test accuracy and flexibility.
  • the addressing method of the memory of the present invention further includes: in normal use, comparing the access address in the address/command input signal with the defect address information, and according to the comparison result, comparing the address/command input signal Perform the corresponding redundant decoding or normal decoding. Specifically, when the access address matches the defective address, the access address is invalid, and the input signal is redundantly pre-decoded to obtain the address of the redundant memory cell that replaces the defective address; when the access address does not match the defective address, The access address is valid, and the input signal is normally decoded to obtain the address of the normal storage unit.

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种存储器及其寻址方法，所述存储器包括：输入模块，用于接收至少包含访问地址、命令以及解码选择指令的地址/命令输入信号；存储阵列，包括多个存储块，每个存储块包括多个阵列排布的存储单元；控制模块，包括多个存储块本地控制单元，各存储块本地控制单元分别连接至各存储块，所述存储块本地控制单元包括：至少一个解码单元，所述解码单元用于对地址/命令输入信号进行冗余解码或正常解码，所述解码单元的输入端耦合至所述输入模块，所述解码单元的输出端耦合至所述存储单元；选择模块，所述选择模块的输入端耦合至所述输入模块、所述选择模块的输出端耦合至所述解码单元。上述存储器的寻址效率提高。

Description

存储器及其寻址方法 技术领域
本发明涉及存储器技术领域，尤其涉及一种存储器及其寻址方法。
背景技术
DRAM存储器的设计，一般会在内部增加冗余单元，来修复制造过程中正常存储位置处有缺陷的行存储位置和列存储位置。
请参考图1，为本发明现有技术的DRAM存储器的正常和冗余存储的布局位置示意图。
其中，仅示出了字线(WL)和位线(BL)，其中，每隔1024条横向字线WLs设置16行冗余存储，对应16条冗余字线RedWLs，每隔512条纵向位线BL设置16列冗余存储，对应16条冗余位线RedBLs。
在存储器芯片测试阶段，需要对正常存储单元进行访问，以测试各正常存储单元是否有效，如果无效，则需要记录该无效存储单元的地址，并用冗余存储单元替代该无效存储单元进行数据存储。
因此，在芯片的测试阶段，需要分别对正常存储单元和冗余存储单元进行测试，由于正常存储单元的地址和冗余存储单元的地址分别采用不同的解码方式，现有技术中，通常会分别对正常存储单元和冗余存储单元通过不同的路径及时序控制，单独进行测试以访问对应的地址，在测试过程中，需要在两种测试之间频繁进行切换操作，增加测试时间；并且，由于测试路径及时序的不同，也会容易引入人为测试误差，导致测试准确性下降。
因此，现有技术中，对存储器的寻址测试效率有待进一步的提高。
发明内容
本发明所要解决的技术问题是，提供一种存储器及其寻址方法，提高对所述存储器的测试效率。
为了解决上述问题，本发明提供了一种存储器，包括：输入模块，用于接收至少包含访问地址、命令以及解码选择指令的地址/命令输入信号，所述访 问地址包括块地址、行地址以及列地址；存储阵列，包括多个存储块，每个存储块包括多个阵列排布的存储单元；控制模块，包括多个存储块本地控制单元，各存储块本地控制单元分别连接至各存储块，用于对具有对应的块地址的地址/命令输入信号进行解码，以选定与所述访问地址对应的存储单元，所述存储块本地控制单元包括：至少一个解码单元，所述解码单元用于对地址/命令输入信号进行冗余解码或正常解码，所述解码单元的输入端耦合至所述输入模块，所述解码单元的输出端耦合至所述存储单元；选择模块，所述选择模块的输入端耦合至所述输入模块、所述选择模块的输出端耦合至所述解码单元，用于根据所述地址/命令输入信号中的解码选择指令，向所述解码单元输出第一使能信号，以控制所述解码单元对所述地址/命令输入信号进行与所述解码选择指令对应的冗余解码或正常解码。
可选的，所述解码单元包括冗余预解码单元、正常预解码单元以及二级解码单元；所述选择模块的输出端耦合至所述冗余预解码单元的使能端和所述正常预解码单元的使能端；所述冗余预解码单元、正常预解码单元的输出端均耦合至所述二级解码单元的输入端。
可选的，所述存储块本地控制单元还包括地址比较单元，所述地址比较单元输入端耦合至所述输入模块，所述地址比较单元的输出端耦合至所述解码单元，所述地址比较单元用于存储缺陷地址信息，并且将所述地址/命令输入信号内的访问地址与所述缺陷地址信息进行比较，并根据比较结果，输出第二使能信号，用于控制所述解码单元对所述地址/命令输入信号进行冗余解码或正常解码。
可选的，所述输入模块包括：输入接口，耦合至所述输入接口的缓冲单元、耦合至所述缓冲单元输出端的逻辑控制单元以及耦合至所述逻辑控制单元输出端的正常地址锁存单元。
可选的，所述存储块本地控制单元还包括：第一本地锁存单元，所述第一本地锁存单元的输入端耦合至所述输入模块的正常地址锁存单元的输出端。
可选的，所述输入接口包括多个输入管脚，所述地址/命令输入信号包括多组数字信号，其中每一组数字信号均包括通过所述多个输入管脚输入的多个 电平信号，其中，所述解码选择指令为其中一组数字信号中的一个管脚输入的电平信号，所述解码选择指令对应于对所述地址/命令输入信号的解码方式。
可选的，所述选择模块包括：多路选择器，所述多路选择器的第一输入端耦合至所述输入模块，第二输入端连接一参考电平，控制端连接至一测试控制信号，所述测试控制信号用于控制所述多路选择器输出所述第一输入端或所述第二输入端对应的信号。
可选的，所述选择模块还包括：测试使能锁存单元，所述测试使能锁存单元的输入端耦合至所述多路选择器的输出端。
可选的，所述解码单元还包括：第二本地锁存单元，所述第二本地锁存单元的输入端耦合至所述选择模块的测试使能锁存单元的输出端。
可选的，所述存储块本地控制单元，包括两个解码单元，分别用于对访问地址内的行地址和列地址进行解码。
本发明的技术方案还提供一种存储器的寻址方法，包括：接收至少包含访问地址、命令以及解码选择指令的地址/命令输入信号，所述访问地址包括块地址、行地址以及列地址；根据所述地址/命令输入信号中的解码选择指令，对所述地址/命令输入信号进行与所述解码选择指令对应的冗余解码或正常解码；根据解码后获得的地址，选定与所述访问地址对应的存储单元。
可选的，所述冗余解码包括冗余预解码和二次解码；所述正常解码包括正常预解码和二次解码。
可选的，还包括：在对存储器的正常使用过程中，将所述地址/命令输入信号内的访问地址与所述缺陷地址信息进行比较，并根据比较结果，对所述地址/命令输入信号进行冗余解码或正常解码。
可选的，通过多个输入管脚，接收所述地址/命令输入信号，所述地址/命令输入信号包括多组数字信号，其中每一组数字信号均包括通过所述多个输入管脚输入的多个电平信号，其中，所述解码选择指令为其中一组数字信号中的一个管脚输入的电平信号，所述解码选择指令对应于对所述地址/命令输入信号的解码方式。
可选的，采用上述方法分别对所述地址/命令输入信号内的行地址和列地 址进行解码。
本发明的存储器，可以通过设置所述解码选择指令控制对地址/命令输入信号进行相应的冗余解码或正常解码，从而使得测试过程更为灵活，无需切换信号输入接口。地址信号输入的路径以及时序与第一使能信号的产生路径与时序一致，可以减少人为测试误差，从而可以提高测试的准确性以及测试的便捷性。
附图说明
图1为本发明一现有技术的存储器的存储阵列的结构示意图；
图2为本发明一具体实施方式的存储器的结构示意图；
图3为本发明一具体实施方式的存储器的结构示意图；
图4为本发明一具体实施方式的存储器的结构示意图；
图5为本发明一具体实施方式的存储器的寻址方法。
具体实施方式
下面结合附图对本发明提供的一种存储器及其寻址方法的具体实施方式做详细说明。
请参考图2，为本发明一具体实施方式的存储器的结构示意图。
所述存储器200包括：输入模块201、存储阵列202、控制模块203以及选择模块204。
所述存储阵列202可以包括多个存储块(Bank)，如Bank1～Bankn。每个Bank可以包括多个阵列分布的存储单元，每个存储单元具有一个行地址和一个列地址。因此，所述存储阵列202内的每个存储单元分别具有一个块地址、一个行地址和一个列地址。在对存储单元寻址时，首先根据块地址，找到存储单元所在的存储块，再根据行地址和列地址找到存储单元在该存储块内的具体位置。每个存储块块内包括阵列排列的正常存储单元和冗余存储单元，所述正常存储单元的地址解码与冗余存储单元的地址解码，需要分别采用不同的解码方式。
所述输入模块201，用于接收至少包含访问地址、命令以及解码选择指令 的地址/命令输入信号，所述访问地址包括块地址、行地址以及列地址。所述解码选择指令与地址解码方式对应，用于指示对地址进行冗余解码或正常解码。
所述控制模块203包括多个存储块本地控制单元，例如存储块本地控制单元1～存储块本地控制单元n，分别连接至对应的存储块Bank1～存储块Bankn，用于对具有对应的块地址的地址/命令输入信号进行解码，以选定与所述访问地址对应的存储单元。
所述输入模块201与所述控制模块203连接，所述输入模块201接收的地址/命令输入信号被处理后，输入至与所述控制模块203内与块地址对应的存储块本地控制单元内进行解码。所述存储块本地控制单元包括：至少一个解码单元，所述解码单元用于对地址/命令输入信号进行冗余解码或正常解码，所述解码单元的输入端耦合至所述输入模块，所述解码单元的输出端耦合至所述存储块。通常每个存储块本地控制单元均包括两个解码单元，分别为行解码单元，用于进行行地址解码，以及列解码单元，用于进行列地址解码。
所述选择模块204的输入端耦合至所述输入模块201、所述选择模块204的输出端耦合至所述存储块本地控制单元内的解码单元，用于根据所述地址/命令输入信号中的解码选择指令，向对应存储块本地控制单元内的解码单元输出第一使能信号，以控制所述解码单元对所述地址/命令输入信号进行冗余解码或正常解码。
请参考图3，为本发明一具体实施方式的所述存储器的结构示意图。
该具体实施方式中，仅示出与列解码相关的电路结构示意图。
所述输入模块303包括：输入接口，耦合至所述输入接口的缓冲单元3031、耦合至所述缓冲单元3031输出端的逻辑控制单元3032以及耦合至所述逻辑控制单元3032输出端的正常地址锁存单元3033。
该具体实施方式中，以LPDDR4为例，输入接口包括6个管脚，分别为管脚CA0～CA5，分别用于输入高低电平信号，形成一组数字信号作为地址/命令输入信号CA<5:0>。可以通过一次或多次输入以输入完整的地址/命令输入信号，所述地址/命令输入信号包括：块地址、列地址、行地址以及命令等信 息，所述命令可以为对行地址解码或列地址解码、读操作、写操作或刷新等操作指令。所述地址/命令输入信号CA<5:0>还包括解码选择指令，所述解码选择指令用于选择对所述地址/命令输入信号进行冗余解码或者正常解码。
通常需要在多个时钟沿时传输多组数字信号，才能将完整的命令及地址信息传输完成以形成完整的地址/命令输入信号，其中在某个特定时钟沿输入的地址/命令输入信号中，会有一个管脚的输入信号对于地址及命令信息而言为无用信号，例如LPDDR4的输入管脚CA3在某一特定的时钟沿不会被用作命令或地址输入，因此，在本发明的具体实施方式中，可以在该特定时钟沿输入解码选择指令，管脚CA3在该特定的时钟沿所接收到的所述解码选择指令仅作为后续解码方式的选择指令，而不会对最终的地址解码结果造成影响。
本发明的具体实施方式中，当输入接口的其中一个管脚在某一时钟沿不作为有效的地址/命令输入管脚时，利用该管脚在该时钟沿时进行解码选择指令的输入，从而无需针对所述解码选择指令增加额外的管脚，也无需改变所述地址/命令输入信号的时序及路径，可以灵活高效的实现解码方式的选择。
该具体实施方式中，所述地址/命令输入信号CA<5:0>经过所述缓冲单元3031缓冲以及经过所述逻辑控制单元3032进行一定的逻辑处理之后，被送入正常地址锁存单元3033锁存需要的列地址信号ColAdr0<9:4>，而后将所述列地址信号ColAdr0<9:4>送入与该地址/命令输入信号内的块地址对应存储块本地控制单元301内，进行列地址解码。
在本发明的其他具体实施方式中，所述输入模块303的具体构成可以采用于本领域普通技术人员知悉的各种技术方案，这里不再详细描述。
该具体实施方式中，所述存储块本地控制单元301包括列解码单元，所述存储块302耦合至所述列二级解码单元3013的输出端，根据所述列二级解码单元3013输出的解码后访问地址，选择与所述访问地址对应的存储单元。
所述列解码单元进一步包括列正常预解码单元3011、列冗余预解码单元3012以及列二级解码单元3013；所述列冗余预解码单元3012、所述列正常预解码单元3011的输出端均耦合至所述列二级解码单元3012的输入端，地址/命令输入信号经过列冗余解码或列正常预解码之后，进入所述列二级解码单元 3013进行二次解码，获取最终的列地址信息。例如，经列正常预解码单元3011、列二级解码单元3013解码后获取正常存储单元的列地址，从而可以选中所述存储块302内的与该列地址对应一列存储单元。再比如，经列冗余预解码单元3012、列二级解码单元3013解码后获取冗余存储单元的列地址，从而可以选中所述存储块302内的与该列地址对应一列冗余存储单元。
该具体实施方式中，所述存储块本地控制单元301还包括第一本地锁存单元3015，所述第一本地锁存单元3015的输入端耦合至所述正常地址锁存单元3033的输出端，所述第一本地锁存单元3015的输出端耦合至所述列冗余预解码单元3012、所述列正常预解码单元3011的输入端。
所述自所述正常地址锁存单元3033输出的列地址信号ColAdr0<9:4>经所述第一本地锁存单元3015后，输出至所述列冗余预解码单元3012以及所述列正常预解码单元3011。
所述存储器还包括选择模块304，所述选择模块304的输出端耦合至所述列冗余预解码单元3012的使能端和所述列正常预解码单元3011的使能端。所述选择模块304的输入端耦合至所述输入模块303，用于在对应时钟沿，接收所述地址/命令输入信号内的解码选择指令，根据地址/命令输入信号内的解码选择指令控制所述列冗余预解码单元3012使能或者控制所述列正常预解码单元3011使能。例如，所述解码选择指令为1(高电平)，则所述选择模块304输出第一使能信号RedColEn＝1，控制所述列冗余预解码单元3012使能，对地址/命令输入信号ColAdr0<9:4>进行列冗余解码，获取冗余存储单元的列地址；若所述解码选择指令为0(低电平)，则所述选择模块304输出第一使能信号RedColEn＝0，控制所述列正常预解码单元3011使能，对地址/命令输入信号ColAdr0<9:4>进行列正常解码，获取正常存储单元的列地址。
该具体实施方式中，所述选择模块304包括：多路选择器MUX，所述多路选择器MUX的第一输入端耦合至所述输入模块303，第二输入端连接一参考电平，该具体实施方式中，所述参考电平为低电平0。所述选择模块304的控制端连接至一测试控制信号Cm0_ts_RedTest，所述测试控制信号Cm0_ts_RedTest用于控制所述多路选择器MUX输出所述第一输入端或第二输 入端对应的信号。所述选择模块304还包括测试使能锁存单元3041，所述测试使能锁存单元3041的输入端耦合至所述多路选择器MUX的输出端。
当所述测试控制信号Cm0_ts_RedTest＝1时，所述多路选择器MUX输出所述第一输入端输入的解码选择指令至所述测试使能锁存单元3041，经过所述测试使能锁存单元3041后输出第一使能信号RedColEn0至所述存储块本地控制单元301内，用于使能所述列正常预解码单元3011或所述列冗余预解码单元3012。
所述存储块本地控制单元301内还包括第二本地锁存单元3016，所述第二本地锁存单元3016的输入端耦合至所述选择模块304的输出端，用于锁存第一使能信号RedColEn0；所述第二本地锁存单元3016的输出端耦合至所述列冗余预解码单元3012和所述列正常预解码单元3011的使能端。
在所述输入模块303输入的地址/命令输入信号经过缓冲单元3031和逻辑控制单元3032后，由所述正常地址所存储器3033锁存需要的地址信息ColAdr<9:4>；同时，选择模块304根据获取的所述地址/命令输入信号内的解码选择指令，输出第一使能信号RedColEn0，所述列地址信号ColAdr<9:4>和第一使能信号RedColEn0分别到达存储块本地控制单元301，再分别由第一本地锁存单元3015和第二本地锁存单元3016锁存。第二本地锁存单元3016输出第一使能信号RedColEn＝1时，会将正常路径的解码停止，将所述列冗余预解码单元3012使能；当所述第一使能信号RedColEn＝0时，则会停止所述列冗余预解码单元3012，不影响正常解码路径。在一个具体实施方式中，所述解码选择指令为1时，所述第一使能信号RedColEn＝1；所述解码选择指令为0时，所述第一使能信号RedColEn＝0。
在对冗余存储单元和正常存储单元进行列测试时，可以通过设置所述解码选择指令控制所述存储块本地控制单元301进行相应的冗余解码或正常解码，从而使得测试过程更为灵活，无需切换信号输入接口。
在正常存储单元和冗余存储单元测试之前进行切换时，只需要对解码选择指令进行控制即可，各锁存单单元均通过同一时钟信号CLK控制，所述列地址信号ColAdr0<9:4>和所述第一使能信号RedColEn的控制时序、经过路径完 全一致，可以减少人为测试误差，从而可以提高测试的准确性以及测试的便捷性。
该具体实施方式中，所述本地存储块控制单元3014还包括列地址比较单元3014，所述列地址比较单元3014的输入端耦合至所述输入模块303，所述列地址比较单元3014的输出端耦合至所述列正常预解码单元3011和所述列冗余预解码单元3011的使能端。
所述地址比较单元3014用于存储在测试过程中获取的缺陷地址信息。在对存储器进行正常的读写操作时，所述地址比较单元3014将所述列地址信号ColAdr<9:4>与所述缺陷地址信息进行比较，并根据比较结果，输出第二使能信号RedColRepair，以控制所述解码单元对所述地址/命令输入信号进行对应的冗余解码或正常解码。具体的，当访问地址与缺陷地址匹配时，所述第二使能信号RedColRepair＝1，访问地址无效，因而使能(Enable)所述列冗余预解码单元3012，对所述输入信号进行列冗余预解码，获取替代该缺陷地址的冗余存储单元的列地址；当访问地址与缺陷地址不匹配时，访问地址有效，所述第二使能信号RedColRepair＝0时，使能(Enable)所述列正常预解码单元3011，对所述输入信号进行列正常预解码3011，获得正常存储单元的列地址。
在对所述存储器进行正常的读写操作时，可以设置测试控制信号Cm0_ts_RedTest＝0，使得所述选择模块304不会获取解码选择指令，停止所述选择模块304对冗余解码路径的选择功能。
请参考图4，为本发明另一具体实施方式的存储器的结构示意图。
图4中仅示出与列解码相关的电路结构示意图。
所述输入模块303包括：输入接口，耦合至所述输入接口的缓冲单元3031、耦合至所述缓冲单元3031输出端的逻辑控制单元3032以及耦合至所述逻辑控制单元3032输出端的正常地址锁存单元4033。地址/命令输入信号CA<5:0>经过所述缓冲单元3031缓冲以及经过所述逻辑控制单元3032进行一定的逻辑处理之后，被送入正常地址锁存单元3033锁存需要的行地址信号RowAdr0<15:0>，而后将所述行地址信号RowAdr0<15:0>送入与该地址/命令输入信号内的块地址对应存储块本地控制单元301内的行解码单元内，进行行地 址解码。
所述存储块本地控制单元301内的行解码单元包括：行正常预解码单元4011、行冗余预解码单元4012以及行二级解码单元4013；所述行冗余预解码单元4012、所述行正常预解码单元4011的输出端均耦合至所述行二级解码单元4012的输入端，地址/命令输入信号经过行冗余解码或行正常预解码之后，进入所述行二级解码单元4012进行二次解码，获取最终的行地址信息。
该具体实施方式中，所述存储块本地控制单元301还包括第一本地锁存单元4015，用于对行地址信号RowAdr0<15:0>进行本地锁存。所述第一本地锁存单元4015的输入端耦合至所述正常地址锁存单元3033的输出端，所述第一本地锁存单元4015的输出端耦合至所述行冗余预解码单元4012、所述行正常预解码单元4011的输入端。
所述存储块本地控制单元301内还包括第二本地锁存单元4016，所述第二本地锁存单元4016的输入端耦合至所述选择模块304的输出端，用于锁存第一使能信号RedRowEn0；所述第二本地锁存单元4016的输出端耦合至所述行冗余预解码单元4012和所述行正常预解码单元4011的使能端。
当所述测试控制信号Cm0_ts_RedTest＝1时，所述多路选择器MUX输出所述第一输入端输入的解码选择指令至所述测试使能锁存单元3041，经过所述测试使能锁存单元3041后输出第一使能信号RedRowEn0至所述存储块本地控制单元301内，用于使能所述行正常预解码单元4011或所述行冗余预解码单元4012。当本地锁存的第一使能信号RedRowEn＝1时，会将正常路径的解码停止，将所述行冗余预解码单元4012使能；当所述第一使能信号RedRowEn＝0时，则会停止所述行冗余预解码单元4012，不影响正常解码路径。
与进行列测试对应的，在进行行测试时，可以通过对地址/命令输入信号内的解码选择指令，控制对行地址信号进行冗余解码还是进行正常解码。
该具体实施方式中，所述本地存储块控制单元301还包括行地址比较单元4014，所述行地址比较单元4014的输入端耦合至所述输入模块303，所述行地址比较单元4014的输出端耦合至所述行正常预解码单元4011和所述行冗余预解码单元4011的使能端。
所述行地址比较单元4014用于存储在测试过程中获取的缺陷地址信息。在对存储器进行正常的读写操作时，所述行地址比较单元4014将所述行地址信号RowAdr<15:0>与所述缺陷地址信息进行比较，并根据比较结果，输出第二使能信号RedRowRepair，以控制所述解码单元对所述地址/命令输入信号进行对应的冗余解码或正常解码。具体的，当访问地址与缺陷地址匹配时，所述第二使能信号RedRowRepair＝1，访问地址无效，因而使能(Enable)所述行冗余预解码单元4012，对所述输入信号进行行冗余预解码，获取替代该缺陷地址的冗余存储单元的行地址；当访问地址与缺陷地址不匹配时，访问地址有效，所述第二使能信号RedRowRepair＝0时，使能(Enable)所述行正常预解码单元4011，对所述输入信号进行行正常预解码4011，获得正常存储单元的行地址。
在对所述存储器进行正常的读写操作时，可以设置测试控制信号Cm0_ts_RedTest＝0，使得所述选择模块304不会获取解码选择指令，停止所述选择模块304对冗余解码路径的选择功能。此时，可以不对所述解码选择指令进行设置。
本发明的具体实施方式还提供一种存储器的寻址方法。
请参考图5，所述存储器的寻址方法如下步骤：
步骤S501：接收至少包含访问地址、命令以及解码选择指令的地址/命令输入信号，所述访问地址包括块地址、行地址以及列地址。
可以通过多个输入管脚，接收所述地址/命令输入信号，所述地址/命令输入信号包括多组数字信号，其中每一组数字信号均包括通过所述多个输入管脚输入的多个电平信号，其中，所述解码选择指令为其中一组数字信号中的一个管脚输入的电平信号，所述解码选择指令对应于对所述地址/命令输入信号的解码方式。
步骤S502：根据所述地址/命令输入信号中的解码选择指令，对所述地址/命令输入信号进行与所述解码选择指令对应的冗余解码或正常解码。
其中，所述冗余解码包括冗余预解码和二次解码；所述正常解码包括正常预解码和二次解码。
可以通过设置所述解码选择指令，选择对地址/命令输入信号进行对应的解码方式。例如，所述解码选择指令为1时，进行正常解码；当解码选择指令为0时，进行冗余解码。
步骤S503：根据解码后获得的地址，选定与所述访问地址对应的存储单元。
可以采用上述步骤分别对行地址和行地址进行解码。
通过设置对应的解码选择指令可以切换对冗余存储单元和正常存储单元的访问，在测试过程中更为灵活，且控制时序一致，可以避免人为测试误差，提高测试准确性和灵活性。
本发明的存储器的寻址方法还包括：在正常使用时，将所述地址/命令输入信号内的访问地址与所述缺陷地址信息进行比较，并根据比较结果，对所述地址/命令输入信号进行对应的冗余解码或正常解码。具体的，当访问地址与缺陷地址匹配时，访问地址无效，对所述输入信号进行冗余预解码，获取替代该缺陷地址的冗余存储单元的地址；当访问地址与缺陷地址不匹配时，访问地址有效，对所述输入信号进行正常解码，获得正常存储单元的地址。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (15)

  1. 一种存储器，其特征在于，包括：
    输入模块，用于接收至少包含访问地址、命令以及解码选择指令的地址/命令输入信号，所述访问地址包括块地址、行地址以及列地址；
    存储阵列，包括多个存储块，每个存储块包括多个阵列排布的存储单元；
    控制模块，包括多个存储块本地控制单元，各存储块本地控制单元分别连接至各存储块，用于对具有对应的块地址的地址/命令输入信号进行解码，以选定与所述访问地址对应的存储单元，所述存储块本地控制单元包括：
    至少一个解码单元，所述解码单元用于对地址/命令输入信号进行冗余解码或正常解码，所述解码单元的输入端耦合至所述输入模块，所述解码单元的输出端耦合至所述存储单元；
    选择模块，所述选择模块的输入端耦合至所述输入模块、所述选择模块的输出端耦合至所述解码单元，用于根据所述地址/命令输入信号中的解码选择指令，向所述解码单元输出第一使能信号，以控制所述解码单元对所述地址/命令输入信号进行与所述解码选择指令对应的冗余解码或正常解码。
  2. 根据权利要求1所述的存储器，其特征在于，所述解码单元包括冗余预解码单元、正常预解码单元以及二级解码单元；所述选择模块的输出端耦合至所述冗余预解码单元的使能端和所述正常预解码单元的使能端；所述冗余预解码单元、正常预解码单元的输出端均耦合至所述二级解码单元的输入端。
  3. 根据权利要求1所述的存储器，其特征在于，所述存储块本地控制单元还包括地址比较单元，所述地址比较单元输入端耦合至所述输入模块，所述地址比较单元的输出端耦合至所述解码单元，所述地址比较单元用于存储缺陷地址信息，并且将所述地址/命令输入信号内的访问地址与所述缺陷地址信息进行比较，并根据比较结果，输出第二使能信号，用于控制所述解码单元对所述地址/命令输入信号进行冗余解码或正常解码。
  4. 根据权利要求1所述的存储器，其特征在于，所述输入模块包括：输入接口，耦合至所述输入接口的缓冲单元、耦合至所述缓冲单元输出端的逻辑 控制单元以及耦合至所述逻辑控制单元输出端的正常地址锁存单元。
  5. 根据权利要求4所述的存储器，其特征在于，所述存储块本地控制单元还包括：第一本地锁存单元，所述第一本地锁存单元的输入端耦合至所述输入模块的正常地址锁存单元的输出端。
  6. 根据权利要求1所述的存储器，其特征在于，所述输入接口包括多个输入管脚，所述地址/命令输入信号包括多组数字信号，其中每一组数字信号均包括通过所述多个输入管脚输入的多个电平信号，其中，所述解码选择指令为其中一组数字信号中的一个管脚输入的电平信号，所述解码选择指令对应于对所述地址/命令输入信号的解码方式。
  7. 根据权利要求1所述的存储器，其特征在于，所述选择模块包括：多路选择器，所述多路选择器的第一输入端耦合至所述输入模块，第二输入端连接一参考电平，控制端连接至一测试控制信号，所述测试控制信号用于控制所述多路选择器输出所述第一输入端或所述第二输入端对应的信号。
  8. 根据权利要求7所述的存储器，其特征在于，所述选择模块还包括：测试使能锁存单元，所述测试使能锁存单元的输入端耦合至所述多路选择器的输出端。
  9. 根据权利要求8所述的存储器，其特征在于，所述解码单元还包括：第二本地锁存单元，所述第二本地锁存单元的输入端耦合至所述选择模块的测试使能锁存单元的输出端。
  10. 根据权利要求1所述的存储器，其特征在于，所述存储块本地控制单元，包括两个解码单元，分别用于对访问地址内的行地址和列地址进行解码。
  11. 一种存储器的寻址方法，其特征在于，包括：
    接收至少包含访问地址、命令以及解码选择指令的地址/命令输入信号，所述访问地址包括块地址、行地址以及列地址；
    根据所述地址/命令输入信号中的解码选择指令，对所述地址/命令输入信号进行与所述解码选择指令对应的冗余解码或正常解码；
    根据解码后获得的地址，选定与所述访问地址对应的存储单元。
  12. 根据权利要求11所述的存储器的寻址方法，其特征在于，所述冗余解码包括冗余预解码和二次解码；所述正常解码包括正常预解码和二次解码。
  13. 根据权利要求11所述的存储器的寻址方法，其特征在于，还包括：在对存储器的正常使用过程中，将所述地址/命令输入信号内的访问地址与所述缺陷地址信息进行比较，并根据比较结果，对所述地址/命令输入信号进行冗余解码或正常解码。
  14. 根据权利要求11所述的存储器的寻址方法，其特征在于，通过多个输入管脚，接收所述地址/命令输入信号，所述地址/命令输入信号包括多组数字信号，其中每一组数字信号均包括通过所述多个输入管脚输入的多个电平信号，其中，所述解码选择指令为其中一组数字信号中的一个管脚输入的电平信号，所述解码选择指令对应于对所述地址/命令输入信号的解码方式。
  15. 根据权利要求11所述的存储器的寻址方法，其特征在于，采用权利要求11至14中任一项所述的寻址方法分别对所述地址/命令输入信号内的行地址和列地址进行解码。
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US11423999B2 (en) 2022-08-23
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