WO2022193101A1 - 一种数据处理方法及相关装置 - Google Patents

一种数据处理方法及相关装置 Download PDF

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Publication number
WO2022193101A1
WO2022193101A1 PCT/CN2021/080883 CN2021080883W WO2022193101A1 WO 2022193101 A1 WO2022193101 A1 WO 2022193101A1 CN 2021080883 W CN2021080883 W CN 2021080883W WO 2022193101 A1 WO2022193101 A1 WO 2022193101A1
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bit sequence
mapped
level signal
inversely
bit
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PCT/CN2021/080883
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English (en)
French (fr)
Inventor
张兴新
王学寰
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华为技术有限公司
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Priority to PCT/CN2021/080883 priority Critical patent/WO2022193101A1/zh
Priority to CN202180001449.8A priority patent/CN113196661B/zh
Publication of WO2022193101A1 publication Critical patent/WO2022193101A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/02—Amplitude modulation, i.e. PAM
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/1505—Golay Codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C

Definitions

  • the present application relates to the field of serializer-deserializer data transmission, and in particular, to a data processing method and a related device.
  • FIG. 1 is a schematic diagram of a DC imbalance.
  • the DC imbalance continuous 0 or continuous 1, only continuous 1 is shown in Figure 1
  • the common mode voltage continues to a The direction is shifted, resulting in an error in the demodulation decision.
  • the existing SerDes system often only provides a single DC balance method to achieve DC balance, which makes it unable to adapt to more DC balance application scenarios.
  • the embodiments of the present application provide a data processing method and a related device, and by implementing the embodiments of the present application, the problem of a single application scenario caused by a single DC balance mode is avoided.
  • a data processing method is provided, the method is applied to a first transmission device, the first transmission device supports at least two DC balance modes, and the method includes:
  • DC balance processing is performed on the first bit sequence to obtain a second bit sequence
  • the at least one level signal is sent.
  • the first transmission device performs DC balancing processing on the first bit sequence by adopting one of the at least two DC balancing methods supported by the first transmission device, thereby avoiding a single DC balancing method.
  • the resulting application scenario is a single problem.
  • multiple DC balance methods can be supported on the same device, so that different DC balance requirements can be adapted.
  • the first transmission device can perform symbol mapping on the bit sequence according to the transmission code type to obtain a level signal, thereby realizing the extended support of multiple transmission code types in the same device. Further, since the same device can be extended to support multiple transmission code types, and symbol mapping can be performed for different transmission code types, module multiplexing is also realized, thereby reducing the cost and power consumption of the product.
  • performing DC balance processing on the first bit sequence to obtain a second bit sequence including:
  • the first bit sequence is divided into M third bit sequences, wherein the M is an integer greater than 0;
  • the M fourth bit sequences are bit combined according to the preset symbol length to obtain the second bit sequence.
  • the first transmission device divides the first bit sequence into multiple bit sequences according to the first preset length, so that line coding can be performed on the multiple bit sequences respectively to obtain encoded multiple bit sequences. bit sequence, thereby improving the efficiency of line coding.
  • the first transmission device performs bit combination on the encoded multiple bit sequences according to the preset symbol length, and then transmits after mapping with specific level symbols, thereby realizing DC balance under multiple transmission code patterns.
  • performing DC balance processing on the first bit sequence to obtain a second bit sequence including:
  • the first transmission device can perform Gray mapping and precoding on the first bit sequence in sequence, thereby realizing another DC balance processing on the first bit sequence on the same device, avoiding the need for a single The single problem of the application scenario caused by the DC balance method, so that it can be adapted to the application of more scenarios and environments.
  • the first bit sequence is a scrambled bit sequence.
  • the scrambled bit sequence is a bit sequence scrambled after symbol interleaving with an interleaving depth of L according to the second preset length, where L is an integer greater than or equal to 1.
  • the second preset length is an integer multiple of a Reed-Solomon (reed-solomon, RS) symbol.
  • RS Reed-Solomon
  • the L is an integer multiple of M.
  • the transmission code type is non-return-to-zero modulation NRZ, or, 2-level pulse amplitude modulation (2-level pulse amplitude modulation, PAM2);
  • the transmission code pattern is 4th-order pulse amplitude modulation (4-level PAM, PAM4);
  • the transmission code pattern is 8th order pulse amplitude modulation (8-level PAM, PAM8);
  • the transmission code pattern is 16-order pulse amplitude modulation (16-level PAM, PAM16).
  • the first preset length is an integer multiple of the preset symbol length, and the preset symbol length is determined according to the line coding.
  • the preset symbol length is 8 bits
  • the preset symbol length is 9 bits.
  • performing symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal including:
  • one bit in the second bit sequence is mapped to a level signal to obtain the at least one level signal.
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • performing symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal including:
  • the transmission code type is the PAM4, mapping every two consecutive bits in the second bit sequence into a level signal to obtain the at least one level signal;
  • the two consecutive bits include one of [a, b], [a', b'], [a', b], and [a, b'];
  • the [a, b] mapping is x, the [a', b'] is mapped to -x, the [a', b] is mapped to y, the [a, b'] is mapped to -y;
  • the a' is the a
  • the binary inversion of the b' is the binary inversion of the b, the value of the a and the b is 0 or 1, and the value set of the x and the y is ⁇ 1, 1/ 3 ⁇ , and the x and y values are different.
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • performing symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal including:
  • the transmission code type is the PAM8, mapping every three consecutive bits in the second bit sequence into a level signal to obtain the at least one level signal;
  • the three consecutive bits include [a, b, c], [a', b', c'], [a', b, c], [a, b', c'], [a , b', c], [a', b, c'], [a', b', c] one of;
  • the [a, b, c] maps is s, the [a', b', c'] is mapped to -s, the [a', b, c] is mapped to w, the [a, b', c'] is mapped to -w,
  • the [a, b', c] is mapped to z, the [a', b, c'] is mapped to -z, the [a, b, c'] is mapped to j, the [a', b', c] is mapped to -j; the a', the b', c]
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • performing symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal including:
  • the transmission code type is the PAM16, mapping every four consecutive bits in the second bit sequence into a level signal to obtain the at least one level signal;
  • the four consecutive bits include: [a, b, c, d], [a', b', c', d'], [a', b, c, d], [a, b', c', d], [a, b', c', d], [a, b, c', d], [a, b, c', d], [a, b, c', d], [a', b' , c, d'], [a', b', c', d], [a', b', c', d], [a', b', c', d], [a, b, c', , d], [a', b, c', , d'], [a', b, c', d], [a, b, c', d'], [a', b, c', d], [a, b
  • the [a, b, c, d] is mapped to t, the [a', b', c', d'] is mapped to -t, and the [a', b, c, d] is mapped to p , the [a, b', c', d'] maps to -p, the [a, b', c, d] maps to v, the [a', b, c', d'] Maps to -v, the [a,b,c',d] maps to u, the [a',b',c,d'] maps to -u, the [a,b,c,d '] maps to k, the [a', b', c', d] maps to -k, the [a', b', c, d] maps to i, the [a, b, c ', d'] is mapped to -i, the [a'
  • the a', the b', the c', and the d' are the binary inversions of the a, the b, the c, and the d, respectively, and the a, the b, and the
  • the value of the c and the d is 0 or 1
  • the value set of the t, the p, the v, the u, the k, the i, the m, and the n is: ⁇ 1,13/15,11/15,9/15,7/15,1/3,1/5,1/15 ⁇ , and the t, the p, the v, the u, the
  • the values of the k, the i, the m, and the n are different from each other.
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • the DC balancing process is a pre-configured DC balancing mode, or a DC balancing mode determined according to received indication information, the indication information being sent by the second transmission device.
  • a data processing method is provided, the method is applied to a second transmission device, and the method includes:
  • the second transmission device performs symbol inverse mapping on the level signal according to the transmission code pattern to obtain the second bit sequence, so as to perform DC de-balancing processing on the second bit sequence to obtain the first bit sequence. sequence, thus avoiding the single problem of application scenarios caused by a single DC balance method.
  • multiple DC balance methods can be supported on the same device, so that different DC balance requirements can be adapted.
  • the second transmission device can perform symbol inverse mapping on the level signal from the first transmission device according to the transmission code type to obtain the second bit sequence, thereby realizing extended support of multiple transmission code types in the same device. Further, since the same device can be extended to support multiple transmission code types, and symbol inverse mapping can be performed for different transmission code types, module multiplexing is also realized, thereby reducing the cost and power consumption of the product.
  • performing DC de-balancing processing on the second bit sequence to obtain the first bit sequence including:
  • De-line coding is performed on the M fourth bit sequences respectively to obtain M third bit sequences
  • the M third bit sequences are combined according to a first preset length to obtain the first bit sequence.
  • the second transmission device obtains multiple bit sequences by splitting the second bit sequence according to the preset symbol length, so that the second transmission device can de-line code the multiple bit sequences respectively,
  • the first bit sequence is obtained by combining the bit sequences after de-line coding, so as to improve the efficiency of de-line coding.
  • performing DC de-balancing processing on the second bit sequence to obtain the first bit sequence including:
  • De-Gray mapping is performed on the decoded second bit sequence to obtain the first bit sequence.
  • the first bit sequence is a scrambled bit sequence.
  • the scrambled bit sequence is a bit sequence scrambled after symbol interleaving with an interleaving depth of L according to the second preset length, where L is an integer greater than or equal to 1.
  • the second preset length is an integer multiple of Reed Solomon RS symbols.
  • the L is an integer multiple of M.
  • the transmission code type is non-return-to-zero modulation NRZ, or second-order pulse amplitude modulation PAM2;
  • the transmission code pattern is 4th-order pulse amplitude modulation PAM4;
  • the transmission code pattern is 8th-order pulse amplitude modulation PAM8;
  • the transmission code pattern is 16-order pulse amplitude modulation PAM16.
  • the first preset length is an integer multiple of the preset symbol length, and the preset symbol length is determined according to the line coding.
  • the preset symbol length is 8 bits
  • the preset symbol length is 9 bits.
  • performing inverse symbol mapping on the at least one level signal according to the transmission code pattern to obtain a second bit sequence including:
  • the transmission code type is the NRZ or the PAM2
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • performing inverse symbol mapping on the at least one level signal according to the transmission code pattern to obtain a second bit sequence including:
  • the transmission code type is the PAM4, inversely map each level signal in the at least one level signal into two consecutive bits to obtain the second bit sequence;
  • each level signal includes one of x, y, -x, -y; the value set of x and y is ⁇ 1, 1/3 ⁇ , and the x and all The value of y is different;
  • the x is inversely mapped to [a, b], the -x is inversely mapped to [a', b'], the y is inversely mapped to [a', b], and the -y is inversely mapped to [a, b']; the a' is the binary inversion of the a, the b' is the binary inversion of the b, and the values of the a and the b are 0 or 1.
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • performing inverse symbol mapping on the at least one level signal according to the transmission code pattern to obtain a second bit sequence including:
  • the transmission code type is the PAM8, inversely map each level signal in the at least one level signal into three consecutive bits to obtain the second bit sequence;
  • each level signal includes one of s, -s, w, -w, z, -z, j, -j; the s, the w, the z, the j
  • the value set is ⁇ 1,5/7,3/7,1/7 ⁇ , and the values of the s, the w, the z, and the j are different from each other;
  • the s is inversely mapped to [a, b, c], the -s is inversely mapped to [a', b', c'], the w is inversely mapped to [a', b, c], the- w is inversely mapped to [a, b', c'], the z is inversely mapped to [a, b', c], the -z is inversely mapped to [a', b, c'], the j inverse
  • the mapping is [a, b, c'], and the -j is inversely mapped to [a', b', c]; the a', the b', and the c' are the a, the b.
  • the binary inversion of the c, the value of the a, the b, and the c is 0 or 1.
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • performing inverse symbol mapping on the at least one level signal according to the transmission code pattern to obtain a second bit sequence including:
  • the transmission code type is the PAM16, inversely map each level signal in the at least one level signal into four consecutive bits to obtain the second bit sequence;
  • each level signal includes t, -t, p, -p, v, -v, u, -u, k, -k, i, -i, m, -m, n, -n A kind of; the value set of the t, the p, the v, the u, the k, the i, the m, and the n is ⁇ 1, 13/15, 11/15 ,9/15,7/15,1/3,1/5,1/15 ⁇ , and the t, the p, the v, the u, the k, the i, the m , the values of n are different from each other;
  • the t is inversely mapped to [a, b, c, d], the -t is inversely mapped to [a', b', c', d'], and the p is inversely mapped to [a', b, c , d], the -p is inversely mapped to [a, b', c', d'], the v is inversely mapped to [a, b', c, d], and the -v is inversely mapped to [a ', b, c', d'], the u inverse mapping is [a, b, c', d], the -u inverse mapping is [a', b', c, d'], the k is inversely mapped to [a, b, c, d'], the -k is inversely mapped to [a', b', c', d], and the i is inversely mapped to
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • the DC balance processing is a pre-configured DC balance mode, or a DC balance mode supported by the second transmission device.
  • a first transmission device supports at least two DC balance modes, and the first transmission device includes a processing module and a transceiver module;
  • the processing module is configured to perform DC balance processing on the first bit sequence to obtain a second bit sequence
  • the processing module is further configured to perform symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal;
  • the transceiver module is used for sending the at least one level signal.
  • the processing module when DC balance processing is performed on the first bit sequence to obtain the second bit sequence, the processing module is configured to:
  • the first bit sequence is divided into M third bit sequences, wherein the M is an integer greater than 0;
  • the M fourth bit sequences are bit combined according to the preset symbol length to obtain the second bit sequence.
  • the processing module when DC balance processing is performed on the first bit sequence to obtain the second bit sequence, the processing module is configured to:
  • the first bit sequence is a scrambled bit sequence.
  • the scrambled bit sequence is a bit sequence scrambled after symbol interleaving with an interleaving depth of L according to the second preset length, where L is an integer greater than or equal to 1.
  • the second preset length is an integer multiple of Reed Solomon RS symbols.
  • the L is an integer multiple of M.
  • the transmission code type is non-return-to-zero modulation NRZ, or second-order pulse amplitude modulation PAM2;
  • the transmission code pattern is 4th-order pulse amplitude modulation PAM4;
  • the transmission code pattern is 8th-order pulse amplitude modulation PAM8;
  • the transmission code pattern is 16-order pulse amplitude modulation PAM16.
  • the first preset length is an integer multiple of the preset symbol length, and the preset symbol length is determined according to the line coding.
  • the preset symbol length is 8 bits
  • the preset symbol length is 9 bits.
  • the processing module when performing symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal, the processing module is configured to:
  • one bit in the second bit sequence is mapped to a level signal to obtain the at least one level signal.
  • the processing module when performing symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal, the processing module is configured to:
  • the transmission code type is the PAM4, mapping every two consecutive bits in the second bit sequence into a level signal to obtain the at least one level signal;
  • the two consecutive bits include one of [a, b], [a', b'], [a', b], and [a, b'];
  • the [a, b] mapping is x, the [a', b'] is mapped to -x, the [a', b] is mapped to y, the [a, b'] is mapped to -y;
  • the a' is the a
  • the binary inversion of the b' is the binary inversion of the b, the value of the a and the b is 0 or 1, and the value set of the x and the y is ⁇ 1, 1/ 3 ⁇ , and the x and y values are different.
  • the processing module when performing symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal, the processing module is configured to:
  • the transmission code type is the PAM8, mapping every three consecutive bits in the second bit sequence into a level signal to obtain the at least one level signal;
  • the three consecutive bits include [a, b, c], [a', b', c'], [a', b, c], [a, b', c'], [a , b', c], [a', b, c'], [a', b', c] one of;
  • the [a, b, c] maps is s, the [a', b', c'] is mapped to -s, the [a', b, c] is mapped to w, the [a, b', c'] is mapped to -w,
  • the [a, b', c] is mapped to z, the [a', b, c'] is mapped to -z, the [a, b, c'] is mapped to j, the [a', b', c] is mapped to -j; the a', the b', c]
  • the processing module when performing symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal, the processing module is configured to:
  • the transmission code type is the PAM16, mapping every four consecutive bits in the second bit sequence into a level signal to obtain the at least one level signal;
  • the four consecutive bits include [a, b, c, d], [a', b', c', d'], [a', b, c, d], [a, b' ,c',d'],[a,b',c,d],[a',b,c',d],[a,b,c',d],[a',b', c, d'], [a, b, c, d'], [a', b', c', d], [a', b', c', d], [a, b, c', d], [a', b, c', d], [a', b, c', d], [a', b, c', d], [a, b', c, d'], [a', b, c, d'], [a', b, c, d'], [a, b', c
  • the [a, b, c, d] is mapped to t, the [a', b', c', d'] is mapped to -t, and the [a', b, c, d] is mapped to p , the [a, b', c', d'] maps to -p, the [a, b', c, d] maps to v, the [a', b, c', d'] Maps to -v, the [a,b,c',d] maps to u, the [a',b',c,d'] maps to -u, the [a,b,c,d '] maps to k, the [a', b', c', d] maps to -k, the [a', b', c, d] maps to i, the [a, b, c ', d'] is mapped to -i, the [a'
  • the a', the b', the c', and the d' are the binary inversions of the a, the b, the c, and the d, respectively, and the a, the b, and the
  • the value of the c and the d is 0 or 1
  • the value set of the t, the p, the v, the u, the k, the i, the m, and the n is: ⁇ 1,13/15,11/15,9/15,7/15,1/3,1/5,1/15 ⁇ , and the t, the p, the v, the u, the
  • the values of the k, the i, the m, and the n are different from each other.
  • the DC balancing process is a pre-configured DC balancing mode, or a DC balancing mode determined according to received indication information, the indication information being sent by the second transmission device.
  • a second transmission device in a fourth aspect, includes a transceiver module and a processing module,
  • the transceiver module for receiving at least one level signal
  • the processing module is configured to perform symbol inverse mapping on the at least one level signal according to the transmission code pattern to obtain a second bit sequence
  • the processing module is further configured to perform DC balance processing on the second bit sequence to obtain a first bit sequence, where the DC balance processing is included in at least two DC balance modes supported by the first transmission device.
  • the processing module when performing de-DC balancing processing on the second bit sequence to obtain the first bit sequence, is configured to:
  • De-line coding is performed on the M fourth bit sequences respectively to obtain M third bit sequences
  • the M third bit sequences are combined according to a first preset length to obtain the first bit sequence.
  • the processing module when performing de-DC balancing processing on the second bit sequence to obtain the first bit sequence, is configured to:
  • De-Gray mapping is performed on the decoded second bit sequence to obtain the first bit sequence.
  • the first bit sequence is a scrambled bit sequence.
  • the scrambled bit sequence is a bit sequence scrambled after symbol interleaving with an interleaving depth of L according to the second preset length, where L is an integer greater than or equal to 1.
  • the second preset length is an integer multiple of Reed Solomon RS symbols.
  • the L is an integer multiple of M.
  • the transmission code type is non-return-to-zero modulation NRZ, or second-order pulse amplitude modulation PAM2;
  • the transmission code pattern is 4th-order pulse amplitude modulation PAM4;
  • the transmission code pattern is 8th-order pulse amplitude modulation PAM8;
  • the transmission code pattern is 16-order pulse amplitude modulation PAM16.
  • the first preset length is an integer multiple of the preset symbol length, and the preset symbol length is determined according to the line coding.
  • the preset symbol length is 8 bits
  • the preset symbol length is 9 bits.
  • the processing module when performing inverse symbol mapping on the at least one level signal according to the transmission code pattern to obtain the second bit sequence, is configured to:
  • the transmission code type is the NRZ or the PAM2
  • the processing module when performing inverse symbol mapping on the at least one level signal according to the transmission code pattern to obtain the second bit sequence, is configured to:
  • the transmission code type is the PAM4, inversely map each level signal in the at least one level signal into two consecutive bits to obtain the second bit sequence;
  • each level signal includes one of x, y, -x, -y; the value set of x and y is ⁇ 1, 1/3 ⁇ , and the x and all The value of y is different;
  • the x is inversely mapped to [a, b], the -x is inversely mapped to [a', b'], the y is inversely mapped to [a', b], and the -y is inversely mapped to [a, b']; the a' is the binary inversion of the a, the b' is the binary inversion of the b, and the values of the a and the b are 0 or 1.
  • the processing module when performing inverse symbol mapping on the at least one level signal according to the transmission code pattern to obtain the second bit sequence, is configured to:
  • the transmission code type is the PAM8, inversely map each level signal in the at least one level signal into three consecutive bits to obtain the second bit sequence;
  • each level signal includes one of s, -s, w, -w, z, -z, j, -j; the s, the w, the z, the j
  • the value set is ⁇ 1,5/7,3/7,1/7 ⁇ , and the values of the s, the w, the z, and the j are different from each other;
  • the s is inversely mapped to [a, b, c], the -s is inversely mapped to [a', b', c'], the w is inversely mapped to [a', b, c], the- w is inversely mapped to [a, b', c'], the z is inversely mapped to [a, b', c], the -z is inversely mapped to [a', b, c'], the j inverse
  • the mapping is [a, b, c'], and the -j is inversely mapped to [a', b', c]; the a', the b', and the c' are the a, the b.
  • the binary inversion of the c, the value of the a, the b, and the c is 0 or 1.
  • the processing module when performing inverse symbol mapping on the at least one level signal according to the transmission code pattern to obtain the second bit sequence, is configured to:
  • the transmission code type is the PAM16, inversely map each level signal in the at least one level signal into four consecutive bits to obtain the second bit sequence;
  • each level signal includes t, -t, p, -p, v, -v, u, -u, k, -k, i, -i, m, -m, n, -n A kind of; the value set of the t, the p, the v, the u, the k, the i, the m, and the n is ⁇ 1, 13/15, 11/15 ,9/15,7/15,1/3,1/5,1/15 ⁇ , and the t, the p, the v, the u, the k, the i, the m , the values of n are different from each other;
  • the t is inversely mapped to [a, b, c, d], the -t is inversely mapped to [a', b', c', d'], and the p is inversely mapped to [a', b, c , d], the -p is inversely mapped to [a, b', c', d'], the v is inversely mapped to [a, b', c, d], and the -v is inversely mapped to [a ', b, c', d'], the u is inversely mapped to [a, b, c', d], the -u is inversely mapped to [a', b', c, d'], the k is inversely mapped to [a, b, c, d'], the -k is inversely mapped to [a', b', c, d'], the -k is
  • the DC balance processing is a pre-configured DC balance mode, or a DC balance mode supported by the second transmission device.
  • a communication device comprising a processor and a memory, the processor invokes a computer program stored in the memory to implement the method according to any one of the first aspect or the second aspect.
  • the communication device further includes an input interface and an output interface, the input interface is used to receive information from other communication devices other than the communication device, and the output interface is used to send information to outside the communication device. output information from other communication devices.
  • the communication apparatus may be a chip implementing the method in the first aspect or the second aspect or a device including the chip.
  • a computer-readable storage medium is provided, and a computer program is stored in the computer-readable storage medium, and when the computer program is executed, any one of the first aspect or the second aspect is implemented. method.
  • a computer program product which, when a computer reads and executes the computer program product, causes the computer to execute the method to implement any one of the first aspect or the second aspect.
  • a communication system including the above-mentioned first transmission device, and/or a second transmission device.
  • Figure 1 is a schematic diagram of a DC imbalance
  • Fig. 2 is a kind of schematic diagram of self-circulating scrambling
  • FIG. 4 is a schematic diagram of a hardware structure of a communication device provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a data processing method provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a bi-level code pattern symbol mapping provided by an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a data processing method provided by an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a data processing method provided by an embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a data processing method provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a communication device according to an embodiment of the present application.
  • At least one (a) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c may be single or multiple .
  • the singular expressions "a”, “an”, “the”, “above”, “the” and “the” are intended to also include such expressions as “one or more” unless the context clearly dictates otherwise. to the contrary.
  • the ordinal numbers such as “first” and “second” mentioned in the embodiments of the present application are used to distinguish multiple objects, and are not used to limit the order, sequence, priority or priority of multiple objects. Importance.
  • references to "one embodiment” or “some embodiments” or the like described in the embodiments of the present application mean that a particular feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically emphasized otherwise.
  • the terms “including”, “including”, “having” and their variants mean “including but not limited to” unless specifically emphasized otherwise.
  • the serializer/deserializer is an interface circuit in high-speed data communication and is used in point-to-point serial communication.
  • the multi-channel low-speed parallel signals are converted into high-speed serial signals by the serializer, and sent to the receiving end device (second transmission device) through a transmission medium (such as a cable, etc.).
  • the high-speed serial signal at the receiving end device (second transmission device) is reconverted into a low-speed parallel signal by the deserializer.
  • This point-to-point serial communication technology makes full use of the channel capacity of the transmission medium and reduces the number of required transmission channels and device pins, thereby greatly reducing communication costs.
  • the in-vehicle image sensor may include, for example, a camera sensor (also referred to as a photosensitive element) or a radar (Radar).
  • a camera sensor also referred to as a photosensitive element
  • a radar Radar
  • the camera sensor includes a plurality of photosensitive points, and each photosensitive point senses an optical signal and converts the optical signal into an electrical signal.
  • radar or referred to as a radar device, also can be referred to as a detector or a detection device. Its working principle is to detect the corresponding target object by transmitting a signal (or called a detection signal) and receiving the reflected signal reflected by the target object.
  • the radar may be, for example, a lidar, an ultrasonic radar, a millimeter-wave radar, or other radars, which are not limited here.
  • the transmission patterns may include bi-level patterns, multi-level patterns, etc., which are not limited here.
  • the bi-level code pattern may include, for example, non-return zero modulation (non-return zero, NRZ), second-order pulse amplitude modulation PAM2, or other code patterns, etc., which are not limited herein.
  • NRZ non-return zero modulation
  • PAM2 second-order pulse amplitude modulation
  • the multi-level code pattern may include, for example, 4th order pulse amplitude modulation (4-level PAM, PAM4), 8th order pulse amplitude modulation (8-level PAM, PAM8), 16th order pulse amplitude modulation (16-level PAM, PAM16 ) or other code types, which are not limited here.
  • the transmission code type may include, for example, one of the following: NRZ, PAM2, PAM4, PAM8, PAM16, etc., which are not limited herein.
  • the input 8-bit (bit) (ABCDEFGH) is divided into two parts, 5-bit (ABCDE) and 3-bit (FGH), respectively, through the mapping table of 5B/6B in Table 1 and the mapping of 3B/4B in Table 2.
  • 10bit output (ABCDEFGH->abcdeifghj) can be obtained. If the running disparity (RD) of the previous 8b/10b is RD- (that is, the number of 0s is more than 1), the next 8b/10b should be mapped to a sequence of RD+ (that is, the number of 0s is less than 1) , so as to achieve DC balance.
  • RD running disparity
  • the first 8 bits are input at time 1, the second 8 bits are input at time 2, and the third 8 bits are input at time 3.
  • time 1 is earlier than time 2, and time 2 is earlier than time 3.
  • time 1 is 9:00
  • time 2 is 9:01:20
  • time 3 is 9:01:55.
  • Table 1 and Table 2 it is assumed that the first 8-bit 00000000 is mapped to 1001111011 after 8b/10b, and its RD is -.
  • the RD of the sequence output by the first 8b/10b encoding is -
  • the RD of the sequence output by the second 8b/10b encoding is +
  • the RD of the sequence output by the third 8b/10b encoding is -.
  • Table 1 Mapping table for 5B/6B
  • Table 2 Mapping table for 3B/4B
  • FIG. 2 is a schematic diagram of a self-circulating scrambling. 2
  • the initial values of the 15 taps are not all zeros (the initialization synchronization seeds of the 15 taps are not all zeros), that is, tap 1, tap 4, tap 6, and tap 8
  • the initial value of 1 is 1, and the initial value of the remaining taps is 0.
  • the value of tap N-1 is passed to tap N, and the values of tap 14 and tap 15 are XORed and then passed to tap 1, thus forming a self-loop.
  • N is an integer greater than or equal to 2 and less than or equal to 15.
  • the values of tap 14 and tap 15 after the values of tap 14 and tap 15 are XORed, they can be XORed with the data input from (IN) to obtain scrambled data. It can be understood that the scrambled data is the data output from (OUT).
  • an embodiment of the present application proposes a data processing method to solve the above problem, and the embodiment of the present application is described in detail below.
  • the technical solutions in the embodiments of the present application can be applied to wired transmission scenarios such as SerDes, such as a camera to a mobile data center (MDC) (MDC is mainly responsible for computing and data storage related to advanced assisted driving or automatic driving functions).
  • MDC mobile data center
  • CDC cockpit domain controller
  • the image output device may be, for example, a display screen or the like, and the display screen may be, for example, a large vehicle-mounted screen, etc., which is not limited herein.
  • FIG. 3 shows an infrastructure of a communication system provided by an embodiment of the present application.
  • the communication system may include a first transmission device 10 and a second transmission device 20 in wired communication with the first transmission device 20 .
  • the first transmission device and the second transmission device in this application support both sending and receiving of data.
  • the device that mainly sends data is called the first transmission device
  • the device that mainly receives data is called the first transmission device.
  • the device is called the second transmission device.
  • FIG. 3 is only a schematic diagram, and does not constitute a limitation on the applicable scenarios of the technical solutions provided in the present application.
  • the first transmission device 10 and the second transmission device 20 may be two independent devices, or different devices in the same device, which are not limited herein.
  • the first transmission device 10 may be, for example, a camera (such as a vehicle-mounted camera), a vehicle-mounted millimeter-wave radar, a lidar, a vehicle-mounted communication box (TelematicsBOX, T-Box), etc.
  • the second transmission device 20 may be, for example, a vehicle-mounted high-performance Computing platform (high-performance computing platform, HCP) equipment or other in-vehicle computing equipment, etc., are not limited here.
  • the HCP device may include, for example, an MDC device or a CDC device, which is not limited herein.
  • the first transmission device 10 or the second transmission device 20 may be, for example, a cellular phone, a smart phone, a cordless phone, a tablet computer, a session initiation protocol (SIP) Telephone, personal digital assistant (PDA) device, laptop computer (laptop computer), machine type communication (MTC) terminal, handheld device with wireless communication capabilities, computing device or connected to a wireless modem other processing devices, wearable devices (also known as wearable smart devices), virtual reality (VR) terminals, augmented reality (AR) terminals, wireless terminals in industrial control (industrial control), Wireless terminals in self-driving, wireless terminals in remote medical, wireless terminals in smart grid, wireless terminals in transportation safety, smart city ), wireless terminals in a smart home (smart home), etc., which are not limited here.
  • SIP session initiation protocol
  • PDA personal digital assistant
  • MTC machine type communication
  • handheld device with wireless communication capabilities computing device or connected to a wireless modem other processing devices
  • wearable devices also known as wearable smart devices
  • VR virtual reality
  • the first transmission device 10 may be, for example, a processor in an in-vehicle device
  • the second transmission device 20 may be, for example, a display screen of the in-vehicle device, a memory in the in-vehicle device, etc.
  • the first transmission device 10 may be, for example, a mobile
  • the camera in the mobile phone and the second transmission device 20 can be, for example, a display screen of a mobile phone, a memory in the mobile phone, etc., which are not limited here.
  • the technical solutions provided by the embodiments of the present application may be applicable to various system architectures.
  • the system architecture and business scenarios described in the embodiments of the present application are for the purpose of illustrating the technical solutions of the embodiments of the present application more clearly, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application.
  • the evolution of the architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
  • each device in FIG. 3 may be implemented by one device, or jointly implemented by multiple devices, or may be a functional module in one device. , which is not specifically limited in the embodiments of the present application. It can be understood that the above functions may be network elements in hardware devices, software functions running on dedicated hardware, or virtualized functions instantiated on a platform (eg, a cloud platform).
  • a platform eg, a cloud platform
  • FIG. 4 is a schematic diagram of a hardware structure of a communication apparatus provided by an embodiment of the present application.
  • the communication device 400 includes at least one processor 401 , a communication line 402 , a memory 403 and at least one communication interface 404 .
  • the processor 401 may be a general-purpose central processing unit (central processing unit, CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more processors for controlling the execution of the programs of the present application. integrated circuit.
  • CPU central processing unit
  • ASIC application-specific integrated circuit
  • Communication line 402 may include a path to communicate information between the aforementioned components.
  • the communication interface 404 is a device such as a wired transceiver, which is used for wired communication with other devices or a communication network, such as Ethernet.
  • Memory 403 may be read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM), or other types of storage devices that can store information and instructions It can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, CD-ROM storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or capable of carrying or storing desired program code in the form of instructions or data structures and capable of being executed by a computer Access any other medium without limitation.
  • the memory may exist independently and be connected to the processor through communication line 402 .
  • the memory can also be integrated with the processor.
  • the memory provided by the embodiments of the present application may generally be non-volatile.
  • the memory 403 is used for storing computer-executed instructions for executing the solution of the present application, and the execution is controlled by the processor 401 .
  • the processor 401 is configured to execute the computer-executed instructions stored in the memory 403, thereby implementing the methods provided by the following embodiments of the present application.
  • the computer-executed instructions in the embodiment of the present application may also be referred to as application code, which is not specifically limited in the embodiment of the present application.
  • the processor 401 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 4 .
  • the communication apparatus 400 may include multiple processors, such as the processor 401 and the processor 407 in FIG. 4 .
  • processors can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the communication apparatus 400 may further include an output device 405 and an input device 406 .
  • the output device 405 is in communication with the processor 401 and can display information in a variety of ways.
  • the output device 405 may be a liquid crystal display (LCD), a light emitting diode (LED) display device, an organic light emitting diode (LED) display device, a cathode ray tube (cathode) ray tube, CRT) display device, or projector (projector).
  • Input device 406 is in communication with processor 401 and can receive user input in a variety of ways.
  • the input device 406 may be a mouse, a keyboard, a touch screen device, a sensor device, or the like.
  • the above-mentioned communication apparatus 400 may be a general-purpose device or a dedicated device.
  • the communication apparatus 400 may be a desktop computer, a portable computer, a network server, a palmtop computer, a mobile phone, a tablet computer, a wireless terminal device, an embedded device or a device with a similar structure in FIG. 4 .
  • This embodiment of the present application does not limit the type of the communication apparatus 400 .
  • FIG. 5 is a schematic flowchart of a data processing method provided by an embodiment of the present application.
  • the first transmission device in FIG. 5 may be the first transmission device 10 in FIG. 3
  • the second transmission device in FIG. 5 may be the second transmission device 20 in FIG. 3 .
  • the method includes but is not limited to the following steps:
  • the first transmission device performs DC balance processing on the first bit sequence to obtain a second bit sequence, and the first transmission device supports at least two DC balance modes.
  • the DC balance processing may be included in at least two DC balance modes.
  • the DC balance processing may be a pre-configured DC balance method, or a DC balance method determined according to received indication information, the indication information being sent by the second transmission device.
  • the above-mentioned DC balance processing is a pre-configured DC balance method, which can be understood as: the above-mentioned DC balance processing is a DC balance method pre-configured in the first transmission device and the second transmission device, and here No restrictions.
  • the above-mentioned DC balance processing is a DC balance method determined according to the received indication information, and the indication information is sent by the second transmission device, which can be understood as: the above-mentioned DC balance processing is a DC balance method determined according to the received signaling, The signaling is sent by the second transmission device, and the signaling may include indication information.
  • the first bit sequence may be a bit sequence after encoding the data to be transmitted according to the preset encoding, or a bit sequence after scramble.
  • the preset coding can be, for example, Reed-Solomon Forward Error Correction Coding (reed-solomon FEC, RS-FEC), low density parity check code (low density parity check code, LDPC) or other coding, which is not limited here .
  • the data to be transmitted can be, for example, image data, video data or other control interface data, such as Inter-Integrated Circuit (I2C) data, general-purpose input/output (GPIO) data, etc. make restrictions.
  • I2C Inter-Integrated Circuit
  • GPIO general-purpose input/output
  • the first bit sequence may include, for example, one or more Reed-Solomon (RS) code blocks.
  • the first RS code block in the one or more RS code blocks may be, for example: Kq_1, Kq-1_1...K2_1, K1_1, Pr_1, Pr-1_1...P2_1, P1_1; the first RS code block in the one or more RS code blocks may be:
  • the two RS code blocks may be, for example: Kq_2, Kq-1_2... Kq-1_J...K2_J, K1_J, Pr_J, Pr-1_J...P2_J, P1_J.
  • Kq_1 to K1_1 are valid data
  • Pr_1 to P1_1 are RS-FEC redundancy check data
  • q indicates the number of RS symbols of valid data
  • r indicates the number of RS symbols of check data
  • J is greater than 0. the integer.
  • K is 100
  • P is 10
  • q is 1-100
  • r is 1-10
  • Kq_1 and Pr_1 can respectively represent an 8-bit sequence.
  • the scrambled bit sequence is a bit sequence scrambled after symbol interleaving with an interleaving depth of L according to the second preset length, where L is an integer greater than or equal to 1.
  • the first bit sequence includes an even number of RS code blocks, such as 2, and the first bit sequence is: ⁇ Kq_1, Kq-1_1... K2_1, K1_1, Pr_1, Pr-1_1... ...P2_1, P1_1, Kq_2, K q-1_2...K2_2, K1_2, Pr_2, Pr-1_2...P2_2, P1_2 ⁇
  • the sequence after the interleaving depth is 2 symbols can be: ⁇ Kq_1, Kq_2, Kq- 1_1, K q-1_2...K2_1, K2_2, K1_1, K1_2, Pr_1, Pr_2, Pr-1_1, Pr-1_2...P2_1, P2_2, P1_1, P1_2 ⁇ .
  • bit sequence after encoding the data to be transmitted according to the preset encoding will be referred to as the fifth bit sequence below.
  • the scrambled bit sequence is the bit sequence scrambled after symbol interleaving with an interleaving depth of L according to the second preset length, which can be understood as: the scrambled bit sequence is A bit sequence obtained after the sixth bit sequence is XORed with the preset bit sequence.
  • the sixth bit sequence is a bit sequence obtained by interleaving symbols with an interleaving depth of L according to the second preset length for the fifth bit sequence, and the second preset length can be an integer multiple of the RS symbol, for example, 8 bits are one For RS symbols, the second preset length may be one or more RS symbols, which is not limited here.
  • the preset bit sequence may be a random sequence similar to that generated by the shift register shown in FIG. 2 .
  • the scrambled bit sequence may be 11000101.
  • step 501 may include: the first transmission device divides the first bit sequence into M third bit sequences according to the first preset length, where M is an integer greater than 0; the first The transmission device performs line coding on the M third bit sequences respectively to obtain M fourth bit sequences; the first transmission device performs bit combination on the M fourth bit sequences according to the preset symbol length to obtain the second bit sequence.
  • the first preset length may be an integer multiple of the preset symbol length, and the preset symbol length is determined according to line coding.
  • the preset symbol length is 8 bits; if the line code is 9B/10B, the preset symbol length is 9 bits.
  • the first transmission device divides the first bit sequence into M third bit sequences according to the first preset length, which can be understood as: the first transmission device divides the The fifth bit sequence or the scrambled bit sequence is divided into M third bit sequences, which is not limited here.
  • M may be, for example, 1, 2, 3, 4 or other positive integer values, which are not limited herein.
  • the first transmission device may divide the first bit sequence into one third bit sequence or two third bit sequences or three third bit sequences or four third bit sequences according to the first preset length. etc., there is no restriction here.
  • the first transmission device may divide the first bit sequence into one third bit sequence according to the first preset length; for PAM4, the first transmission device may According to the first preset length, the first bit sequence is split into two third bit sequences; for PAM8, the first transmission device can split the first bit sequence into three third bit sequences according to the first preset length;
  • the first transmission device may divide the first bit sequence into four third bit sequences according to the first preset length.
  • each of the M third bit sequences has the same length.
  • the length of each third bit sequence in the M third bit sequences is the same, and it can be understood that the length of each third bit sequence in the M third bit sequences is the first preset length.
  • the first transmission device performs bit-combination on the M fourth bit sequences according to the preset symbol length to obtain the second bit sequence, for reference to the following examples.
  • the two fourth bit sequences may include a seventh bit sequence and an eighth bit sequence
  • the seventh bit sequence may be A 1 B 1 C 1 D 1 E 1 F 1 G 1 ...
  • the eighth bit sequence can be a 1 b 1 c 1 d 1 e 1 f 1 g 1 ...
  • the second bit sequence can be A 1 a 1 B 1 b 1 C 1 c 1 D 1 d 1 E 1 e 1 F 1 f 1 G 1 g 1 ....
  • L can be an integer multiple of M.
  • the first transmission device divides the first bit sequence into multiple bit sequences according to the first preset length, so that line coding can be performed on the multiple bit sequences respectively to obtain encoded multiple bit sequences. bit sequence, thereby improving the efficiency of line coding.
  • the first transmission device performs bit-combination on the encoded multiple bit sequences according to the preset symbol length, and then transmits after mapping with a specific level symbol, thereby realizing DC balance under various transmission code patterns.
  • step 501 may include: the first transmission device performs Gray mapping on the first bit sequence to obtain the first bit sequence after Gray mapping; the first transmission device performs Gray mapping on the first bit sequence after Gray mapping Precoding is performed to obtain a second bit sequence.
  • the first transmission device performs Gray mapping on the first bit sequence to obtain the first bit sequence after Gray mapping, which can be understood as: the first transmission device performs the scrambled bit sequence (that is, the first bit sequence is the scrambled bit sequence The first bit sequence after Gray mapping is obtained.
  • the code pattern is the first bit sequence of PAM4, and the Gray mapping may include: [0,0] is mapped to 0; [0,1] is mapped to 1; [1,1] is mapped to 2; [1,0] ] maps to 3.
  • the code pattern is the first bit sequence of PAM8, and the Gray mapping may include: [0,0,0] is mapped to 0; [0,0,1] is mapped to 1; [0,1,0] is mapped to 2; [0,1,1] maps to 3; [1,0,0] maps to 4; [1,0,1] maps to 5; [1,1,0] maps to 6; [1,1] ,1] maps to 7.
  • the code pattern is the first bit sequence of PAM16
  • the Gray mapping may include: [0,0,0,0] is mapped to 0; [0,0,0,1] is mapped to 1; [0,0, 1,0] is mapped to 2; [0,0,1,1] is mapped to 3; [0,1,0,0] is mapped to 4; [0,1,0,1] is mapped to 5; [0, 1,1,0] maps to 6; [0,1,1,1] maps to 7; [1,0,0,0] maps to 8; [1,0,0,1] maps to 9; [ 1,0,1,0] maps to 10; [1,0,1,1] maps to 11; [1,1,0,0] maps to 12; [1,1,0,1] maps to 13 ; [1,1,1,0] maps to 14; [1,1,1,1] maps to 15.
  • the first transmission device can perform Gray mapping and precoding on the first bit sequence in sequence, so as to implement another DC balance processing on the first bit sequence on the same device, avoiding the current situation.
  • the first transmission device performs symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal.
  • the transmission code type may be NRZ or PAM2; if M is 2, the transmission code type may be PAM4; if M is 3, the transmission code type may be PAM8; if M is 4.
  • the transmission code type can be PAM16.
  • step 502 may include: if the transmission code type is NRZ or PAM2, the first transmission device maps one bit in the second bit sequence to a level signal to obtain at least one level signal.
  • the first transmission device maps one bit in the second bit sequence to a level signal to obtain at least one level signal, which can be understood as: the first transmission device maps the first bit value in the second bit sequence to the first level signal. level, the first transmission device maps the second bit value in the second bit sequence to the second level, so as to obtain the above-mentioned at least one level signal.
  • the first bit value and the second bit value are different. If the value of the first bit is 0, the value of the second bit may be 1; if the value of the first bit is 1, the value of the second bit may be 0, which is not limited herein.
  • the first level and the second level are different.
  • the first level may be 1, and the second level may be -1, which is not limited herein.
  • FIG. 6 is a schematic diagram of a bi-level code pattern symbol mapping provided by an embodiment of the present application. 6, it can be seen that 0 in 00101 is mapped to the first level (1), and 1 in 00101 is mapped to the second level (-1).
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • step 502 may include: if the transmission code type is PAM4, mapping every two consecutive bits in the second bit sequence into a level signal to obtain at least one level signal; wherein, Every two consecutive bits includes one of [a, b], [a', b'], [a', b], [a, b']; [a, b] is mapped to x, [a'] , b'] is mapped to -x, [a', b] is mapped to y, [a, b'] is mapped to -y; a' is the binary inversion of a, b' is the binary inversion of b; a and The value of b is 0 or 1, the value set of x and y is ⁇ 1, 1/3 ⁇ , and the values of x and y are different.
  • [0, 0] is mapped to level-1/3, [1, 0] is mapped to level-1, [0, 1] is mapped to level 1, and [1, 1] is mapped to level 1/3; or, [0, 0] is mapped to level-1, [1, 0] is mapped to level-1/3, [0, 1] is mapped to level 1/3, [1, 1] Mapped to level 1; or, [0, 0] mapped to level 1, [1, 0] mapped to level 1/3, [0, 1] mapped to level -1/3, [1, 1] ] is mapped to level-1; or, [0, 0] is mapped to level 1/3, [1, 0] is mapped to level 1, [0, 1] is mapped to level-1, [1, 1] ] is mapped to level-1/3; or, [0, 0] is mapped to level-1/3, [1, 0] is mapped to level-1/3, [1, 0] is mapped to level-1/3, [1, 0] is mapped to level-1
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • step 502 may include: if the transmission code type is PAM8, mapping every three consecutive bits in the second bit sequence into a level signal to obtain at least one level signal; wherein, Every three consecutive bits includes [a, b, c], [a', b', c'], [a', b, c], [a, b', c'], [a, b', One of c], [a', b, c'], [a, b, c'], [a', b', c]; [a, b, c] is mapped to s, [a' , b', c'] is mapped to -s, [a', b, c] is mapped to w, [a, b', c'] is mapped to -w, [a, b', c] is mapped to z, [a', b, c'] is mapped to -z, [a', b, c']
  • [0, 0, 0] is mapped to level 1, [1, 1, 1] is mapped to level-1, [1, 0, 0] is mapped to level 5/7, [0, 1] , 1] is mapped to level-5/7, [0, 1, 0] is mapped to level 3/7, [1, 0, 1] is mapped to level-3/7, [0, 0, 1] Mapped to level 1/7, [1, 1, 0] mapped to level -1/7.
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • step 502 may include: if the transmission code type is PAM16, mapping every four consecutive bits in the second bit sequence into a level signal to obtain at least one level signal; wherein, Every four consecutive bits includes one of the following: [a, b, c, d], [a', b', c', d'], [a', b, c, d], [a, b' ,c',d'],[a,b',c,d],[a',b,c',d'],[a,b,c',d],[a',b', c, d'], [a, b, c, d'], [a', b', c', d], [a', b', c', d], [a', b', c', d], [a', b', c', d], [a, b, c', d], [a', b, c', d],
  • [0, 0, 0, 0] is mapped to level 1, [1, 1, 1, 1] is mapped to level-1, and [1, 0, 0, 0] is mapped to level 13/ 15, [0, 1, 1, 1] is mapped to level -13/15, [0, 1, 0, 0] is mapped to level 11/15, [1, 0, 1, 1] is mapped to level -11/15, [0, 0, 1, 0] maps to level 9/15, [1, 1, 0, 1] maps to level -9/15, [0, 0, 0, 1] maps is level 7/15, [1, 1, 1, 0] is mapped to level -7/15, [1, 1, 0, 0] is mapped to level 1/3, [0, 0, 1, 1 ] is mapped to level-1/3, [1, 0, 1, 0] is mapped to level 1/5, [0, 1, 0, 1] is mapped to level-1/5, [1, 0, 0, 1] is mapped to level 1/15, and [0, 1, 1, 0] is mapped to level -1/15.
  • the level signal still has the characteristic of DC balance, and the transmission quality is improved.
  • the first transmission device performs DC balancing processing on the first bit sequence by adopting one of at least two DC balancing methods, thereby avoiding applications caused by a single DC balancing method. Scenario single problem.
  • multiple DC balance methods can be supported on the same device, so that different DC balance requirements can be adapted.
  • the first transmission device can perform symbol mapping on the bit sequence according to the transmission code type to obtain a level signal, thereby realizing the extended support of multiple transmission code types in the same device. Further, since the same device can be extended to support multiple transmission code types, and symbol mapping can be performed for different transmission code types, module multiplexing is also realized, thereby reducing the cost and power consumption of the product.
  • the first transmission device can first encode the data to be transmitted according to RS-FEC to obtain the fifth bit sequence; then, the first transmission device can perform DC balance processing on the fifth bit sequence to obtain the second bit sequence sequence; then, the first transmission device can perform symbol mapping on the second bit sequence to obtain at least one level signal, for example, the first transmission device can perform symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal signal; finally, the first transmission device may send at least one level signal to the second transmission device.
  • the first transmission device performs DC balance processing on the fifth bit sequence to obtain the second bit sequence, which can be understood as: the first transmission device first divides the fifth bit sequence. For example, the first transmission device can follow the first preset length, the fifth bit sequence is divided into M third bit sequences; then, the first transmission device can respectively perform line coding on the divided fifth bit sequences, for example, the first transmission device can respectively encode the M third bit sequences Perform line coding to obtain M fourth bit sequences; finally, the first transmission device may interleave the line-coded bit sequences to obtain a second bit sequence, for example, the first transmission device may perform an analysis of the M fourth bit sequences according to the preset symbol length. The four-bit sequence is interleaved to obtain a second bit sequence.
  • the first transmission device can perform line coding on the branched fifth bit sequence in parallel.
  • the first transmission device may perform line coding on M third bit sequences in parallel to obtain M fourth bit sequences.
  • the first transmission device performs DC balance processing on the fifth bit sequence to obtain the second bit sequence, which can be understood as: the first transmission device performs RS symbol interleaving on the fifth bit sequence to obtain the sixth bit sequence, such as the first transmission device.
  • the device obtains the sixth bit sequence after the symbol interleaving with an interleaving depth of L according to the second preset length for the fifth bit sequence; then, the first transmission device performs XOR processing on the sixth bit sequence and the preset bit sequence to obtain the addition. scrambled bit sequence; then, the first transmission device performs Gray mapping on the scrambled bit sequence to obtain a gray-mapped bit sequence; finally, the first transmission device precodes the gray-mapped bit sequence to obtain the first two-bit sequence.
  • FIG. 8 is a schematic flowchart of a data processing method provided by an embodiment of the present application.
  • the first transmission device can first perform DC balance processing on the scrambled bit sequence to obtain a second bit sequence; then, the first transmission device can perform symbol mapping on the second bit sequence to obtain at least For a level signal, for example, the first transmission device can perform symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one level signal; finally, the first transmission device can send at least one level signal to the second transmission device .
  • the scrambled bit sequence may be the bit sequence obtained after the sixth bit sequence and the preset bit sequence are XORed; the sixth bit sequence may be the fifth bit sequence.
  • the bit sequence after RS symbol interleaving for example, the sixth bit sequence may be the bit sequence after symbol interleaving with an interleaving depth of L according to the second preset length for the fifth bit sequence, and the second preset length may refer to the above-mentioned correlation The description will not be repeated here;
  • the fifth bit sequence may be a bit sequence after encoding the data to be transmitted according to a preset encoding (eg, RS-FEC).
  • the first transmission device performs DC balance processing on the scrambled bit sequence to obtain the second bit sequence, which can be understood as: the first transmission device first divides the scrambled bit sequence. For example, the first transmission device can follow the For the first preset length, the scrambled bit sequence is divided into M third bit sequences; then, the first transmission device can respectively perform line coding on the divided bit sequences, for example, the first transmission device can respectively The third bit sequence is line-coded to obtain M fourth bit sequences; finally, the first transmission device can interleave the line-coded bit sequence to obtain the second bit sequence, for example, the first transmission device can follow the preset symbol length The M fourth bit sequences are interleaved to obtain the second bit sequence.
  • the first transmission device can perform line coding on the split bit sequence in parallel.
  • the first transmission device may perform line coding on M third bit sequences in parallel to obtain M fourth bit sequences.
  • the first transmission device may perform DC balance processing on the scrambled bit sequence to obtain the second bit sequence, which can be understood as: the first transmission device may perform Gray mapping on the scrambled bit sequence to obtain the gray-mapped bit sequence; then, the first transmission device precodes the gray-mapped bit sequence to obtain a second bit sequence.
  • FIG. 9 is a schematic flowchart of a data processing method provided by an embodiment of the present application.
  • the first transmission device in FIG. 9 may be the first transmission device 10 in FIG. 3
  • the second transmission device in FIG. 9 may be the second transmission device 20 in FIG. 3 .
  • the method includes but is not limited to the following steps:
  • the first transmission device sends at least one level signal to the second transmission device.
  • the second transmission device performs symbol inverse mapping on at least one level signal according to the transmission code pattern to obtain a second bit sequence.
  • step 902 may include: if the transmission code type is NRZ or PAM2, the second transmission device inversely maps each level signal in the at least one level signal into a bit to obtain the second bit sequence.
  • each of the above-mentioned level signals may be the first level or the second level
  • the second transmission device may inversely map the first level to the first bit value, and inversely map the second level to the second level bit value.
  • first level, the second level, the first bit value, and the second bit value reference may be made to the above-mentioned related descriptions, and details are not repeated here.
  • step 902 may include: if the transmission code type is PAM4, the second transmission device inversely maps each level signal in the at least one level signal into two consecutive bits to obtain the second bit sequence;
  • each level signal includes one of x, y, -x, -y; the value set of x and y is ⁇ 1, 1/3 ⁇ , and the values of x and y are different;
  • x is inversely mapped to [a, b]
  • -x is inversely mapped to [a', b']
  • y is inversely mapped to [a', b]
  • -y is inversely mapped to [a, b']
  • a' is a
  • the binary inversion of , b' is the binary inversion of b, and the values of a and b are 0 or 1.
  • level-1/3 is inversely mapped to [0, 0]
  • level-1 is inversely mapped to [1, 0]
  • level-1 is inversely mapped to [0, 1]
  • level 1/3 is inversely mapped is [1, 1].
  • step 902 may include: if the transmission code type is PAM8, the second transmission device inversely maps each level signal in the at least one level signal into three consecutive bits to obtain the second Bit sequence; wherein, each level signal includes one of s, -s, w, -w, z, -z, j, -j; the value set of s, w, z, j is ⁇ 1, 5/7,3/7,1/7 ⁇ , and the values of s, w, z, and j are different from each other; the inverse mapping of s is [a, b, c], and the inverse mapping of -s is [a', b ', c'], w is inversely mapped to [a', b, c], -w is inversely mapped to [a, b', c'], z is inversely mapped to [a, b', c], -z is inversely mapped Mapping is [a', PAM8, the second transmission
  • level 1 is inversely mapped to [0, 0, 0]
  • level-1 is inversely mapped to [1, 1, 1]
  • level 5/7 is inversely mapped to [1, 0, 0]
  • Level-5/7 is inversely mapped to [0, 1, 1]
  • level 3/7 is inversely mapped to [0, 1, 0]
  • level-3/7 is inversely mapped to [1, 0, 1]
  • Level 1/7 is inversely mapped to [0, 0, 1]
  • level -1/7 is inversely mapped to [1, 1, 0].
  • step 902 may include: if the transmission code type is PAM16, the second transmission device inversely maps each level signal in the at least one level signal into four consecutive bits to obtain the second Bit sequence; wherein each level signal includes t, -t, p, -p, v, -v, u, -u, k, -k, i, -i, m, -m, n, -n One of them; the value set of t, p, v, u, k, i, m, n is ⁇ 1, 13/15, 11/15, 9/15, 7/15, 1/3, 1/ 5,1/15 ⁇ , and the values of t, p, v, u, k, i, m, and n are different from each other; the inverse mapping of t is [a, b, c, d], and the inverse mapping of -t is [ a', b', c', d'], p is inverse
  • level 1 is inversely mapped to [0, 0, 0, 0]
  • level-1 is inversely mapped to [1, 1, 1, 1]
  • level 13/15 is inversely mapped to [1, 0, 0, 0], level-13/15 inverse mapping to [0, 1, 1, 1], level 11/15 inverse mapping to [0, 1, 0, 0], level-11/15 inverse mapping is [1, 0, 1, 1]
  • level 9/15 is inversely mapped to [0, 0, 1, 0]
  • level-9/15 is inversely mapped to [1, 1, 0, 1]
  • level 7/15 is inversely mapped to [0, 0, 0, 1]
  • level -7/15 is inversely mapped to [1, 1, 1, 0], and level 1/3 is inversely mapped to [1, 1, 0, 0], level-1/3 is inversely mapped to [0, 0, 1, 1], level 1/5 is inversely mapped to [1, 0, 1, 0], and level-1/5 is inversely mapped to [ 0, 1, 0, 1], level 1/15 is inversely mapped to [1, 0, 0,
  • the second transmission device performs DC balance processing on the second bit sequence to obtain the first bit sequence, where the DC balance processing is included in at least two DC balance modes supported by the first transmission device.
  • the DC balance processing is a pre-configured DC balance mode, or a DC balance mode supported by the second transmission device.
  • step 903 may include: the second transmission device shunts the second bit sequence according to the preset symbol length to obtain M fourth bit sequences, where M is an integer greater than 0; the second The transmission device de-line codes the M fourth bit sequences respectively to obtain M third bit sequences; the second transmission device combines the M third bit sequences according to the first preset length according to the first preset length, Get the first bit sequence.
  • M may be, for example, 1, 2, 3, 4 or other positive integer values, which are not limited herein.
  • the second transmission device divides the second bit sequence according to the preset symbol length, and can obtain 1 fourth bit sequence or 2 fourth bit sequences or 3 fourth bit sequences or 4 fourth bit sequences. etc., there is no restriction here.
  • the second transmission device may divide the second bit sequence into one fourth bit sequence according to the preset symbol length; for PAM4, the second transmission device may follow With a preset symbol length, the second bit sequence is split into two fourth bit sequences; for PAM8, the second transmission device can split the second bit sequence into three fourth bit sequences according to the preset symbol length; for PAM16, The second transmission device may divide the second bit sequence into four fourth bit sequences according to the preset symbol length.
  • each of the M fourth bit sequences has the same length.
  • the length of each fourth bit sequence in the M fourth bit sequences is the same, and it can be understood that the length of each fourth bit sequence in the M fourth bit sequences is a preset symbol length.
  • the second transmission device combines the M third bit sequences according to the first preset length to obtain the first bit sequence, which can be understood as: the second transmission device combines the M third bit sequences according to the first preset length. Combining to obtain the bit sequence encoded according to the preset encoding, or the bit sequence after scrambled, the data to be transmitted is obtained, which is not limited here.
  • P2_2, P2_4, P1_2, P1_4 ⁇ After the two fourth bit sequences are combined according to the first preset length, they may be ⁇ K100_1, K100_2, K100_3, K100_4, K99_1, K99_2, K99_3, K99_4, ..., K2_1, K2_2, K2_3, K2_4, K1_1, K1_2, K1_3, K1_4, P10_1, P10_2, P10_3, P10_4, P9_1, P9_2, P9_3, P9_4, ..., P1_1, P1_2, P1_3, P1_4 ⁇ .
  • the second transmission device obtains multiple bit sequences by splitting the second bit sequence according to the preset symbol length, so that the second transmission device can de-line code the multiple bit sequences respectively,
  • the first bit sequence is obtained by combining the bit sequences after de-line coding, so as to improve the efficiency of de-line coding.
  • step 903 may include: the second transmission device performs precoding and decoding on the second bit sequence to obtain the decoded second bit sequence; the second transmission device performs precoding and decoding on the decoded second bit sequence; Perform de-Gray mapping to obtain the first bit sequence.
  • the second transmission device performs de-Gray mapping on the decoded second bit sequence to obtain the first bit sequence, which can be understood as: the second transmission device performs de-Gray mapping on the decoded second bit sequence to obtain the scrambled second bit sequence. bit sequence.
  • the decoded second bit sequence may be a bit sequence whose code type is PAM4, PAM8 or PAM16.
  • the de-Gray mapping may include: 0 de-Gray mapping to [0,0]; 1 de-Gray mapping to [0,1]; 2 solution Gray map is [1,1]; 3 solution Gray map is [1,0].
  • the de-Gray mapping may include: 0 de-Gray mapping is [0,0,0]; 1 de-Gray mapping is [0,0] ,1]; 2 solution Gray map is [0,1,0]; 3 solution Gray map is [0,1,1]; 4 solution Gray map is [1,0,0]; 5[1,0,1 ] Solution Gray map is; 6 solution Gray map is [1,1,0]; 7 solution Gray map is [1,1,1].
  • the de-Gray mapping may include: 0 de-Gray mapping is [0, 0, 0, 0]; 1 de-Gray mapping is [0 ,0,0,1]; 2 solution Gray mapping is [0,0,1,0]; 3 solution Gray mapping is [0,0,1,1]; 4 solution Gray mapping is [0,1,0, 0]; 5 solution Gray map is [0,1,0,1]; 6 solution Gray map is [0,1,1,0]; 7 solution Gray map is [0,1,1,1]; 8 solution Gray map is [1,0,0,0]; 9 solution Gray map is [1,0,0,1]; 10 solution Gray map is [1,0,1,0]; 11 solution Gray map is [1 ,0,1,1]; 12 solution Gray mapping is [1,1,0,0]; 13 solution Gray mapping is [1,1,0,1]; 14 solution Gray mapping is [1,1,1, 0]; 15 solves the Gray map to [1,1,1,1,
  • the method further includes: the second transmission device may perform an encoding process on the first bit sequence. Decode to obtain effective transmission data.
  • the second transmission device may perform de-RS-FEC processing on the first bit sequence to obtain valid transmission data.
  • the method further includes: the second transmission device may descramble the first bit sequence and then use the depth De-interleaving is performed for L, and then the first bit sequence after de-interleaving is de-coded to obtain effective transmission data.
  • the descrambled bit sequence can be ⁇ K100_1, K100_2, K100_3, K100_4, K99_1, K99_2, K99_3, K99_4, ..., K2_1, K2_2, K2_3, K2_4, K1_1, K1_2, K1_3, K1_4, P10_1, P10_2, P10_3, P10_4, P9_1, P9_2, P9_3, P9_4, ..., P1_1, P1_2, P1_3, P1_4 ⁇ , then, after deinterleaving with a depth of 4, it can be:
  • the second transmission device performs symbol inverse mapping on the level signal from the first transmission device according to the transmission code pattern to obtain a second bit sequence, which is included in the support of the first transmission device.
  • the first DC balance mode among the at least two DC balance modes determines the first bit sequence corresponding to the second bit sequence, thereby avoiding the problem of a single application scenario caused by a single DC balance mode.
  • multiple DC balance methods can be supported on the same device, so that different DC balance requirements can be adapted.
  • the second transmission device can perform symbol inverse mapping on the level signal from the first transmission device according to the transmission code type to obtain the second bit sequence, thereby realizing extended support of multiple transmission code types in the same device. Further, since the same device can be extended to support multiple transmission code types, and symbol inverse mapping can be performed for different transmission code types, module multiplexing is also realized, thereby reducing the cost and power consumption of the product.
  • the solution provided by the present application has been introduced above mainly from the perspective of interaction between various devices. It can be understood that, in order to realize the above-mentioned functions, the above-mentioned implementing devices include corresponding hardware structures and/or software modules for executing the various functions. Those skilled in the art should easily realize that the present application can be implemented in hardware or in the form of a combination of hardware and computer software. Whether a function is performed by hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.
  • the first transmission device or the second transmission device may be divided into functional modules according to the foregoing method examples.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one
  • the above-mentioned integrated modules may be implemented in the form of hardware or in the form of software function modules. It should be noted that, the division of modules in the embodiments of the present application is schematic, and is only a logical function division, and there may be other division manners in actual implementation.
  • FIG. 10 is a schematic structural diagram of a communication device according to an embodiment of the present application.
  • the communication device 1000 can be applied to any of the methods shown in FIG. 5 to FIG. 9 above.
  • the communication device 1000 includes a transceiver module 1001 and a processing module 1002 .
  • the transceiver module 1001 may be a transceiver or a communication interface
  • the processing module 1002 may be one or more processors.
  • the communication apparatus can be used to implement the first transmission device or the second transmission device involved in any of the above method embodiments, or to implement the functions of the devices involved in any of the above method embodiments.
  • the communication apparatus may be a first transmission device or a second transmission device.
  • the first transmission device or the second transmission device may be either a network element in a hardware device, a software function running on dedicated hardware, or a virtualized function instantiated on a platform (eg, a cloud platform).
  • the communication apparatus 1000 may further include a storage module 1003 for storing program codes and data of the communication apparatus 1000 .
  • the communication device 1000 when the communication device is used as a first transmission device or a chip applied in the first transmission device, the communication device 1000 includes a transceiver module 1001 and a processing module 1002, and executes the method described above by the first transmission device. steps to perform.
  • the transceiver module 1001 is used for supporting wired communication with a second transmission device, etc., and specifically performs the sending and/or receiving actions performed by the first transmission device in FIGS. 5-9 , which will not be repeated here.
  • the first transmission device is supported to perform one or more of step 503, step 901, and/or other processes for the techniques described herein.
  • the processing module 1002 may be configured to support the communication apparatus 1000 to perform the processing actions in the foregoing method embodiments, and details are not described herein.
  • the first transmission device is enabled to perform one or more of steps 501, 502, and/or other processes for the techniques described herein.
  • the processing module 1002 is configured to perform DC balance processing on the first bit sequence to obtain a second bit sequence; the processing module 1002 is configured to perform symbol mapping on the second bit sequence according to the transmission code pattern to obtain at least one electrical signal. level signal; the transceiver module 1001 is used for sending at least one level signal.
  • the communication device 1000 when the communication device is used as a second transmission device or a chip applied in the second transmission device, the communication device 1000 includes a transceiver module 1001 and a processing module 1002, and executes the method described above by the second transmission device. steps to perform.
  • the transceiver module 1001 is used for supporting wired communication with a second transmission device, etc., and specifically performs the sending and/or receiving actions performed by the second transmission device in FIGS. 5-9 , which will not be repeated here.
  • the processing module 1002 may be configured to support the communication apparatus 1000 to perform the processing actions in the foregoing method embodiments, and details are not described herein.
  • the second transmission device is enabled to perform one or more of steps 902, 903, and/or other processes for the techniques described herein.
  • the transceiver module is used to receive at least one level signal; the processing module is used to perform symbol inverse mapping on the at least one level signal according to the transmission code pattern to obtain a second bit sequence; The two-bit sequence is subjected to DC balance processing to obtain a first bit sequence, and the DC balance processing is included in at least two DC balance modes supported by the first transmission device.
  • the transceiver module 1001 may be an interface, a pin, a circuit, or the like.
  • the interface can be used to input data to be processed to the processor, and can output the processing result of the processor to the outside.
  • the interface can be a general purpose input output (GPIO) interface, which can communicate with multiple peripheral devices (such as a display (LCD), a camera (camara), a radio frequency (RF) module, an antenna, etc. )connect.
  • GPIO general purpose input output
  • peripheral devices such as a display (LCD), a camera (camara), a radio frequency (RF) module, an antenna, etc.
  • the interface is connected to the processor through a bus.
  • the processing module 1002 may be a processor, and the processor may execute computer-executable instructions stored in the memory module, so that the chip executes the methods involved in the embodiments of FIGS. 5-9 .
  • the processor may include a controller, an arithmetic unit and a register.
  • the controller is mainly responsible for instruction decoding, and sends control signals for operations corresponding to the instructions.
  • the arithmetic unit is mainly responsible for performing fixed-point or floating-point arithmetic operations, shift operations, and logical operations, and can also perform address operations and conversions.
  • Registers are mainly responsible for saving register operands and intermediate operation results temporarily stored during instruction execution.
  • the hardware architecture of the processor may be an application specific integrated circuits (ASIC) architecture, a microprocessor without interlocked piped stages architecture (MIPS) architecture, advanced reduced instructions Set machine (advanced RISC machines, ARM) architecture or network processor (network processor, NP) architecture and so on.
  • ASIC application specific integrated circuits
  • MIPS microprocessor without interlocked piped stages architecture
  • ARM advanced reduced instructions Set machine
  • NP network processor
  • the storage module 1003 may be a storage module in the chip, such as a register, a cache, and the like.
  • the storage module can also be a storage module located outside the chip, such as read only memory (Read Only Memory, ROM) or other types of static storage devices that can store static information and instructions, random access memory (Random Access Memory, RAM), etc. .
  • Read Only Memory ROM
  • RAM random access memory
  • processors and the interface can be implemented by hardware design, software design, or a combination of software and hardware, which is not limited here.
  • the present application also provides a communication device, including a memory and a processor, the memory is used for storing computer-executed instructions, the processor is used for executing the computer-executed instructions stored in the memory, and the execution of the computer-executed instructions stored in the memory causes the processor to execute the 5-FIG. 9
  • a communication device including a memory and a processor, the memory is used for storing computer-executed instructions, the processor is used for executing the computer-executed instructions stored in the memory, and the execution of the computer-executed instructions stored in the memory causes the processor to execute the 5-FIG. 9
  • the method in any possible implementation.
  • the present application also provides another communication device, including a memory and a communication interface, the communication interface is used for inputting and/or outputting information, and the processor is used for executing a computer program, so that the device executes any of the possible implementations in FIGS. 5 to 9 . Methods.
  • the present application also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a computer, enables the computer to implement the method in any of the possible implementation manners as shown in FIG. 5 to FIG. 9 .
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated units are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium.
  • the technical solutions of the present application are essentially or part of contributions to the prior art, or all or part of the technical solutions can be embodied in the form of software products, and the computer software products are stored in a storage medium , including several instructions to cause a computer device (which may be a personal computer, a cloud server, or a network device, etc.) to execute all or part of the steps of the above methods in the various embodiments of the present application.
  • a computer device which may be a personal computer, a cloud server, or a network device, etc.
  • the aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .
  • U disk mobile hard disk
  • Read-Only Memory ROM, Read-Only Memory
  • RAM Random Access Memory
  • magnetic disk or optical disk and other media that can store program codes .

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Abstract

本申请提供了一种数据处理方法及相关装置，该方法应用于第一传输设备，所述第一传输设备支持至少两种直流平衡方式，该方法包括：对第一比特序列进行直流平衡处理，得到第二比特序列；根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号；发送所述至少一个电平信号。实施本申请实施例，避免了单一的直流平衡方式所导致的应用场景单一的问题。

Description

一种数据处理方法及相关装置 技术领域
本申请涉及串行解串器数据传输领域，尤其涉及一种数据处理方法及相关装置。
背景技术
在串行解串器(serializer deserializer，SerDes)传输领域，大多数高速串行链路交流(alternating current，AC)耦合工作，即发射机(又可以称为串行器(serializer，SER))和接收机(又可以称为解串器(deserializer，DES))之间的路径采用隔直流电容器(DC-blocking capactitor)，以平衡该路径所传输的比特序列。图1为一种直流失衡的示意图，如图1所示，直流失衡(连续的0或者连续的1，图1中仅示出连续的1)，经过隔直流电容器后，共模电压持续向一个方向偏移，导致解调判决错误。而为了避免解调判决错误，现有SerDes系统往往只提供单一的直流平衡方式，来实现直流平衡，由此导致其无法适配更多的直流平衡应用场景。
发明内容
本申请实施例提供了一种数据处理方法及相关装置，实施本申请实施例，避免了单一的直流平衡方式所导致的应用场景单一的问题。
第一方面，提供一种数据处理方法，所述方法应用于第一传输设备，所述第一传输设备支持至少两种直流平衡方式，所述方法包括：
对第一比特序列进行直流平衡处理，得到第二比特序列；
根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号；
发送所述至少一个电平信号。
可以看出，上述技术方案中，第一传输设备通过采用其所支持的至少两种直流平衡方式中的一种直流平衡方式对第一比特序列进行直流平衡处理，从而避免了单一的直流平衡方式所导致的应用场景单一的问题。同时，在同一设备上可以支持多种直流平衡方式，从而可以适配不同的直流平衡需求。另外，第一传输设备可以根据传输码型，对比特序列进行符号映射，得到电平信号，从而实现了在同一设备扩展支持多种传输码型。进一步的，由于在同一设备可以扩展支持多种传输码型，且针对不同传输码型可以进行符号映射，也实现了模块复用，进而降低了产品的成本和功耗。
可选的，所述对第一比特序列进行直流平衡处理，得到第二比特序列，包括：
按照第一预设长度，将所述第一比特序列分流为M个第三比特序列，其中，所述M为大于0的整数；
分别对所述M个第三比特序列进行线路编码，得到M个第四比特序列；
按照预设符号长度对所述M个第四比特序列进行比特合并，得到所述第二比特序列。
可以看出，上述技术方案中，第一传输设备按照第一预设长度，将第一比特序列分流为多个比特序列，从而可以分别对多个比特序列进行线路编码，得到编码后的多个比特序列，从而提高了线路编码的效率。同时，第一传输设备按照预设符号长度对编码后的多个 比特序列进行比特合并，后续以特定的电平符号映射后传输，从而实现多种传输码型下的直流平衡。
可选的，所述对第一比特序列进行直流平衡处理，得到第二比特序列，包括：
对所述第一比特序列进行格雷映射，得到格雷映射后的第一比特序列；
对所述格雷映射后的第一比特序列进行预编码，得到所述第二比特序列。
可以看出，上述技术方案中，第一传输设备可以对第一比特序列依次进行格雷映射、预编码，从而实现了在同一设备上对第一比特序列进行又一种直流平衡处理，避免了单一的直流平衡方式所导致的应用场景单一的问题，从而可以适配更多场景和环境的应用。
可选的，所述第一比特序列为加扰后的比特序列。
可选的，所述加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，所述L为大于或等于1的整数。
可选的，所述第二预设长度为里德所罗门(reed-solomon，RS)符号的整数倍。
可选的，所述L为M的整数倍。
可选的，若M为1，所述传输码型为非归零调制NRZ，或，2阶脉冲幅度调制(2-level pulse amplitude modulation，PAM2)；
若M为2，所述传输码型为4阶脉冲幅度调制(4-level PAM，PAM4)；
若M为3，所述传输码型为8阶脉冲幅度调制(8-level PAM，PAM8)；
若M为4，所述传输码型为16阶脉冲幅度调制(16-level PAM，PAM16)。
可选的，所述第一预设长度为所述预设符号长度的整数倍，所述预设符号长度根据所述线路编码确定。
可选的，若所述线路编码为8B/10B，则所述预设符号长度为8比特；
若所述线路编码为9B/10B，则所述预设符号长度为9比特。
可选的，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
若所述传输码型为所述NRZ或所述PAM2，则将所述第二比特序列中一个比特映射为一个电平信号，得到所述至少一个电平信号。
可以看出，上述技术方案中，通过将比特序列映射为双电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
可选的，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
若所述传输码型为所述PAM4，则将所述第二比特序列中每两个连续比特映射为一个电平信号，得到所述至少一个电平信号；
其中，所述每两个连续比特包括[a，b]、[a’，b’]、[a’，b]、[a，b’]中的一种；所述[a，b]映射为x，所述[a’，b’]映射为-x，所述[a’，b]映射为y，所述[a，b’]映射为-y；所述a’为所述a的二进制取反，所述b’为所述b的二进制取反，所述a和所述b的取值为0或1，所述x和所述y的取值集合为{1，1/3}，且所述x和所述y取值不同。
可以看出，上述技术方案中，通过将比特序列映射为多电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
可选的，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
若所述传输码型为所述PAM8，则将所述第二比特序列中每三个连续比特映射为一个电平信号，得到所述至少一个电平信号；
其中，所述每三个连续比特包括[a，b，c]、[a’，b’，c’]、[a’，b，c]、[a，b’，c’]、[a，b’，c]、[a’，b，c’]、[a，b，c’]、[a’，b’，c]中的一种；所述[a，b，c]映射为s，所述[a’，b’，c’]映射为-s，所述[a’，b，c]映射为w，所述[a，b’，c’]映射为-w，所述[a，b’，c]映射为z，所述[a’，b，c’]映射为-z，所述[a，b，c’]映射为j，所述[a’，b’，c]映射为-j；所述a’、所述b’、所述c’分别为所述a、所述b、所述c的二进制取反，所述a、所述b、所述c的取值为0或1，所述s、所述w、所述z、所述j的取值集合为{1,5/7,3/7,1/7}，且所述s、所述w、所述z、所述j的取值互不相同。
可以看出，上述技术方案中，通过将比特序列映射为多电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
可选的，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
若所述传输码型为所述PAM16，则将所述第二比特序列中每四个连续比特映射为一个电平信号，得到所述至少一个电平信号；
其中，所述每四个连续比特包括：[a，b，c，d]、[a’，b’，c’，d’]、[a’，b，c，d]、[a，b’，c’，d’]、[a，b’，c，d]、[a’，b，c’，d’]、[a，b，c’，d]、[a’，b’，c，d’]、[a，b，c，d’]、[a’，b’，c’，d]、[a’，b’，c，d]、[a，b，c’，d’]、[a’，b，c’，d]、[a，b’，c，d’]、[a’，b，c，d’]、[a，b’，c’，d]中的一种；
所述[a，b，c，d]映射为t，所述[a’，b’，c’，d’]映射为-t，所述[a’，b，c，d]映射为p，所述[a，b’，c’，d’]映射为-p，所述[a，b’，c，d]映射为v，所述[a’，b，c’，d’]映射为-v，所述[a，b，c’，d]映射为u，所述[a’，b’，c，d’]映射为-u，所述[a，b，c，d’]映射为k，所述[a’，b’，c’，d]映射为-k，所述[a’，b’，c，d]映射为i，所述[a，b，c’，d’]映射为-i，所述[a’，b，c’，d]映射为m，所述[a，b’，c，d’]映射为-m，所述[a’，b，c，d’]映射为n，所述[a，b’，c’，d]映射为-n；
所述a’、所述b’、所述c’、所述d’分别为所述a、所述b、所述c、所述d的二进制取反，所述a、所述b、所述c、所述d的取值为0或1，所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值互不相同。
可以看出，上述技术方案中，通过将比特序列映射为多电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
可选的，所述直流平衡处理为预先配置的直流平衡方式，或，根据接收到的指示信息确定的直流平衡方式，所述指示信息是所述第二传输设备发送的。
第二方面，提供一种数据处理方法，所述方法应用于第二传输设备，所述方法包括：
接收至少一个电平信号；
根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列；
对所述第二比特序列进行解直流平衡处理，得到第一比特序列，所述直流平衡处理包含在所述第一传输设备支持的至少两种直流平衡方式中。
可以看出，上述技术方案中，第二传输设备通过根据传输码型，对电平信号进行符号逆映射，得到第二比特序列，以对第二比特序列进行解直流平衡处理，得到第一比特序列，从而避免了单一的直流平衡方式所导致的应用场景单一的问题。同时，在同一设备上可以支持多种直流平衡方式，从而可以适配不同的直流平衡需求。另外，第二传输设备可以根据传输码型，对来自第一传输设备的电平信号进行符号逆映射，得到第二比特序列，从而实现了在同一设备扩展支持多种传输码型。进一步的，由于在同一设备可以扩展支持多种传输码型，且针对不同传输码型可以进行符号逆映射，也实现了模块复用，进而降低了产品的成本和功耗。
可选的，所述对所述第二比特序列进行解直流平衡处理，得到第一比特序列，包括：
按照预设符号长度对所述第二比特序列进行分流，得到M个第四比特序列，其中，所述M为大于0的整数；
分别对所述M个第四比特序列进行解线路编码，得到M个第三比特序列；
将所述M个第三比特序列按照第一预设长度进行合并，得到所述第一比特序列。
可以看出，上述技术方案中，第二传输设备通过按照预设符号长度对第二比特序列进行分流得到多个比特序列，从而使得第二传输设备可以分别对多个比特序列进行解线路编码，以对解线路编码后的比特序列进行合并，进而得到第一比特序列，提高了解线路编码的效率。
可选的，所述对所述第二比特序列进行解直流平衡处理，得到第一比特序列，包括：
对所述第二比特序列进行预编码解码，得到解码后的第二比特序列；
对所述解码后的第二比特序列进行解格雷映射，得到所述第一比特序列。
可选的，所述第一比特序列为加扰后的比特序列。
可选的，所述加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，所述L为大于或等于1的整数。
可选的，所述第二预设长度为里德所罗门RS符号的整数倍。
可选的，所述L为M的整数倍。
可选的，若M为1，所述传输码型为非归零调制NRZ，或，2阶脉冲幅度调制PAM2；
若M为2，所述传输码型为4阶脉冲幅度调制PAM4；
若M为3，所述传输码型为8阶脉冲幅度调制PAM8；
若M为4，所述传输码型为16阶脉冲幅度调制PAM16。
可选的，所述第一预设长度为所述预设符号长度的整数倍，所述预设符号长度根据所述线路编码确定。
可选的，若所述线路编码为8B/10B，则所述预设符号长度为8比特；
若所述线路编码为9B/10B，则所述预设符号长度为9比特。
可选的，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
若所述传输码型为所述NRZ或所述PAM2，则将所述至少一个电平信号中的一个电平 信号逆映射为一个比特，得到所述第二比特序列。
可以看出，上述技术方案中，通过将比特序列映射为双电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
可选的，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
若所述传输码型为所述PAM4，则将所述至少一个电平信号中每个电平信号逆映射为两个连续的比特，得到所述第二比特序列；
其中，所述每个电平信号包括x、y、-x、-y中的一种；所述x和所述y的取值集合为{1，1/3}，且所述x和所述y取值不同；
所述x逆映射为[a，b]，所述-x逆映射为[a’，b’]，所述y逆映射为[a’，b]，所述-y逆映射为[a，b’]；所述a’为所述a的二进制取反，所述b’为所述b的二进制取反，所述a和所述b的取值为0或1。
可以看出，上述技术方案中，通过将比特序列映射为多电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
可选的，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
若所述传输码型为所述PAM8，则将所述至少一个电平信号中每个电平信号逆映射为三个连续的比特，得到所述第二比特序列；
其中，所述每个电平信号包括s、-s、w、-w、z、-z、j、-j中的一种；所述s、所述w、所述z、所述j的取值集合为{1,5/7,3/7,1/7}，且所述s、所述w、所述z、所述j的取值互不相同；
所述s逆映射为[a，b，c]，所述-s逆映射为[a’，b’，c’]，所述w逆映射为[a’，b，c]，所述-w逆映射为[a，b’，c’]，所述z逆映射为[a，b’，c]，所述-z逆映射为[a’，b，c’]，所述j逆映射为[a，b，c’]，所述-j逆映射为[a’，b’，c]；所述a’、所述b’、所述c’分别为所述a、所述b、所述c的二进制取反，所述a、所述b、所述c的取值为0或1。
可以看出，上述技术方案中，通过将比特序列映射为多电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
可选的，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
若所述传输码型为所述PAM16，则将所述至少一个电平信号中每个电平信号逆映射为四个连续的比特，得到所述第二比特序列；
其中，所述每个电平信号包括t、-t、p、-p、v、-v、u、-u、k、-k、i、-i、m、-m、n、-n中的一种；所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值互不相同；
所述t逆映射为[a，b，c，d]，所述-t逆映射为[a’，b’，c’，d’]，所述p逆映射为[a’，b，c，d]，所述-p逆映射为[a，b’，c’，d’]，所述v逆映射为[a，b’，c，d]，所述-v逆映射为[a’，b，c’，d’]，所述u逆映射为[a，b，c’，d]，所述-u逆映射为[a’，b’，c，d’]， 所述k逆映射为[a，b，c，d’]，所述-k逆映射为[a’，b’，c’，d]，所述i逆映射为[a’，b’，c，d]，所述-i逆映射为[a，b，c’，d’]，所述m逆映射为[a’，b，c’，d]，所述-m逆映射为[a，b’，c，d’]，所述n逆映射为[a’，b，c，d’]，所述-n逆映射为[a，b’，c’，d]；所述a’、所述b’、所述c’、所述d’分别为所述a、所述b、所述c、所述d的二进制取反，所述a、所述b、所述c、所述d的取值为0或1。
可以看出，上述技术方案中，通过将比特序列映射为多电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
可选的，所述直流平衡处理为预先配置的直流平衡方式，或，第二传输设备所支持的直流平衡方式。
第三方面，提供一种第一传输设备，所述第一传输设备支持至少两种直流平衡方式，所述第一传输设备包括处理模块和收发模块；
所述处理模块，用于对第一比特序列进行直流平衡处理，得到第二比特序列；
所述处理模块，还用于根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号；
所述收发模块，用于发送所述至少一个电平信号。
可选的，在对第一比特序列进行直流平衡处理，得到第二比特序列时，所述处理模块，用于：
按照第一预设长度，将所述第一比特序列分流为M个第三比特序列，其中，所述M为大于0的整数；
分别对所述M个第三比特序列进行线路编码，得到M个第四比特序列；
按照预设符号长度对所述M个第四比特序列进行比特合并，得到所述第二比特序列。
可选的，在对第一比特序列进行直流平衡处理，得到第二比特序列时，所述处理模块，用于：
对所述第一比特序列进行格雷映射，得到格雷映射后的第一比特序列；
对所述格雷映射后的第一比特序列进行预编码，得到所述第二比特序列。
可选的，所述第一比特序列为加扰后的比特序列。
可选的，所述加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，所述L为大于或等于1的整数。
可选的，所述第二预设长度为里德所罗门RS符号的整数倍。
可选的，所述L为M的整数倍。
可选的，若M为1，所述传输码型为非归零调制NRZ，或，2阶脉冲幅度调制PAM2；
若M为2，所述传输码型为4阶脉冲幅度调制PAM4；
若M为3，所述传输码型为8阶脉冲幅度调制PAM8；
若M为4，所述传输码型为16阶脉冲幅度调制PAM16。
可选的，所述第一预设长度为所述预设符号长度的整数倍，所述预设符号长度根据所述线路编码确定。
可选的，若所述线路编码为8B/10B，则所述预设符号长度为8比特；
若所述线路编码为9B/10B，则所述预设符号长度为9比特。
可选的，在根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号时，所述处理模块，用于：
若所述传输码型为所述NRZ或所述PAM2，则将所述第二比特序列中一个比特映射为一个电平信号，得到所述至少一个电平信号。
可选的，在根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号时，所述处理模块，用于：
若所述传输码型为所述PAM4，则将所述第二比特序列中每两个连续比特映射为一个电平信号，得到所述至少一个电平信号；
其中，所述每两个连续比特包括[a，b]、[a’，b’]、[a’，b]、[a，b’]中的一种；所述[a，b]映射为x，所述[a’，b’]映射为-x，所述[a’，b]映射为y，所述[a，b’]映射为-y；所述a’为所述a的二进制取反，所述b’为所述b的二进制取反，所述a和所述b的取值为0或1，所述x和所述y的取值集合为{1，1/3}，且所述x和所述y取值不同。
可选的，在根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号时，所述处理模块，用于：
若所述传输码型为所述PAM8，则将所述第二比特序列中每三个连续比特映射为一个电平信号，得到所述至少一个电平信号；
其中，所述每三个连续比特包括[a，b，c]、[a’，b’，c’]、[a’，b，c]、[a，b’，c’]、[a，b’，c]、[a’，b，c’]、[a，b，c’]、[a’，b’，c]中的一种；所述[a，b，c]映射为s，所述[a’，b’，c’]映射为-s，所述[a’，b，c]映射为w，所述[a，b’，c’]映射为-w，所述[a，b’，c]映射为z，所述[a’，b，c’]映射为-z，所述[a，b，c’]映射为j，所述[a’，b’，c]映射为-j；所述a’、所述b’、所述c’分别为所述a、所述b、所述c的二进制取反，所述a、所述b、所述c的取值为0或1，所述s、所述w、所述z、所述j的取值集合为{1,5/7,3/7,1/7}，且所述s、所述w、所述z、所述j的取值互不相同。
可选的，在根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号时，所述处理模块，用于：
若所述传输码型为所述PAM16，则将所述第二比特序列中每四个连续比特映射为一个电平信号，得到所述至少一个电平信号；
其中，所述每四个连续比特包括[a，b，c，d]、[a’，b’，c’，d’]、[a’，b，c，d]、[a，b’，c’，d’]、[a，b’，c，d]、[a’，b，c’，d’]、[a，b，c’，d]、[a’，b’，c，d’]、[a，b，c，d’]、[a’，b’，c’，d]、[a’，b’，c，d]、[a，b，c’，d’]、[a’，b，c’，d]、[a，b’，c，d’]、[a’，b，c，d’]、[a，b’，c’，d]中的一种；
所述[a，b，c，d]映射为t，所述[a’，b’，c’，d’]映射为-t，所述[a’，b，c，d]映射为p，所述[a，b’，c’，d’]映射为-p，所述[a，b’，c，d]映射为v，所述[a’，b，c’，d’]映射为-v，所述[a，b，c’，d]映射为u，所述[a’，b’，c，d’]映射为-u，所述[a，b，c，d’]映射为k，所述[a’，b’，c’，d]映射为-k，所述[a’，b’，c，d]映射为i，所述[a，b，c’，d’]映射为-i，所述[a’，b，c’，d]映射为m，所述[a，b’，c，d’]映射为-m，所述[a’，b，c，d’]映射为n，所述[a，b’，c’，d]映射为-n；
所述a’、所述b’、所述c’、所述d’分别为所述a、所述b、所述c、所述d的二进制取反，所述a、所述b、所述c、所述d的取值为0或1，所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值互不相同。
可选的，所述直流平衡处理为预先配置的直流平衡方式，或，根据接收到的指示信息确定的直流平衡方式，所述指示信息是所述第二传输设备发送的。
第四方面，提供一种第二传输设备，所述第二传输设备包括收发模块和处理模块，
所述收发模块，用于接收至少一个电平信号；
所述处理模块，用于根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列；
所述处理模块，还用于对所述第二比特序列进行解直流平衡处理，得到第一比特序列，所述直流平衡处理包含在第一传输设备支持的至少两种直流平衡方式中。
可选的，在对所述第二比特序列进行解直流平衡处理，得到第一比特序列时，所述处理模块，用于：
按照预设符号长度对所述第二比特序列进行分流，得到M个第四比特序列，其中，所述M为大于0的整数；
分别对所述M个第四比特序列进行解线路编码，得到M个第三比特序列；
将所述M个第三比特序列按照第一预设长度进行合并，得到所述第一比特序列。
可选的，在对所述第二比特序列进行解直流平衡处理，得到第一比特序列时，所述处理模块，用于：
对所述第二比特序列进行预编码解码，得到解码后的第二比特序列；
对所述解码后的第二比特序列进行解格雷映射，得到所述第一比特序列。
可选的，所述第一比特序列为加扰后的比特序列。
可选的，所述加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，所述L为大于或等于1的整数。
可选的，所述第二预设长度为里德所罗门RS符号的整数倍。
可选的，所述L为M的整数倍。
可选的，若M为1，所述传输码型为非归零调制NRZ，或，2阶脉冲幅度调制PAM2；
若M为2，所述传输码型为4阶脉冲幅度调制PAM4；
若M为3，所述传输码型为8阶脉冲幅度调制PAM8；
若M为4，所述传输码型为16阶脉冲幅度调制PAM16。
可选的，所述第一预设长度为所述预设符号长度的整数倍，所述预设符号长度根据所述线路编码确定。
可选的，若所述线路编码为8B/10B，则所述预设符号长度为8比特；
若所述线路编码为9B/10B，则所述预设符号长度为9比特。
可选的，在根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列时，所述处理模块，用于：
若所述传输码型为所述NRZ或所述PAM2，则将所述至少一个电平信号中每个电平信号逆映射为一个比特，得到所述第二比特序列。
可选的，在根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列时，所述处理模块，用于：
若所述传输码型为所述PAM4，则将所述至少一个电平信号中每个电平信号逆映射为两个连续的比特，得到所述第二比特序列；
其中，所述每个电平信号包括x、y、-x、-y中的一种；所述x和所述y的取值集合为{1，1/3}，且所述x和所述y取值不同；
所述x逆映射为[a，b]，所述-x逆映射为[a’，b’]，所述y逆映射为[a’，b]，所述-y逆映射为[a，b’]；所述a’为所述a的二进制取反，所述b’为所述b的二进制取反，所述a和所述b的取值为0或1。
可选的，在根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列时，所述处理模块，用于：
若所述传输码型为所述PAM8，则将所述至少一个电平信号中每个电平信号逆映射为三个连续的比特，得到所述第二比特序列；
其中，所述每个电平信号包括s、-s、w、-w、z、-z、j、-j中的一种；所述s、所述w、所述z、所述j的取值集合为{1,5/7,3/7,1/7}，且所述s、所述w、所述z、所述j的取值互不相同；
所述s逆映射为[a，b，c]，所述-s逆映射为[a’，b’，c’]，所述w逆映射为[a’，b，c]，所述-w逆映射为[a，b’，c’]，所述z逆映射为[a，b’，c]，所述-z逆映射为[a’，b，c’]，所述j逆映射为[a，b，c’]，所述-j逆映射为[a’，b’，c]；所述a’、所述b’、所述c’分别为所述a、所述b、所述c的二进制取反，所述a、所述b、所述c的取值为0或1。
可选的，在根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列时，所述处理模块，用于：
若所述传输码型为所述PAM16，则将所述至少一个电平信号中每个电平信号逆映射为四个连续的比特，得到所述第二比特序列；
其中，所述每个电平信号包括t、-t、p、-p、v、-v、u、-u、k、-k、i、-i、m、-m、n、-n中的一种；所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值互不相同；
所述t逆映射为[a，b，c，d]，所述-t逆映射为[a’，b’，c’，d’]，所述p逆映射为[a’，b，c，d]，所述-p逆映射为[a，b’，c’，d’]，所述v逆映射为[a，b’，c，d]，所述-v逆映射为[a’，b，c’，d’]，所述u逆映射为[a，b，c’，d]，所述-u逆映射为[a’，b’，c，d’]，所述k逆映射为[a，b，c，d’]，所述-k逆映射为[a’，b’，c’，d]，所述i逆映射为[a’，b’，c，d]，所述-i逆映射为[a，b，c’，d’]，所述m逆映射为[a’，b，c’，d]，所述-m逆映射为[a，b’，c，d’]，所述n逆映射为[a’，b，c，d’]，所述-n逆映射为[a，b’，c’，d]；所述a’、所述b’、所述c’、所述d’分别为所述a、所述b、所述c、所述d的二进制取反，所述a、所述b、所述c、所述d的取值为0或1。
可选的，所述直流平衡处理为预先配置的直流平衡方式，或，第二传输设备所支持的直流平衡方式。
第五方面，提供一种通信装置，包括处理器和存储器，所述处理器调用所述存储器中存储的计算机程序实现如第一方面或第二方面任一项所述的方法。
可选的，所述通信装置还包括输入接口和输出接口，所述输入接口用于接收来自所述通信装置之外的其它通信装置的信息，所述输出接口用于向所述通信装置之外的其它通信装置输出信息。
在一种可能的实施方式中，该通信装置可以是实现第一方面或第二方面中方法的芯片或者包含芯片的设备。
第六方面，提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，当所述计算机程序被运行时，实现如第一方面或第二方面任一项所述的方法。
第七方面，提供一种计算机程序产品，当计算机读取并执行所述计算机程序产品时，使得计算机执行实现如第一方面或第二方面任一项所述的方法。
第八方面，提供一种通信系统，包括上述第一传输设备，和/或，第二传输设备。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
其中：
图1为一种直流失衡的示意图；
图2为一种自循环加扰的示意图；
图3为本申请实施例提供的通信系统的基础架构；
图4为本申请实施例提供的通信装置的硬件结构示意图；
图5为本申请实施例提供的一种数据处理方法的流程示意图；
图6为本申请实施例提供的一种双电平码型符号映射示意图；
图7为本申请实施例提供的一种数据处理方法的流程示意图；
图8为本申请实施例提供的一种数据处理方法的流程示意图；
图9为本申请实施例提供的一种数据处理方法的流程示意图；
图10为本申请实施例提供的一种通信装置的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
需要理解的是，本申请实施例中的术语“系统”和“网络”可被互换使用。“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一种(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一种(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。以及，除非有相反的说明，本申请实施例提及“第一”、“第二”等序数词是用于对多个对象进行区分，不用于限定多个对象的顺序、时序、优先级或者重要程度。
在本申请实施例中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
下面对本申请所涉及到的一些部分名词进行解释说明。
1.串行器/解串器
串行器/解串器是高速数据通信中的接口电路，应用于点对点串行通信中。在发送端设备(第一传输设备)多路低速并行的信号被串行器转换成高速串行的信号，经过传输媒体(如线缆等)，发送至接收端设备(第二传输设备)。在接收端设备(第二传输设备)高速串行的信号被解串器重新转换成低速并行的信号。这种点对点的串行通信技术充分利用传输媒体的信道容量，减少所需的传输信道和器件引脚数目，从而大大的降低通信成本。
2.车载图像传感器
车载图像传感器例如可以包括摄像头传感器(也可以称为是感光元件)或雷达(Radar)等。
其中，摄像头传感器包括多个感光点，每个感光点感应光信号，将光信号转换为电信号。
其中，雷达：或称为雷达装置，也可以称为探测器或者探测装置。其工作原理是通过发射信号(或者称为探测信号)，并接收经过目标物体反射的反射信号，来探测相应的目标物体。在本申请中，雷达例如可以为激光雷达、超声波雷达、毫米波雷达或其他雷达，在此不做限制。
3.传输码型
传输码型可以包括双电平码型、多电平码型等，在此不做限制。
其中，双电平码型例如可以包括非归零调制(non-return zero，NRZ)、2阶脉冲幅度调制PAM2或其他码型等，在此不做限制。
其中，多电平码型例如可以包括4阶脉冲幅度调制(4-level PAM，PAM4)、8阶脉冲 幅度调制(8-level PAM，PAM8)、16阶脉冲幅度调制(16-level PAM，PAM16)或其他码型，在此不做限制。
可以理解的，传输码型例如可以包括以下一种：NRZ、PAM2、PAM4、PAM8、PAM16等，在此不做限制。
为了便于理解本申请，在此介绍本申请实施例涉及的相关技术知识。
目前，在SerDes传输领域，一般只支持单一的直流平衡方式。如针对双电平(非归零调制或脉冲幅度调制)SerDes系统，一般可以采用线路编码(如8B/10B、9B/10B)实现直流平衡；针对多电平(PAM4、PAM8)等SerDes系统，一般可以采用伪随机扰码实现直流平衡。
示例性的，例如将输入8比特(bit)(ABCDEFGH)分为5bit(ABCDE)和3bit(FGH)两部分，分别通过下面表1中5B/6B的映射表和表2中3B/4B的映射表处理后，可以得到10bit输出(ABCDEFGH->abcdeifghj)。若前一个8b/10b的不平衡(runningdisparity，RD)为RD-(即0比1的个数多)，则下一个8b/10b应映射为RD+(即0比1的个数少)的序列，从而实现直流平衡。比如，在时刻1输入第一个8比特，在时刻2输入第二个8比特，在时刻3输入第三个8比特。其中，时刻1早于时刻2，时刻2早于时刻3，如时刻1为9点，时刻2为9点01分20秒，时刻3为9点01分55秒。结合表1和表2，假设第一个8比特00000000，经过8b/10b后映射为1001111011，其RD为-。其中，100111为表1中D.00对应的RD＝-1时的序列，1011为表2中D.x.0对应的RD＝-1时的序列。假设第二个8比特00000000，经过8b/10b后映射为0110000100，其中，011000为表1中D.00对应的RD＝+1时的序列，0100为表2中D.x.0对应的RD＝+1时的序列。假设第三个8比特00000000，经过8b/10b后映射为1001111011，其中，100111为表1中D.00对应的RD＝-1时的序列，1011为表2中D.x.0对应的RD＝-1时的序列。综上可以看出，第一个8b/10b编码输出的序列其RD为-，第二个8b/10b编码输出的序列其RD为+，第三个8b/10b编码输出的序列其RD为-。即相邻时刻的8b/10b编码输出的序列，其RD出现+/-交替，因此实现了直流平衡。
表1：5B/6B的映射表
Figure PCTCN2021080883-appb-000001
Figure PCTCN2021080883-appb-000002
表2：3B/4B的映射表
Figure PCTCN2021080883-appb-000003
示例性的，参见图2，图2为一种自循环加扰的示意图。结合图2，可以看出，其涉及到15个抽头，15个抽头的初始值非全零(15个抽头的初始化同步种子非全零)，即，抽头1、抽头4、抽头6、抽头8的初始值为1，其余抽头的初始值为0。在每个处理周期，抽头N-1的值传递给抽头N，抽头14和抽头15的值进行异或处理后，传递给抽头1，从而形成了自循环。其中，N为大于或等于2，且小于或等于15的整数。另外，抽头14和抽头15的值进行异或处理后，可以与从(IN)中输入的数据进行异或处理，以得到加扰后的数据。可以理解的，加扰后的数据即为从(OUT)中输出的数据。
综上所述，现有SerDes系统往往只提供单一的直流平衡方式，来实现直流平衡。这导致其无法适配更多的直流平衡应用场景。
基于此，本申请实施例提出一种数据处理方法以解决上述问题，下面对本申请实施例进行详细介绍。
应理解，本申请实施例的技术方案可以应用于SerDes等有线传输场景，如摄像头到移动数据中心(mobile data center，MDC)(MDC主要负责具备高级辅助驾驶或自动驾驶功能相关的计算和数据存储)的传输场景，驾驶舱控制器(cockpit domain controller，CDC)(CDC主要控制座舱智能娱乐)到图像输出装置的传输场景。其中，图像输出装置例如可以为显示屏等，显示屏例如可以为车载大屏等，在此不做限制。
下面介绍本申请实施例提供的通信系统的基础架构。参见图3，图3为本申请实施例提供的通信系统的基础架构。如图3所示，该通信系统可以包括第一传输设备10以及与第一传输设备20进行有线通信的第二传输设备20。需要说明的是，本申请中的第一传输设备和第二传输设备同时支持数据的发送和接收，为了方便描述，将发送数据为主的设备称 为第一传输设备，将接收数据为主的设备称为第二传输设备。图3仅为示意图，并不构成对本申请提供的技术方案的适用场景的限定。
其中，第一传输设备10和第二传输设备20可以为两个独立的设备，或同一设备中不同的器件，在此不做限制。
示例性的，第一传输设备10例如可以为摄像头(如车载摄像头)、车载毫米波雷达、激光雷达、车载通信盒(TelematicsBOX，T-Box)等，第二传输设备20例如可以为车载高性能计算平台(high-performance computing platform，HCP)设备或其它车载计算设备等，在此不做限制。其中，HCP设备例如可以包括MDC设备或CDC设备，在此不做限制。
又示例性的，第一传输设备10或第二传输设备20例如可以为蜂窝电话(cellular phone)、智能电话(smart phone)、无绳电话、平板型电脑、会话启动协议(session initiation protocol，SIP)电话、个人数字处理(personal digital assistant，PDA)设备、膝上型电脑(laptop computer)、机器类型通信(machine type communication，MTC)终端、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、可穿戴设备(也可以称为穿戴式智能设备)、虚拟现实(virtual reality，VR)终端、增强现实(augmented reality，AR)终端、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等，在此不做限制。
又示例性的，第一传输设备10例如可以为车载设备中的处理器，第二传输设备20例如可以为车载设备的显示屏、车载设备中的存储器等；第一传输设备10例如可以为移动手机中的摄像头，第二传输设备20例如可以为移动手机的显示屏、移动手机中的存储器等，在此不做限制。
另外，本申请实施例提供的技术方案可适用于多种系统架构。本申请实施例描述的系统架构以及业务场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着系统架构的演变和新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
可选的，图3中的各设备(例如第一传输设备10、第二传输设备20等)可以由一个设备实现，也可以由多个设备共同实现，还可以是一个设备内的一个功能模块，本申请实施例对此不作具体限定。可以理解的是，上述功能既可以是硬件设备中的网络元件，也可以是在专用硬件上运行的软件功能，或者是平台(例如，云平台)上实例化的虚拟化功能。
例如，图3中的各设备均可以通过图4中的通信装置400来实现。图4本申请实施例提供的通信装置的硬件结构示意图。该通信装置400包括至少一个处理器401，通信线路402，存储器403以及至少一个通信接口404。
处理器401可以是一个通用中央处理器(central processing unit，CPU)，微处理器，特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制本申请方案程序执行的集成电路。
通信线路402可包括一通路，在上述组件之间传送信息。
通信接口404，是有线的收发器一类的装置，用于与其他设备或通信网络进行有线通信，如以太网等。
存储器403可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器可以是独立存在，通过通信线路402与处理器相连接。存储器也可以和处理器集成在一起。本申请实施例提供的存储器通常可以具有非易失性。其中，存储器403用于存储执行本申请方案的计算机执行指令，并由处理器401来控制执行。处理器401用于执行存储器403中存储的计算机执行指令，从而实现本申请下述实施例提供的方法。
可选的，本申请实施例中的计算机执行指令也可以称之为应用程序代码，本申请实施例对此不作具体限定。
在一种可能的实施方式中，处理器401可以包括一个或多个CPU，例如图4中的CPU0和CPU1。
在一种可能的实施方式中，通信装置400可以包括多个处理器，例如图4中的处理器401和处理器407。这些处理器中的每一个可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
在一种可能的实施方式中，通信装置400还可以包括输出设备405和输入设备406。输出设备405和处理器401通信，可以以多种方式来显示信息。例如，输出设备405可以是液晶显示器(liquid crystal display，LCD)，发光二级管(light emitting diode，LED)显示设备，有机发光二极管(organic light emitting diode，LED)显示设备，阴极射线管(cathode ray tube，CRT)显示设备，或投影仪(projector)等。输入设备406和处理器401通信，可以以多种方式接收用户的输入。例如，输入设备406可以是鼠标、键盘、触摸屏设备或传感设备等。
上述的通信装置400可以是一个通用设备或者是一个专用设备。在具体实现中，通信装置400可以是台式机、便携式电脑、网络服务器、掌上电脑、移动手机、平板电脑、无线终端设备、嵌入式设备或有图4中类似结构的设备。本申请实施例不限定通信装置400的类型。
以下，结合附图，说明本申请实施例提供的技术方案。
参见图5，图5为本申请实施例提供的一种数据处理方法的流程示意图。其中，图5中的第一传输设备可以为图3中的第一传输设备10，图5中的第二传输设备可以为图3中的第二传输设备20。如图5所示，该方法包括但不限于以下步骤：
501.第一传输设备对第一比特序列进行直流平衡处理，得到第二比特序列，第一传输 设备支持至少两种直流平衡方式。
可以理解的，上述直流平衡处理可以包含在至少两种直流平衡方式中。该直流平衡处理可以为预先配置的直流平衡方式，或，根据接收到的指示信息确定的直流平衡方式，指示信息是第二传输设备发送的。
需要说明的，在本申请中，上述直流平衡处理为预先配置的直流平衡方式，可以理解为：上述直流平衡处理为在第一传输设备和第二传输设备中预先配置的直流平衡方式，在此不做限制。
其中，上述直流平衡处理为根据接收到的指示信息确定的直流平衡方式，指示信息是第二传输设备发送的，可以理解为：上述直流平衡处理为根据接收到的信令确定的直流平衡方式，信令是第二传输设备发送的，该信令可以包括指示信息。
可选的，第一比特序列可以为按照预设编码对待传输数据进行编码后的比特序列，或，加扰后的比特序列。
其中，预设编码例如可以为里德所罗门前向纠错编码(reed-solomon FEC，RS-FEC)、低密度校验码(low density parity check code，LDPC)或其他编码，在此不做限制。待传输数据例如可以为图像数据、视频数据或其他控制接口数据，如内部集成电路(Inter-Integrated Circuit，I2C)数据、通用输入输出(general-purpose input/output，GPIO)数据等，在此不做限制。
示例性的，第一比特序列例如可以包括一个或多个里德所罗门(reed-solomon，RS)码块。其中，一个或多个RS码块中第一RS码块例如可以为：Kq_1，Kq-1_1……K2_1，K1_1，Pr_1，Pr-1_1……P2_1，P1_1；一个或多个RS码块中第二RS码块例如可以为：Kq_2，Kq-1_2……K2_2，K1_2，Pr_2，Pr-1_2……P2_2，P1_2；一个或多个RS码块中第J个RS码块例如可以为：Kq_J，Kq-1_J……K2_J，K1_J，Pr_J，Pr-1_J……P2_J，P1_J。可以理解的，Kq_1～K1_1为有效数据，Pr_1～P1_1为RS-FEC的冗余校验数据，q指示有效数据的RS符号个数、r指示校验数据的RS符号个数、J为大于0的整数。以8比特RS(110,100,8)为例，K为100，P为10，q的取值为1～100，r的取值为1～10，Kq_1、Pr_1可以分别代表一个8比特的序列。
其中，加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，L为大于或等于1的整数。
示例性的，以L＝2为例，第一比特序列包括偶数个RS码块，比如2个，第一比特序列为：{Kq_1，Kq-1_1……K2_1，K1_1，Pr_1，Pr-1_1……P2_1，P1_1，Kq_2，K q-1_2……K2_2，K1_2，Pr_2，Pr-1_2……P2_2，P1_2}，进过交织深度为2符号交织后的序列可以为：{Kq_1，Kq_2，Kq-1_1，K q-1_2……K2_1，K2_2，K1_1，K1_2，Pr_1，Pr_2，Pr-1_1，Pr-1_2……P2_1，P2_2，P1_1，P1_2}。
可以理解的，为了便于描述，下面将按照预设编码对待传输数据进行编码后的比特序列称为第五比特序列。
需要说明的，在本申请中，加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，可以理解为：加扰后的比特序列是第六比特序列与预设比特序列进行异或处理后得到的比特序列。其中，第六比特序列为对第五比特序列按 照第二预设长度，经过交织深度为L的符号交织后的比特序列，第二预设长度可以为RS符号的整数倍，如8比特为一个RS符号，第二预设长度可以为一个或多个RS符号，在此不做限制。预设比特序列可以是类似图2所示的移位寄存器产生的随机序列。
示例性的，若第六比特序列为00001111，预设比特序列为11001010，则加扰后的比特序列可以为11000101。
在一种可能的实施方式中，步骤501可以包括：第一传输设备按照第一预设长度，将第一比特序列分流为M个第三比特序列，其中，M为大于0的整数；第一传输设备分别对M个第三比特序列进行线路编码，得到M个第四比特序列；第一传输设备按照预设符号长度对M个第四比特序列进行比特合并，得到第二比特序列。
可选的，第一预设长度可以为预设符号长度的整数倍，预设符号长度根据线路编码确定。其中，若线路编码为8B/10B，则预设符号长度为8比特；若线路编码为9B/10B，则预设符号长度为9比特。
需要说明的，在本申请中，第一传输设备按照第一预设长度，将第一比特序列分流为M个第三比特序列，可以理解为：第一传输设备按照第一预设长度，将第五比特序列或加扰后的比特序列分流为M个第三比特序列，在此不做限制。
其中，M例如可以为1、2、3、4或其他正整数值，在此不做限定。
示例性的，第一传输设备可以按照第一预设长度，将第一比特序列分流为1个第三比特序列或2个第三比特序列或3个第三比特序列或4个第三比特序列等，在此不做限制。例如，在一种可能的实施方式中，针对NRZ或PAM2，第一传输设备可以按照第一预设长度，将第一比特序列分流为1个第三比特序列；针对PAM4，第一传输设备可以按照第一预设长度，将第一比特序列分流为2个第三比特序列；针对PAM8，第一传输设备可以按照第一预设长度，将第一比特序列分流为3个第三比特序列；针对PAM16，第一传输设备可以按照第一预设长度，将第一比特序列分流为4个第三比特序列。
其中，若M为大于1的整数，M个第三比特序列中的每个第三比特序列的长度相同。M个第三比特序列中的每个第三比特序列的长度相同，可以理解为，M个第三比特序列中的每个第三比特序列的长度均为第一预设长度。
在一种可能的实施方式中，当M为大于1的整数时，第一传输设备按照预设符号长度对M个第四比特序列进行比特合并，得到第二比特序列，可以参考以下示例。具体的，当M为2时，假设2个第四比特序列可以包括第七比特序列和第八比特序列，第七比特序列可以为A 1B 1C 1D 1E 1F 1G 1……；第八比特序列可以为a 1b 1c 1d 1e 1f 1g 1……；那么第二比特序列可以为A 1a 1B 1b 1C 1c 1D 1d 1E 1e 1F 1f 1G 1g 1……。
可选的，L可以为M的整数倍。
可以看出，上述技术方案中，第一传输设备按照第一预设长度，将第一比特序列分流为多个比特序列，从而可以分别对多个比特序列进行线路编码，得到编码后的多个比特序列，进而提高了线路编码的效率。同时，第一传输设备按照预设符号长度对编码后的多个比特序列进行比特合并，为后续以特定的电平符号映射后传输，从而实现多种传输码型下的直流平衡。
在一种可能的实施方式中，步骤501可以包括：第一传输设备对第一比特序列进行格 雷映射，得到格雷映射后的第一比特序列；第一传输设备对格雷映射后的第一比特序列进行预编码，得到第二比特序列。
其中，第一传输设备对第一比特序列进行格雷映射，得到格雷映射后的第一比特序列，可以理解为：第一传输设备对加扰后的比特序列(即第一比特序列为加扰后的比特序列)进行格雷映射，得到格雷映射后的第一比特序列。
示例性的，码型为PAM4的第一比特序列，格雷映射可以包括：[0,0]映射为0；[0,1]映射为1；[1,1]映射为2；[1,0]映射为3。
示例性的，码型为PAM8的第一比特序列，格雷映射可以包括：[0,0,0]映射为0；[0,0,1]映射为1；[0,1,0]映射为2；[0,1,1]映射为3；[1,0,0]映射为4；[1,0,1]映射为5；[1,1,0]映射为6；[1,1,1]映射为7。
示例性的，码型为PAM16的第一比特序列，格雷映射可以包括：[0,0,0,0]映射为0；[0,0,0,1]映射为1；[0,0,1,0]映射为2；[0,0,1,1]映射为3；[0,1,0,0]映射为4；[0,1,0,1]映射为5；[0,1,1,0]映射为6；[0,1,1,1]映射为7；[1,0,0,0]映射为8；[1,0,0,1]映射为9；[1,0,1,0]映射为10；[1,0,1,1]映射为11；[1,1,0,0]映射为12；[1,1,0,1]映射为13；[1,1,1,0]映射为14；[1,1,1,1]映射为15。
可以看出，上述技术方案中，第一传输设备可以对第一比特序列依次进行格雷映射、预编码，从而实现了在同一设备上对第一比特序列进行又一种直流平衡处理，避免了现有方案中只提供单一的直流平衡方式所导致的应用场景单一的问题，从而可以适配更多场景和环境的应用。
502.第一传输设备根据传输码型，对第二比特序列进行符号映射，得到至少一个电平信号。
其中，传输码型可以参考上述相关描述，在此不加赘述。
在一种可能的实施方式中，若M为1，传输码型可以为NRZ或PAM2；若M为2，传输码型可以为PAM4；若M为3，传输码型可以为PAM8；若M为4，传输码型可以为PAM16。
在一种可能的实施方式中，步骤502可以包括：若传输码型为NRZ或PAM2，第一传输设备将第二比特序列中一个比特映射为一个电平信号，得到至少一个电平信号。
其中，第一传输设备将第二比特序列中一个比特映射为一个电平信号，得到至少一个电平信号，可以理解为：第一传输设备将第二比特序列中第一比特值映射为第一电平，第一传输设备将第二比特序列中第二比特值映射为第二电平，以得到上述至少一个电平信号。
需要说明的，在本申请中，第一比特值和第二比特值不同。若第一比特值为0，则第二比特值可以为1；若第一比特值为1，第二比特值可以为0，在此不做限制。
其中，第一电平和第二电平不同。例如第一电平可以为1，第二电平可以为-1，在此不做限制。
示例性的，若第二比特序列为00101。参见图6，图6为本申请实施例提供的一种双电平码型符号映射示意图。结合图6，可以看出，00101中0映射为第一电平(1)，00101中1映射为第二电平(-1)。
可以看出，上述技术方案中，通过将比特序列映射为双电平码型的电平信号，使得电 平信号仍然具备直流平衡的特性，提升传输质量。
在又一种可能的实施方式中，步骤502可以包括：若传输码型为PAM4，则将第二比特序列中每两个连续比特映射为一个电平信号，得到至少一个电平信号；其中，每两个连续比特包括[a，b]、[a’，b’]、[a’，b]、[a，b’]中的一种；[a，b]映射为x，[a’，b’]映射为-x，[a’，b]映射为y，[a，b’]映射为-y；a’为a的二进制取反，b’为b的二进制取反；a和b的取值为0或1，x和y的取值集合为{1，1/3}，且x和y取值不同。
示例性的，[0，0]映射为电平-1/3，[1，0]映射为电平-1，[0，1]映射为电平1，[1，1]映射为电平1/3；或，[0，0]映射为电平-1，[1，0]映射为电平-1/3，[0，1]映射为电平1/3，[1，1]映射为电平1；或，[0，0]映射为电平1，[1，0]映射为电平1/3，[0，1]映射为电平-1/3，[1，1]映射为电平-1；或，[0，0]映射为电平1/3，[1，0]映射为电平1，[0，1]映射为电平-1，[1，1]映射为电平-1/3；或，[0，0]映射为电平-1/3，[1，0]映射为电平1，[0，1]映射为电平-1，[1，1]映射为电平1/3；或，[0，0]映射为电平-1，[1，0]映射为电平1/3，[0，1]映射为电平-1/3，[1，1]映射为电平1；或，[0，0]映射为电平1，[1，0]映射为电平-1/3，[0，1]映射为电平1/3，[1，1]映射为电平-1；或，[0，0]映射为电平1/3，[1，0]映射为电平-1，[0，1]映射为电平1，[1，1]映射为电平-1/3。
可以看出，上述技术方案中，通过将比特序列映射为多电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
在又一种可能的实施方式中，步骤502可以包括：若传输码型为PAM8，则将第二比特序列中每三个连续比特映射为一个电平信号，得到至少一个电平信号；其中，每三个连续比特包括[a，b，c]、[a’，b’，c’]、[a’，b，c]、[a，b’，c’]、[a，b’，c]、[a’，b，c’]、[a，b，c’]、[a’，b’，c]中的一种；[a，b，c]映射为s，[a’，b’，c’]映射为-s，[a’，b，c]映射为w，[a，b’，c’]映射为-w，[a，b’，c]映射为z，[a’，b，c’]映射为-z，[a，b，c’]映射为j，[a’，b’，c]映射为-j；a’、b’、c’分别为a、b、c的二进制取反，a、b、c的取值为0或1；s、w、z、j的取值集合为{1,5/7,3/7,1/7}，且s、w、z、j的取值互不相同。
示例性的，[0，0，0]映射为电平1，[1，1，1]映射为电平-1，[1，0，0]映射为电平5/7，[0，1，1]映射为电平-5/7，[0，1，0]映射为电平3/7，[1，0，1]映射为电平-3/7，[0，0，1]映射为电平1/7，[1，1，0]映射为电平-1/7。
可以看出，上述技术方案中，通过将比特序列映射为多电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
在又一种可能的实施方式中，步骤502可以包括：若传输码型为PAM16，则将第二比特序列中每四个连续比特映射为一个电平信号，得到至少一个电平信号；其中，每四个连续比特包括以下一种：[a，b，c，d]、[a’，b’，c’，d’]、[a’，b，c，d]、[a，b’，c’，d’]、[a，b’，c，d]、[a’，b，c’，d’]、[a，b，c’，d]、[a’，b’，c，d’]、[a，b，c，d’]，[a’，b’，c’，d]、[a’，b’，c，d]、[a，b，c’，d’]、[a’，b，c’，d]、[a，b’，c，d’]、[a’，b，c，d’]、[a，b’，c’，d]中的一种；[a，b，c，d]映射为t，[a’，b’，c’，d’]映射为-t，[a’，b，c，d]映射为p，[a，b’，c’，d’]映射为-p，[a，b’，c，d]映射为v，[a’，b，c’，d’]映射为-v，[a，b，c’，d]映射为u，[a’，b’，c，d’]映射为-u，[a，b，c，d’]映射为k，[a’，b’，c’，d]映射为-k，[a’，b’，c，d]映射为i，[a，b，c’，d’]映射为-i，[a’，b， c’，d]映射为m，[a，b’，c，d’]映射为-m，[a’，b，c，d’]映射为n，[a，b’，c’，d]映射为-n；a’、b’、c’、d’分别为a、b、c、d的二进制取反，a、b、c、d的取值为0或1；t、p、v、u、k、i、m、n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且t、p、v、u、k、i、m、n的取值互不相同。
示例性的，[0，0，0，0]映射为电平1，[1，1，1，1]映射为电平-1，[1，0，0，0]映射为电平13/15，[0，1，1，1]映射为电平-13/15，[0，1，0，0]映射为电平11/15，[1，0，1，1]映射为电平-11/15，[0，0，1，0]映射为电平9/15，[1，1，0，1]映射为电平-9/15，[0，0，0，1]映射为电平7/15，[1，1，1，0]映射为电平-7/15，[1，1，0，0]映射为电平1/3，[0，0，1，1]映射为电平-1/3，[1，0，1，0]映射为电平1/5，[0，1，0，1]映射为电平-1/5，[1，0，0，1]映射为电平1/15，[0，1，1，0]映射为电平-1/15。
可以看出，上述技术方案中，通过将比特序列映射为多电平码型的电平信号，使得电平信号仍然具备直流平衡的特性，提升传输质量。
503.第一传输设备向第二传输设备发送的至少一个电平信号。
可以看出，上述技术方案中，第一传输设备通过采用至少两种直流平衡方式中的一种直流平衡方式对第一比特序列进行直流平衡处理，从而避免了单一的直流平衡方式所导致的应用场景单一的问题。同时，在同一设备上可以支持多种直流平衡方式，从而可以适配不同的直流平衡需求。另外，第一传输设备可以根据传输码型，对比特序列进行符号映射，得到电平信号，从而实现了在同一设备扩展支持多种传输码型。进一步的，由于在同一设备可以扩展支持多种传输码型，且针对不同传输码型可以进行符号映射，也实现了模块复用，进而降低了产品的成本和功耗。
下面结合图7以及图8来说明本申请可能提供的编码相关技术方案。
示例性的，参见图7，图7为本申请实施例提供的一种数据处理方法的流程示意图。结合图7，可以看出，第一传输设备可以先按照RS-FEC对待传输数据进行编码得到第五比特序列；接着，第一传输设备可以对第五比特序列进行直流平衡处理，得到第二比特序列；然后，第一传输设备可以对第二比特序列进行符号映射，得到至少一个电平信号，如第一传输设备可以根据传输码型，对第二比特序列进行符号映射，得到至少一个电平信号；最后，第一传输设备可以向第二传输设备发送至少一个电平信号。
其中，第一传输设备对第五比特序列进行直流平衡处理，得到第二比特序列，可以理解为：第一传输设备先将第五比特序列进行分流，如第一传输设备可以按照第一预设长度，将第五比特序列分流为M个第三比特序列；接着，第一传输设备可以分别对分流后的第五比特序列进行线路编码，如第一传输设备可以分别对M个第三比特序列进行线路编码，得到M个第四比特序列；最后，第一传输设备可以对线路编码后的比特序列进行交织，得到第二比特序列，如第一传输设备可以按照预设符号长度对M个第四比特序列进行交织，得到第二比特序列。
其中，结合图7，可以看出，第一传输设备可以并行的对分流后的第五比特序列进行线路编码。例如，第一传输设备可以并行的对M个第三比特序列进行线路编码，得到M个第四比特序列。
其中，第一传输设备对第五比特序列进行直流平衡处理，得到第二比特序列，可以理解为：第一传输设备对第五比特序列进行RS符号交织，得到第六比特序列，如第一传输设备对第五比特序列按照第二预设长度，经过交织深度为L的符号交织后得到第六比特序列；接着，第一传输设备对第六比特序列和预设比特序列进行异或处理得到加扰后的比特序列；然后，第一传输设备对加扰后的比特序列进行格雷映射，得到格雷映射后的比特序列；最后，第一传输设备对格雷映射后的比特序列进行预编码，得到第二比特序列。
需要说明的，图7中涉及的内容，具体可以参考图5中相关描述，在此不加赘述。
示例性的，参见图8，图8为本申请实施例提供的一种数据处理方法的流程示意图。结合图8，可以看出，第一传输设备可以先对加扰后的比特序列进行直流平衡处理，得到第二比特序列；然后，第一传输设备可以对第二比特序列进行符号映射，得到至少一个电平信号，如第一传输设备可以根据传输码型，对第二比特序列进行符号映射，得到至少一个电平信号；最后，第一传输设备可以向第二传输设备发送至少一个电平信号。
可以理解的，结合图8，可以看出，加扰后的比特序列可以是第六比特序列与预设比特序列进行异或处理后得到的比特序列；第六比特序列可以为对第五比特序列经过RS符号交织后的比特序列，如第六比特序列可以为对第五比特序列按照第二预设长度，经过交织深度为L的符号交织后的比特序列，第二预设长度可以参考上述相关描述，在此不加赘述；第五比特序列可以为按照预设编码(如RS-FEC)对待传输数据进行编码后的比特序列。
其中，第一传输设备对加扰后的比特序列进行直流平衡处理，得到第二比特序列，可以理解为：第一传输设备先将加扰后的比特序列进行分流，如第一传输设备可以按照第一预设长度，将加扰后的比特序列分流为M个第三比特序列；接着，第一传输设备可以分别对分流后的比特序列进行线路编码，如第一传输设备可以分别对M个第三比特序列进行线路编码，得到M个第四比特序列；最后，第一传输设备可以对线路编码后的比特序列进行交织，得到第二比特序列，如第一传输设备可以按照预设符号长度对M个第四比特序列进行交织，得到第二比特序列。
其中，结合图8，可以看出，第一传输设备可以并行的对分流后的比特序列进行线路编码。例如，第一传输设备可以并行的对M个第三比特序列进行线路编码，得到M个第四比特序列。
其中，第一传输设备可以对加扰后的比特序列进行直流平衡处理，得到第二比特序列，可以理解为：第一传输设备可以对加扰后的比特序列进行格雷映射，得到格雷映射后的比特序列；然后，第一传输设备对格雷映射后的比特序列进行预编码，得到第二比特序列。
需要说明的，图8中涉及的内容，具体可以参考图5中相关描述，在此不加赘述。
下面结合图9来说明本申请提供的解码相关的技术方案。参见图9，图9为本申请实施例提供的一种数据处理方法的流程示意图。其中，图9中的第一传输设备可以为图3中的第一传输设备10，图9中的第二传输设备可以为图3中的第二传输设备20。如图9所示，该方法包括但不限于以下步骤：
901.第一传输设备向第二传输设备发送至少一个电平信号。
902.第二传输设备根据传输码型，对至少一个电平信号进行符号逆映射，得到第二比 特序列。
其中，关于传输码型，可以参考上述相关描述，在此不加赘述。
在一种可能的实施方式中，步骤902可以包括：若传输码型为NRZ或PAM2，第二传输设备将至少一个电平信号中的每个电平信号逆映射为一个比特，得到第二比特序列。
其中，上述每个电平信号可以为第一电平或第二电平，那么，第二传输设备可以将第一电平逆映射为第一比特值，将第二电平逆映射为第二比特值。其中，关于第一电平、第二电平、第一比特值和第二比特值可以参考上述相关描述，在此不加赘述。
在又一种可能的实施方式中，步骤902可以包括：若传输码型为PAM4，第二传输设备将至少一个电平信号中每个电平信号逆映射为两个连续的比特，得到第二比特序列；
其中，每个电平信号包括x、y、-x、-y中的一种；x和y的取值集合为{1，1/3}，且x和y取值不同；
x逆映射为[a，b]，-x逆映射为[a’，b’]，y逆映射为[a’，b]，-y逆映射为[a，b’]；a’为a的二进制取反，b’为b的二进制取反，a和b的取值为0或1。
示例性的，电平-1/3逆映射为[0，0]，电平-1逆映射为[1，0]，电平1逆映射为[0，1，电平1/3逆映射为[1，1]。
在又一种可能的实施方式中，步骤902可以包括：若传输码型为PAM8，第二传输设备将至少一个电平信号中每个电平信号逆映射为三个连续的比特，得到第二比特序列；其中，每个电平信号包括s、-s、w、-w、z、-z、j、-j中的一种；s、w、z、j的取值集合为{1,5/7,3/7,1/7}，且s、w、z、j的取值互不相同；s逆映射为[a，b，c]，-s逆映射为[a’，b’，c’]，w逆映射为[a’，b，c]，-w逆映射为[a，b’，c’]，z逆映射为[a，b’，c]，-z逆映射为[a’，b，c’]，j逆映射为[a，b，c’]，-j逆映射为[a’，b’，c]；a’、b’、c’分别为a、b、c的二进制取反，a、b、c的取值为0或1。
示例性的，电平1逆映射为[0，0，0]，电平-1逆映射为[1，1，1]，电平5/7逆映射为[1，0，0]，电平-5/7逆映射为[0，1，1]，电平3/7逆映射为[0，1，0]，电平-3/7逆映射为[1，0，1]，电平1/7逆映射为[0，0，1]，电平-1/7逆映射为[1，1，0]。
在又一种可能的实施方式中，步骤902可以包括：若传输码型为PAM16，第二传输设备将至少一个电平信号中每个电平信号逆映射为四个连续的比特，得到第二比特序列；其中，每个电平信号包括t、-t、p、-p、v、-v、u、-u、k、-k、i、-i、m、-m、n、-n中的一种；t、p、v、u、k、i、m、n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且t、p、v、u、k、i、m、n的取值互不相同；t逆映射为[a，b，c，d]，-t逆映射为[a’，b’，c’，d’]，p逆映射为[a’，b，c，d]，-p逆映射为[a，b’，c’，d’]，v逆映射为[a，b’，c，d]，-v逆映射为[a’，b，c’，d’]，u逆映射为[a，b，c’，d]，-u逆映射为[a’，b’，c，d’]，k逆映射为[a，b，c，d’]，-k逆映射为[a’，b’，c’，d]，i逆映射为[a’，b’，c，d]，-i逆映射为[a，b，c’，d’]，m逆映射为[a’，b，c’，d]，-m逆映射为[a，b’，c，d’]，n逆映射为[a’，b，c，d’]，-n逆映射为[a，b’，c’，d]；a’、b’、c’、d’分别为a、b、c、d的二进制取反，a、b、c、d的取值为0或1。
示例性的，电平1逆映射为[0，0，0，0]，电平-1逆映射为[1，1，1，1]，电平13/15逆映射为[1，0，0，0]，电平-13/15逆映射为[0，1，1，1]，电平11/15逆映射为[0，1， 0，0]，电平-11/15逆映射为[1，0，1，1]，电平9/15逆映射为[0，0，1，0]，电平-9/15逆映射为[1，1，0，1]，电平7/15逆映射为[0，0，0，1]，电平-7/15逆映射为[1，1，1，0]，电平1/3逆映射为[1，1，0，0]，电平-1/3逆映射为[0，0，1，1]，电平1/5逆映射为[1，0，1，0]，电平-1/5逆映射为[0，1，0，1]，电平1/15逆映射为[1，0，0，1]，电平-1/15逆映射为[0，1，1，0]。
903.第二传输设备对第二比特序列进行解直流平衡处理，得到第一比特序列，直流平衡处理包含在第一传输设备支持的至少两种直流平衡方式中。
其中，关于第一比特序列，可以参考上述相关描述，在此不加赘述。
其中，直流平衡处理为预先配置的直流平衡方式，或，第二传输设备所支持的直流平衡方式。
在一种可能的实施方式中，步骤903可以包括：第二传输设备按照预设符号长度对第二比特序列进行分流，得到M个第四比特序列，其中，M为大于0的整数；第二传输设备分别对M个第四比特序列进行解线路编码，得到M个第三比特序列；第二传输设备按照第一预设长度将M个第三比特序列进行按照第一预设长度进行合并，得到第一比特序列。
其中，关于预设符号长度，可以参考上述相关描述，在此不加赘述。
其中，关于线路编码，可以参考上述相关描述，在此不加赘述。
其中，关于第一预设长度，可以参考上述相关描述，在此不加赘述。
其中，关于L，可以参考上述相关描述，在此不加赘述。
其中，M例如可以为1、2、3、4或其他正整数值，在此不做限定。
示例性的，第二传输设备按照预设符号长度对第二比特序列进行分流，可以得到1个第四比特序列或2个第四比特序列或3个第四比特序列或4个第四比特序列等，在此不做限制。例如，在一种可能的实施方式中，针对NRZ或PAM2，第二传输设备可以按照预设符号长度，将第二比特序列分流为1个第四比特序列；针对PAM4，第二传输设备可以按照预设符号长度，将第二比特序列分流为2个第四比特序列；针对PAM8，第二传输设备可以按照预设符号长度，将第二比特序列分流为3个第四比特序列；针对PAM16，第二传输设备可以按照预设符号长度，将第二比特序列分流为4个第四比特序列。
其中，若M为大于1的整数，M个第四比特序列中的每个第四比特序列的长度相同。M个第四比特序列中的每个第四比特序列的长度相同，可以理解为，M个第四比特序列中的每个第四比特序列的长度均为预设符号长度。
其中，第二传输设备将M个第三比特序列按照第一预设长度进行合并，得到第一比特序列，可以理解为：第二传输设备将M个第三比特序列按照第一预设长度进行合并，得到按照预设编码对待传输数据进行编码后的比特序列，或，加扰后的比特序列，在此不做限制。
示例性的，M＝2，L＝4，线路编码为8b/10b，RS-FEC为RS{110,100,8}，第一预设长度8比特，2个第四比特序列可以分别为{K100_1，K100_3，K99_1，K99_3，……K2_1，K2_3，K1_1，K1_3，P10_1，P10_3，P9_1，P9_3，……P2_1，P2_3，P1_1，P1_3},{K100_2，K100_4，K99_2，K99_4，……K2_2，K2_4，K1_2，K1_4，P10_2，P10_4，P9_2，P9_4，……P2_2，P2_4，P1_2，P1_4}。2个第四比特序列按照第一预设长度合并后可以为{K100_1，K100_2， K100_3，K100_4，K99_1，K99_2，K99_3，K99_4，……,K2_1，K2_2，K2_3，K2_4,K1_1，K1_2，K1_3，K1_4,P10_1，P10_2，P10_3，P10_4，P9_1，P9_2，P9_3，P9_4,……,P1_1，P1_2,P1_3，P1_4}。
可以看出，上述技术方案中，第二传输设备通过按照预设符号长度对第二比特序列进行分流得到多个比特序列，从而使得第二传输设备可以分别对多个比特序列进行解线路编码，以对解线路编码后的比特序列进行合并，进而得到第一比特序列，提高了解线路编码的效率。
在又一种可能的实施方式中，步骤903可以包括：第二传输设备对第二比特序列进行预编码解码，得到解码后的第二比特序列；第二传输设备对解码后的第二比特序列进行解格雷映射，得到第一比特序列。
其中，第二传输设备对解码后的第二比特序列进行解格雷映射，得到第一比特序列，可以理解为：第二传输设备对解码后的第二比特序列进行解格雷映射，得到加扰后的比特序列。
其中，解码后的第二比特序列可以是码型为PAM4、PAM8或PAM16的比特序列。
示例性的，若解码后的第二比特序列可以是码型为PAM4比特序列，则解格雷映射可以包括：0解格雷映射为[0,0]；1解格雷映射为[0,1]；2解格雷映射为[1,1]；3解格雷映射为[1,0]。
示例性的，若解码后的第二比特序列可以是码型为PAM8比特序列，则解格雷映射可以包括：0解格雷映射为[0,0,0]；1解格雷映射为[0,0,1]；2解格雷映射为[0,1,0]；3解格雷映射为[0,1,1]；4解格雷映射为[1,0,0]；5[1,0,1]解格雷映射为；6解格雷映射为[1,1,0]；7解格雷映射为[1,1,1]。
示例性的，若解码后的第二比特序列可以是码型为PAM16比特序列，则解格雷映射可以包括：0解格雷映射为[0,0,0,0]；1解格雷映射为[0,0,0,1]；2解格雷映射为[0,0,1,0]；3解格雷映射为[0,0,1,1]；4解格雷映射为[0,1,0,0]；5解格雷映射为[0,1,0,1]；6解格雷映射为[0,1,1,0]；7解格雷映射为[0,1,1,1]；8解格雷映射为[1,0,0,0]；9解格雷映射为[1,0,0,1]；10解格雷映射为[1,0,1,0]；11解格雷映射为[1,0,1,1]；12解格雷映射为[1,1,0,0]；13解格雷映射为[1,1,0,1]；14解格雷映射为[1,1,1,0]；15解格雷映射为[1,1,1,1]。
在一种可能的实施方式中，在步骤903之后，若第一比特序列为按照预设编码对待传输数据进行编码后的比特序列，该方法还包括：第二传输设备可以对第一比特序列进行解编码，得到有效传输数据。
示例性的，第二传输设备可以对第一比特序列进行解RS-FEC处理，得到有效传输数据。
在又一种可能的实施方式中，在步骤903之后，若第一比特序列为加扰后的比特序列，该方法还包括：第二传输设备可以对第一比特序列进行解扰码后以深度为L进行解交织，再对解交织后的第一比特序列进行解编码，得到有效传输数据。
示例性的，若解扰码后的比特序列可以为{K100_1，K100_2，K100_3，K100_4，K99_1，K99_2，K99_3，K99_4，……,K2_1，K2_2，K2_3，K2_4,K1_1，K1_2，K1_3，K1_4,P10_1， P10_2，P10_3，P10_4，P9_1，P9_2，P9_3，P9_4,……,P1_1，P1_2,P1_3，P1_4}，那么，经过深度为4的解交织后可以为:
{K100_1，K99_1，……,K2_1,P10_1,P9_1,……,P1_1,
K100_2，K99_2，……,K2_2,P10_2,P9_2,……,P1_2,
K100_3，K99_3，……,K2_3,P10_3,P9_3,……,P1_3,
K100_4，K99_4，……,K2_4,P10_4,P9_4,……,P1_4}。
可以看出，上述技术方案中，第二传输设备通过根据传输码型，对来自第一传输设备的电平信号进行符号逆映射，得到第二比特序列，以根据包含在第一传输设备支持的至少两种直流平衡方式中的第一直流平衡方式，确定第二比特序列对应的第一比特序列，从而避免了单一的直流平衡方式所导致的应用场景单一的问题。同时，在同一设备上可以支持多种直流平衡方式，从而可以适配不同的直流平衡需求。另外，第二传输设备可以根据传输码型，对来自第一传输设备的电平信号进行符号逆映射，得到第二比特序列，从而实现了在同一设备扩展支持多种传输码型。进一步的，由于在同一设备可以扩展支持多种传输码型，且针对不同传输码型可以进行符号逆映射，也实现了模块复用，进而降低了产品的成本和功耗。
上述主要从各个设备之间交互的角度对本申请提供的方案进行了介绍。可以理解的是，上述实现各设备为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的模块及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对第一传输设备或第二传输设备进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中，上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
图10为本申请实施例提供的一种通信装置的结构示意图。该通信装置1000可应用于上述图5-图9所示的任一方法中，如图10所示，该通信装置1000包括收发模块1001和处理模块1002。收发模块1001可以是收发器或者通信接口，处理模块1002可以是一个或多个处理器。该通信装置可用于实现上述任一方法实施例中涉及第一传输设备或第二传输设备，或用于实现上述任一方法实施例中涉及设备的功能。例如，该通信装置可以为第一传输设备或第二传输设备。该第一传输设备或第二传输设备既可以是硬件设备中的网络元件，也可以是在专用硬件上运行的软件功能，或者是平台(例如，云平台)上实例化的虚拟化功能。可选的，该通信装置1000还可以包括存储模块1003，用于存储通信装置1000的程序代码和数据。
示例性的，当该通信装置作为第一传输设备或为应用于第一传输设备中的芯片，该通 信装置1000包括收发模块1001和处理模块1002，并执行上述方法实施例中由第一传输设备执行的步骤。收发模块1001，用于支持与第二传输设备等之间的有线通信，具体执行图5-图9中由第一传输设备执行的发送和/或接收的动作，在此不加赘述。例如支持第一传输设备执行步骤503、步骤901中的一个或多个步骤，和/或用于本文中所描述的技术的其他过程。处理模块1002可用于支持通信装置1000执行上述方法实施例中的处理动作，在此不加赘述。例如，支持第一传输设备执行步骤501、步骤502中的一个或多个步骤，和/或用于本文所描述的技术的其它过程。
示例性的，处理模块1002，用于对第一比特序列进行直流平衡处理，得到第二比特序列；处理模块1002，用于根据传输码型，对第二比特序列进行符号映射，得到至少一个电平信号；收发模块1001，用于发送至少一个电平信号。
示例性的，当该通信装置作为第二传输设备或为应用于第二传输设备中的芯片，该通信装置1000包括收发模块1001和处理模块1002，并执行上述方法实施例中由第二传输设备执行的步骤。收发模块1001，用于支持与第二传输设备等之间的有线通信，具体执行图5-图9中由第二传输设备执行的发送和/或接收的动作，在此不加赘述。处理模块1002可用于支持通信装置1000执行上述方法实施例中的处理动作，在此不加赘述。例如，支持第二传输设备执行步骤902、步骤903中的一个或多个步骤，和/或用于本文所描述的技术的其它过程。
示例性的，收发模块，用于接收至少一个电平信号；处理模块，用于根据传输码型，对至少一个电平信号进行符号逆映射，得到第二比特序列；处理模块，用于对第二比特序列进行解直流平衡处理，得到第一比特序列，解直流平衡处理包含在第一传输设备支持的至少两种直流平衡方式中。
在一种可能的实施方式中，当通信装置为芯片时，收发模块1001可以是接口、管脚或电路等。接口可用于输入待处理的数据至处理器，并可以向外输出处理器的处理结果。具体实现中，接口可以是通用输入输出(general purpose input output，GPIO)接口，可以和多个外围设备(如显示器(LCD)、摄像头(camara)、射频(radio frequency，RF)模块、天线等等)连接。接口通过总线与处理器相连。
处理模块1002可以是处理器，该处理器可以执行存储模块存储的计算机执行指令，以使该芯片执行图5-图9实施例涉及的方法。
进一步的，处理器可以包括控制器、运算器和寄存器。示例性的，控制器主要负责指令译码，并为指令对应的操作发出控制信号。运算器主要负责执行定点或浮点算数运算操作、移位操作以及逻辑操作等，也可以执行地址运算和转换。寄存器主要负责保存指令执行过程中临时存放的寄存器操作数和中间操作结果等。具体实现中，处理器的硬件架构可以是专用集成电路(application specific integrated circuits，ASIC)架构、无互锁管道阶段架构的微处理器(microprocessor without interlocked piped stages architecture，MIPS)架构、进阶精简指令集机器(advanced RISC machines，ARM)架构或者网络处理器(network processor，NP)架构等等。处理器可以是单核的，也可以是多核的。
该存储模块1003可以为该芯片内的存储模块，如寄存器、缓存等。存储模块也可以是 位于芯片外部的存储模块，如只读存储器(Read Only Memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(Random Access Memory，RAM)等。
需要说明的，处理器、接口各自对应的功能既可以通过硬件设计实现，也可以通过软件设计来实现，还可以通过软硬件结合的方式来实现，这里不作限制。
本申请还提供一种通信装置，包括存储器和处理器，存储器用于存储计算机执行指令，处理器用于执行存储器存储的计算机执行指令，并且对存储器中存储的计算机执行指令的执行使得处理器执行图5-图9任一可能的实现方式中的方法。
本申请还提供又一种通信装置，包括存储器和通信接口，通信接口用于输入和/或输出信息，处理器用于执行计算机程序，使得该装置执行图5-图9任一可能的实现方式中的方法。
本申请还提供一种计算机可读存储介质，其上存储有计算机程序，计算机程序被计算机执行时使得计算机实现如图5-图9任一可能的实现方式中的方法。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例方案的目的。另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，云服务器，或者网络设备等)执行本申请各个实施例上述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (62)

  1. 一种数据处理方法，其特征在于，所述方法应用于第一传输设备，所述第一传输设备支持至少两种直流平衡方式，所述方法包括：
    对第一比特序列进行直流平衡处理，得到第二比特序列；
    根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号；
    发送所述至少一个电平信号。
  2. 根据权利要求1所述的方法，其特征在于，所述对第一比特序列进行直流平衡处理，得到第二比特序列，包括：
    按照第一预设长度，将所述第一比特序列分流为M个第三比特序列，其中，所述M为大于0的整数；
    分别对所述M个第三比特序列进行线路编码，得到M个第四比特序列；
    按照预设符号长度对所述M个第四比特序列进行比特合并，得到所述第二比特序列。
  3. 根据权利要求1所述的方法，其特征在于，所述对第一比特序列进行直流平衡处理，得到第二比特序列，包括：
    对所述第一比特序列进行格雷映射，得到格雷映射后的第一比特序列；
    对所述格雷映射后的第一比特序列进行预编码，得到所述第二比特序列。
  4. 根据权利要求1-3任意一项所述的方法，其特征在于，所述第一比特序列为加扰后的比特序列。
  5. 根据权利要求4所述的方法，其特征在于，所述加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，所述L为大于或等于1的整数。
  6. 根据权利要求5所述的方法，其特征在于，所述第二预设长度为里德所罗门RS符号的整数倍。
  7. 根据权利要求5所述的方法，其特征在于，所述L为M的整数倍。
  8. 根据权利要求1或2或7所述的方法，其特征在于，
    若M为1，所述传输码型为非归零调制NRZ，或，2阶脉冲幅度调制PAM2；
    若M为2，所述传输码型为4阶脉冲幅度调制PAM4；
    若M为3，所述传输码型为8阶脉冲幅度调制PAM8；
    若M为4，所述传输码型为16阶脉冲幅度调制PAM16。
  9. 根据权利要求2所述的方法，其特征在于，所述第一预设长度为所述预设符号长度 的整数倍，所述预设符号长度根据所述线路编码确定。
  10. 根据权利要求9所述的方法，其特征在于，
    若所述线路编码为8B/10B，则所述预设符号长度为8比特；
    若所述线路编码为9B/10B，则所述预设符号长度为9比特。
  11. 根据权利要求1-10任意一项所述的方法，其特征在于，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
    若所述传输码型为所述NRZ或所述PAM2，则将所述第二比特序列中一个比特映射为一个电平信号，得到所述至少一个电平信号。
  12. 根据权利要求1-10任意一项所述的方法，其特征在于，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
    若所述传输码型为所述PAM4，则将所述第二比特序列中每两个连续比特映射为一个电平信号，得到所述至少一个电平信号；
    其中，所述每两个连续比特包括[a，b]、[a’，b’]、[a’，b]、[a，b’]中的一种；所述[a，b]映射为x，所述[a’，b’]映射为-x，所述[a’，b]映射为y，所述[a，b’]映射为-y；所述a’为所述a的二进制取反，所述b’为所述b的二进制取反，所述a和所述b的取值为0或1，所述x和所述y的取值集合为{1，1/3}，且所述x和所述y取值不同。
  13. 根据权利要求1-10任意一项所述的方法，其特征在于，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
    若所述传输码型为所述PAM8，则将所述第二比特序列中每三个连续比特映射为一个电平信号，得到所述至少一个电平信号；
    其中，所述每三个连续比特包括[a，b，c]、[a’，b’，c’]、[a’，b，c]、[a，b’，c’]、[a，b’，c]、[a’，b，c’]、[a，b，c’]、[a’，b’，c]中的一种；所述[a，b，c]映射为s，所述[a’，b’，c’]映射为-s，所述[a’，b，c]映射为w，所述[a，b’，c’]映射为-w，所述[a，b’，c]映射为z，所述[a’，b，c’]映射为-z，所述[a，b，c’]映射为j，所述[a’，b’，c]映射为-j；所述a’、所述b’、所述c’分别为所述a、所述b、所述c的二进制取反，所述a、所述b、所述c的取值为0或1，所述s、所述w、所述z、所述j的取值集合为{1,5/7,3/7,1/7}，且所述s、所述w、所述z、所述j的取值互不相同。
  14. 根据权利要求1-10任意一项所述的方法，其特征在于，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
    若所述传输码型为所述PAM16，则将所述第二比特序列中每四个连续比特映射为一个电平信号，得到所述至少一个电平信号；
    其中，所述每四个连续比特包括[a，b，c，d]、[a’，b’，c’，d’]、[a’，b，c，d]、[a，b’，c’，d’]、[a，b’，c，d]、[a’，b，c’，d’]、[a，b，c’，d]、[a’，b’，c，d’]、[a， b，c，d’]、[a’，b’，c’，d]、[a’，b’，c，d]、[a，b，c’，d’]、[a’，b，c’，d]、[a，b’，c，d’]、[a’，b，c，d’]、[a，b’，c’，d]中的一种；
    所述[a，b，c，d]映射为t，所述[a’，b’，c’，d’]映射为-t，所述[a’，b，c，d]映射为p，所述[a，b’，c’，d’]映射为-p，所述[a，b’，c，d]映射为v，所述[a’，b，c’，d’]映射为-v，所述[a，b，c’，d]映射为u，所述[a’，b’，c，d’]映射为-u，所述[a，b，c，d’]映射为k，所述[a’，b’，c’，d]映射为-k，所述[a’，b’，c，d]映射为i，所述[a，b，c’，d’]映射为-i，所述[a’，b，c’，d]映射为m，所述[a，b’，c，d’]映射为-m，所述[a’，b，c，d’]映射为n，所述[a，b’，c’，d]映射为-n；
    所述a’、所述b’、所述c’、所述d’分别为所述a、所述b、所述c、所述d的二进制取反，所述a、所述b、所述c、所述d的取值为0或1，所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值互不相同。
  15. 根据权利要求1-3任意一项所述的方法，其特征在于，所述直流平衡处理为预先配置的直流平衡方式，或，根据接收到的指示信息确定的直流平衡方式；所述指示信息是所述第二传输设备发送的。
  16. 一种数据处理方法，其特征在于，所述方法应用于第二传输设备，所述方法包括：
    接收至少一个电平信号；
    根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列；
    对所述第二比特序列进行解直流平衡处理，得到第一比特序列，所述直流平衡处理属于第一传输设备支持的至少两种直流平衡方式。
  17. 根据权利要求16所述的方法，其特征在于，所述对所述第二比特序列进行解直流平衡处理，得到第一比特序列，包括：
    按照预设符号长度对所述第二比特序列进行分流，得到M个第四比特序列，其中，所述M为大于0的整数；
    分别对所述M个第四比特序列进行解线路编码，得到M个第三比特序列；
    将所述M个第三比特序列按照第一预设长度进行合并，得到所述第一比特序列。
  18. 根据权利要求16所述的方法，其特征在于，所述对所述第二比特序列进行解直流平衡处理，得到第一比特序列，包括：
    对所述第二比特序列进行预编码解码，得到解码后的第二比特序列；
    对所述解码后的第二比特序列进行解格雷映射，得到所述第一比特序列。
  19. 根据权利要求16-18任意一项所述的方法，其特征在于，所述第一比特序列为加扰后的比特序列。
  20. 根据权利要求19所述的方法，其特征在于，所述加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，所述L为大于或等于1的整数。
  21. 根据权利要求20所述的方法，其特征在于，所述第二预设长度为里德所罗门RS符号的整数倍。
  22. 根据权利要求19所述的方法，其特征在于，所述L为M的整数倍。
  23. 根据权利要求16或17或22所述的方法，其特征在于，
    若M为1，所述传输码型为非归零调制NRZ，或，2阶脉冲幅度调制PAM2；
    若M为2，所述传输码型为4阶脉冲幅度调制PAM4；
    若M为3，所述传输码型为8阶脉冲幅度调制PAM8；
    若M为4，所述传输码型为16阶脉冲幅度调制PAM16。
  24. 根据权利要求17所述的方法，其特征在于，所述第一预设长度为所述预设符号长度的整数倍，所述预设符号长度根据所述线路编码确定。
  25. 根据权利要求24所述的方法，其特征在于，
    若所述线路编码为8B/10B，则所述预设符号长度为8比特；
    若所述线路编码为9B/10B，则所述预设符号长度为9比特。
  26. 根据权利要求16-25任意一项所述的方法，其特征在于，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
    若所述传输码型为所述NRZ或所述PAM2，则将所述至少一个电平信号中每个电平信号逆映射为一个比特，得到所述第二比特序列。
  27. 根据权利要求16-25任意一项所述的方法，其特征在于，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
    若所述传输码型为所述PAM4，则将所述至少一个电平信号中每个电平信号逆映射为两个连续的比特，得到所述第二比特序列；
    其中，所述每个电平信号包括x、y、-x、-y中的一种；所述x和所述y的取值集合为{1，1/3}，且所述x和所述y取值不同；
    所述x逆映射为[a，b]，所述-x逆映射为[a’，b’]，所述y逆映射为[a’，b]，所述-y逆映射为[a，b’]；所述a’为所述a的二进制取反，所述b’为所述b的二进制取反，所述a和所述b的取值为0或1。
  28. 根据权利要求16-25任意一项所述的方法，其特征在于，所述根据传输码型，对 所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
    若所述传输码型为所述PAM8，则将所述至少一个电平信号中每个电平信号逆映射为三个连续的比特，得到所述第二比特序列；
    其中，所述每个电平信号包括s、-s、w、-w、z、-z、j、-j中的一种；所述s、所述w、所述z、所述j的取值集合为{1,5/7,3/7,1/7}，且所述s、所述w、所述z、所述j的取值互不相同；
    所述s逆映射为[a，b，c]，所述-s逆映射为[a’，b’，c’]，所述w逆映射为[a’，b，c]，所述-w逆映射为[a，b’，c’]，所述z逆映射为[a，b’，c]，所述-z逆映射为[a’，b，c’]，所述j逆映射为[a，b，c’]，所述-j逆映射为[a’，b’，c]；所述a’、所述b’、所述c’分别为所述a、所述b、所述c的二进制取反，所述a、所述b、所述c的取值为0或1。
  29. 根据权利要求16-25任意一项所述的方法，其特征在于，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
    若所述传输码型为所述PAM16，则将所述至少一个电平信号中每个电平信号逆映射为四个连续的比特，得到所述第二比特序列；
    其中，所述每个电平信号包括t、-t、p、-p、v、-v、u、-u、k、-k、i、-i、m、-m、n、-n中的一种；所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值互不相同；
    所述t逆映射为[a，b，c，d]，所述-t逆映射为[a’，b’，c’，d’]，所述p逆映射为[a’，b，c，d]，所述-p逆映射为[a，b’，c’，d’]，所述v逆映射为[a，b’，c，d]，所述-v逆映射为[a’，b，c’，d’]，所述u逆映射为[a，b，c’，d]，所述-u逆映射为[a’，b’，c，d’]，所述k逆映射为[a，b，c，d’]，所述-k逆映射为[a’，b’，c’，d]，所述i逆映射为[a’，b’，c，d]，所述-i逆映射为[a，b，c’，d’]，所述m逆映射为[a’，b，c’，d]，所述-m逆映射为[a，b’，c，d’]，所述n逆映射为[a’，b，c，d’]，所述-n逆映射为[a，b’，c’，d]；所述a’、所述b’、所述c’、所述d’分别为所述a、所述b、所述c、所述d的二进制取反，所述a、所述b、所述c、所述d的取值为0或1。
  30. 根据权利要求16-18任意一项所述的方法，其特征在于，所述直流平衡处理为预先配置的直流平衡方式，或，所述第二传输设备所支持的直流平衡方式。
  31. 一种第一传输设备，其特征在于，所述第一传输设备支持至少两种直流平衡方式，所述第一传输设备包括处理模块和收发模块；
    所述处理模块，用于对第一比特序列进行直流平衡处理，得到第二比特序列；
    所述处理模块，还用于根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号；
    所述收发模块，用于发送所述至少一个电平信号。
  32. 根据权利要求31所述的设备，其特征在于，所述对第一比特序列进行直流平衡处理，得到第二比特序列，包括：
    按照第一预设长度，将所述第一比特序列分流为M个第三比特序列，其中，所述M为大于0的整数；
    分别对所述M个第三比特序列进行线路编码，得到M个第四比特序列；
    按照预设符号长度对所述M个第四比特序列进行比特合并，得到所述第二比特序列。
  33. 根据权利要求31所述的设备，其特征在于，所述对第一比特序列进行直流平衡处理，得到第二比特序列时，包括：
    对所述第一比特序列进行格雷映射，得到格雷映射后的第一比特序列；
    对所述格雷映射后的第一比特序列进行预编码，得到所述第二比特序列。
  34. 根据权利要求31-33任意一项所述的设备，其特征在于，所述第一比特序列为加扰后的比特序列。
  35. 根据权利要求34所述的设备，其特征在于，所述加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，所述L为大于或等于1的整数。
  36. 根据权利要求35所述的设备，其特征在于，所述第二预设长度为里德所罗门RS符号的整数倍。
  37. 根据权利要求35所述的设备，其特征在于，所述L为M的整数倍。
  38. 根据权利要求31或32或37所述的设备，其特征在于，
    若M为1，所述传输码型为非归零调制NRZ，或，2阶脉冲幅度调制PAM2；
    若M为2，所述传输码型为4阶脉冲幅度调制PAM4；
    若M为3，所述传输码型为8阶脉冲幅度调制PAM8；
    若M为4，所述传输码型为16阶脉冲幅度调制PAM16。
  39. 根据权利要求32所述的设备，其特征在于，所述第一预设长度为所述预设符号长度的整数倍，所述预设符号长度根据所述线路编码确定。
  40. 根据权利要求39所述的设备，其特征在于，
    若所述线路编码为8B/10B，则所述预设符号长度为8比特；
    若所述线路编码为9B/10B，则所述预设符号长度为9比特。
  41. 根据权利要求31-40任意一项所述的设备，其特征在于，所述根据传输码型，对 所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
    若所述传输码型为所述NRZ或所述PAM2，则将所述第二比特序列中一个比特映射为一个电平信号，得到所述至少一个电平信号。
  42. 根据权利要求31-40任意一项所述的设备，其特征在于，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
    若所述传输码型为所述PAM4，则将所述第二比特序列中每两个连续比特映射为一个电平信号，得到所述至少一个电平信号；
    其中，所述每两个连续比特包括[a，b]、[a’，b’]、[a’，b]、[a，b’]中的一种；所述[a，b]映射为x，所述[a’，b’]映射为-x，所述[a’，b]映射为y，所述[a，b’]映射为-y；所述a’为所述a的二进制取反，所述b’为所述b的二进制取反，所述a和所述b的取值为0或1，所述x和所述y的取值集合为{1，1/3}，且所述x和所述y取值不同。
  43. 根据权利要求31-40任意一项所述的设备，其特征在于，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
    若所述传输码型为所述PAM8，则将所述第二比特序列中每三个连续比特映射为一个电平信号，得到所述至少一个电平信号；
    其中，所述每三个连续比特包括[a，b，c]、[a’，b’，c’]、[a’，b，c]、[a，b’，c’]、[a，b’，c]、[a’，b，c’]、[a，b，c’]、[a’，b’，c]中的一种；所述[a，b，c]映射为s，所述[a’，b’，c’]映射为-s，所述[a’，b，c]映射为w，所述[a，b’，c’]映射为-w，所述[a，b’，c]映射为z，所述[a’，b，c’]映射为-z，所述[a，b，c’]映射为j，所述[a’，b’，c]映射为-j；所述a’、所述b’、所述c’分别为所述a、所述b、所述c的二进制取反，所述a、所述b、所述c的取值为0或1，所述s、所述w、所述z、所述j的取值集合为{1,5/7,3/7,1/7}，且所述s、所述w、所述z、所述j的取值互不相同。
  44. 根据权利要求31-40任意一项所述的设备，其特征在于，所述根据传输码型，对所述第二比特序列进行符号映射，得到至少一个电平信号，包括：
    若所述传输码型为所述PAM16，则将所述第二比特序列中每四个连续比特映射为一个电平信号，得到所述至少一个电平信号；
    其中，所述每四个连续比特包括[a，b，c，d]、[a’，b’，c’，d’]、[a’，b，c，d]、[a，b’，c’，d’]、[a，b’，c，d]、[a’，b，c’，d’]、[a，b，c’，d]、[a’，b’，c，d’]、[a，b，c，d’]、[a’，b’，c’，d]、[a’，b’，c，d]、[a，b，c’，d’]、[a’，b，c’，d]、[a，b’，c，d’]、[a’，b，c，d’]、[a，b’，c’，d]中的一种；
    所述[a，b，c，d]映射为t，所述[a’，b’，c’，d’]映射为-t，所述[a’，b，c，d]映射为p，所述[a，b’，c’，d’]映射为-p，所述[a，b’，c，d]映射为v，所述[a’，b，c’，d’]映射为-v，所述[a，b，c’，d]映射为u，所述[a’，b’，c，d’]映射为-u，所述[a，b，c，d’]映射为k，所述[a’，b’，c’，d]映射为-k，所述[a’，b’，c，d]映射为i，所述[a，b，c’，d’]映射为-i，所述[a’，b，c’，d]映射为m，所述[a，b’，c，d’]映射为-m，所述[a’，b，c， d’]映射为n，所述[a，b’，c’，d]映射为-n；
    所述a’、所述b’、所述c’、所述d’分别为所述a、所述b、所述c、所述d的二进制取反，所述a、所述b、所述c、所述d的取值为0或1，所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值互不相同。
  45. 根据权利要求31-33任意一项所述的设备，其特征在于，所述直流平衡处理为预先配置的直流平衡方式，或，根据接收到的指示信息确定的直流平衡方式；所述指示信息是所述第二传输设备发送的。
  46. 一种第二传输设备，其特征在于，所述第二传输设备包括收发模块和处理模块，
    所述收发模块，用于接收至少一个电平信号；
    所述处理模块，用于根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列；
    所述处理模块，还用于对所述第二比特序列进行解直流平衡处理，得到第一比特序列，所述直流平衡处理属于第一传输设备支持的至少两种直流平衡方式。
  47. 根据权利要求46所述的设备，其特征在于，所述对所述第二比特序列进行解直流平衡处理，得到第一比特序列，包括：
    按照预设符号长度对所述第二比特序列进行分流，得到M个第四比特序列，其中，所述M为大于0的整数；
    分别对所述M个第四比特序列进行解线路编码，得到M个第三比特序列；
    将所述M个第三比特序列按照第一预设长度进行合并，得到所述第一比特序列。
  48. 根据权利要求46所述的设备，其特征在于，所述对所述第二比特序列进行解直流平衡处理，得到第一比特序列，包括：
    对所述第二比特序列进行预编码解码，得到解码后的第二比特序列；
    对所述解码后的第二比特序列进行解格雷映射，得到所述第一比特序列。
  49. 根据权利要求46-48任意一项所述的设备，其特征在于，所述第一比特序列为加扰后的比特序列。
  50. 根据权利要求49所述的设备，其特征在于，所述加扰后的比特序列是按照第二预设长度，经过交织深度为L的符号交织后进行加扰的比特序列，所述L为大于或等于1的整数。
  51. 根据权利要求50所述的设备，其特征在于，所述第二预设长度为里德所罗门RS符号的整数倍。
  52. 根据权利要求49所述的设备，其特征在于，所述L为M的整数倍。
  53. 根据权利要求46或47或52所述的设备，其特征在于，
    若M为1，所述传输码型为非归零调制NRZ，或，2阶脉冲幅度调制PAM2；
    若M为2，所述传输码型为4阶脉冲幅度调制PAM4；
    若M为3，所述传输码型为8阶脉冲幅度调制PAM8；
    若M为4，所述传输码型为16阶脉冲幅度调制PAM16。
  54. 根据权利要求46所述的设备，其特征在于，所述第一预设长度为所述预设符号长度的整数倍，所述预设符号长度根据所述线路编码确定。
  55. 根据权利要求54所述的设备，其特征在于，
    若所述线路编码为8B/10B，则所述预设符号长度为8比特；
    若所述线路编码为9B/10B，则所述预设符号长度为9比特。
  56. 根据权利要求46-55任意一项所述的设备，其特征在于，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
    若所述传输码型为所述NRZ或所述PAM2，则将所述至少一个电平信号中每个电平信号逆映射为一个比特，得到所述第二比特序列。
  57. 根据权利要求46-55任意一项所述的设备，其特征在于，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
    若所述传输码型为所述PAM4，则将所述至少一个电平信号中每个电平信号逆映射为两个连续的比特，得到所述第二比特序列；
    其中，所述每个电平信号包括x、y、-x、-y中的一种；所述x和所述y的取值集合为{1，1/3}，且所述x和所述y取值不同；
    所述x逆映射为[a，b]，所述-x逆映射为[a’，b’]，所述y逆映射为[a’，b]，所述-y逆映射为[a，b’]；所述a’为所述a的二进制取反，所述b’为所述b的二进制取反，所述a和所述b的取值为0或1。
  58. 根据权利要求46-55任意一项所述的设备，其特征在于，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
    若所述传输码型为所述PAM8，则将所述至少一个电平信号中每个电平信号逆映射为三个连续的比特，得到所述第二比特序列；
    其中，所述每个电平信号包括s、-s、w、-w、z、-z、j、-j中的一种；所述s、所述w、所述z、所述j的取值集合为{1,5/7,3/7,1/7}，且所述s、所述w、所述z、所述j的取值互不相同；
    所述s逆映射为[a，b，c]，所述-s逆映射为[a’，b’，c’]，所述w逆映射为[a’，b，c]，所述-w逆映射为[a，b’，c’]，所述z逆映射为[a，b’，c]，所述-z逆映射为[a’，b，c’]，所述j逆映射为[a，b，c’]，所述-j逆映射为[a’，b’，c]；所述a’、所述b’、所述c’分别为所述a、所述b、所述c的二进制取反，所述a、所述b、所述c的取值为0或1。
  59. 根据权利要求46-55任意一项所述的设备，其特征在于，所述根据传输码型，对所述至少一个电平信号进行符号逆映射，得到第二比特序列，包括：
    若所述传输码型为所述PAM16，则将所述至少一个电平信号中每个电平信号逆映射为四个连续的比特，得到所述第二比特序列；
    其中，所述每个电平信号包括t、-t、p、-p、v、-v、u、-u、k、-k、i、-i、m、-m、n、-n中的一种；所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值集合为{1,13/15,11/15,9/15,7/15,1/3,1/5,1/15}，且所述t、所述p、所述v、所述u、所述k、所述i、所述m、所述n的取值互不相同；
    所述t逆映射为[a，b，c，d]，所述-t逆映射为[a’，b’，c’，d’]，所述p逆映射为[a’，b，c，d]，所述-p逆映射为[a，b’，c’，d’]，所述v逆映射为[a，b’，c，d]，所述-v逆映射为[a’，b，c’，d’]，所述u逆映射为[a，b，c’，d]，所述-u逆映射为[a’，b’，c，d’]，所述k逆映射为[a，b，c，d’]，所述-k逆映射为[a’，b’，c’，d]，所述i逆映射为[a’，b’，c，d]，所述-i逆映射为[a，b，c’，d’]，所述m逆映射为[a’，b，c’，d]，所述-m逆映射为[a，b’，c，d’]，所述n逆映射为[a’，b，c，d’]，所述-n逆映射为[a，b’，c’，d]；所述a’、所述b’、所述c’、所述d’分别为所述a、所述b、所述c、所述d的二进制取反，所述a、所述b、所述c、所述d的取值为0或1。
  60. 根据权利要求46-48任意一项所述的设备，其特征在于，所述直流平衡处理为预先配置的直流平衡方式，或，第二传输设备所支持的直流平衡方式。
  61. 一种通信装置，其特征在于，包括处理器和存储器，所述处理器调用所述存储器中存储的计算机程序实现如权利要求1-15或16-30任一项所述的方法。
  62. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机程序，当所述计算机程序被运行时，实现如权利要求1-15或16-30任一项所述的方法。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101312385A (zh) * 2007-05-23 2008-11-26 华为技术有限公司 信息编码译码方法及装置
US20100202555A1 (en) * 2009-02-10 2010-08-12 Hiroshi Takahashi Transmission device
WO2019076340A1 (en) * 2017-10-18 2019-04-25 Zte Corporation FRAME HEADERS FOR MULTI-LEVEL MODULATED SIGNALS IN PASSIVE OPTICAL NETWORKS
CN110784266A (zh) * 2019-10-17 2020-02-11 烽火通信科技股份有限公司 一种匹配码型的调制解调方法及超高速光模块

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101312385A (zh) * 2007-05-23 2008-11-26 华为技术有限公司 信息编码译码方法及装置
US20100202555A1 (en) * 2009-02-10 2010-08-12 Hiroshi Takahashi Transmission device
WO2019076340A1 (en) * 2017-10-18 2019-04-25 Zte Corporation FRAME HEADERS FOR MULTI-LEVEL MODULATED SIGNALS IN PASSIVE OPTICAL NETWORKS
CN110784266A (zh) * 2019-10-17 2020-02-11 烽火通信科技股份有限公司 一种匹配码型的调制解调方法及超高速光模块

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