WO2022190702A1

WO2022190702A1 - Level shift circuit and electronic device

Info

Publication number: WO2022190702A1
Application number: PCT/JP2022/003479
Authority: WO
Inventors: 大輔宮崎
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2021-03-08
Filing date: 2022-01-31
Publication date: 2022-09-15
Also published as: JPWO2022190702A1

Abstract

[Problem] To reduce power consumption. [Solution] This level shift circuit is provided with two transistors of different conductivity types, connected in a cascode connection between two reference voltages having different voltage levels, a signal input unit that supplies, via a capacitor, an input signal having a high or a low voltage level to at least one of two control terminals of each of the two transistors, and an impedance unit that biases the voltage level of the control terminal to which the input signal is supplied via the capacitor to a predetermined voltage level.

Description

Level shift circuit and electronic equipment

Embodiments according to the present disclosure relate to level shift circuits and electronic devices.

The level shift circuit outputs a signal obtained by converting the voltage level of the input signal. As an example of the configuration of the level shift circuit, the use of a cross-couple configuration is known (see, for example, Patent Document 1).

JP-A-4-97616 JP 2004-242084 A

However, the cross-couple configuration has a problem of increased power consumption because a through current flows at the timing when the voltage level of the input signal changes.

Therefore, the present disclosure provides a level shift circuit and an electronic device capable of reducing power consumption.

In order to solve the above problems, according to the present disclosure,
two transistors of different conductivity types cascoded between two reference voltages having different voltage levels;
a signal input unit that supplies an input signal having a high-level or low-level voltage level through a capacitor to at least one of two control terminals of the two transistors, respectively;
and an impedance section for biasing the voltage level of the control terminal to which the input signal is supplied via the capacitor to a predetermined voltage level.

The impedance section may be biased based on the voltage level of the reference voltage of the transistor having the control terminal to which the input signal is supplied via the capacitor.

The impedance section is provided between the control terminal to which the input signal is supplied via the capacitor and the reference voltage of the transistor having the control terminal to which the input signal is supplied via the capacitor. may be connected.

The impedance section may have an impedance equal to or higher than a predetermined value.

The two transistors are
a first transistor on the first reference voltage side;
a second transistor on a second reference voltage side having a voltage level different from the first reference voltage;
The signal input section supplies the input signal to a first control terminal of the first transistor through the capacitor and supplies the input signal to a second control terminal of the second transistor without the capacitor. death,
The impedance section may bias the voltage level of the first control terminal to a predetermined voltage level.

Either the high level or the low level of the input signal may be the same as the voltage level of either the first reference voltage or the second reference voltage.

The two transistors are
a first transistor on the first reference voltage side;
a second transistor on a second reference voltage side having a voltage level different from the first reference voltage;
The signal input section supplies the input signal to a first control terminal of the first transistor via a first capacitor, and the second control terminal of the second transistor via a second capacitor different from the first capacitor. supplying the input signal to a control terminal;
The impedance section is
a first impedance unit that biases the voltage level of the first control terminal to a predetermined voltage level;
and a second impedance section for biasing the voltage level of the second control terminal to a predetermined voltage level.

The high level and low level of the input signal may be different from the voltage levels of the first reference voltage and the second reference voltage.

The first reference voltage and the second reference voltage may be a positive voltage and a negative voltage, respectively, or may be a negative voltage and a positive voltage, respectively.

a signal output unit connected between the two cascode-connected transistors for outputting an output signal obtained by converting the voltage level of the input signal;
a high impedance detection unit that detects that the signal output unit is high impedance;
A logic fixer that fixes the voltage level of the output signal to one of the two reference voltages when the signal output section has a high impedance.

a signal output unit connected between the two cascode-connected transistors for outputting an output signal obtained by converting the voltage level of the input signal;
a level detection unit that detects the voltage level of at least one of the input signal and the two control terminals;
When the voltage level of the input signal and at least one of the two control terminals continues at a high level or a low level for a predetermined period or longer, the voltage level of the output signal is set to either one of the two reference voltages. and a logic fixer that fixes the level.

The impedance section may be a transistor whose control terminal is connected to one of the two reference voltages.

The impedance unit is a diode,
the anode of the diode is electrically connected to the lower voltage side of the two reference voltages;
A cathode of the diode may be electrically connected to a higher voltage side of the two reference voltages.

The impedance unit is a resistive element,
The resistance element may have a resistance value corresponding to the operating frequency of the level shift circuit and the capacitance of the capacitor.

The resistance element may have a resistance value such that a cutoff frequency of a high-pass filter of the resistance element and the capacitor is lower than an operating frequency of the level shift circuit.

It may further include a logic inverting section that supplies the input signal with its high level and low level inverted to each of the two control terminals.

The voltage level of the input signal may alternately become high level or low level according to time.

According to the present disclosure, a DAC (Digital to Analog Converter) that converts a digital signal to an analog signal;
a level shift circuit that converts the voltage level range of the input digital signal into the voltage level range of the analog signal and outputs the converted voltage level range to the DAC;
The level shift circuit is
two transistors of different conductivity types cascoded between two reference voltages having different voltage levels;
a signal input unit that supplies an input signal having a high-level or low-level voltage level through a capacitor to at least one of two control terminals of the two transistors, respectively;
and an impedance section that biases the voltage level of the control terminal to which the input signal is supplied via the capacitor to a predetermined voltage level.

It is a block diagram showing an example of composition of electronic equipment in a 1st embodiment. 2 is a circuit diagram showing an example of the configuration of a first level shift circuit in the first embodiment; FIG. 4 is a timing chart showing an example of the operation of the first level shift circuit in the first embodiment; 4 is a circuit diagram showing an example of the configuration of a second level shift circuit in the first embodiment; FIG. 4 is a timing chart showing an example of the operation of the second level shift circuit in the first embodiment; FIG. 4 is a circuit diagram showing an example of a configuration of a first level shift circuit in a comparative example; 7 is a timing chart showing an example of the operation of the first level shift circuit in the comparative example; It is a circuit diagram showing an example of the configuration of a first level shift circuit in the second embodiment. It is a circuit diagram showing an example of the configuration of a second level shift circuit in the second embodiment. It is a circuit diagram showing an example of the configuration of a first level shift circuit in the third embodiment. FIG. 11 is a circuit diagram showing an example of the configuration of a level shift circuit according to a fourth embodiment; FIG. FIG. 11 is a circuit diagram showing an example of the configuration of a level shift circuit according to a fifth embodiment; FIG. 14 is a circuit diagram showing an example of a configuration of a first level shift circuit in a sixth embodiment; FIG. FIG. 14 is a circuit diagram showing an example of a configuration of a first level shift circuit in a seventh embodiment; FIG.

Embodiments of a level shift circuit and an electronic device will be described below with reference to the drawings. Although the main components of the level shift circuit and the electronic device will be mainly described below, the level shift circuit and the electronic device may have components and functions that are not illustrated or described. The following description does not exclude components or features not shown or described.

(First embodiment)
FIG. 1 is a block diagram showing an example of the configuration of an electronic device 1 according to the first embodiment.

The electronic device 1 is, for example, a multi-bit audio DAC (Digital to Analog Converter). The electronic device 1 includes a signal processing section 10 , a level shift circuit 20 and a DAC 30 . An amplifier 40 and a speaker 50 are also connected to the electronic device 1 .

The signal processing unit 10 digitally processes the input audio data. The signal processing unit 10 converts a voice signal (audio signal) into a multi-bit (for example, 192-bit) digital signal.

The level shift circuit 20 converts the voltage level range of the input digital signal from the digital power domain to the analog power domain. A power domain is a plurality of regions with different voltage level ranges that are managed separately. Level shift circuit 20 includes a first level shift circuit 21 and a second level shift circuit 22 .

The first level shift circuit 21 converts the voltage level of the digital signal on the high voltage side from the reference voltage DVDD to the reference voltage VDDH. The voltage level of reference voltage VDDH is a positive voltage and is higher than the voltage level of reference voltage DVDD. Details of the first level shift circuit 21 will be described later with reference to FIGS. 2 and 3. FIG.

The second level shift circuit 22 converts the voltage level of the digital signal on the low voltage side from the ground (reference voltage) GND to the reference voltage VDDM. The voltage level of reference voltage VDDM is a negative voltage and lower than the voltage level of ground GND. The second level shift circuit 22 converts the voltage level in a range different from that of the first level shift circuit 21 , but converts the voltage level in substantially the same manner as the first level shift circuit 21 . Details of the second level shift circuit 22 will be described later with reference to FIGS. 4 and 5. FIG.

The DAC 30 converts the level-shifted digital signal into an analog signal.

The amplifier 40 amplifies the analog signal to drive the speaker 50 .

The speaker 50 receives the amplified analog signal and reproduces the sound.

Next, the details of the first level shift circuit 21 will be described.

FIG. 2 is a circuit diagram showing an example of the configuration of the first level shift circuit 21 in the first embodiment. The first level shift circuit 21 converts an input signal Din having a voltage level from the reference voltage DVDD to the ground GND into an output signal Dout having a voltage level from the reference voltage VDDH to the ground GND. The first level shift circuit 21 level-shifts the high voltage level of the input signal Din from the reference voltage DVDD to the reference voltage VDDH. The low voltage levels of input signal Din and output signal Dout are common at ground GND.

The first level shift circuit 21 includes transistors MN1 and MP1, a capacitor C, a signal input section Ein, a signal output section Eout, a logic inverting element INV, and an impedance section 201.

The two transistors MN1 and MP1 are cascode-connected between the reference voltage VDDH and the ground GND. Also, the two transistors MN1 and MP1 have different conductivity types.

The transistor MN1 is arranged on the ground GND side. The transistor MN1 is, for example, an N-type MOS (Metal Oxide Semiconductor) transistor.

The transistor MP1 is arranged on the reference voltage VDDH side. Transistor MP1 is, for example, a P-type MOS transistor.

A capacitor C is connected between the gate of the transistor MN1 and the gate of the transistor MP1.

An input signal Din having a high or low voltage level is input to the signal input section Ein. The signal input section Ein supplies an input signal Din through a capacitor C to at least one of the two gates of the two transistors MN1 and MP1. If the input signal Din is a PWM (Pulse Width Modulation) modulated audio signal, the voltage level of the input signal Din alternately becomes high or low at each modulation time.

The signal output unit Eout is connected between two cascode-connected transistors MN1 and MP1, and outputs an output signal Dout.

The logic inverting element INV inverts the logic of the inputted input signal Din and outputs it. The logic inverting element INV supplies an input signal Din whose voltage level is inverted between high and low to each of the two gates of the transistors MN1 and MP1. The logic inverting element INV is connected between the signal input Ein, the capacitor C and the gate of the transistor MN1. A logic inverting element INV (signal input section Ein) is connected to the gate of the transistor MP1 with a capacitor C interposed therebetween. The logic inverting element INV (signal input section Ein) is connected to the gate of the transistor MN1 without the capacitor C interposed therebetween.

The impedance section 201 is an impedance element. More specifically, the impedance section 201 is a high impedance element having an impedance equal to or higher than a predetermined value. The impedance section 201 is connected between the gate of the transistor MP1, the capacitor C, and the reference voltage VDDH. Impedance unit 201 biases the voltage level of the gate of transistor MP1 based on reference voltage VDDH. More specifically, impedance section 201 biases (clamps) the voltage level of the gate of transistor MP1 to a predetermined voltage level. The impedance unit 201 is, for example, an off transistor (diode-connected transistor) whose gate and source are connected. The impedance unit 201 is a transistor MP2 whose gate is connected to the reference voltage VDDH. Transistor MP2 is, for example, a P-type MOS transistor.

Next, the operation of the first level shift circuit 21 will be described.

FIG. 3 is a timing chart showing an example of the operation of the first level shift circuit 21 in the first embodiment.

First, at time t1 in the initial state, the voltage level of input signal Din is low and ground GND. The voltage level of the node NA (A in FIG. 3) is the high level obtained by inverting the voltage level of the input signal Din by the logic inverting element INV, and is the reference voltage DVDD. The voltage level of node NB (B in FIG. 3) is high, as is the voltage level of node NA. The voltage level of the node NB is the voltage level Vp2 higher than the reference voltage VDDH by the threshold voltage Vth of the transistor MP2. This is because the voltage level of node NB is clamped by transistor MP2, as will be described later.

The voltage level of the node NA is higher than the voltage level Vn1 which is higher than the ground GND by the threshold voltage Vth of the transistor MN1. Therefore, transistor MN1 is on. Also, the voltage level of the node NB is higher than the voltage level Vp1 which is lower than the reference voltage VDDH by the threshold voltage Vth of the transistor MP1. Therefore, transistor MP1 is off. This causes the voltage level of the output signal Dout to be low and ground GND.

Next, at time t2, the voltage level of the input signal Din changes from low to high and reaches the reference voltage DVDD. The voltage level of the node NA becomes low by inverting the voltage level of the input signal Din by the logic inverting element INV, and becomes the ground GND. Due to capacitive coupling, the voltage level of node NB lowers as the voltage level of node NA lowers. Therefore, the voltage level of node NB becomes low.

When the voltage level of the node NA becomes lower than the voltage level Vn1, the transistor MN1 is turned off. When the voltage level of node NB becomes lower than voltage level Vp1, transistor MP1 is turned on. As a result, the voltage level of the output signal Dout changes from low to high to reach the reference voltage VDDH.

Here, the impedance unit 201 biases the voltage level of the gate based on the voltage level of the reference voltage VDDH of the transistor MP1 having the gate to which the input signal Din is supplied via the capacitor C. That is, when the voltage level of input signal Din is low, the high voltage level of node NB (gate voltage of transistor MP1) is constrained (clamped) to voltage level Vp2 by transistor MP2. This makes the voltage level of the node NB lower than the voltage level Vp1 by going low. That is, the transistor MP1 can be turned on. As a result, the voltage level of the output signal Dout can be made high at time t2.

Next, at time t3, the voltage level of the input signal Din changes from high to low to ground GND. The voltage level of the node NA becomes high by inverting the voltage level of the input signal Din by the logic inverting element INV, and becomes the reference voltage DVDD. Due to capacitive coupling, the voltage level of node NB rises as the voltage level of node NA rises. Therefore, the voltage level at node NB goes high and is clamped to voltage level Vp2 as described above. Therefore, as at time t1, the voltage level of the output signal Dout goes low and goes to ground GND.

Next, the details of the second level shift circuit 22 will be described.

FIG. 4 is a circuit diagram showing an example of the configuration of the second level shift circuit 22 in the first embodiment. The second level shift circuit 22 converts the input signal Din with a voltage level from the reference voltage VDDH to the ground GND into an output signal Dout with a voltage level from the reference voltage VDDH to the reference voltage VDDM. The first level shift circuit 21 level-shifts the low voltage level of the input signal Din from the ground GND to the reference voltage VDDM. The high voltage level of the input signal Din and the output signal Dout is common at the reference voltage VDDH.

The logic inverting element INV is connected between the signal input section Ein, the capacitor C and the gate of the transistor MP1. A logic inverting element INV (signal input section Ein) is connected to the gate of the transistor MN1 with a capacitor C interposed therebetween. The logic inverting element INV (signal input section Ein) is connected to the gate of the transistor MP1 without the capacitor C interposed therebetween.

The impedance section 201 is connected between the gate of the transistor MN1, the capacitor C, and the reference voltage VDDM. Impedance unit 201 biases the voltage level of the gate of transistor MN1 based on reference voltage VDDM. More specifically, impedance section 201 biases (clamps) the voltage level of the gate of transistor MN1 to a predetermined voltage level. The impedance unit 201 is, for example, an off transistor having a gate and a source connected to each other. Impedance unit 201 is transistor MN2 whose gate is connected to reference voltage VDDM. The transistor MN2 is, for example, an N-type MOS transistor.

FIG. 5 is a timing chart showing an example of the operation of the second level shift circuit 22 in the first embodiment.

The operation of the second level shift circuit 22 is substantially the same as the operation of the first level shift circuit 21 described with reference to FIG. The low voltage level of node NB (B in FIG. 5) is clamped to a voltage level lower than reference voltage VDDM by the threshold voltage Vth of transistor MN2. As a result, the voltage level of the node NB becomes high, so that the transistor MN1 can be turned on.

As described above, according to the level shift circuit of the first embodiment, the transistor MP1 or the transistor MN1 is driven via the capacitor C. Also, the impedance unit 201 biases the gate voltage of the transistor MP1 or the transistor MP2 driven through the capacitor C. FIG. As a result, the voltage level can be converted almost without passing through current. As a result, power consumption can be suppressed.

(Comparative example)
FIG. 6 is a circuit diagram showing an example of the configuration of the first level shift circuit 21 in the comparative example. The first level shift circuit 21 in the comparative example has a cross-couple configuration.

In the example shown in FIG. 6, the first level shift circuit 21 includes two cross-coupled P-type MOS transistors (transistors MPa, MPb) and two N-type MOS transistors (transistors MNa, MNb).

An input signal Din that has passed through two logic inverting elements INV1 and INV2 is input to the gate of the transistor MNa. An input signal Din that has passed through one logic inverting element INV1 is input to the gate of the transistor MNb.

FIG. 7 is a timing chart showing an example of the operation of the first level shift circuit 21 in the comparative example.

First, at time t11 in the initial state, the voltage level of input signal Din is low. The voltage level at the gate of transistor MNa (FIG. 7A) is low and the voltage level at the gate of transistor MNb (FIG. 7B) is high. Therefore, the transistors MNb and MPa are on, and the transistors MNa and MPb are off. The voltage level of output signal Dout is low.

Next, at time t12, the voltage level of input signal Din changes from low to high. The voltage level at the gate of transistor MNa (A in FIG. 7) goes from low to high, and the voltage level at the gate of transistor MNb (B in FIG. 7) goes from high to low. As a result, a current Ia flows through the transistors MPa and MNa that are on. After that, the transistor MPa is turned off and the transistor MPb is turned on. This causes the voltage level of the output signal Dout to change from low to high.

At time t13, even when the voltage level of input signal Din changes from high to low, current Ib flows through transistors MPb and MNb.

Thus, in the cross-couple configuration, a through current flows at the timing when the voltage level of the input signal Din changes to high or low (logic). This through current increases the power consumption of the level shift circuit.

In contrast, in the first embodiment, the gate voltage of transistor MP1 or transistor MN1 is driven by capacitive coupling without using the cross-couple configuration. As a result, it is possible to substantially prevent the through current from flowing. As a result, power consumption can be suppressed. Also, in the first embodiment, the number of transistors is three as shown in FIG. 2 or 4, and the number of transistors can be reduced compared to the cross-couple configuration shown in FIG.

As a method for reducing the through current, for example, as in Patent Document 1, a method of using a current source in the cross-couple part and limiting the through current by the current source has been proposed. However, with this method, it is impossible to completely eliminate the feed-through current component, and the operating frequency is slowed down by limiting the current.

On the other hand, in the first embodiment, the through current can be made almost zero by the capacitor C. Moreover, since current limitation is not performed, the level shift circuit can be operated at higher speed.

In addition, the effect of reducing power consumption by suppressing through current increases as the number of level shift signals (the number of level shift circuits) increases. For example, in a multi-bit audio DAC for audio use as shown in FIG. 1, 192 level shift circuits corresponding to 192 bits are used.

Although the transistors MN1, MP1, MN2, and MP2 are MOS transistors, they are not limited to this, and may be bipolar transistors.

Also, the impedance section 201 is not limited to a transistor, and may be another impedance element.

(Second embodiment)
FIG. 8 is a circuit diagram showing an example of the configuration of the first level shift circuit 21 in the second embodiment. 2nd Embodiment differs in the structure of the impedance part 201 compared with 1st Embodiment.

The impedance section 201 is, for example, a reverse diode. Impedance section 201 is diode D1. The anode of the diode D1 is electrically connected to the low voltage side (ground GND side), and the cathode of the diode D1 is electrically connected to the high voltage side (reference voltage VDDH side). Diode D1 functions in much the same way as transistor MP2 of FIG. 2 described in the first embodiment. That is, diode D1 clamps the voltage level of the gate of transistor MP1 based on reference voltage VDDH.

FIG. 9 is a circuit diagram showing an example of the configuration of the second level shift circuit 22 in the second embodiment.

The impedance section 201 is a diode D2. The anode of diode D2 is arranged on the low voltage side and electrically connected to reference voltage VDDM. The cathode of the diode D2 is arranged on the high voltage side and electrically connected to the reference voltage VDDH. Diode D2 functions in much the same way as transistor MN2 of FIG. 4 described in the first embodiment. That is, diode D2 clamps the voltage level of the gate of transistor MN1 based on reference voltage VDDM.

(Third embodiment)
FIG. 10 is a circuit diagram showing an example of the configuration of the first level shift circuit 21 according to the third embodiment. 3rd Embodiment differs in the structure of the impedance part 201 compared with 1st Embodiment.

The impedance section 201 is, for example, a resistance element R. Resistive element R functions together with capacitor C as a high-pass filter. In this case, it is preferable that the lower limit of the cutoff frequency of the high-pass filter is sufficiently lower than the operating frequency. The lower limit of the cut-off frequency of the high-pass filter is preferably, for example, 1/10 of the operating frequency. That is, the resistance value of the resistance element R is set according to the operating frequency of the level shift circuit and the capacitance of the capacitor C, for example, so as to obtain a desired cutoff frequency of the high-pass filter. More specifically, the resistance element R preferably has a resistance value such that the cutoff frequency of the high-pass filter of the resistance element R and the capacitor C is lower than the operating frequency of the level shift circuit.

In a high-pass filter, a change in voltage is usually converted into a current by a capacitor, and this current is converted into a voltage by flowing through a resistive element. 10, the voltage level at the gate of transistor MP1 is biased by the voltage level of reference voltage VDDH and the voltage of resistive element R. In FIG. That is, the resistance element R, which is the impedance section 201, can bias the voltage level of the gate of the transistor MP1. The resistance value of the resistance element R is set, for example, according to the operating frequency of the level shift circuit and the capacitance of the capacitor C so that a desired voltage of the resistance element R can be obtained.

Note that the impedance section 201 of the second level shift circuit 22 may also be the resistance element R.

(Fourth embodiment)
FIG. 11 is a circuit diagram showing an example of the configuration of the level shift circuit 20 according to the fourth embodiment. Compared to the first embodiment, the fourth embodiment simultaneously converts the voltage level of the first level shift circuit 21 and the voltage level of the second level shift circuit 22 .

The level shift circuit 20 converts the input signal Din at the voltage level from the reference voltage DVDD to the ground GND into the output signal Dout at the voltage level from the reference voltage VDDH to the reference voltage VDDM. The first level shift circuit 21 level-shifts the high voltage level of the input signal Din from the reference voltage DVDD to the reference voltage VDDH, and shifts the low voltage level of the input signal Din from the ground GND to the reference voltage VDDM. The high or low voltage level of the input signal Din is different from the voltage levels of the reference voltages VDDH and VDDM.

2 and 4 of the first embodiment, one of the high voltage level and the low voltage level of the input signal Din is common to one of the high voltage side and the low voltage side of the voltage level of the output signal Dout. In contrast, in the fourth embodiment, the two voltage levels of the output signal Dout are different from the two voltage levels of the input signal Din.

The level shift circuit 20 includes capacitors C1 and C2 and

impedance units

2011 and 2012.

Capacitors C1 and C2 are connected in series between the gate of transistor MP1 and the gate of transistor MN1. Capacitors C1 and C2 are arranged corresponding to the two transistors MP1 and MN1, respectively.

The capacitor C1 is connected between the signal input section Ein, the transistor MP1 and the impedance section 2011. Therefore, the logic inverting element INV (signal input section Ein) is connected to the gate of the transistor MP1 via the capacitor C1. Capacitor C1 corresponds to capacitor C described with reference to FIG. 2 of the first embodiment.

The capacitor C2 is arranged between the signal input section Ein, the transistor MN1 and the impedance section 2012. Therefore, the logic inverting element INV (signal input section Ein) is connected to the gate of the transistor MN1 via the capacitor C2. Capacitor C2 corresponds to capacitor C described with reference to FIG. 4 of the first embodiment.

Impedance units

2011 and 2012 bias the voltage levels of the respective gates of the two transistors MP1 and MN1.

The impedance section 2011 is connected between the capacitor C1 and the transistor MP1 and the reference voltage VDDH. Impedance section 2011 biases the gate of transistor MP1 to a predetermined voltage level. The impedance section 2011 corresponds to the impedance section 201 described with reference to FIG. 2 of the first embodiment.

The impedance section 2012 is connected between the capacitor C2 and the transistor MN1 and the reference voltage VDDM. Impedance section 2012 biases the gate of transistor MN1 to a predetermined voltage level. The impedance section 2012 corresponds to the impedance section 201 described with reference to FIG. 4 of the first embodiment.

In this way, the capacitors C1 and C2 and the

impedance units

2011 and 2012 may be provided on both the transistor MP1 side and the transistor MN1 side. As a result, the voltage levels on both the high voltage side and the low voltage side can be level-shifted. In addition, audio signals often change in voltage level between a positive voltage and a negative voltage with the ground GND interposed therebetween. Therefore, in the audio signal level shift circuit, level shift is performed in a range between a positive voltage (reference voltage VDDH) and a negative voltage (reference voltage VDDM).

(Fifth embodiment)
FIG. 12 is a circuit diagram showing an example of the configuration of the level shift circuit 20 according to the fifth embodiment. The fifth embodiment differs from the fourth embodiment in the configurations of

impedance units

2011 and 2012 .

The

impedance units

2011 and 2012 are diodes D1 and D2, respectively. Therefore, the fifth embodiment is a combination of the second and fourth embodiments.

(Sixth embodiment)
FIG. 13 is a circuit diagram showing an example of the configuration of the first level shift circuit 21 according to the sixth embodiment.

The first level shift circuit 21 further includes a HiZ (high impedance) detection circuit 202 and a logic fixing circuit 203 .

A HiZ detection circuit 202 as a high impedance detection section detects that the signal output section Eout is high impedance.

A logic fixing circuit 203 as a logic fixing section fixes the logic of the signal output section Eout. That is, the logic fixing circuit 203 fixes the voltage level of the output signal Dout to one of the two reference voltages when the signal output section Eout is in high impedance.

If the voltage level of the input signal Din is fixed (left) high, the voltage level of the node NB is fixed low. In this case, a leakage current may flow from the reference voltage VDDH through the transistor MP2 to the node NB, and the voltage level of the node NB may rise. In FIG. 3, when the voltage level of node NB exceeds voltage level Vp1, transistor MP1 is turned off. Therefore, both the transistors MP1 and MN1 are turned off, and the signal output section Eout becomes high impedance (floating state). When the signal output section Eout becomes high impedance, a through current may flow in the output destination circuit of the first level shift circuit 21 .

Therefore, the HiZ detection circuit 202 detects that the signal output section Eout is in high impedance, and the logic fixing circuit 203 fixes the logic of the output to the voltage level of the reference voltage VDDH. As a result, it is possible to suppress the output from becoming high impedance, and to suppress the through current from flowing in the circuit of the output destination.

The second level shift circuit 22 shown in FIG. 4 of the first embodiment may also be provided with the HiZ detection circuit 202 and the logic fixation circuit 203 . If the voltage level of input signal Din is fixed (left) low, the voltage level of node NB is fixed high. In this case, a leakage current may flow from the node NB through the transistor MN2 to the reference voltage VDDM, and the voltage level of the node NB may drop. In this case, since the transistor MN1 is turned off from the on state, the signal output section Eout becomes high impedance. Therefore, the logic fixing circuit 203 fixes the output logic to the voltage level of the reference voltage VDDM. As a result, it is possible to prevent the output from becoming high impedance in the second level shift circuit 22 as well, and it is possible to prevent a through current from flowing in the output destination circuit.

(Seventh embodiment)
FIG. 14 is a circuit diagram showing an example of the configuration of the first level shift circuit 21 according to the seventh embodiment. The seventh embodiment differs from the sixth embodiment in that the HiZ detection circuit 202 acquires the signal of the node NA.

A HiZ detection circuit 202 as a level detection unit detects the voltage level of the gate (node NA) of the transistor MN1.

The logic fixing circuit 203 fixes the voltage level of the output signal Dout to one of the two reference voltages when the voltage level of the gate of the transistor MN1 is low for a predetermined period or longer.

As described in the sixth embodiment, the input signal Din is fixed at high and the voltage levels of the gates of the transistors MN1 and MP1 are fixed at low, whereby the signal output section Eout becomes high impedance. Therefore, the voltage level of the gate of transistor MN1 may be used to determine the logic fixation of logic fixation circuit 203. FIG.

It should be noted that the logic fixing determination is not limited to the voltage level of the gate of the transistor MN1. The HiZ detection circuit 202 may detect, for example, the input signal Din or the voltage level of the gate (node NB) of the transistor MP1. The logic fixing circuit 203 may fix the logic of the signal output section Eout based on, for example, the input signal Din or the voltage level of the gate of the transistor MP1.

In addition, this technique can take the following structures.
(1) two transistors of different conductivity types cascode-connected between two reference voltages having different voltage levels;
a signal input unit that supplies an input signal having a high-level or low-level voltage level through a capacitor to at least one of two control terminals of the two transistors, respectively;
and an impedance unit that biases the voltage level of the control terminal to which the input signal is supplied via the capacitor to a predetermined voltage level.
(2) The level shift circuit according to (1), wherein the impedance section is biased based on the voltage level of the reference voltage of the transistor having the control terminal to which the input signal is supplied via the capacitor.
(3) The impedance section includes the reference voltage of the transistor having the control terminal to which the input signal is supplied via the capacitor, and the control terminal to which the input signal is supplied via the capacitor; The level shift circuit according to (1) or (2), which is connected between.
(4) The level shift circuit according to any one of (1) to (3), wherein the impedance section has an impedance equal to or greater than a predetermined value.
(5) the two transistors are
a first transistor on the first reference voltage side;
a second transistor on a second reference voltage side having a voltage level different from the first reference voltage;
The signal input section supplies the input signal to a first control terminal of the first transistor through the capacitor and supplies the input signal to a second control terminal of the second transistor without the capacitor. death,
The level shift circuit according to any one of (1) to (4), wherein the impedance section biases the voltage level of the first control terminal to a predetermined voltage level.
(6) The level shift circuit according to (5), wherein one of the high level and the low level of the input signal is the same as the voltage level of one of the first reference voltage and the second reference voltage. .
(7) the two transistors,
a first transistor on the first reference voltage side;
a second transistor on a second reference voltage side having a voltage level different from the first reference voltage;
The signal input section supplies the input signal to a first control terminal of the first transistor via a first capacitor, and the second control terminal of the second transistor via a second capacitor different from the first capacitor. supplying the input signal to a control terminal;
The impedance section is
a first impedance unit that biases the voltage level of the first control terminal to a predetermined voltage level;
A level shift circuit according to any one of (1) to (4), further comprising a second impedance section that biases the voltage level of the second control terminal to a predetermined voltage level.
(8) The level shift circuit according to (7), wherein the high level and low level of the input signal are different from the voltage levels of the first reference voltage and the second reference voltage.
(9) The level shift circuit according to (7) or (8), wherein the first reference voltage and the second reference voltage are a positive voltage and a negative voltage, respectively, or a negative voltage and a positive voltage, respectively.
(10) a signal output unit connected between the two cascode-connected transistors for outputting an output signal obtained by converting the voltage level of the input signal;
a high impedance detection unit that detects that the signal output unit is high impedance;
(1) to (9), further comprising a logic fixing unit that fixes the voltage level of the output signal to one of the two reference voltages when the signal output unit is high impedance. A level shift circuit according to any one of the preceding claims.
(11) a signal output unit connected between the two cascode-connected transistors for outputting an output signal obtained by converting the voltage level of the input signal;
a level detection unit that detects the voltage level of at least one of the input signal and the two control terminals;
When the voltage level of the input signal and at least one of the two control terminals continues at a high level or a low level for a predetermined period or longer, the voltage level of the output signal is set to either one of the two reference voltages. The level shift circuit according to any one of (1) to (9), further comprising a logic fixer that fixes the level.
(12) The level shift circuit according to any one of (1) to (11), wherein the impedance section is a transistor whose control terminal is connected to one of the two reference voltages.
(13) the impedance unit is a diode;
the anode of the diode is electrically connected to the lower voltage side of the two reference voltages;
The level shift circuit according to any one of (1) to (11), wherein the cathode of the diode is electrically connected to a higher voltage side of the two reference voltages.
(14) the impedance unit is a resistive element,
The level shift circuit according to any one of (1) to (11), wherein the resistance element has a resistance value corresponding to the operating frequency of the level shift circuit and the capacitance of the capacitor.
(15) The level shift circuit according to (14), wherein the resistive element has a resistance value such that a cutoff frequency of a high-pass filter of the resistive element and the capacitor is lower than an operating frequency of the level shift circuit.
(16) The device according to any one of (1) to (15), further comprising a logic inverting unit that supplies the input signal whose high level and low level are inverted to each of the two control terminals. level shift circuit.
(17) The level shift circuit according to any one of (1) to (16), wherein the voltage level of the input signal alternates between high level and low level depending on time.
(18) a DAC (Digital to Analog Converter) that converts a digital signal into an analog signal;
a level shift circuit that converts the voltage level range of the input digital signal into the voltage level range of the analog signal and outputs the converted voltage level range to the DAC;
The level shift circuit is
two transistors of different conductivity types cascoded between two reference voltages having different voltage levels;
a signal input unit that supplies an input signal having a high-level or low-level voltage level through a capacitor to at least one of two control terminals of the two transistors, respectively;
and an impedance section that biases the voltage level of the control terminal to which the input signal is supplied via the capacitor to a predetermined voltage level.

Aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, changes, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the content defined in the claims and equivalents thereof.

1 electronic device, 20 level shift circuit, 21 first level shift circuit, 22 second level shift circuit, 201 impedance section, 2011 impedance section, 2012 impedance section, 202 HiZ detection circuit, 203 logic fixed circuit, C capacitor, C1 capacitor , C2 Capacitor, D1 Diode, D2 Diode, Din Input signal, Dout Output signal, Ein Signal input section, Eout Signal output section, INV Inverting element, MN1 Transistor, MN2 Transistor, MP1 Transistor, MP2 Transistor, R Resistive element, GND Ground, DVDD Reference voltage, VDDH Reference voltage, VDDM Reference voltage

Claims

two transistors of different conductivity types cascoded between two reference voltages having different voltage levels;
a signal input unit that supplies an input signal having a high-level or low-level voltage level through a capacitor to at least one of two control terminals of the two transistors, respectively;
and an impedance unit that biases the voltage level of the control terminal to which the input signal is supplied via the capacitor to a predetermined voltage level.
2. The level shift circuit according to claim 1, wherein said impedance section is biased based on the voltage level of said reference voltage of said transistor having said control terminal to which said input signal is supplied via said capacitor.
The impedance section is provided between the control terminal to which the input signal is supplied via the capacitor and the reference voltage of the transistor having the control terminal to which the input signal is supplied via the capacitor. 2. The level shift circuit of claim 1, connected.
3. The level shift circuit according to claim 1, wherein said impedance section has an impedance equal to or greater than a predetermined value.
The two transistors are
a first transistor on the first reference voltage side;
a second transistor on a second reference voltage side having a voltage level different from the first reference voltage;
The signal input section supplies the input signal to a first control terminal of the first transistor through the capacitor and supplies the input signal to a second control terminal of the second transistor without the capacitor. death,
2. The level shift circuit of claim 1, wherein said impedance section biases the voltage level of said first control terminal to a predetermined voltage level.
6. The level shift circuit according to claim 5, wherein one of the high level and low level of the input signal is the same as the voltage level of one of the first reference voltage and the second reference voltage.
The two transistors are
a first transistor on the first reference voltage side;
a second transistor on a second reference voltage side having a voltage level different from the first reference voltage;
The signal input section supplies the input signal to a first control terminal of the first transistor via a first capacitor, and the second control terminal of the second transistor via a second capacitor different from the first capacitor. supplying the input signal to a control terminal;
The impedance section is
a first impedance unit that biases the voltage level of the first control terminal to a predetermined voltage level;
2. The level shifting circuit of claim 1, comprising a second impedance section for biasing the voltage level of the second control terminal to a predetermined voltage level.
8. The level shift circuit according to claim 7, wherein the high level and low level of said input signal are different from the voltage levels of said first reference voltage and said second reference voltage.
8. The level shift circuit according to claim 7, wherein the first reference voltage and the second reference voltage are a positive voltage and a negative voltage, respectively, or a negative voltage and a positive voltage, respectively.
a signal output unit connected between the two cascode-connected transistors for outputting an output signal obtained by converting the voltage level of the input signal;
a high impedance detection unit that detects that the signal output unit is high impedance;
2. The level shifter according to claim 1, further comprising a logic fixing section that fixes the voltage level of the output signal to one of the two reference voltages when the signal output section has a high impedance. circuit.
a signal output unit connected between the two cascode-connected transistors for outputting an output signal obtained by converting the voltage level of the input signal;
a level detection unit that detects the voltage level of at least one of the input signal and the two control terminals;
When the voltage level of the input signal and at least one of the two control terminals continues at a high level or a low level for a predetermined period or longer, the voltage level of the output signal is set to either one of the two reference voltages. 2. The level shift circuit of claim 1, further comprising a logic fixer that fixes the level.
3. The level shift circuit according to claim 1, wherein said impedance section is a transistor whose control terminal is connected to one of said two reference voltages.
The impedance unit is a diode,
the anode of the diode is electrically connected to the lower voltage side of the two reference voltages;
2. The level shift circuit according to claim 1, wherein the cathode of said diode is electrically connected to the higher voltage side of said two reference voltages.
The impedance unit is a resistive element,
2. The level shift circuit according to claim 1, wherein said resistance element has a resistance value corresponding to the operating frequency of said level shift circuit and the capacitance of said capacitor.
15. The level shift circuit according to claim 14, wherein said resistance element has a resistance value such that a cutoff frequency of a high-pass filter of said resistance element and said capacitor is lower than an operating frequency of said level shift circuit.
2. The level shift circuit according to claim 1, further comprising a logic inverting section that supplies the input signal with its high level and low level inverted to each of said two control terminals.
3. The level shift circuit according to claim 1, wherein the voltage level of said input signal alternates between high level and low level according to time.
a DAC (Digital to Analog Converter) that converts a digital signal into an analog signal;
a level shift circuit that converts the voltage level range of the input digital signal into the voltage level range of the analog signal and outputs the converted voltage level range to the DAC;
The level shift circuit is
two transistors of different conductivity types cascoded between two reference voltages having different voltage levels;
a signal input unit that supplies an input signal having a high-level or low-level voltage level through a capacitor to at least one of two control terminals of the two transistors, respectively;
and an impedance section that biases the voltage level of the control terminal to which the input signal is supplied via the capacitor to a predetermined voltage level.