WO2022190424A1 - Dispositif et programme de traitement d'informations - Google Patents

Dispositif et programme de traitement d'informations Download PDF

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Publication number
WO2022190424A1
WO2022190424A1 PCT/JP2021/034557 JP2021034557W WO2022190424A1 WO 2022190424 A1 WO2022190424 A1 WO 2022190424A1 JP 2021034557 W JP2021034557 W JP 2021034557W WO 2022190424 A1 WO2022190424 A1 WO 2022190424A1
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Prior art keywords
mode
processor
control device
task
control
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PCT/JP2021/034557
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English (en)
Japanese (ja)
Inventor
英輝 原田
州平 遠坂
大輔 若林
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オムロン株式会社
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Publication of WO2022190424A1 publication Critical patent/WO2022190424A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to an information processing device and a program, and more particularly to an information processing device and program for setting a control device.
  • Patent Document 1 discloses that a processor of a control device executes a high-priority program and a low-priority program within a certain control cycle, and a high-priority program It discloses executing a low-priority program during a processor's idle time so as not to interfere with the execution of a program.
  • the processor repeatedly executes the first program with a high priority at regular intervals. Furthermore, the processor is caused to execute the second program and the third program during the processor's idle time during the control cycle so as not to interfere with the execution of the first program. From the viewpoint of improving the computation speed and performance, the processor performs computation until the last possible time within the set control cycle. However, since the processor and peripheral circuits are in a high load state, the power consumption of the control device is large. The greater the power consumption of the control device, the greater the amount of heat emitted from the control device.
  • the controller is designed so that it can be used at a certain operating ambient temperature.
  • the actually manufactured device is evaluated whether it can be used up to its operating ambient temperature.
  • the design and evaluation are performed under conditions that are severe for the controller, i.e., the condition that the processor is operating until just before the end of the control period (maximum load condition).
  • the heat dissipation capacity of the control device may not be sufficient. For example, if the control device is operated under maximum load at an ambient temperature higher than the upper limit of the operating ambient temperature determined at the design and evaluation stage, the control device may malfunction, stop, or fail. occurs.
  • Some processors have a function that automatically lowers the clock frequency when the temperature is high. By lowering the clock frequency, the power consumption of the processor is reduced, so the amount of heat generated by the processor can be reduced.
  • control devices such as PLCs used in production sites, a problem arises in that control performance is degraded when the clock frequency is lowered. Therefore, the operation of the object (manufacturing device) controlled by the control device may change.
  • control devices can be used at a temperature higher than the assumed operating ambient temperature. For example, if an attempt is made to improve the heat dissipation performance of the control device by enlarging the housing, a new design of the control device is required. Hardware changes are not easy due to size and manufacturing cost requirements.
  • One object of the present invention is to provide an information processing device and a program executed by the information processing device for setting the control device so that the control device can be used at a higher ambient temperature.
  • An information processing device is an information processing device that includes a processor and performs settings related to a task to be executed by a control device that controls a controlled object.
  • An input unit for receiving data, a setting unit for setting operating conditions of the control device according to user input, and a transfer unit for transferring the operating conditions for the control device set by the setting unit to the control device.
  • the operating modes include a first mode and a second mode for operating the controller at a temperature higher than the operating temperature in the first mode. When the second mode is selected by the user input, the setting unit allocates the idle time of the processor within the control cycle of the task.
  • the information processing device allocates processor idle time within the control cycle. Since the processor does not operate during idle time, the amount of heat generated by the processor is suppressed. It is thus possible to operate the control device at temperatures higher than the ambient temperature in the first mode.
  • the information processing device can configure the controller such that the controller can operate at a temperature higher than the ambient temperature in the first mode.
  • the setting unit determines the priority of execution by the processor among the plurality of tasks within the first remaining time excluding the idle time from the control cycle Allocate execution time for high-priority tasks.
  • the controller can be operated at high ambient temperatures without affecting the performance of tasks of high importance.
  • the setting unit sets the number of tasks within the second remaining time excluding the idle time and the execution time of the high-priority task from the control cycle. Among them, it is determined whether or not a low-priority task with a low execution priority can be assigned. If the low-priority task can be allocated within the second remaining time, the setting unit allocates the execution time of the low-priority task within the second remaining time. If the low-priority task cannot be assigned within the second remaining time, the setting unit assigns the second remaining time to the free time.
  • the control cycle by executing the high priority task and the low priority task within the control cycle, it is possible to improve the control performance of the controlled object. If the low-priority task cannot be executed, the idle time within the control cycle can be made longer. Therefore, the effect of suppressing the amount of heat generated by the processor can be enhanced.
  • the setting unit sets the maximum execution time of the high-priority task based on fluctuations in the execution time of the high-priority task within the first remaining time. assign.
  • the setting unit allocates at least part of the free time immediately after the high-priority task ends.
  • the setting unit when the first mode is selected by the user input, the setting unit does not secure an idle time within the control cycle, and executes a plurality of tasks within the control cycle in descending order of priority. Assign multiple tasks as needed.
  • a program for causing a computer to perform settings related to a task to be executed by a control device that has a processor and controls a controlled object the computer providing: The steps of accepting user input, setting the operating conditions of the controller according to the user input, and transferring the operating conditions of the controller to the controller are performed.
  • the operating modes include a first mode and a second mode for operating the controller at a temperature higher than the operating temperature in the first mode.
  • the setting step includes allocating processor idle time within a task control period when the second mode is selected by user input.
  • control device can be set so that the control device can be used at higher ambient temperatures.
  • control device can be set so that the control device can be used at higher ambient temperatures.
  • FIG. 4 is a schematic diagram showing an example of a program execution schedule in default mode in the control device according to the present embodiment
  • FIG. 4 is a schematic diagram showing an example of a program execution schedule in an extended mode in the control device according to the present embodiment
  • 1 is a schematic diagram of a control system including a control device according to an embodiment
  • FIG. 3 is a schematic diagram showing an example of a hardware configuration of an arithmetic unit that constitutes the control device according to the embodiment
  • FIG. 2 is a block diagram showing a hardware configuration example of a support device that configures the system according to the present embodiment
  • FIG. 3 is a schematic diagram showing an example of a software configuration of an arithmetic unit that constitutes the control device according to the present embodiment
  • FIG. 3 is a diagram showing an example of a screen for setting an operation mode provided by a display unit of a support device; 4 is a flowchart showing an overview of operation mode setting processing of the control device according to the first embodiment;
  • FIG. 10 is a diagram illustrating priority of allocation of time within a control cycle in default mode and extended mode;
  • FIG. 4 is a diagram illustrating an example of task processing executed by an arithmetic unit of a control device in default mode;
  • FIG. 4 is a diagram illustrating an example of task processing executed by an arithmetic unit of a control device in an extended mode;
  • FIG. 10 is a diagram illustrating another example of task processing executed by the arithmetic unit of the control device in the extended mode;
  • FIG. 10 is a diagram explaining still another example of task processing executed by the arithmetic unit of the control device in the extended mode;
  • FIG. 11 is a flow chart showing an outline of operation mode setting processing of the control device according to the second embodiment;
  • FIG. 11 is a flowchart for explaining processing related to control of processor idle time when a task is executed by a control device;
  • FIG. 10 is a diagram illustrating an example of task processing executed in an extended mode by an arithmetic unit of a control device according to a second embodiment;
  • FIG. 1 An example of a scene to which the present invention is applied will be described with reference to FIGS. 1 and 2.
  • FIG. 1 An example of a scene to which the present invention is applied will be described with reference to FIGS. 1 and 2.
  • FIG. 1 An example of a scene to which the present invention is applied will be described with reference to FIGS. 1 and 2.
  • FIG. 1 An example of a scene to which the present invention is applied will be described with reference to FIGS. 1 and 2.
  • a control device is a computer for controlling an arbitrary controlled object, and has one or more processors.
  • the controller has two modes of operation. The first mode of operation is the default (standard) mode. The second mode of operation is extended mode.
  • FIG. 1 is a schematic diagram showing an example of a program execution schedule in the default mode in the control device according to the present embodiment.
  • FIG. 2 is a schematic diagram showing an example of a program execution schedule in extended mode in the control device according to the present embodiment.
  • the control device when operating the control device in the default mode, the control device executes a high priority task 20 and a low priority task 30 within the control cycle.
  • a "task” is a basic unit to be controlled for allocating computing resources, and one or more programs to be executed are set for each task. That is, when computing resources are allocated to any task and the task becomes ready to be executed, execution of one or more programs set for the task is started or resumed.
  • the high priority task 20 is a task that should be executed within the control cycle.
  • the high-priority task 20 is set with a program having the highest execution priority (hereinafter also simply referred to as "priority") that is repeatedly executed by the processor of the control device.
  • the high-priority task 20 may include, for example, input/output data update processing, sequence operation processing that should be executed with the highest priority, and the like.
  • the processing time of the high priority task 20 is allocated within the control cycle so that the high priority task 20 is always executed within the control cycle.
  • the low-priority task 30 is a task whose execution priority is lower than that of the high-priority task 20, and is executed, for example, upon request.
  • a program having a lower priority than the program set to the high priority task 20 is set to the low priority task 30 .
  • the control device manages the execution timing of each program set for these tasks according to the scheduler program.
  • Program execution management by the scheduler program can be realized by allocating computing resources to each program at appropriate times and periods.
  • the scheduler program is set to the low-priority task 30 when the high-priority task 20 is not being executed within the control period so as not to interfere with the execution of the program set to the high-priority task 20. is executed by the processor.
  • the scheduler program allocates the execution time of the low-priority task 30 within a control cycle so as not to exceed a preset control cycle. Therefore, in a certain control cycle, even with the high priority task 20 and the low priority task 30 assigned, it is possible that the processor will have idle time. Also, in another control cycle, only the high priority task 20 may be assigned, and the remaining time may be the idle time of the processor.
  • the extended mode is selected when operating the control device at an ambient temperature (eg, 60° C.) higher than the operating ambient temperature (eg, 55° C. or less) of the standard control device.
  • the scheduler program reserves a predetermined percentage of the control period for processor idle time 40 .
  • the ratio of the idle time 40 to the control period may be a value determined by, for example, the developer of the control device by performing a temperature measurement test while changing the idle time using the actual device.
  • the scheduler program allocates the processing time of the high-priority task 20 to the remaining time (first remaining time) after subtracting the idle time 40 of the control cycle. Subsequently, the scheduler program determines whether the low priority task 30 can be allocated to the second remaining time obtained by subtracting the idle time 40 and the processing time of the high priority task 20 from the control period.
  • the low-priority task 30 can be assigned to the second remaining time, the high-priority task 20 and the low-priority task 30 are assigned and executed in that control cycle. Furthermore, in the control period, an idle time 40 having a predetermined length is secured. On the other hand, when the low-priority task 30 cannot be assigned to the second remaining time, only the high-priority task 20 is executed in that control cycle. That is, the time other than the execution time of the high-priority task 20 becomes the idle time 40 of the processor. Therefore, the actual processor idle time is longer than the pre-assigned time.
  • the control device when the control device is operating in default mode, the maximum processing time for high-priority tasks increases, and it is possible that free time cannot be secured within the control cycle.
  • the control period when the ambient temperature of the control device increases, the control period must be set longer. However, if the control period is lengthened, the processing performance of high priority tasks will be degraded. That is, the control performance of the control device is degraded.
  • the control device in the extended mode, can always secure an idle time 40 of a length equal to or longer than a certain period of time within the control cycle.
  • the processor suspends operations during idle time. Therefore, power consumption of the processor can be reduced compared to operation in the default mode. By reducing the power consumption of the processor, the amount of heat generated by the processor can be suppressed. This allows the enhanced mode to operate the controller at higher ambient temperatures than the default mode.
  • FIG. 3 is a schematic diagram of a control system including a control device according to one embodiment.
  • a control device according to the present embodiment is provided, for example, in an FA production line 10 and controls a control target.
  • the production line 10 includes controllers 1A, 1B, 1C, 1D, 1E, 1F, 1G and 1H.
  • the controllers 1A-1H are implemented by PLCs, for example.
  • the control devices 1A to 1H are connected to the communication device 4.
  • the control devices 1A to 1H can exchange data with each other via the communication device 4.
  • the communication device 4 is a device for realizing real-time performance required for communication performed in the industrial field, and is, for example, a switch complying with IEEE 802.1.TSN.
  • the control devices 1A, 1B, 1C, 1D, 1E, 1F, 1G, and 1H are synchronized with each other.
  • the control devices 1A, 1B, 1C, 1D, 1E, 1F, 1G and 1H have a timer function.
  • At least one of the control devices 1A to 1H in the production line 10 shown in FIG. 3 is the control device according to the embodiment.
  • the control device 1A will be described as a control device according to the embodiment.
  • all of the control devices 1A to 1H may correspond to the control device according to the present embodiment.
  • FIG. 3 is not intended to limit the number of controllers included in production line 10 .
  • the control device 1A executes control processing for the field device 5 to be controlled.
  • the control device 1A includes a plurality of functional units in which functions for executing the control processing are implemented. As shown in FIG. 1, the control device 1A includes an arithmetic unit 100A, functional units 201A, 201B, 201C, 201D and an I/O unit 300A.
  • the type of field device 5 is not particularly limited, and may include, for example, a servomotor.
  • each of the functional units 201A, 201B, 201C, and 201D are not particularly limited.
  • functional units 201A, 201B, 201C, 201D may include communication units.
  • functional unit 201D is a communication unit and is connected to communication device 4 via a network.
  • the AC-DC power supply 400A converts the AC voltage into a DC voltage and supplies the DC voltage to the control device 1A as a power supply voltage.
  • the power supply voltage of the control device 1A is, for example, DC24V.
  • the control device 1B includes an arithmetic unit 100B, a functional unit 202A and an I/O unit 300B.
  • Functional unit 202A is, for example, a communication unit and is connected to communication device 4 via a network.
  • AC-DC power supply 400B supplies power supply voltage (eg, 24 V DC) to each functional unit of controller 1B.
  • the support device 8 is a device that supports preparations necessary for the control devices 1A to 1H to control the target. Specifically, the support device 8 provides a setting environment related to tasks executed by each of the control devices 1A to 1H, a monitor screen of the execution status of the tasks in the control devices 1A to 1H, and the like.
  • FIG. 4 is a schematic diagram showing an example of the hardware configuration of the arithmetic unit 100A that constitutes the control device 1A according to the present embodiment.
  • arithmetic unit 100A includes processor 101, chipset 102, main memory 104, nonvolatile memory 106, system timer 108, PLC system bus controller 120, field network controller 140, and a USB connector 110 .
  • Chipset 102 and other components are each coupled via various buses.
  • the processor 101 and chipset 102 are typically configured according to general-purpose computer architecture. That is, the processor 101 interprets and executes instruction codes sequentially supplied from the chipset 102 according to the internal clock. The chipset 102 exchanges internal data with various connected components and generates instruction codes necessary for the processor 101 . Furthermore, the chipset 102 has a function of caching data obtained as a result of arithmetic processing executed by the processor 101 .
  • processor 101 For convenience of explanation, one processor 101 is depicted in FIG. The performance and configuration of processor 101 may be determined according to the required computing resources.
  • the arithmetic unit 100A has a main memory 104 and a nonvolatile memory 106 as storage means.
  • the main memory 104 is a volatile storage area (RAM), and holds various programs to be executed by the processor 101 after power is turned on to the arithmetic unit 100A.
  • the main memory 104 is also used as a working memory when the processor 101 executes various programs.
  • a device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) is used.
  • the nonvolatile memory 106 nonvolatilely holds data such as a real-time OS (Operating System), the system program of the control device 1A, user programs, and system setting parameters. These programs and data are copied to the main memory 104 so that the processor 101 can access them as needed.
  • a semiconductor memory such as a flash memory can be used as such a nonvolatile memory 106 .
  • a magnetic recording medium such as a hard disk drive may be used as the nonvolatile memory 106 .
  • the system timer 108 generates an interrupt signal and provides it to the processor 101 .
  • it is configured to generate interrupt signals at multiple different cycles, but depending on the OS (Operating System) or BIOS (Basic Input Output System), etc., interrupts can be generated at arbitrary cycles. It can also be set to generate a signal.
  • a control operation is realized for each control period.
  • the arithmetic unit 100A has a PLC system bus controller 120 and a field network controller 140 as communication circuits. These communication circuits transmit output data, such as arbitrary command values, and receive input data, such as detection values obtained from arbitrary sensors.
  • the PLC system bus controller 120 controls data exchange via a PLC system bus (not shown). More specifically, the PLC system bus controller 120 includes a DMA (Dynamic Memory Access) control circuit 122, a PLC system bus control circuit 124, and a buffer memory 126. PLC system bus controller 120 is internally connected to the PLC system bus via PLC system bus connector 130 .
  • DMA Dynamic Memory Access
  • the buffer memory 126 is a transmission buffer for data (output data) output to other units via the PLC system bus, and a transmission buffer for data (input data) input from other units via the PLC system bus. Acts as a receive buffer.
  • the DMA control circuit 122 transfers output data from the main memory 104 to the buffer memory 126 and transfers input data from the buffer memory 126 to the main memory 104 .
  • the PLC system bus control circuit 124 performs processing of transmitting output data of the buffer memory 126 and processing of receiving and storing input data in the buffer memory 126 with other units connected to the PLC system bus.
  • the field network controller 140 controls data exchange via a field network (not shown). That is, the field network controller 140 controls transmission of output data and reception of input data according to the standard of the field network used. More specifically, field network controller 140 includes DMA control circuitry 142 , field network control circuitry 144 , and buffer memory 146 .
  • Buffer memory 146 is a transmission buffer for data (output data) to be output to other devices via the field network, and a transmission buffer for data (input data) to be input from other devices via the field network. Acts as a receive buffer.
  • the DMA control circuit 142 transfers output data from the main memory 104 to the buffer memory 146 and transfers input data from the buffer memory 146 to the main memory 104 .
  • the field network control circuit 144 performs processing of transmitting output data of the buffer memory 146 and processing of receiving and storing input data in the buffer memory 146 with other devices connected to the field network.
  • the USB connector 110 is an interface for connecting an external device and the arithmetic unit 100A.
  • arithmetic unit 100A is connected to support device 8 via USB connector 110 and a USB cable.
  • a program or the like executable by the processor 101 of the arithmetic unit 100A is transferred from the support device 8 and taken into the control device 1A via the USB connector 110.
  • the temperature sensor 161 detects the internal temperature of the arithmetic unit 100A and outputs the temperature value.
  • the temperature values are sent to processor 101 via chipset 102 .
  • Support device 8 is implemented, for example, by hardware (for example, a general-purpose personal computer) that follows a general-purpose architecture executing a program.
  • FIG. 5 is a block diagram showing a hardware configuration example of the support device 8 that configures the system according to this embodiment.
  • support device 8 includes a processor 802 such as a CPU or MPU, an optical drive 804, a main storage device 806, a secondary storage device 808, a USB controller 812, an input unit 816, and a display. 818. These components are connected via bus 820 .
  • the processor 802 reads various programs stored in the secondary storage device 808, develops them in the main storage device 806, and executes them, thereby realizing various processes to be described later.
  • the processor 802 corresponds to a setting unit that sets operating conditions of the control device 1A according to user input.
  • the secondary storage device 808 is composed of, for example, an HDD or SSD.
  • the secondary storage device 808 typically stores a development program 822, which is a tool for creating user programs and setting tasks.
  • the secondary storage device 808 may store the OS and other necessary programs.
  • the support device 8 can have an optical drive 804 .
  • the optical drive 804 reads a program stored therein from a recording medium 805 (for example, an optical recording medium such as a DVD (Digital Versatile Disc)) that non-transitory stores a computer-readable program.
  • the program read from the recording medium 805 may be installed in the secondary storage device 808 or the like.
  • Various programs to be executed by the support device 8 may be downloaded from a server device or the like on the network and installed on the support device 8 . Also, the functions provided by the support device 8 may be realized by using some of the modules provided by the OS.
  • the USB controller 812 controls data exchange with the control device 1A via a USB connection.
  • the USB controller 812 implements a transfer unit for transferring the operating conditions of the control device 1A to the control device 1A.
  • the input unit 816 is composed of a keyboard, a mouse, and the like, and receives user operations, user inputs, and the like. In this embodiment, the input unit 816 is configured to accept user input regarding the operation mode of the control device 1A.
  • a display unit 818 is composed of a display, various indicators, a printer, and the like, and outputs processing results from the processor 802 and the like.
  • FIG. 5 shows a configuration example in which necessary functions are provided by the processor 802 executing a program. Alternatively, it may be implemented using an FPGA, etc.).
  • FIG. 6 is a schematic diagram showing an example of the software configuration of the arithmetic unit 100A that constitutes the control device 1A according to the present embodiment.
  • FIG. 6 shows an example of a software group for providing various functions according to this embodiment. Instruction codes included in these software groups are read at appropriate timings and executed by the processor 101 of the arithmetic unit 100A.
  • software executed by the arithmetic unit 100A includes a real-time OS 200, a system program 210, and a user program 234.
  • the real-time OS 200 is designed according to the computer architecture of the arithmetic unit 100A, and provides a basic execution environment for the processor 101 to execute the system program 210 and the user program 234.
  • This real-time OS is typically provided by a control device manufacturer or a specialized software company.
  • the system program 210 is a software group for providing the functions of the control device 1A.
  • system program 210 includes scheduler program 212 , IO processing program 214 (including input processing program 216 and output processing program 218 ), sequence instruction execution unit 232 , and system service program 220 .
  • the user program 234 is created according to the control purpose of the user. That is, it is a program that is arbitrarily created according to the controlled object to be controlled using the control device 1A.
  • the user program 234 is generated in the support device 8, for example.
  • the user program 234 is transferred from the support device 8 to the arithmetic unit 100A and stored in the nonvolatile memory 106 or the like.
  • the user program 234 consists of an IEC (International Electrotechnical Commission) program 236 consisting of command codes such as sequence commands and motion commands, and an application program 238 expressing control application procedures for controlling drive devices such as servo motors. including.
  • IEC International Electrotechnical Commission
  • the IEC program 236 includes a program consisting of one or more instructions written according to the international standard IEC61131-3 defined by IEC.
  • the application program 238 includes one or more commands that define the target trajectory.
  • the application program 238 may be a program written in an interpreter type language such as robot language or G language.
  • the sequence command execution unit 232 executes the IEC program 236 and outputs command values.
  • the sequence instruction execution unit 232 interprets sequence instructions included in the IEC program 236 and executes designated sequence operations (logical operations). Furthermore, the sequence command execution unit 232 calculates command values according to motion commands included in the IEC program 236 .
  • a motion command defines calculation of a command value over a plurality of control cycles by one command. Update.
  • the system service program 220 collectively indicates a group of programs for realizing various functions of the control device 1A, other than the programs shown individually in FIG.
  • the system service program 220 is, for example, a program that implements processing for transmitting and receiving files and data to and from an external device (that is, a program related to communication processing), a program that implements abnormality monitoring processing, various analysis processing, and the like. may
  • the programs included in the system service program 220 are classified into at least two priorities.
  • the system service programs 220 include a high priority service program 222 set to the high priority task 20 and a low priority service program 226 set to the low priority task.
  • the high-priority service program 222 has a higher execution priority than the low-priority service program 226 .
  • the high priority service program 222 includes an application program execution unit (not shown).
  • the application program execution unit for example, executes the application program 238 by an interpreter method and outputs a command value for a controlled object (for example, a servomotor).
  • the scheduler program 212 causes the processor 101 to execute a program set for each task according to the priority set for each task. That is, the scheduler program 212 controls the IO processing program 214, the system service program 220, and the like to start processing in each execution cycle and to resume processing after processing interruption.
  • the scheduler program 212 includes a control function 2120 and a monitoring function 2122.
  • the control function 2120 controls allocation of computing resources to each process.
  • a monitoring function 2122 monitors the execution status of each program included in the system service program 220 .
  • the monitoring function 2122 grasps the execution status of each service based on the notification by the notification function program of the high-priority service program 222 included in the system service program 220 .
  • the IO processing program 214 is in charge of updating the data (input data and output data) available in the arithmetic unit 100A.
  • Input processing program 216 of IO processing program 214 rearranges input data received by PLC system bus controller 120 and/or field network controller 140 into a form suitable for use by processor 101 of arithmetic unit 100A.
  • the output processing program 218 rearranges the output data generated by execution of the user program 234 into a form suitable for transfer to the PLC system bus controller 120 and/or field network controller 140 .
  • output processing program 218 issues such commands.
  • FIG. 7 is a diagram showing an example of a screen for setting an operation mode provided by the display unit 818 of the support device 8.
  • FIG. 7 In the example of the setting screen shown in FIG. 7, a default mode and an extended mode are displayed on the screen.
  • the default mode is the operating mode of the control device 1A when the operating ambient temperature is the standard temperature (55°C in this example).
  • the extended mode is an operation mode of the control device 1A in which the operating ambient temperature is higher than the operating ambient temperature in the default mode (for example, 60°C).
  • the input unit 816 accepts an operation mode input by the user when the user performs a determination operation on the input unit 816 .
  • C Setting the operation mode of the control device> (C-1. Setting by tool)
  • the support device 8 sets the idle time within the control period.
  • FIG. 8 is a flowchart showing an outline of operation mode setting processing of the control device according to the first embodiment.
  • the processing shown in FIG. 8 is executed by the support device 8 executing the program.
  • the setting process first includes a mode setting process (step S11) executed in support device 8.
  • the operation mode is determined by the user operating the setting screen of the support device 8 (see FIG. 7).
  • the input unit 816 receives an operation mode input by the user.
  • step S12 the processor 802 of the support device 8 determines whether the operating mode accepted by the input unit 816 is the default mode or the extended mode. In the case of the default mode, in step S13, settings for control processing in the default mode are executed. On the other hand, in the extended mode, settings for control processing in the extended mode are executed in step S14.
  • the user uses the user interface provided by the support device 8 to determine the length of the control cycle, assignment of high-priority tasks, and assignment of low-priority tasks. Set quotas, etc. The assignment of tasks within the control cycle differs between the default mode and the extended mode.
  • Fig. 9 is a diagram explaining the priority of time allocation within the control cycle in the default mode and the extended mode.
  • high-priority tasks priority: high
  • low-priority tasks priority: medium to low
  • the idle time of the processor is allocated with the highest priority within the control cycle.
  • processing time for high priority tasks priority: high
  • a low priority task is assigned if the remaining time in the control cycle can be assigned to the low priority task.
  • the user sets the assignment of high-priority tasks, the assignment of low-priority tasks, and the length of the control cycle.
  • the processor 802 of the support device 8 does not secure processor idle time within the control period.
  • processor 802 allows multiple tasks to be assigned such that multiple tasks are executed within a control cycle in order of priority. Therefore, in the default mode, basically no processor idle time occurs within the control cycle. Alternatively, even if processor idle time occurs in the default mode, the idle time is extremely short.
  • the processor 802 of the support device 8 secures a certain percentage (for example, 10%) of the control cycle as processor idle time. Further, the processor 802 accepts the user's setting so that the high-priority task is assigned within the remaining time (first remaining time) within the control cycle.
  • the processor 802 calculates the processing (task) exclusive time in consideration of the maximum fluctuation in the processing time of high-priority tasks. That is, processor 802 calculates the maximum processing time of the high-priority task and displays the calculation result on display unit 818 .
  • the user determines the allocation of high-priority tasks and the control period based on the calculation results. Since the ratio of the processor idle time to the control cycle is constant, the processor idle time is determined according to the length of the control cycle set by the user. Therefore, even if the execution time of the high-priority task becomes long, it is possible to secure the free time of the processor within the control period.
  • the processor 802 determines whether or not the low priority task can be assigned within the second remaining time from the control period excluding the idle time and the execution time of the high priority task. If a low priority task is assignable within the second remaining time, the processor 802 allocates execution time for the low priority task within the second remaining time. On the other hand, if no low priority task can be assigned within the second remaining time, the processor 802 allocates the second remaining time to processor idle time. Therefore, if the low-priority task cannot be assigned within the control period, the processor idle time becomes longer than the initially secured time.
  • step S13 or step S14 When the setting by the user is completed in step S13 or step S14, the program and setting contents are transferred from the support device 8 to the control device 1A (PLC) in step S15.
  • the extended mode in addition to the contents transferred from the support device 8 to the control device 1A (PLC) in the default mode, information indicating that there is processor idle time within the control cycle and the length of the idle time. Information is sent to the controller 1A.
  • the arithmetic unit 100A When the arithmetic unit 100A receives the information regarding the extended mode setting, the arithmetic unit 100A sets an interrupt request to the processor 101 based on the idle time information included in the information. As a result, a circuit (eg, system timer 108) inside arithmetic unit 100A generates an interrupt signal at the set timing and provides the interrupt signal to processor 101.
  • a circuit eg, system timer 108
  • FIG. 10 is a diagram explaining an example of task processing executed by the arithmetic unit of the control device 1A in the default mode.
  • an IRQ is generated every set control cycle.
  • the processor 101 of the arithmetic unit 100A starts processing in response to the IRQ and executes the high priority task 20 and the low priority task 30.
  • FIG. 11 is a diagram explaining an example of task processing executed by the arithmetic unit of the control device 1A in the extended mode.
  • extended mode an IRQ is generated at the start of idle time in addition to the start of a control cycle.
  • the processor 101 of the arithmetic unit 100A stops arithmetic processing according to the IRQ within the control cycle.
  • the time from when the processor 101 stops the calculation to when the next control cycle starts corresponds to the idle time 40 .
  • the next IRQ is generated at the start of the control cycle.
  • the processor 101 starts computation (execution of the high-priority task 20) in the next control cycle according to the IRQ.
  • FIG. 12 is a diagram explaining another example of task processing executed by the arithmetic unit of the control device 1A in the extended mode.
  • the end of the idle time 40 may be notified to the processor 101 by an IRQ.
  • the idle time 40 can be arranged in any period within the control period.
  • the idle time 40 may be arranged between the high priority task 20 and the low priority task 30 (in other words, immediately after the high priority task 20 ends).
  • FIG. 13 is a diagram explaining still another example of task processing executed by the arithmetic unit of the control device 1A in the extended mode.
  • a plurality of idle times 40 may be arranged within the control cycle.
  • the beginning and end of each idle time 40 is signaled to processor 101 by an IRQ.
  • IRQ IRQ
  • the time during which the processor 101 operates continuously can be shortened, so that a large rise in the temperature of the processor 101 can be suppressed without changing the control cycle.
  • free time may be allocated for each divided task.
  • the arithmetic unit 100A of the control device 1A determines the idle time within the control cycle based on the measured value of the temperature sensor 161 (see FIG. 4).
  • FIG. 14 is a flowchart showing an outline of operation mode setting processing of the control device according to the second embodiment.
  • processor 101 executes scheduler program 212 of control device 1A to execute the processing shown in FIG.
  • the arithmetic unit 100A receives an input of a program and setting contents.
  • the user determines the operation mode, sets the length of the control cycle, assigns high-priority tasks, assigns low-priority tasks, and the like.
  • the program and setting contents are transferred from the support device 8 to the control device 1A.
  • the setting content includes information about the operation mode.
  • the processor 101 of the arithmetic unit 100A determines, based on the information transferred from the support device 8, whether the operation mode set by the user is the default mode or the extension mode. In default mode, in step S23, processor 101 performs settings for control processing in default mode. On the other hand, in the extended mode, in step S24, the processor 101 performs settings for control processing in the extended mode.
  • the processor 101 does not secure processor idle time within the control cycle. Furthermore, the processor 101 allocates a plurality of tasks within the control cycle so that the plurality of tasks are executed within the control cycle in order of priority.
  • the processor 101 reserves a certain percentage (for example, 10%) of the control cycle as processor idle time. Then, the processor 101 assigns high priority tasks within the remaining time (first remaining time) within the control cycle. In this case, the processor 101 allocates the high-priority task within the control period in consideration of the maximum fluctuation of the processing time of the high-priority task.
  • the processor 101 determines whether or not the low priority task can be assigned within the second remaining time, excluding the idle time and the execution time of the high priority task, from the control cycle. If a low priority task is assignable within the second remaining time, processor 101 allocates the execution time of the low priority task within the second remaining time. On the other hand, if the low-priority task cannot be assigned within the second remaining time, the processor 101 assigns the second remaining time to processor idle time.
  • the task processing executed in the default mode and the task processing executed in the extended mode are basically the same as the processing described in the first embodiment, so detailed description will not be repeated.
  • the ratio of the processor idle time to the control cycle changes according to the temperature measured by the temperature sensor 161 (that is, the operating ambient temperature of the control device 1A). In this respect, the second embodiment differs from the first embodiment.
  • FIG. 15 is a flow chart for explaining processing related to control of processor idle time during task execution by the control device 1A.
  • the processor 101 acquires a temperature value (temperature sensor value) from the temperature sensor 161 .
  • the processor 101 may acquire measured values from the temperature sensor 161 at predetermined intervals and calculate the average value of the measured values as the temperature value.
  • the processor 101 obtains the ratio of idle time to the control period.
  • a method for obtaining the idle time from the temperature value is not particularly limited.
  • the processor 101 may use an arithmetic expression for obtaining the ratio of the idle time to the control period from the temperature value.
  • the processor 101 can obtain the ratio of the idle time to the control cycle from the arithmetic expression and the detection value of the temperature sensor 161, and determine the idle time based on the ratio and the control cycle.
  • the non-volatile memory 106 of the arithmetic unit 100A may store a table that associates the temperature with the ratio of free time to the control period.
  • the processor 101 obtains the ratio of the idle time to the control period from the table and the detection value of the temperature sensor 161, and can determine the idle time based on the ratio and the control period. In both the calculation formula and the table, the ratio of idle time to control period is set to increase as the temperature rises.
  • the processor 101 determines the idle time within the control cycle.
  • the processor 101 sets the idle time information in the IRQ.
  • the processor 101 executes processing according to the above settings.
  • the generation of an IRQ causes processor 101 to stop processing.
  • the IRQ informs processor 101 when the next control cycle begins.
  • the processor 101 starts calculation and processing in that control cycle in response to the IRQ.
  • the idle time is the time during which the processor 101 stops computing.
  • FIG. 16 is a diagram explaining an example of task processing executed in the extended mode by the arithmetic unit of the control device 1A according to the second embodiment.
  • the processor 101 lengthens the idle time 40 within the control period as the measured value of the temperature sensor 161 increases.
  • the measured value of temperature sensor 161 represents the operating ambient temperature of control device 1A.
  • the control device 1A shortens the idle time 40.
  • the ratio of idle time to the control period is kept higher than the ratio set by support device 8 .
  • the length of the control cycle does not change although the length of the idle time changes according to the temperature. If the length of the control cycle changes during system operation, the processing performance of the high-priority task may change (increase or decrease). A change in the processing performance of the high-priority task may affect the operation of the controlled object (for example, manufacturing equipment). By not changing the length of the control cycle, it is possible to prevent the processing performance of the high-priority task from changing.
  • FIG. 16 shows an example in which a high priority task and a low priority task are executed within one control cycle.
  • the remaining time within the control cycle may be idle time.
  • priority is given to allocation of idle time within the control cycle, followed by priority to allocation of high priority tasks. Therefore, the idle time of the processor can be secured within the control period. As a result, it is possible to suppress an increase in the amount of heat generated by the processor, thereby suppressing a large increase in the temperature of the processor.
  • IRQs can adopt the same arrangement of idle times as shown in FIGS. 12 and 13 .
  • the arrangement of the idle times 40 within the control cycle is not particularly limited.
  • the setting unit (802) performs, among a plurality of tasks, within a first remaining time excluding the idle time (40) from the control cycle,
  • the information processing apparatus (8) according to configuration 1, wherein an execution time of a high priority task (20) having a high priority to be executed by the processor (101) is allocated.
  • the setting unit (802) removes the idle time (40) and the execution time of the high-priority task (20) from the control cycle, and selects the second mode. within the remaining time of, among the plurality of tasks, determine whether a low-priority task (30) having a low execution priority can be assigned, If the low-priority task (30) can be assigned within the second remaining time, the setting unit (802) executes the low-priority task (30) within the second remaining time. assign time, If the low-priority task (30) cannot be assigned within the second remaining time, the setting unit (802) assigns the second remaining time to the free time (40). Information processing device (8) as described.
  • the setting unit (802) sets the maximum execution time of the high priority task (20) based on fluctuations in the execution time of the high priority task (20). is allocated within the first remaining time (8) according to configuration 2.
  • the setting unit (802) does not secure the idle time (40) within the control period and a plurality of tasks have high priority.
  • the information processing apparatus (8) according to any one of configurations 1 to 5, wherein the plurality of tasks are assigned so as to be executed in order within the control cycle.
  • the step of setting (S13, S14) includes: A program comprising a step (S14) of allocating idle time (40) of said processor (101) within a control cycle of said task when said second mode is selected by said user input.

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Abstract

Ce dispositif de traitement d'informations comprend : une unité d'entrée qui reçoit une entrée d'utilisateur associée à un mode de fonctionnement d'un dispositif de commande ; une unité de réglage qui règle une condition de fonctionnement pour le dispositif de commande conformément à l'entrée d'utilisateur ; et une unité de transfert qui transfère, au dispositif de commande, l'état de fonctionnement pour le dispositif de commande réglé par l'unité de réglage. Le mode de fonctionnement comprend un premier mode et un second mode pour faire fonctionner le dispositif de commande à une température supérieure à une température de fonctionnement dans le premier mode. Lorsque le second mode est sélectionné par l'entrée d'utilisateur, l'unité de réglage attribue un temps de réserve pour un processeur du dispositif de commande dans une période de commande pour une tâche.
PCT/JP2021/034557 2021-03-08 2021-09-21 Dispositif et programme de traitement d'informations WO2022190424A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002229663A (ja) * 2001-02-06 2002-08-16 Seiko Epson Corp 情報処理装置
JP2005165470A (ja) * 2003-11-28 2005-06-23 Toshiba Corp 電子機器およびプロセッサ速度制御方法
JP2020061055A (ja) * 2018-10-12 2020-04-16 オムロン株式会社 制御システム、制御装置および制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002229663A (ja) * 2001-02-06 2002-08-16 Seiko Epson Corp 情報処理装置
JP2005165470A (ja) * 2003-11-28 2005-06-23 Toshiba Corp 電子機器およびプロセッサ速度制御方法
JP2020061055A (ja) * 2018-10-12 2020-04-16 オムロン株式会社 制御システム、制御装置および制御方法

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