WO2022188348A1 - 半导体结构及半导体结构的制作方法 - Google Patents

半导体结构及半导体结构的制作方法 Download PDF

Info

Publication number
WO2022188348A1
WO2022188348A1 PCT/CN2021/110616 CN2021110616W WO2022188348A1 WO 2022188348 A1 WO2022188348 A1 WO 2022188348A1 CN 2021110616 W CN2021110616 W CN 2021110616W WO 2022188348 A1 WO2022188348 A1 WO 2022188348A1
Authority
WO
WIPO (PCT)
Prior art keywords
contact pad
conductive
conductive contact
semiconductor structure
support
Prior art date
Application number
PCT/CN2021/110616
Other languages
English (en)
French (fr)
Inventor
张志伟
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21873688.2A priority Critical patent/EP4287243A1/en
Priority to US17/650,389 priority patent/US20220293542A1/en
Publication of WO2022188348A1 publication Critical patent/WO2022188348A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for fabricating the semiconductor structure.
  • the bonding between chips is realized by connecting metal pads on the chips to each other, but due to process limitations, the problem of open circuit or short-circuit connection between the two metal pads between the two chips is likely to occur.
  • the present disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure to improve the performance of the semiconductor structure.
  • a semiconductor structure comprising:
  • the first chip includes a first substrate, a first conductive connection, a first conductive contact pad and a second conductive contact pad, the first conductive contact pad and the second conductive contact pad are spaced apart and are both connected to the first conductive contact pad. connected by conductive wires;
  • the second chip includes a second substrate, a second conductive wire, a third conductive contact pad and a fourth conductive contact pad, the third conductive contact pad and the fourth conductive contact pad are spaced apart and are both connected to the second connected by conductive wires;
  • both the first conductive contact pad and the second conductive contact pad are alternately connected to the third conductive contact pad, and both the first conductive contact pad and the second conductive contact pad are alternately connected to the fourth conductive contact pad.
  • a semiconductor structure comprising:
  • Conductive connection lines, the conductive connection lines are located in the substrate;
  • the first conductive contact pad is located in the substrate, the first conductive contact pad is connected with the conductive connection line, and is located above the conductive connection line;
  • the second conductive contact pad is located in the substrate, the second conductive contact pad is connected with the conductive connection line, and is located above the conductive connection line;
  • the first conductive contact pad is spaced apart from the second conductive contact pad.
  • a method for fabricating a semiconductor structure comprising:
  • a substrate is provided, and conductive wires are formed in the substrate;
  • a first conductive contact pad and a second conductive contact pad are formed in the substrate, the first conductive contact pad is connected to the conductive connection line and is located above the conductive connection line, the second conductive contact pad is connected to the conductive connection line, and above the conductive connection;
  • the first conductive contact pad is spaced apart from the second conductive contact pad.
  • the semiconductor structure of the present disclosure includes a first chip and a second chip, the first conductive wire of the first chip is connected to the first conductive contact pad and the second conductive contact pad, and the second conductive wire of the second chip is connected to the third conductive contact pads and fourth conductive contact pads, by making the first conductive contact pads and the second conductive contact pads both interlaced with the third conductive contact pads, and the first conductive contact pads and the second conductive contact pads are interlaced with the fourth conductive contact pads Therefore, the reliable electrical connection between the first conductive connection and the second conductive connection is ensured, and the open circuit problem of the first conductive connection and the second conductive connection is avoided, thereby improving the performance of the semiconductor structure.
  • FIG. 1 is a schematic diagram of a combined structure of a semiconductor structure according to an exemplary embodiment
  • FIG. 2 is a schematic diagram of an exploded structure of a semiconductor structure according to an exemplary embodiment
  • FIG. 3 is a schematic cross-sectional structural diagram of a semiconductor structure according to an exemplary embodiment
  • FIG. 4 is a schematic diagram showing a connection structure of a partial structure of a semiconductor structure according to an exemplary embodiment
  • FIG. 5 is a schematic diagram of another connection structure of a partial structure of a semiconductor structure according to an exemplary embodiment
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment
  • FIG. 7 is a schematic cross-sectional structural diagram of a semiconductor structure according to an exemplary embodiment
  • FIG. 8 is a schematic flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 9 is a schematic structural diagram of forming a conductive connection according to a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 10 is a schematic structural diagram of forming a second insulating layer according to a method for fabricating a semiconductor structure shown in an exemplary embodiment
  • FIG. 11 is a schematic structural diagram of forming an opening according to a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 12 is a schematic structural diagram of forming a conductive contact pad according to a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • the first chip 41, the first substrate; 42, the first conductive connection; 43, the first conductive contact pad; 44, the second conductive contact pad; 45, the first support contact pad; 50, the second chip 51, the second substrate; 52, the second conductive connection; 53, the third conductive contact pad; 54, the fourth conductive contact pad; 55, the second support contact pad.
  • the semiconductor structure includes: a first chip 40 , the first chip 40 includes a first substrate 41 , a first conductive wire 42 , a first The conductive contact pads 43 and the second conductive contact pads 44, the first conductive contact pads 43 and the second conductive contact pads 44 are spaced apart, and are connected to the first conductive connection lines 42; the second chip 50, the second chip 50 includes The second substrate 51 , the second conductive connection 52 , the third conductive contact pad 53 and the fourth conductive contact pad 54 , the third conductive contact pad 53 and the fourth conductive contact pad 54 are spaced apart and are all connected to the second conductive contact pad 54 .
  • Lines 52 are connected; wherein, the first conductive contact pads 43 and the second conductive contact pads 44 are alternately connected with the third conductive contact pads 53, and both the first conductive contact pads 43 and the second conductive contact pads 44 are in contact with the fourth conductive contact pad
  • the pads 54 are staggered.
  • the semiconductor structure of an embodiment of the present disclosure includes a first chip 40 and a second chip 50 , the first conductive connection 42 of the first chip 40 is connected to the first conductive contact pad 43 and the second conductive contact pad 44 , The second conductive connection line 52 is connected to the third conductive contact pad 53 and the fourth conductive contact pad 54.
  • first conductive contact pad 43 and the second conductive contact pad 44 By making the first conductive contact pad 43 and the second conductive contact pad 44 connected to the third conductive contact pad 53 alternately, the first conductive contact pad 43 and the second conductive contact pad 44 are alternately connected to the third conductive contact pad 53
  • the contact pads 43 and the second conductive contact pads 44 are alternately connected to the fourth conductive contact pads 54, so as to ensure a reliable electrical connection between the first conductive connection line 42 and the second conductive connection line 52, and avoid the first conductive connection line. 42 and the second conductive connection 52 have open circuit problems, thereby improving the performance of the semiconductor structure.
  • the conductive connection lines between the upper and lower bonded chips are connected through a larger contact surface, while in this embodiment, the first conductive contact pad 43 and the The second conductive contact pads 44 are alternately connected to the third conductive contact pads 53, and the first conductive contact pads 43 and the second conductive contact pads 44 are alternately connected to the fourth conductive contact pads 54, so as to ensure a reliable contact surface, and This ensures reliable electrical connection between the first conductive wire 42 and the second conductive wire 52 .
  • the first conductive wire 42 , the first conductive contact pad 43 and the second conductive contact pad 44 are all located in the first substrate 41 , the second conductive wire 52 , the third conductive contact pad 53 and the The four conductive contact pads 54 are all located in the second substrate 51 , and the first chip 40 and the second chip 50 are bonded.
  • first conductive contact pads 43 and the second conductive contact pads 44 may be partially located in the first substrate 41 , or may all be located in the first substrate 41 .
  • third conductive contact pads 53 and the fourth conductive contact pads 54 may be partially located in the second substrate 51 , or may be completely located in the second substrate 51 .
  • the first conductive contact pads 43 and the second conductive contact pads 44 may be located on the surface of the first substrate 41 .
  • the third conductive contact pad 53 and the fourth conductive contact pad 54 may be on the surface of the second substrate 51 .
  • the first chip 40 includes a first substrate 41 , a first conductive wire 42 , a first conductive contact pad 43 and a second conductive contact pad 44
  • the second chip 50 includes a first The two substrates 51, the second conductive wires 52, the third conductive contact pads 53 and the fourth conductive contact pads 54, after the first chip 40 and the second chip 50 are bonded, the first substrate 41 and the second substrate 51 is bonded, and the first conductive contact pad 43 and the second conductive contact pad 44 are both connected with the third conductive contact pad 53 and the fourth conductive contact pad 54, in some cases even if there is a dislocation, there may be mutual contact part, thereby ensuring reliable electrical connection between the first conductive wire 42 and the second conductive wire 52 .
  • first conductive contact pad 43 and the second conductive contact pad 44 may be identical structures.
  • the third conductive contact pad 53 and the fourth conductive contact pad 54 may be of the same structure.
  • first conductive contact pad 43 and the second conductive contact pad 44 may be of different structures.
  • the third conductive contact pad 53 and the fourth conductive contact pad 54 may be of different structures.
  • At least one of the first conductive contact pad 43 and the second conductive contact pad 44 may be plural. At least one of the third conductive contact pad 53 and the fourth conductive contact pad 54 may be plural.
  • the extending direction of the first conductive contact pad 43 is consistent with the extending direction of the second conductive contact pad 44, that is, the distance between the first conductive contact pad 43 and the second conductive contact pad 44 is a fixed value .
  • the extending direction of the third conductive contact pad 53 is consistent with the extending direction of the fourth conductive contact pad 54 , that is, the distance between the third conductive contact pad 53 and the fourth conductive contact pad 54 is a fixed value.
  • the first conductive contact pad 43 and the second conductive contact pad 44 both extend in a linear direction
  • the third conductive contact pad 53 and the fourth conductive contact pad 54 both extend in a linear direction.
  • first conductive contact pads 43 and the second conductive contact pads 44 both extend in the curvilinear direction
  • third conductive contact pads 53 and the fourth conductive contact pads 54 both extend in the curvilinear direction.
  • first conductive contact pads 43 and the second conductive contact pads 44 are parallel, that is, the first conductive contact pads 43 and the second conductive contact pads 44 extend in a linear direction, so as to reduce the size of the first conductive contact pads 43 and the length of the second conductive contact pad 44.
  • the third conductive contact pads 53 and the fourth conductive contact pads 54 are parallel, that is, the third conductive contact pads 53 and the fourth conductive contact pads 54 extend in a linear direction, thereby reducing the distance between the third conductive contact pads 53 and the fourth conductive contact pads 54 .
  • the first conductive contact pad 43 is perpendicular to the third conductive contact pad 53 .
  • the first conductive contact pad 43 is parallel to the second conductive contact pad 44
  • the third conductive contact pad 53 is parallel to the fourth conductive contact pad 54
  • the first conductive contact pad 43 is parallel to the fourth conductive contact pad 54 .
  • the three conductive contact pads 53 are perpendicular to each other, that is, the contact area between the upper and lower contact pads can be minimized, but a stable contact area can be guaranteed. Even if misaligned bonding occurs, that is, poor bonding alignment, the contact area can still be guaranteed to remain unchanged, and the contact surface resistance has little effect, as shown in Figure 5.
  • the included angle between the first conductive contact pad 43 and the third conductive contact pad 53 may be greater than 0 degrees and less than 180 degrees, that is, it is sufficient to ensure that the staggered arrangement can occur.
  • the third conductive contact pads 53 are perpendicular to each other, and the contact area between the upper and lower contact pads will be larger at this time.
  • the first chip 40 further includes a first support contact pad 45 , the first support contact pad 45 is spaced apart from the first conductive connection line 42 , and the first conductive contact pad 43 and the second conductive contact pad 44 are spaced apart from the first support contact pad 45;
  • the second chip 50 further includes a second support contact pad 55, the second support contact pad 55 is spaced from the second conductive connection line 52, and the third conductive contact pad 55 is Both the contact pads 53 and the fourth conductive contact pads 54 are spaced apart from the second support contact pads 55 ; wherein the first support contact pads 45 and the second support contact pads 55 are alternately connected.
  • the arrangement of the first supporting contact pad 45 and the second supporting contact pad 55 may not realize electrical connection, they can play a supporting and protective role, thereby improving the stability and strength of the semiconductor structure.
  • the length of the first support contact pad 45 is greater than the diameter of the first conductive wire 42 , that is, the first support contact pad 45 is not connected to the first conductive wire 42 , and both ends of the first support contact pad 45 are Located on the periphery of the first conductive connection 42 .
  • the length of the second support contact pad 55 is greater than the diameter of the second conductive connection line 52 , that is, the second support contact pad 55 is not connected with the second conductive connection line 52 , and both ends of the second support contact pad 55 are connected to each other. Located on the periphery of the second conductive connection 52 .
  • the first support contact pad 45 is located within the first substrate 41 , and the first support contact pad 45 may be completely located within the first substrate 41 with the upper surface of which is the same as the upper surface of the first substrate 41 . Flush, or the first support contact pad 45 may be partially located within the first substrate 41 , that is, the first support contact pad 45 protrudes from the upper surface of the first substrate 41 .
  • the second support contact pad 55 is located in the second substrate 51, the second support contact pad 55 may be completely located in the second substrate 51, and its upper surface is flush with the upper surface of the second substrate 51, Alternatively, the second support contact pad 55 may be partially located within the second substrate 51 , that is, the second support contact pad 55 protrudes from the upper surface of the second substrate 51 .
  • the first support contact pad 45 is located on the upper surface of the first substrate 41
  • the second support contact pad 55 is located on the upper surface of the second substrate 51 .
  • the first support contact pads 45 are arranged in pairs, and the first conductive contact pads 43 and the second conductive contact pads 44 are located between the pair of two first support contact pads 45 , that is, the outermost two The first support contact pad 45 achieves reliable protection.
  • the second support contact pads 55 are arranged in pairs, and the third conductive contact pad 53 and the fourth conductive contact pad 54 are located between the pair of two second support contact pads 55 .
  • the number of the first support contact pads 45 and the second support contact pads 55 may both be greater than two, which is not limited herein.
  • the orthographic projection of the first support contact pad 45 in the direction perpendicular to the first substrate 41 coincides with the first conductive connection 42 , that is, at least part of the first support contact pad 45 may be located on the first conductive connection Right above the line 42 , but spaced apart between the first support contact pad 45 and the first conductive connection line 42 .
  • the orthographic projection of the second support contact pad 55 in the direction perpendicular to the second substrate 51 coincides with the second conductive connection line 52 , that is, at least part of the second support contact pad 55 may be located on the second conductive connection line 52 .
  • the orthographic projection of the second support contact pad 55 in the direction perpendicular to the second substrate 51 coincides with the second conductive connection line 52 , that is, at least part of the second support contact pad 55 may be located on the second conductive connection line 52 .
  • the orthographic projection of the second support contact pad 55 in the direction perpendicular to the second substrate 51 coincides with the second conductive connection line 52 , that is, at least part of the second support contact pad 55 may be located on the second conductive connection line 52 .
  • the orthographic projection of the first support contact pad 45 along the direction perpendicular to the first substrate 41 does not coincide with the first conductive connection 42 , that is, the first support contact pad 45 is located at the periphery of the first conductive connection 42 area.
  • the lower surface of the first support contact pad 45 may be higher than the upper surface of the first conductive connection 42, or the lower surface of the first support contact pad 45 may be equal to the upper surface of the first conductive connection 42, or the first support The lower surface of the contact pad 45 may be lower than the upper surface of the first conductive wire 42 .
  • the orthographic projection of the second support contact pad 55 along the direction perpendicular to the second substrate 51 does not coincide with the second conductive connection line 52 , that is, the second support contact pad 55 is located in the peripheral area of the second conductive connection line 52 .
  • the lower surface of the second support contact pad 55 may be higher than the upper surface of the second conductive connection 52, or the lower surface of the second support contact pad 55 may be equal to the upper surface of the second conductive connection 52, or the second support The lower surface of the contact pad 55 may be lower than the upper surface of the second conductive wire 52 .
  • the spacing between the first conductive contact pad 43 and the second conductive contact pad 44 is equal to the spacing between the third conductive contact pad 53 and the fourth conductive contact pad 54 .
  • the spacing between the first conductive contact pad 43 and the second conductive contact pad 44 is not equal to the spacing between the third conductive contact pad 53 and the fourth conductive contact pad 54, even if the first chip 40 and the The bonding deviation between the two chips 50 can also ensure that the contact pads of the first chip 40 and the second chip 50 have sufficient contact area to avoid the problem of open circuit.
  • the first conductive wire 42 is a first TSV; the second conductive wire 52 is a second TSV. That is, the first through-silicon via and the second through-silicon via are connected through interdigitated contact pads.
  • the lengths of the first conductive contact pads 43 and the second conductive contact pads 44 are both greater than the diameters of the first conductive connection lines 42 , that is, both ends of the first conductive contact pads 43 and the second conductive contact pads 44 may be They are all located outside the first conductive wires 42 and are not in direct contact with the first conductive wires 42 .
  • the lengths of the third conductive contact pad 53 and the fourth conductive contact pad 54 are both larger than the diameter of the second conductive connection line 52, that is, both ends of the third conductive contact pad 53 and the fourth conductive contact pad 54 may be located in the The outer sides of the two conductive wires 52 are not in direct contact with the second conductive wires 52 .
  • first conductive contact pads 43 and the second conductive contact pads 44 may both be rectangular structures, and the third conductive contact pads 53 and the fourth conductive contact pads 54 may both be rectangular structures.
  • the first support contact pad 45 and the second support contact pad 55 may both have a rectangular structure.
  • the first conductive connection 42, the first conductive contact pad 43, and the second conductive contact pad 44 may include copper (Cu), tungsten (W), etc. related integrated circuit conductive materials.
  • the second conductive wiring 52 , the third conductive contact pad 53 and the fourth conductive contact pad 54 may include copper (Cu), tungsten (W) and other related integrated circuit conductive materials.
  • the first support contact pad 45 and the second support contact pad 55 may include copper (Cu), tungsten (W), etc. related integrated circuit conductive materials.
  • the width of at least one of the first conductive contact pad 43 , the second conductive contact pad 44 and the first support contact pad 45 may be 100 nm ⁇ 1000 nm, and the depth may be 100 nm ⁇ 500 nm.
  • At least one of the third conductive contact pad 53 , the fourth conductive contact pad 54 and the second support contact pad 55 may have a width of 100 nm ⁇ 1000 nm and a depth of 100 nm ⁇ 500 nm.
  • At least one of the first conductive contact pad 43 and the second conductive contact pad 44 may be the same structure as the first support contact pad 45 .
  • At least one of the third conductive contact pad 53 and the fourth conductive contact pad 54 may be the same structure as the second support contact pad 55 .
  • both the first conductive contact pad 43 and the second conductive contact pad 44 may be of different structures from the first support contact pad 45 .
  • Both the third conductive contact pad 53 and the fourth conductive contact pad 54 may have different structures from the second support contact pad 55 .
  • the semiconductor structure includes: a substrate 10 ; a conductive wire 20 , the conductive wire 20 is located in the substrate 10 ; a first conductive contact pad 30, the first conductive contact pad 30 is located in the substrate 10, the first conductive contact pad 30 is connected to the conductive connection line 20, and is located above the conductive connection line 20; the second conductive contact pad 31, the second conductive contact pad 31 Inside the substrate 10 , the second conductive contact pads 31 are connected to the conductive connection lines 20 and are located above the conductive connection lines 20 ; wherein the first conductive contact pads 30 and the second conductive contact pads 31 are spaced apart.
  • the semiconductor structure of an embodiment of the present disclosure includes a substrate 10 and a conductive wire 20.
  • the conductive wire 20 is connected with a first conductive contact pad 30 and a second conductive contact pad 31.
  • the conductive contact pads 31 are arranged at intervals, thereby changing the contact surface of the conductive wire 20 for connecting with other conductive structures, thereby improving the connection reliability of the semiconductor structure and improving the conductive connection performance of the semiconductor structure.
  • first conductive contact pads 30 are located in the substrate 10 , and the first conductive contact pads 30 may be partially located in the substrate 10 , or may be located entirely in the substrate 10 .
  • the second conductive contact pads 31 located in the substrate 10 may be partially located in the substrate 10 , or may be located entirely in the substrate 10 .
  • the first conductive contact pad 30 and the second conductive contact pad 31 may be the same structure.
  • the first conductive contact pad 30 and the second conductive contact pad 31 may be of different structures.
  • At least one of the first conductive contact pad 30 and the second conductive contact pad 31 may be plural.
  • the extension direction of the first conductive contact pad 30 is consistent with the extension direction of the second conductive contact pad 31 , that is, the distance between the first conductive contact pad 30 and the second conductive contact pad 31 is a fixed value .
  • both the first conductive contact pad 30 and the second conductive contact pad 31 extend in a linear direction.
  • both the first conductive contact pads 30 and the second conductive contact pads 31 extend in a curvilinear direction.
  • first conductive contact pads 30 and the second conductive contact pads 31 are parallel to each other, that is, the first conductive contact pads 30 and the second conductive contact pads 31 extend in a linear direction, so as to reduce the size of the first conductive contact pads 30 and the length of the second conductive contact pad 31.
  • the semiconductor structure further includes: supporting contact pads 32 , the supporting contact pads 32 are located in the substrate 10 , and the supporting contact pads 32 are spaced apart from the conductive wires 20 ; Both a conductive contact pad 30 and a second conductive contact pad 31 are spaced apart from the support contact pad 32 .
  • the arrangement of the support contact pads 32 may not realize electrical connection, it can play a supporting and protective role, so as to improve the stability and strength of the semiconductor structure.
  • the length of the supporting contact pad 32 is greater than the diameter of the conductive wire 20 , that is, the supporting contact pad 32 is not connected to the conductive wire 20 , and both ends of the supporting contact pad 32 are located on the periphery of the conductive wire 20 .
  • the support contact pads 32 are located within the substrate 10 , and the support contact pads 32 may be partially located within the substrate 10 , or may be located entirely within the substrate 10 .
  • the support contact pads 32 are arranged in pairs, and the first conductive contact pad 30 and the second conductive contact pad 31 are located between the pair of two support contact pads 32 , that is, the two outermost support contact pads 32 for reliable protection.
  • the number of supporting contact pads 32 may be greater than two, which is not limited here.
  • the orthographic projection of the support contact pads 32 in the direction perpendicular to the substrate 10 coincides with the conductive lines 20 , that is, at least part of the support contact pads 32 may be located directly above the conductive lines 20 , but the support contact pads 32 and the conductive wires 20 are spaced apart.
  • the orthographic projection of the support contact pads 32 in the direction perpendicular to the substrate 10 does not coincide with the conductive lines 20 , that is, the support contact pads 32 may be located in the peripheral area of the conductive lines 20 , but the support contact pads 32 and the conductive lines 20 do not overlap.
  • the interval between the connection lines 20 is set.
  • the lower surface of the supporting contact pad 32 may be higher than the upper surface of the conductive wire 20, or the lower surface of the supporting contact pad 32 may be equal to the upper surface of the conductive wire 20, or the lower surface of the supporting contact pad 32 may be lower than the conductive wire 20.
  • the upper surface of the wire 20 is set.
  • the conductive lines 20 are through silicon vias.
  • the lengths of the first conductive contact pads 30 and the second conductive contact pads 31 are both greater than the diameters of the conductive wires 20 , that is, both ends of the first conductive contact pads 30 and the second conductive contact pads 31 may be located at The outer side of the conductive wire 20 is not in direct contact with the conductive wire 20 .
  • first conductive contact pads 30 and the second conductive contact pads 31 may both be rectangular structures, and the support contact pads 32 may be rectangular structures.
  • the first conductive contact pads 30, the second conductive contact pads 31, and the support contact pads 32 may comprise copper (Cu), tungsten (W), etc. related integrated circuit conductive materials.
  • the width of at least one of the first conductive contact pad 30 , the second conductive contact pad 31 and the support contact pad 32 may be 100 nm ⁇ 1000 nm, and the depth may be 100 nm ⁇ 500 nm.
  • At least one of the first conductive contact pad 30 and the second conductive contact pad 31 may be the same structure as the support contact pad 32 .
  • both the first conductive contact pad 30 and the second conductive contact pad 31 may be different structures from the support contact pad 32 .
  • An embodiment of the present disclosure also provides a method for fabricating a semiconductor structure, please refer to FIG. 8 , including:
  • a substrate 10 is provided, and conductive wires 20 are formed in the substrate 10;
  • the first conductive contact pad 30 is connected to the conductive wire 20, and is located above the conductive wire 20
  • the second conductive contact pad 31 is connected to the conductive wire 20, and is located above the conductive wire 20;
  • the first conductive contact pad 30 is spaced apart from the second conductive contact pad 31 .
  • a first conductive contact pad 30 and a second conductive contact pad 31 are formed which are connected to the conductive wire 20 , and the first conductive contact pad 30 and the second conductive contact pad 31 are formed. 31 are arranged at intervals, thereby changing the contact surface of the conductive wire 20 for connecting with other conductive structures, thereby improving the connection reliability of the semiconductor structure and helping to improve the conductive connection performance of the semiconductor structure.
  • the substrate 10 includes a silicon substrate and an insulating layer formed above the silicon substrate, the upper portion of the conductive wire 20 is located in the insulating layer, and both the first conductive contact pad 30 and the second conductive contact pad 31 are formed In the insulating layer, the upper surface of the first conductive contact pad 30 and the upper surface of the second conductive contact pad 31 are both flush with the upper surface of the insulating layer. That is, when used for bonding two wafers, the insulating layers of the two wafers are bonded, and the corresponding conductive contact pads are bonded.
  • the silicon substrate may be formed of a silicon-containing material.
  • the silicon substrate may be formed of any suitable material, including, for example, at least one of silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.
  • the insulating layer may include silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon carbon nitride (SiCN) and other related integrated circuit insulating materials.
  • the insulating layer includes a first insulating layer 12, and the upper portion of the conductive wire 20 is located in the first insulating layer 12. As shown in FIG. 9, a second insulating layer 13 is formed on the first insulating layer 12, and The second insulating layer 13 covers the tops of the conductive wires 20 , as shown in FIG. 10 .
  • conductive structures may also be provided in the silicon substrate and the insulating layer, which are not limited here, and may be selected according to the needs in the related art.
  • the first conductive contact pads 30 and the second conductive contact pads 31 are formed in the corresponding openings 11 .
  • a support contact pad 32 is formed in at least one of the plurality of openings 11 , and the support contact pad 32 is spaced from the conductive wire 20 .
  • a plurality of spaced openings 11 are formed on the second insulating layer 13 , and the openings 11 penetrate through the second insulating layer 13 , as shown in FIG. 11 . Then, first conductive contact pads 30 , second conductive contact pads 31 and support contact pads 32 are formed in the plurality of openings 11 , as shown in FIG. 12 .
  • the formation process of the second insulating layer 13, the first conductive contact pad 30, the second conductive contact pad 31 and the supporting contact pad 32 can be performed in a physical vapor deposition (Physical Vapor Deposition, PVD) process, chemical vapor deposition ( Chemical Vapor Deposition (CVD) process, Atomic Layer Deposition (ALD) process, In-Situ Steam Generation (ISSG) process and spin on dielectric (SOD) process, etc. Make a selection, which is not limited here.
  • PVD Physical Vapor Deposition
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • ISSG In-Situ Steam Generation
  • SOD spin on dielectric
  • the formation process of the opening 11 includes photolithography and etching. After each coating is formed, a polishing (Chemical Mechanical Polishing, CMP) process can be combined to ensure the flatness of the coating.
  • CMP Chemical Mechanical Polishing
  • the formation of the first conductive contact pads 30 , the second conductive contact pads 31 and the supporting contact pads 32 may adopt a process such as electroplating or sputtering, which is not limited herein.
  • the semiconductor structure may be formed by the above-described method of fabricating a semiconductor structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开涉及半导体技术领域，提出了一种半导体结构及半导体结构的制作方法。半导体结构包括第一芯片和第二芯片，第一导电接触垫和第二导电接触垫相间隔，且均与第一导电连线相连接；第三导电接触垫和第四导电接触垫相间隔，且均与第二导电连线相连接；第一导电接触垫和第二导电接触垫均与第三导电接触垫交错连接，第一导电接触垫和第二导电接触垫均与第四导电接触垫交错连接，以此保证第一导电连线和第二导电连线之间的可靠电连接，避免第一导电连线和第二导电连线出现断路问题，从而改善半导体结构的性能。

Description

半导体结构及半导体结构的制作方法
交叉引用
本公开要求于2021年03月10日提交的申请号为202110259349.7、名称为“半导体结构及半导体结构的制作方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及半导体结构的制作方法。
背景技术
相关技术中，芯片之间的键合是通过芯片上的金属垫相互连接而实现，但由于工艺限制，两个芯片之间的两个金属垫之间很容易出现断路或短路连接的问题。
发明内容
本公开提供一种半导体结构及半导体结构的制作方法，以改善半导体结构的性能。
根据本公开的第一个方面，提供了一种半导体结构，包括：
第一芯片，第一芯片包括第一衬底、第一导电连线、第一导电接触垫以及第二导电接触垫，第一导电接触垫和第二导电接触垫相间隔，且均与第一导电连线相连接；
第二芯片，第二芯片包括第二衬底、第二导电连线、第三导电接触垫以及第四导电接触垫，第三导电接触垫和第四导电接触垫相间隔，且均与第二导电连线相连接；
其中，第一导电接触垫和第二导电接触垫均与第三导电接触垫交错连接，第一导电接触垫和第二导电接触垫均与第四导电接触垫交错连接。
根据本公开的第二个方面，提供了一种半导体结构，包括：
衬底；
导电连线，导电连线位于衬底内；
第一导电接触垫，第一导电接触垫位于衬底内，第一导电接触垫与导电连线相连接，且位于导电连线的上方；
第二导电接触垫，第二导电接触垫位于衬底内，第二导电接触垫与导电连线相连接，且位于导电连线的上方；
其中，第一导电接触垫与第二导电接触垫相间隔。
根据本公开的第三个方面，提供了一种半导体结构的制作方法，包括：
提供一衬底，衬底内形成有导电连线；
在衬底内形成第一导电接触垫和第二导电接触垫，第一导电接触垫与导电连线相连接，且位于导电连线的上方，第二导电接触垫与导电连线相连接，且位于导电连线的上方；
其中，第一导电接触垫与第二导电接触垫相间隔。
本公开的半导体结构包括第一芯片和第二芯片，第一芯片的第一导电连线连接第一导电接触垫和第二导电接触垫，第二芯片的第二导电连线连接第三导电接触垫和第四导电接触垫，通过使得第一导电接触垫和第二导电接触垫均与第三导电接触垫交错连接，第一导电接触垫和第二导电接触垫均与第四导电接触垫交错连接，以此保证第一导电连线和第二导电连线之间的可靠电连接，避免第一导电连线和第二导电连线出现断路问题，从而改善半导体结构的性能。
附图说明
通过结合附图考虑以下对本公开的优选实施方式的详细说明，本公开的各种目标，特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标记始终表示相同或类似的部件。其中：
图1是根据一示例性实施方式示出的一种半导体结构的组合结构示意图；
图2是根据一示例性实施方式示出的一种半导体结构的分解结构示意图；
图3是根据一示例性实施方式示出的一种半导体结构的剖面结构示意图；
图4是根据一示例性实施方式示出的一种半导体结构的部分结构的一种连接结构示意图；
图5是根据一示例性实施方式示出的一种半导体结构的部分结构的另一种连接结构示意图；
图6是根据一示例性实施方式示出的一种半导体结构的结构示意图；
图7是根据一示例性实施方式示出的一种半导体结构的剖面结构示意图；
图8是根据一示例性实施方式示出的一种半导体结构的制作方法的流程示意图；
图9是根据一示例性实施方式示出的一种半导体结构的制作方法形成导电连线的结构示意图；
图10是根据一示例性实施方式示出的一种半导体结构的制作方法形成第二绝缘层的 结构示意图；
图11是根据一示例性实施方式示出的一种半导体结构的制作方法形成开口的结构示意图；
图12是根据一示例性实施方式示出的一种半导体结构的制作方法形成导电接触垫的结构示意图。
附图标记说明如下：
10、衬底；11、开口；12、第一绝缘层；13、第二绝缘层；20、导电连线；30、第一导电接触垫；31、第二导电接触垫；32、支撑接触垫；
40、第一芯片；41、第一衬底；42、第一导电连线；43、第一导电接触垫；44、第二导电接触垫；45、第一支撑接触垫；50、第二芯片；51、第二衬底；52、第二导电连线；53、第三导电接触垫；54、第四导电接触垫；55、第二支撑接触垫。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构，系统和步骤。应理解的是，可以使用部件，结构，示例性装置，系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”，“之间”，“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本公开的一个实施例提供了一种半导体结构，请参考图1至图3，半导体结构包括：第一芯片40，第一芯片40包括第一衬底41、第一导电连线42、第一导电接触垫43以及第二导电接触垫44，第一导电接触垫43和第二导电接触垫44相间隔，且均与第一导电连线42相连接；第二芯片50，第二芯片50包括第二衬底51、第二导电连线52、第三导电接触垫53以及第四导电接触垫54，第三导电接触垫53和第四导电接触垫54相间隔，且均与第二导电连线52相连接；其中，第一导电接触垫43和第二导电接触垫44均与第三导电接触垫53交错连接，第一导电接触垫43和第二导电接触垫44均与第四导电接触垫 54交错连接。
本公开一个实施例的半导体结构包括第一芯片40和第二芯片50，第一芯片40的第一导电连线42连接第一导电接触垫43和第二导电接触垫44，第二芯片50的第二导电连线52连接第三导电接触垫53和第四导电接触垫54，通过使得第一导电接触垫43和第二导电接触垫44均与第三导电接触垫53交错连接，第一导电接触垫43和第二导电接触垫44均与第四导电接触垫54交错连接，以此保证第一导电连线42和第二导电连线52之间的可靠电连接，避免第一导电连线42和第二导电连线52出现断路问题，从而改善半导体结构的性能。
需要说明的是，相对于相关技术中，上下两个键合的芯片之间的导电连接线是通过较大的一个接触面实现连接，而本实施例中，通过使得第一导电接触垫43和第二导电接触垫44均与第三导电接触垫53交错连接，第一导电接触垫43和第二导电接触垫44均与第四导电接触垫54交错连接，从而能够保证可靠的接触面，以此保证第一导电连线42和第二导电连线52之间的可靠电连接。
在一些实施例中，第一导电连线42、第一导电接触垫43以及第二导电接触垫44均位于第一衬底41内，第二导电连线52、第三导电接触垫53以及第四导电接触垫54均位于第二衬底51内，第一芯片40和第二芯片50键合。
需要说明的是，第一导电接触垫43以及第二导电接触垫44可以部分位于第一衬底41内，也可以全部位于第一衬底41内。相应的，第三导电接触垫53以及第四导电接触垫54可以部分位于第二衬底51内，也可以全部位于第二衬底51内。
在一些实施例中，第一导电接触垫43以及第二导电接触垫44可以位于第一衬底41的表面。相应的，第三导电接触垫53以及第四导电接触垫54可以第二衬底51的表面。
具体的，如图1和图2所示，第一芯片40包括第一衬底41、第一导电连线42、第一导电接触垫43以及第二导电接触垫44，第二芯片50包括第二衬底51、第二导电连线52、第三导电接触垫53以及第四导电接触垫54，在第一芯片40和第二芯片50键合后，第一衬底41和第二衬底51相键合，而第一导电接触垫43和第二导电接触垫44均与第三导电接触垫53和第四导电接触垫54相连接，在某些情况下即使出现错位，也可以存在相互接触的部分，从而保证第一导电连线42和第二导电连线52之间的可靠电连接。
在一些实施例中，第一导电接触垫43和第二导电接触垫44可以是完全相同的结构。第三导电接触垫53和第四导电接触垫54可以是完全相同的结构。
在一些实施例中，第一导电接触垫43和第二导电接触垫44可以是不相同的结构。第 三导电接触垫53和第四导电接触垫54可以是不相同的结构。
在一些实施例中，第一导电接触垫43和第二导电接触垫44中的至少之一可以是多个。第三导电接触垫53和第四导电接触垫54中的至少之一可以是多个。
在一个实施例中，第一导电接触垫43的延伸方向与第二导电接触垫44的延伸方向相一致，即第一导电接触垫43和第二导电接触垫44之间的距离是一个固定值。
相应的，第三导电接触垫53的延伸方向与第四导电接触垫54的延伸方向相一致，即第三导电接触垫53和第四导电接触垫54之间的距离是一个固定值。
在一些实施例中，第一导电接触垫43和第二导电接触垫44均沿直线方向延伸，第三导电接触垫53和第四导电接触垫54均沿直线方向延伸。
在一些实施例中，第一导电接触垫43和第二导电接触垫44均沿曲线方向延伸，第三导电接触垫53和第四导电接触垫54均沿曲线方向延伸。
在一个实施例中，第一导电接触垫43与第二导电接触垫44相平行，即第一导电接触垫43与第二导电接触垫44沿直线方向延伸，以此减小第一导电接触垫43与第二导电接触垫44的长度。
相应的，第三导电接触垫53与第四导电接触垫54相平行，即第三导电接触垫53与第四导电接触垫54沿直线方向延伸，以此减小第三导电接触垫53与第四导电接触垫54的长度。
在一些实施例中，第一导电接触垫43与第三导电接触垫53相垂直。
具体的，如图4所示，第一导电接触垫43和第二导电接触垫44相平行，第三导电接触垫53与第四导电接触垫54相平行，且第一导电接触垫43与第三导电接触垫53相垂直，即上下接触垫之间的接触面积可以是最小，但可以保证稳定的接触面积。即使出现错位键合，即键合对准不良，接触面积依然可以保证不变，接触面阻值影响很小，如图5所示。
在一些实施例中，第一导电接触垫43与第三导电接触垫53之间的夹角可以大于0度小于180度，即保证可以出现交错设置即可，相对于第一导电接触垫43与第三导电接触垫53相垂直，此时上下接触垫之间的接触面积会较大。
在一个实施例中，如图1和图2所示，第一芯片40还包括第一支撑接触垫45，第一支撑接触垫45与第一导电连线42相间隔，第一导电接触垫43和第二导电接触垫44均与第一支撑接触垫45相间隔；第二芯片50还包括第二支撑接触垫55，第二支撑接触垫55与第二导电连线52相间隔，第三导电接触垫53和第四导电接触垫54均与第二支撑接触垫55相间隔；其中，第一支撑接触垫45和第二支撑接触垫55交错连接。第一支撑接触 垫45和第二支撑接触垫55的设置虽然可以不实现电连接，但能够起到支撑保护作用，以此提高半导体结构的稳定性和强度。
进一步地，第一支撑接触垫45的长度大于第一导电连线42的直径，即第一支撑接触垫45不与第一导电连线42相连接，且第一支撑接触垫45的两端均位于第一导电连线42的外围。
相应的，第二支撑接触垫55的长度大于第二导电连线52的直径，即第二支撑接触垫55不与第二导电连线52相连接，且第二支撑接触垫55的两端均位于第二导电连线52的外围。
在一些实施例中，第一支撑接触垫45位于第一衬底41内，第一支撑接触垫45可以完全位于第一衬底41内，且其上表面与第一衬底41的上表面相平齐，或者第一支撑接触垫45可以部分位于第一衬底41内，即第一支撑接触垫45凸出第一衬底41的上表面。
相应的，第二支撑接触垫55位于第二衬底51内，第二支撑接触垫55可以完全位于第二衬底51内，且其上表面与第二衬底51的上表面相平齐，或者第二支撑接触垫55可以部分位于第二衬底51内，即第二支撑接触垫55凸出第二衬底51的上表面。
在一些实施例中，第一支撑接触垫45位于第一衬底41的上表面，第二支撑接触垫55位于第二衬底51的上表面。
在一个实施例中，第一支撑接触垫45成对设置，第一导电接触垫43和第二导电接触垫44位于成对的两个第一支撑接触垫45之间，即最外侧的两个第一支撑接触垫45实现可靠保护。
相应的，第二支撑接触垫55成对设置，第三导电接触垫53和第四导电接触垫54位于成对的两个第二支撑接触垫55之间。
在一些实施例中，第一支撑接触垫45和第二支撑接触垫55的数量可以均大于两个，此处不作限定。
在一些实施例中，第一支撑接触垫45沿垂直第一衬底41方向上的正投影与第一导电连线42相重合，即第一支撑接触垫45的至少部分可以位于第一导电连线42的正上方，但第一支撑接触垫45与第一导电连线42之间间隔设置。
相应的，第二支撑接触垫55沿垂直第二衬底51方向上的正投影与第二导电连线52相重合，即第二支撑接触垫55的至少部分可以位于第二导电连线52的正上方，但第二支撑接触垫55与第二导电连线52之间间隔设置。
在一些实施例中，第一支撑接触垫45沿垂直第一衬底41方向上的正投影与第一导电 连线42不重合，即第一支撑接触垫45位于第一导电连线42的外围区域。其中，第一支撑接触垫45的下表面可以高于第一导电连线42的上表面，或者第一支撑接触垫45的下表面可以等于第一导电连线42的上表面，或者第一支撑接触垫45的下表面可以低于第一导电连线42的上表面。
相应的，第二支撑接触垫55沿垂直第二衬底51方向上的正投影与第二导电连线52不重合，即第二支撑接触垫55位于第二导电连线52的外围区域。其中，第二支撑接触垫55的下表面可以高于第二导电连线52的上表面，或者第二支撑接触垫55的下表面可以等于第二导电连线52的上表面，或者第二支撑接触垫55的下表面可以低于第二导电连线52的上表面。
在一些实施例中，第一导电接触垫43和第二导电接触垫44之间的间距等于第三导电接触垫53和第四导电接触垫54之间的间距。
在一些实施例中，第一导电接触垫43和第二导电接触垫44之间的间距不等于第三导电接触垫53和第四导电接触垫54之间的间距，即使第一芯片40和第二芯片50之间出现键合偏差，也可以保证第一芯片40和第二芯片50的接触垫之间具有足够的接触面积，避免出现断路问题。
在一个实施例中，第一导电连线42为第一硅通孔；第二导电连线52为第二硅通孔。即第一硅通孔和第二硅通孔通过相互交错的接触垫实现连接。
在一些实施例中，第一导电接触垫43和第二导电接触垫44的长度均大于第一导电连线42的直径，即第一导电接触垫43和第二导电接触垫44的两端可以均位于第一导电连线42的外侧，不与第一导电连线42直接接触。
相应的，第三导电接触垫53和第四导电接触垫54的长度均大于第二导电连线52的直径，即第三导电接触垫53和第四导电接触垫54的两端可以均位于第二导电连线52的外侧，不与第二导电连线52的直接接触。
在一些实施例中，第一导电接触垫43和第二导电接触垫44可以均为矩形结构，第三导电接触垫53和第四导电接触垫54可以均为矩形结构。第一支撑接触垫45和第二支撑接触垫55可以均为矩形结构。
在一些实施例中，第一导电连线42、第一导电接触垫43以及第二导电接触垫44可以包括铜(Cu)、钨(W)等等相关集成电路导电材料。
相应的，第二导电连线52、第三导电接触垫53以及第四导电接触垫54可以包括铜(Cu)、钨(W)等等相关集成电路导电材料。第一支撑接触垫45和第二支撑接触垫55 可以包括铜(Cu)、钨(W)等等相关集成电路导电材料。
在一些实施例中，第一导电接触垫43、第二导电接触垫44以及第一支撑接触垫45中的至少之一的宽度可以为100nm～1000nm，深度可为100nm～500nm。
第三导电接触垫53、第四导电接触垫54以及第二支撑接触垫55第二支撑接触垫55中的至少之一的宽度可以为100nm～1000nm，深度可为100nm～500nm。
在一些实施例中，第一导电接触垫43和第二导电接触垫44中的至少一个可以与第一支撑接触垫45为相同的结构。第三导电接触垫53和第四导电接触垫54中的至少一个可以与第二支撑接触垫55为相同的结构。
在一些实施例中，第一导电接触垫43和第二导电接触垫44均可以与第一支撑接触垫45为不相同的结构。第三导电接触垫53和第四导电接触垫54均可以与第二支撑接触垫55为不相同的结构。
本公开的一个实施例还提供了一种半导体结构，请参考图6和图7，半导体结构包括：衬底10；导电连线20，导电连线20位于衬底10内；第一导电接触垫30，第一导电接触垫30位于衬底10内，第一导电接触垫30与导电连线20相连接，且位于导电连线20的上方；第二导电接触垫31，第二导电接触垫31位于衬底10内，第二导电接触垫31与导电连线20相连接，且位于导电连线20的上方；其中，第一导电接触垫30与第二导电接触垫31相间隔。
本公开一个实施例的半导体结构包括衬底10和导电连线20，导电连线20上连接有第一导电接触垫30和第二导电接触垫31，通过将第一导电接触垫30和第二导电接触垫31间隔设置，从而改变了导电连线20用于与其他导电结构相连接的接触面，以此改善半导体结构的连接可靠性，有利于提高半导体结构的导电连接性能。
需要说明的是，第一导电接触垫30位于衬底10内，第一导电接触垫30可以是部分位于衬底10内，也可以是全部位于衬底10内。相应的，第二导电接触垫31位于衬底10内可以是部分位于衬底10内，也可以是全部位于衬底10内。
在一些实施例中，第一导电接触垫30和第二导电接触垫31可以是相同的结构。
在一些实施例中，第一导电接触垫30和第二导电接触垫31可以是不相同的结构。
在一些实施例中，第一导电接触垫30和第二导电接触垫31中的至少之一可以是多个。
在一个实施例中，第一导电接触垫30的延伸方向与第二导电接触垫31的延伸方向相一致，即第一导电接触垫30和第二导电接触垫31之间的距离是一个固定值。
在一些实施例中，第一导电接触垫30和第二导电接触垫31均沿直线方向延伸。
在一些实施例中，第一导电接触垫30和第二导电接触垫31均沿曲线方向延伸。
在一个实施例中，第一导电接触垫30与第二导电接触垫31相平行，即第一导电接触垫30与第二导电接触垫31沿直线方向延伸，以此减小第一导电接触垫30与第二导电接触垫31的长度。
在一个实施例中，如图6和图7所示，半导体结构还包括：支撑接触垫32，支撑接触垫32位于衬底10内，支撑接触垫32与导电连线20相间隔；其中，第一导电接触垫30和第二导电接触垫31均与支撑接触垫32相间隔。支撑接触垫32的设置能够虽然可以不实现电连接，但能够起到支撑保护作用，以此提高半导体结构的稳定性和强度。
进一步地，支撑接触垫32的长度大于导电连线20的直径，即支撑接触垫32不与导电连线20相连接，且支撑接触垫32的两端均位于导电连线20的外围。
在一些实施例中，支撑接触垫32位于衬底10内，支撑接触垫32可以是部分位于衬底10内，也可以是全部位于衬底10内。
在一个实施例中，支撑接触垫32成对设置，第一导电接触垫30和第二导电接触垫31位于成对的两个支撑接触垫32之间，即最外侧的两个支撑接触垫32实现可靠保护。
在一些实施例中，支撑接触垫32的数量可以均大于两个，此处不作限定。
在一些实施例中，支撑接触垫32沿垂直衬底10方向上的正投影与导电连线20相重合，即支撑接触垫32的至少部分可以位于导电连线20的正上方，但支撑接触垫32与导电连线20之间间隔设置。
在一些实施例中，支撑接触垫32沿垂直衬底10方向上的正投影与导电连线20不重合，即支撑接触垫32可以位于导电连线20的外围区域，但支撑接触垫32与导电连线20之间间隔设置。其中，支撑接触垫32的下表面可以高于导电连线20的上表面，或者支撑接触垫32的下表面可以等于导电连线20的上表面，或者支撑接触垫32的下表面可以低于导电连线20的上表面。
在一个实施例中，导电连线20为硅通孔。
在一些实施例中，第一导电接触垫30和第二导电接触垫31的长度均大于导电连线20的直径，即第一导电接触垫30和第二导电接触垫31的两端可以均位于导电连线20的外侧，不与导电连线20直接接触。
在一些实施例中，第一导电接触垫30和第二导电接触垫31可以均为矩形结构，支撑接触垫32可以为矩形结构。
在一些实施例中，第一导电接触垫30、第二导电接触垫31以及支撑接触垫32可以包 括铜(Cu)、钨(W)等等相关集成电路导电材料。
第一导电接触垫30、第二导电接触垫31以及支撑接触垫32中的至少之一的宽度可以为100nm～1000nm，深度可为100nm～500nm。
在一些实施例中，第一导电接触垫30和第二导电接触垫31中的至少一个可以与支撑接触垫32为相同的结构。
在一些实施例中，第一导电接触垫30和第二导电接触垫31均可以与支撑接触垫32为不相同的结构。
本公开的一个实施例还提供了一种半导体结构的制作方法，请参考图8，包括：
S101，提供一衬底10，衬底10内形成有导电连线20；
S103，在衬底10内形成第一导电接触垫30和第二导电接触垫31，第一导电接触垫30与导电连线20相连接，且位于导电连线20的上方，第二导电接触垫31与导电连线20相连接，且位于导电连线20的上方；
其中，第一导电接触垫30与第二导电接触垫31相间隔。
本公开一个实施例的半导体结构的制作方法，通过形成有与导电连线20连接的第一导电接触垫30和第二导电接触垫31，且使得第一导电接触垫30和第二导电接触垫31间隔设置，从而改变了导电连线20用于与其他导电结构相连接的接触面，以此改善半导体结构的连接可靠性，有利于提高半导体结构的导电连接性能。
在一个实施例中，衬底10包括硅衬底和形成于硅衬底上方的绝缘层，导电连线20的上部位于绝缘层内，第一导电接触垫30与第二导电接触垫31均形成于绝缘层内，第一导电接触垫30的上表面和第二导电接触垫31的上表面均与绝缘层的上表面相平齐。即在用于两个晶圆键合时，两个晶圆的绝缘层相键合，相应的导电接触垫相键合。
具体的，硅衬底可以由含硅材料形成。硅衬底可以由任何合适的材料形成，例如，包括硅、单晶硅、多晶硅、非晶硅、硅锗、单晶硅锗、多晶硅锗以及碳掺杂硅中的至少一种。
绝缘层可以包括二氧化硅(SiO2)、碳氧化硅(SiOC)、氮化硅(SiN)、碳氮化硅(SiCN)等相关集成电路绝缘材料。
在一些实施例中，绝缘层包括第一绝缘层12，导电连线20的上部位于第一绝缘层12内，如图9所示，在第一绝缘层12上形成第二绝缘层13，且第二绝缘层13覆盖导电连线20的顶端，如图10所示。
需要说明的是，硅衬底以及绝缘层内还可以设置有其他导电结构，此处不作限定，可以根据相关技术中的需要进行相应的选择。
在一个实施例中，在绝缘层上形成多个相间隔的开口11之后，第一导电接触垫30与第二导电接触垫31形成于相应的开口11内。
在一个实施例中，多个开口11中的至少一个内形成有支撑接触垫32，支撑接触垫32与导电连线20相间隔。
在图10的基础上，在第二绝缘层13上形成多个间隔的开口11，开口11贯穿第二绝缘层13，如图11所示。然后在多个开口11内形成第一导电接触垫30、第二导电接触垫31以及支撑接触垫32，如图12所示。
需要说明的是，第二绝缘层13、第一导电接触垫30、第二导电接触垫31以及支撑接触垫32的形成工艺可以在物理气相沉积(Physical Vapor Deposition，PVD)工艺、化学气相沉积(Chemical Vapor Deposition，CVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、原位水汽生成(In-Situ Steam Generation，ISSG)工艺以及旋涂介电层(spin on dielectric，SOD)工艺等中进行选择，此处不作限定。
开口11的形成工艺包括光刻以及蚀刻等。在每个涂层形成后可以结合抛光(Chemical Mechanical Polishing，CMP)工艺进行处理，以此保证涂层的平整度。第一导电接触垫30、第二导电接触垫31以及支撑接触垫32的形成可以采用电镀或者溅射等工艺，此处不作限定。
在一个实施例中，半导体结构可以由上述的半导体结构的制作方法形成。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本公开的真正范围和精神由前面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (20)

  1. 一种半导体结构，包括：
    第一芯片，所述第一芯片包括第一衬底、第一导电连线、第一导电接触垫以及第二导电接触垫，所述第一导电接触垫和所述第二导电接触垫相间隔，且均与所述第一导电连线相连接；
    第二芯片，所述第二芯片包括第二衬底、第二导电连线、第三导电接触垫以及第四导电接触垫，所述第三导电接触垫和所述第四导电接触垫相间隔，且均与所述第二导电连线相连接；
    其中，所述第一导电接触垫和所述第二导电接触垫均与所述第三导电接触垫交错连接，所述第一导电接触垫和所述第二导电接触垫均与所述第四导电接触垫交错连接。
  2. 根据权利要求1所述的半导体结构，其中，所述第一导电接触垫的延伸方向与所述第二导电接触垫的延伸方向相一致；
    所述第三导电接触垫的延伸方向与所述第四导电接触垫的延伸方向相一致。
  3. 根据权利要求2所述的半导体结构，其中，所述第一导电接触垫与所述第二导电接触垫相平行；
    所述第三导电接触垫与所述第四导电接触垫相平行。
  4. 根据权利要求3所述的半导体结构，其中，所述第一导电接触垫与所述第三导电接触垫相垂直。
  5. 根据权利要求1所述的半导体结构，其中，所述第一芯片还包括第一支撑接触垫，所述第一支撑接触垫与所述第一导电连线相间隔，所述第一导电接触垫和所述第二导电接触垫均与所述第一支撑接触垫相间隔；
    所述第二芯片还包括第二支撑接触垫，所述第二支撑接触垫与所述第二导电连线相间隔，所述第三导电接触垫和所述第四导电接触垫均与所述第二支撑接触垫相间隔；
    其中，所述第一支撑接触垫和所述第二支撑接触垫交错连接。
  6. 根据权利要求5所述的半导体结构，其中，所述第一支撑接触垫成对设置，所述第一导电接触垫和所述第二导电接触垫位于成对的两个所述第一支撑接触垫之间；
    所述第二支撑接触垫成对设置，所述第三导电接触垫和所述第四导电接触垫位于成对的两个所述第二支撑接触垫之间。
  7. 根据权利要求5或6所述的半导体结构，其中，所述第一支撑接触垫沿垂直所述第 一衬底方向上的正投影与所述第一导电连线不重合；
    所述第二支撑接触垫沿垂直所述第二衬底方向上的正投影与所述第二导电连线不重合。
  8. 根据权利要求1所述的半导体结构，其中，所述第一导电接触垫和所述第二导电接触垫之间的间距不等于所述第三导电接触垫和所述第四导电接触垫之间的间距。
  9. 根据权利要求1所述的半导体结构，其中，所述第一导电连线为第一硅通孔；
    所述第二导电连线为第二硅通孔。
  10. 一种半导体结构，包括：
    衬底；
    导电连线，所述导电连线位于所述衬底内；
    第一导电接触垫，所述第一导电接触垫位于所述衬底内，所述第一导电接触垫与所述导电连线相连接，且位于所述导电连线的上方；
    第二导电接触垫，所述第二导电接触垫位于所述衬底内，所述第二导电接触垫与所述导电连线相连接，且位于所述导电连线的上方；
    其中，所述第一导电接触垫与所述第二导电接触垫相间隔。
  11. 根据权利要求10所述的半导体结构，其中，所述第一导电接触垫的延伸方向与所述第二导电接触垫的延伸方向相一致。
  12. 根据权利要求11所述的半导体结构，其中，所述第一导电接触垫与所述第二导电接触垫相平行。
  13. 根据权利要求10所述的半导体结构，其中，所述半导体结构还包括：
    支撑接触垫，所述支撑接触垫位于所述衬底内，所述支撑接触垫与所述导电连线相间隔；
    其中，所述第一导电接触垫和所述第二导电接触垫均与所述支撑接触垫相间隔。
  14. 根据权利要求13所述的半导体结构，其中，所述支撑接触垫成对设置，所述第一导电接触垫和所述第二导电接触垫位于成对的两个所述支撑接触垫之间。
  15. 根据权利要求13或14所述的半导体结构，其中，所述支撑接触垫沿垂直所述衬底方向上的正投影与所述导电连线不重合。
  16. 根据权利要求10所述的半导体结构，其中，所述导电连线为硅通孔。
  17. 一种半导体结构的制作方法，包括：
    提供一衬底，所述衬底内形成有导电连线；
    在所述衬底内形成第一导电接触垫和第二导电接触垫，所述第一导电接触垫与所述导电连线相连接，且位于所述导电连线的上方，所述第二导电接触垫与所述导电连线相连接，且位于所述导电连线的上方；
    其中，所述第一导电接触垫与所述第二导电接触垫相间隔。
  18. 根据权利要求17所述的半导体结构的制作方法，其中，所述衬底包括硅衬底和形成于所述硅衬底上方的绝缘层，所述导电连线的上部位于所述绝缘层内，所述第一导电接触垫与所述第二导电接触垫均形成于所述绝缘层内，所述第一导电接触垫的上表面和所述第二导电接触垫的上表面均与所述绝缘层的上表面相平齐。
  19. 根据权利要求18所述的半导体结构的制作方法，其中，在所述绝缘层上形成多个相间隔的开口之后，所述第一导电接触垫与所述第二导电接触垫形成于相应的所述开口内。
  20. 根据权利要求19所述的半导体结构的制作方法，其中，多个所述开口中的至少一个内形成有支撑接触垫，所述支撑接触垫与所述导电连线相间隔。
PCT/CN2021/110616 2021-03-10 2021-08-04 半导体结构及半导体结构的制作方法 WO2022188348A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21873688.2A EP4287243A1 (en) 2021-03-10 2021-08-04 Semiconductor structure and method for manufacturing semiconductor structure
US17/650,389 US20220293542A1 (en) 2021-03-10 2022-02-09 Semiconductor structure and manufacturing method of semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110259349.7 2021-03-10
CN202110259349.7A CN115083933A (zh) 2021-03-10 2021-03-10 半导体结构及半导体结构的制作方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/650,389 Continuation US20220293542A1 (en) 2021-03-10 2022-02-09 Semiconductor structure and manufacturing method of semiconductor structure

Publications (1)

Publication Number Publication Date
WO2022188348A1 true WO2022188348A1 (zh) 2022-09-15

Family

ID=83226201

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/110616 WO2022188348A1 (zh) 2021-03-10 2021-08-04 半导体结构及半导体结构的制作方法

Country Status (2)

Country Link
CN (1) CN115083933A (zh)
WO (1) WO2022188348A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810649A (zh) * 2014-12-29 2016-07-27 格科微电子（上海）有限公司 半导体装置键合结构及其键合方法
US9620480B1 (en) * 2013-06-28 2017-04-11 STATS ChipPAC Pte. Ltd Integrated circuit packaging system with unplated leadframe and method of manufacture thereof
US20170309549A1 (en) * 2016-04-21 2017-10-26 Texas Instruments Incorporated Sintered Metal Flip Chip Joints
CN109950221A (zh) * 2019-04-15 2019-06-28 德淮半导体有限公司 半导体装置及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620480B1 (en) * 2013-06-28 2017-04-11 STATS ChipPAC Pte. Ltd Integrated circuit packaging system with unplated leadframe and method of manufacture thereof
CN105810649A (zh) * 2014-12-29 2016-07-27 格科微电子（上海）有限公司 半导体装置键合结构及其键合方法
US20170309549A1 (en) * 2016-04-21 2017-10-26 Texas Instruments Incorporated Sintered Metal Flip Chip Joints
CN109950221A (zh) * 2019-04-15 2019-06-28 德淮半导体有限公司 半导体装置及其制造方法

Also Published As

Publication number Publication date
CN115083933A (zh) 2022-09-20

Similar Documents

Publication Publication Date Title
TWI731782B (zh) 半導體結構及其形成方法
US9779992B2 (en) Semiconductor device and method of manufacturing the same
TW480693B (en) Improved bonding pad and support structure and method for their fabrication
TW201935642A (zh) 包含通孔插塞的半導體裝置及其形成方法
TW201743430A (zh) 三維積體電路結構及其形成方法
US9449811B2 (en) Air-gap scheme for BEOL process
TW200919633A (en) Semiconductor contact structure
CN102760563A (zh) 集成变压器
JP2012033796A (ja) 半導体装置
TWI652514B (zh) 波導結構以及其製作方法
JP2004031439A (ja) 半導体集積回路装置およびその製造方法
US20210028129A1 (en) Semiconductor device with guard ring
TW202032801A (zh) 新穎的電容器結構及其形成方法
TWI758122B (zh) 半導體結構及其形成方法
WO2022188348A1 (zh) 半导体结构及半导体结构的制作方法
KR100873450B1 (ko) 복수의 도전성 구조체 레벨을 갖는 집적 회로 장치 및 방법
TWI707401B (zh) 基本原則區域中完全對準介層窗
WO2022188346A1 (zh) 半导体结构及半导体结构的制作方法
US20220293542A1 (en) Semiconductor structure and manufacturing method of semiconductor structure
US11569188B2 (en) Semiconductor device including elongated bonding structure between the substrate
CN112018074B (zh) 半导体结构与连线结构的制作方法
TWI825707B (zh) 具有多堆疊載體結構之半導體元件的製備方法
TW201639162A (zh) 半導體裝置及其製造方法
KR100718451B1 (ko) 반도체 장치의 금속 배선 및 그 제조 방법
TW202242175A (zh) 改善晶圓翹曲的方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21873688

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE