WO2022188342A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2022188342A1
WO2022188342A1 PCT/CN2021/109969 CN2021109969W WO2022188342A1 WO 2022188342 A1 WO2022188342 A1 WO 2022188342A1 CN 2021109969 W CN2021109969 W CN 2021109969W WO 2022188342 A1 WO2022188342 A1 WO 2022188342A1
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Prior art keywords
layer
dielectric layer
dielectric
current blocking
lower electrode
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English (en)
French (fr)
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袁盼
苏星松
张强
应战
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/648,350 priority Critical patent/US12295151B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and a method of fabricating the same.
  • the capacitors need to have higher capacitance in a smaller size.
  • it is usually realized by increasing the dielectric constant of the material of the dielectric layer in the capacitor.
  • the dielectric constant of the material of the dielectric layer is related to the crystal structure of the material itself. How to improve the dielectric constant of the material of the dielectric layer without changing the material of the dielectric layer has become an urgent problem to be solved.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof.
  • An embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate; forming a lower electrode layer on the substrate, wherein the crystal structure of the lower electrode layer includes a tetragonal crystal system; and using the lower electrode layer as a crystal seed layer, a first dielectric layer is formed on the surface of the lower electrode layer, and the crystal structure of the first dielectric layer includes a tetragonal system; a first current blocking layer is formed on the surface of the first dielectric layer.
  • An embodiment of the present application further provides a semiconductor structure, including: a substrate; a lower electrode layer, the lower electrode layer is located on the substrate, and the crystal structure of the lower electrode layer includes a tetragonal crystal system; a first dielectric layer, The first dielectric layer is located on the surface of the lower electrode layer, and the crystal structure of the first dielectric layer includes a tetragonal system; the first current blocking layer is located on the first dielectric layer. surface of the electrical layer.
  • FIG. 1 is a schematic partial cross-sectional structural diagram corresponding to a step of forming a lower electrode layer on a substrate according to an embodiment of the present application;
  • FIG. 2 is a schematic partial cross-sectional structural diagram corresponding to a step of forming a first dielectric layer on the surface of the lower electrode layer according to an embodiment of the present application;
  • FIG. 3 is a schematic partial cross-sectional structural diagram corresponding to a step of forming a first current blocking layer on the surface of the first dielectric layer according to an embodiment of the present application;
  • FIG. 4 is a schematic partial cross-sectional structural diagram corresponding to a step of sequentially stacking a first sacrificial layer, an intermediate support layer, a second sacrificial layer and a top support layer on a substrate according to an embodiment of the present application;
  • FIG. 5 is a schematic partial cross-sectional structural diagram corresponding to a step of forming a base lower electrode layer on the bottom and sidewalls of a capacitor hole according to an embodiment of the present application;
  • FIG. 6 is a schematic partial cross-sectional structural diagram corresponding to the steps of forming a substrate and forming a lower electrode layer on the substrate according to an embodiment of the present application;
  • FIG. 7 is a schematic partial cross-sectional structural diagram corresponding to the step of forming a dielectric layer on the surface of the lower electrode layer according to an embodiment of the present application;
  • FIG. 8 is a schematic partial cross-sectional structural diagram corresponding to a step of forming a second dielectric layer on the surface of the first current blocking layer according to another embodiment of the present application;
  • FIG. 9 is a schematic partial cross-sectional structural diagram corresponding to a step of depositing a second current blocking layer on the surface of the second dielectric layer according to another embodiment of the present application.
  • FIG. 10 is a schematic partial cross-sectional structural diagram corresponding to a step of forming a second dielectric layer on the first current blocking layer according to still another embodiment of the present application;
  • FIG. 11 is a schematic partial cross-sectional structure diagram corresponding to a step of depositing a second current blocking layer on the surface of the second dielectric layer according to still another embodiment of the present application.
  • the presence of the seed layer in the dielectric layer increases the overall thickness of the dielectric layer, thereby reducing the capacitor's performance. capacitance, and it is also not conducive to the formation of smaller capacitors.
  • Embodiments of the present application provide a semiconductor structure and a fabrication method thereof.
  • the crystal structure of the lower electrode layer is tetragonal
  • the lower electrode layer is used as a seed layer to form the first dielectric layer, so that the crystal structure of the first dielectric layer is also tetragonal, which is beneficial to not change the first dielectric layer.
  • forming a first dielectric layer with a higher dielectric constant is beneficial to improve the capacitance of the capacitor in the semiconductor structure, thereby improving the electrical properties of the semiconductor structure, and it is not necessary to use an annealing process to form crystals
  • the structure of the first dielectric layer of the tetragonal system is beneficial to simplify the process steps of preparing the first dielectric layer.
  • the technical solution is beneficial to reduce the thickness of the dielectric layer, thereby further improving the capacitance of the subsequently formed capacitor.
  • 1 to 7 are schematic partial cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • 3 is a schematic diagram of a cross-sectional structure of the region I in FIG. 7 .
  • a substrate 100 is provided; a lower electrode layer 101 is formed on the substrate 100 .
  • the crystal structure of the lower electrode layer 101 is a tetragonal crystal system, which is beneficial to be used as a seed layer for forming the first dielectric layer later, without additionally forming a seed layer in the first dielectric layer, which is beneficial to reduce the
  • the thickness of a dielectric layer is beneficial to improve the capacitance of the capacitor formed subsequently and realize the miniaturization of the capacitor size.
  • the material of the lower electrode layer 101 includes at least one of ruthenium oxide or iridium oxide. Using ruthenium oxide and iridium oxide to form the lower electrode layer 101 can form the lower electrode layer 101 with a tetragonal crystal structure without an annealing process, which is beneficial to simplify the process steps for preparing the lower electrode layer 101 .
  • a method of forming the lower electrode layer 101 includes an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.
  • the lower electrode layer 101 is formed by the atomic layer deposition process. Since the atomic layer deposition process is a method that can deposit substances on the surface of the substrate 100 layer by layer in the form of a single atomic film, the atomic layer deposition process is adopted. The process of forming the lower electrode layer 101 can ensure that the atoms in the lower electrode layer 101 are arranged in a repeated and regular manner, and ensure that the crystal structure of the lower electrode layer 101 is a tetragonal crystal system.
  • the temperature parameter of the atomic layer deposition process is 280° C. ⁇ 400° C., which is favorable for forming the lower electrode layer 101 with higher density and higher strength.
  • the thickness of the lower electrode layer 101 is 1 nm ⁇ 30 nm, for example, 5 nm, 15 nm or 25 nm.
  • the lower electrode layer 101 is a seed layer, and a first dielectric layer 102 is formed on the surface of the lower electrode layer 101 .
  • the first dielectric layer 102 is formed by an epitaxial process. Since the epitaxial process is favorable for forming the first dielectric layer 102 with the same crystal structure as the lower electrode layer 101, the first dielectric layer 102 with a tetragonal crystal structure can be formed without an annealing process, which is beneficial to simplify the preparation of the first dielectric layer 102.
  • a process step of the dielectric layer 102 In the direction perpendicular to the surface of the substrate 100, the thickness of the first dielectric layer 102 is 0.1 nm ⁇ 10 nm, for example, 0.5 nm, 4 nm or 8 nm.
  • the material of the first dielectric layer 102 is hafnium oxide; the process temperature of the epitaxy process is 250°C ⁇ 600°C.
  • the dielectric constant of hafnium oxide whose crystal structure is monoclinic is 20 to 25, and the dielectric constant of hafnium oxide whose crystal structure is tetragonal is 40 to 60. It can be seen that using the lower electrode layer 101 with the crystal structure of the tetragonal system as the seed layer, and forming the first dielectric layer 102 with the crystal structure of the tetragonal system on the surface of the lower electrode layer 101 through an epitaxial process is beneficial to the first dielectric layer 102 without changing the first In the case of the material for forming the dielectric layer 102, the dielectric constant of the first dielectric layer 102 itself is increased; the dielectric layer of the capacitor formed subsequently includes the first dielectric layer 102, which is beneficial to improve the capacitance of the capacitor.
  • the material of the first dielectric layer 102 includes tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate, etc. at least one of the dielectric materials.
  • the method further includes: forming a first current blocking layer 103 on the surface of the first dielectric layer 102 .
  • the thickness of the first current blocking layer 103 is 0.1 nm ⁇ 5 nm, for example, 0.5 nm, 2 nm or 4 nm.
  • the material of the first current blocking layer 103 includes at least one of aluminum oxide, silicon oxide or silicon nitride. Since aluminum oxide, silicon oxide, and silicon nitride are all high-bandgap materials, that is, the energy difference between the lowest point of the conduction band and the highest point of the valence band in the first current blocking layer 103 is large, electrons are excited from the valence band to The more difficult the conduction band is, therefore, the conductivity of the first current blocking layer 103 is lower, and the dielectric layer of the capacitor formed subsequently includes the first current blocking layer 103, which is beneficial to improve the dielectric constant of the capacitor while reducing the electrical conductivity in the capacitor. leakage current to increase the capacitance of the capacitor, thereby improving the electrical performance of the semiconductor structure.
  • the method for forming the first current blocking layer 103 includes an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process, and the process temperature for forming the first current blocking layer 103 is 200° C. ⁇ 700° C.
  • the material of the first current blocking layer 103 is aluminum oxide
  • the first current blocking layer 103 is formed by an atomic layer deposition process
  • the process temperature of the atomic layer deposition process is 200°C to 700°C, which is beneficial to ensure the first current
  • the barrier layer 103 has a good inhibitory effect on the leakage current in the first dielectric layer 102 , thereby helping to improve the electrical performance of the subsequently formed capacitor.
  • an upper electrode layer may be directly formed on the first current blocking layer to form a capacitor.
  • a dielectric layer may also be formed on the first current blocking layer, and then an upper electrode layer may be directly formed on the dielectric layer to form a capacitor.
  • the step 101 of providing the substrate 100 and forming the lower electrode layer on the substrate 100 includes:
  • a substrate 11 is provided, and a first sacrificial layer 12 , a middle supporting layer 13 , a second sacrificial layer 14 and a top supporting layer 15 are formed in sequence on the substrate 11 .
  • the top support layer 15 , the second sacrificial layer 14 , the middle support layer 13 , the first sacrificial layer 12 and the substrate 11 are patterned to form through the top support layer 15 , the second sacrificial layer 14 , and the middle support layer 13 , the first sacrificial layer 12 and part of the capacitor holes of the substrate 11 , and the capacitor holes expose the substrate 11 .
  • a base lower electrode layer 111 is formed on the bottom and sidewalls of the capacitor hole.
  • part of the top support layer 15 , part of the middle support layer 13 , part of the base lower electrode layer 111 , the first sacrificial layer 12 and the second sacrificial layer 14 are removed to form the substrate 100 and to form on the substrate 100
  • the lower electrode layer 101 is
  • the first sacrificial layer 12 and the second sacrificial layer 14 are completely removed to expose the outer surface of the lower electrode layer 101 so as to facilitate the subsequent formation of the first dielectric layer on the surface of the lower electrode layer 101 .
  • FIG. 6 is a partial cross-sectional structural schematic diagram of the semiconductor structure, and the removed part of the top support layer 15 and the part of the middle support layer 13 are not shown in FIG. 6 .
  • FIG. 6 only actually illustrates one type of substrate 100 , and there may actually be more types of substrates for forming the lower electrode layer on the substrate, so as to facilitate the subsequent formation of capacitors on the substrate.
  • a dielectric layer 16 is formed on the surface of the lower electrode layer 101 .
  • the dielectric layer 16 includes the first dielectric layer 102 (refer to FIG. 3 ) and the first current blocking layer 103 (refer to FIG. 3 ) formed above.
  • the process steps of forming the first dielectric layer 102 on the surface of the lower electrode layer 101 include: conformally covering the surface of the structure formed by the lower electrode layer 101, the middle support layer 13 and the top support layer 15 with the first dielectric layer 102; A surface of a dielectric layer 102 conformally covers the first current blocking layer 103 .
  • the following electrode layer 101 is used as a seed layer to form the first dielectric layer 102, so that the crystal structure of the first dielectric layer 102 is also tetragonal, which is beneficial to form a first dielectric layer with a higher dielectric constant.
  • the dielectric layer 102; the dielectric layer of the capacitor to be formed subsequently includes at least the first dielectric layer 102, which is beneficial to improve the capacitance of the capacitor and thus the electrical performance of the semiconductor structure.
  • a first current blocking layer 103 may be formed on the upper surface of the first dielectric layer 102 to reduce leakage current in the first dielectric layer 102 to further improve the electrical performance of the semiconductor structure.
  • Yet another embodiment of the present application also provides a method for fabricating a semiconductor structure.
  • the fabrication method of the semiconductor structure provided in the second embodiment of the present application will be described in detail below with reference to the accompanying drawings. For the same or corresponding parts as the foregoing embodiments, reference may be made to the detailed descriptions of the foregoing embodiments, which will not be repeated here.
  • FIG. 8 to 9 are partial cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to another embodiment of the present application. It should be noted that FIG. 9 is a schematic diagram of a cross-sectional structure of the region I in FIG. 7 .
  • the second dielectric layer 204 is formed on the surface of the first current blocking layer 203.
  • the first current blocking layer 203 is beneficial to reduce leakage current in the first dielectric layer 202, and the dielectric layer of the capacitor formed subsequently includes the first current blocking layer 203, which is beneficial to improve the electrical performance of the capacitor.
  • the atomic layer deposition process is used to form the first current blocking layer 203 and the second dielectric layer 204, and in the direction perpendicular to the surface of the substrate 200, the thickness of the first current blocking layer 203 is 0.1 nm ⁇ 5 nm, For example, 0.5 nm, 2 nm or 4 nm, the thickness of the second dielectric layer 204 is 0.1 nm ⁇ 10 nm, for example, 0.5 nm, 4 nm or 8 nm.
  • a second current blocking layer 205 is deposited on the surface of the second dielectric layer 204 , and the deposition temperature is greater than or equal to the crystallization temperature required for the crystal structure of the second dielectric layer 204 to be transformed into a tetragonal system.
  • the process temperature used for depositing the second current blocking layer 205 is greater than or equal to the crystallization temperature required for the crystal structure in the second dielectric layer 204 to be transformed into the tetragonal system, after the second current blocking layer 205 is formed, the second dielectric
  • the crystal structure of the layer 204 is converted into a tetragonal crystal system, and an additional annealing process is not required to form the second dielectric layer 204 with a crystal structure of the tetragonal crystal system, which is beneficial to simplify the process steps for preparing the second dielectric layer 204 .
  • the crystal structure of the second dielectric layer 204 is a tetragonal crystal system.
  • the tetragonal crystal system has a relatively high dielectric constant, which is beneficial to the formation of the second dielectric layer 204 without changing it.
  • the dielectric constant of the second dielectric layer 204 is increased; the dielectric layer of the capacitor formed subsequently includes at least the first dielectric layer 202 and the second dielectric layer 204, which is beneficial to improve the capacitance of the capacitor.
  • the material of the second current blocking layer 205 includes at least one of aluminum oxide, silicon oxide or silicon nitride, which is beneficial to reduce the leakage current in the first dielectric layer 202 and the second dielectric layer 204, so as to further The capacitance of the capacitor is substantially increased, thereby improving the electrical performance of the semiconductor structure.
  • the method for depositing the second current blocking layer 205 includes an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process, and the process temperature for depositing the second current blocking layer 205 is 200°C ⁇ 700°C.
  • the material of the second dielectric layer 204 is zirconium oxide, and the thickness of the second dielectric layer 204 in the direction perpendicular to the surface of the substrate 200 is 0.1 nm ⁇ 10 nm, for example, 2 nm or 5 nm, and an atomic layer deposition process is used.
  • a second current blocking layer 205 is formed, the material of the second current blocking layer 205 is aluminum oxide, and the process temperature of the atomic layer deposition process is 200° C. ⁇ 700° C., for example, 330° C.
  • the crystal structure of the second dielectric layer 204 will be transformed into a tetragonal crystal system, and after forming the second current blocking layer 205 , the material of the second dielectric layer 204 is tetragonal crystal Series of zirconia.
  • an upper electrode layer may be directly formed on the second current blocking layer to form a capacitor.
  • a dielectric layer may also be formed on the second current blocking layer, and then an upper electrode layer may be directly formed on the dielectric layer to form a capacitor.
  • the crystal structure of the second dielectric layer 204 can be converted into a tetragonal system without an additional annealing process for the second dielectric layer 204 .
  • the dielectric constant of the second dielectric layer 204 is increased, so as to improve the capacitance of the capacitor and simplify the process steps of preparing the second dielectric layer 204 .
  • the second current blocking layer 205 is beneficial to reduce the leakage current in the first dielectric layer 202 and the second dielectric layer 204, so as to further improve the electrical performance of the semiconductor structure.
  • the dielectric layer 16 in the capacitor into a stacked structure, that is, the dielectric layer 16 at least includes the first dielectric layer 202 and the second dielectric layer 204, it is beneficial to improve the structural stability of the capacitor.
  • Another embodiment of the present application also provides a method for fabricating a semiconductor structure.
  • the fabrication method of the semiconductor structure provided by the third embodiment of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those of the previous embodiments, reference may be made to the detailed descriptions of the previous embodiments, which will not be omitted here. Repeat.
  • 10 to 11 are schematic partial cross-sectional structural diagrams corresponding to each step of the semiconductor structure provided by another embodiment of the present application. 10 to 11 are schematic diagrams of two cross-sectional structures of the region I in FIG. 7 .
  • the second dielectric layer 304 is formed on the first current blocking layer 303
  • the second dielectric layer 304 is formed on the first current blocking layer 303 .
  • the dielectric constant of the material of the electrical layer 304 is greater than the dielectric constant of the material of the first dielectric layer 302 .
  • the thickness of the second dielectric layer 304 is 0.1 nm ⁇ 10 nm, for example, 0.5 nm, 4 nm or 8 nm.
  • the dielectric layer 16 (referring to FIG. 7 ) includes a first dielectric layer 302 , a first current blocking layer 303 and a second dielectric layer 304 which are sequentially stacked.
  • the first current blocking layer 303 is beneficial to reduce the leakage current in the first dielectric layer 302; the capacitor formed subsequently includes the first current blocking layer 303, thus, is conducive to improving the electrical performance of the capacitor.
  • the dielectric constant of the material of the second dielectric layer 304 is greater than the dielectric constant of the material of the first dielectric layer 302 , and the dielectric layer 16 (refer to FIG. 15 ) of the subsequently formed capacitor includes the first dielectric layer 302 and the second dielectric layer 304, so as to further improve the capacitance of the capacitor.
  • the material of the second dielectric layer 304 is titanium oxide.
  • the dielectric constant of titanium oxide is 75-85. It can be seen from the description of the above first embodiment that the dielectric constant of the first dielectric layer 302 is 40-60.
  • the second dielectric layer 304 is titanium oxide, the second The dielectric constant of the dielectric layer 304 is much larger than that of the first dielectric layer 302 , which is beneficial to improve the effect of the second dielectric layer 304 on the overall dielectric constant of the dielectric layer 16 (refer to FIG. 7 ).
  • the method for forming the second dielectric layer 304 includes an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process.
  • the second dielectric layer 304 is formed by an atomic layer deposition process, and the temperature parameter of the atomic layer deposition process is 200°C ⁇ 700°C.
  • the material of the second dielectric layer may be at least one of titanium oxide, barium oxide or lanthanum lutetium oxide.
  • the method further includes: depositing a second current blocking layer on the surface of the second dielectric layer 304 Barrier layer 305 . Since the conductivity of the second current blocking layer 305 is relatively low, it is beneficial to reduce the leakage current in the second dielectric layer 304 and the first dielectric layer 302 ; the dielectric layer 16 of the subsequently formed capacitor also includes the second current blocking layer 305 , to further increase the capacitance of the capacitor, thereby improving the electrical performance of the semiconductor structure.
  • an upper electrode layer may be directly formed on the second current blocking layer to form a capacitor.
  • a dielectric layer may also be formed on the second current blocking layer, and then an upper electrode layer may be directly formed on the dielectric layer to form a capacitor.
  • a second dielectric layer 304 is further formed on the first dielectric layer 302, and the dielectric constant of the material of the second dielectric layer 304 is greater than the dielectric constant of the material of the first dielectric layer 302, then
  • the dielectric layer 16 of the subsequently formed capacitor is a laminated structure including the first dielectric layer 302 and the second dielectric layer 304 , which is beneficial to further improve the capacitance of the capacitor while improving the structural stability of the capacitor.
  • still another embodiment of the present application further provides a semiconductor structure, and the semiconductor structure is manufactured by the manufacturing method of the semiconductor structure provided by any of the above embodiments.
  • the semiconductor structure includes: a substrate 100; a lower electrode layer 101, the lower electrode layer 101 is located on the substrate 100, and the crystal structure of the lower electrode layer 101 includes a tetragonal system; a first dielectric layer 102, the first dielectric layer 102 is located on the surface of the lower electrode layer 101, and the crystal structure of the first dielectric layer 102 includes a tetragonal system, which is beneficial to improve the dielectric constant of the first dielectric layer 102; the first current blocking layer 103, the first current blocking layer 103 Located on the surface of the first dielectric layer 102, it is beneficial to reduce the leakage current in the first dielectric layer 102; further, the dielectric layer 16 is used to form a capacitor in the semiconductor structure, and the dielectric layer 16 includes the first dielectric layer 102 and the first dielectric layer 102.
  • a current blocking layer 103 in this way, is beneficial to improve the capacitance of the capacitor, thereby helping to improve the electrical performance of the semiconductor structure.
  • the thickness of the first dielectric layer is 0.1-10 nm, for example, 0.5 nm, 4 nm or 8 nm.
  • the material of the first dielectric layer 102 includes at least one of tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate and other dielectric materials. kind.
  • the base 100 includes: a substrate 11 ; an intermediate support layer 13 , the intermediate support layer 13 is located above the substrate 11 and has a distance from the substrate 11 ; a top support layer 15 , the top support layer 15 It is located above the intermediate support layer 13 and has a distance from the intermediate support layer 13 .
  • the thickness of the middle support layer 13 is 10 nm ⁇ 50 nm
  • the thickness of the top support layer 15 is 10 nm ⁇ 100 nm.
  • the material of the middle support layer 13 includes at least one of silicon nitride or silicon carbonitride, and the material of the top support layer 15 is the same as that of the middle support layer 13 . In other embodiments, the material of the top support layer 15 and the material of the middle support layer 13 may also be different.
  • the bottom and sidewalls of the lower electrode layer 101 enclose a through hole, and the bottom of the through hole is in contact with the substrate 11 ; the middle support layer 13 and the top support layer 15 are both separated from the lower electrode layer 101 away from the through hole. Part of the side walls are abutted.
  • the dielectric layer 16 conformally covers the surface of the structure formed by the lower electrode layer 101 , the middle support layer 13 and the top support layer 15 .
  • the dielectric layer 16 includes at least the first dielectric layer 102 described above.
  • FIG. 6 only actually illustrates one type of substrate 100 , in fact, there may be more types of substrates for forming the lower electrode layer on the substrate, so as to facilitate the subsequent formation of the capacitor with the dielectric layer 16 on the substrate .
  • the dielectric layer 16 further includes: a first current blocking layer 103, the first current blocking layer 103 is located on the surface of the first dielectric layer 102, which is beneficial to improve the dielectric constant of the capacitor in the semiconductor structure At the same time, the leakage current in the capacitor is reduced to further increase the capacitance of the capacitor, thereby improving the electrical performance of the semiconductor structure.
  • the dielectric layer 16 is formed by stacking the first dielectric layer 102 and the first current blocking layer 103 in sequence.
  • the dielectric layer 16 further includes: a first current blocking layer 203, the first current blocking layer 203 is located on the surface of the first dielectric layer 202; a second dielectric layer 204, the second dielectric layer 204 is located on the first On the surface of the current blocking layer 203 , the crystal structure of the second dielectric layer 204 includes a tetragonal system; the second current blocking layer 205 is located on the surface of the second dielectric layer of the second dielectric layer 204 . Further, the material of the second dielectric layer 204 includes zirconia.
  • the crystal structure of the second dielectric layer 204 is a tetragonal crystal system, which is beneficial to improve the dielectric constant of the capacitor in the semiconductor structure, while reducing the first dielectric layer 202 and passing through the first current blocking layer 203 .
  • the second current blocking layer 205 reduces leakage current in the second dielectric layer 204 to improve the electrical performance of the semiconductor structure.
  • the dielectric layer 16 is formed by stacking a first dielectric layer 202 , a first current blocking layer 203 , a second dielectric layer 204 and a second current blocking layer 205 in sequence.
  • the dielectric layer 16 further includes: a first current blocking layer 303, the first current blocking layer 303 is located on the surface of the first dielectric layer 302; a second dielectric layer 304, the second dielectric layer 304 is located on the first A surface of the current blocking layer 303, the dielectric constant of the material of the second dielectric layer 304 is greater than the dielectric constant of the material of the first dielectric layer 302; the second current blocking layer 305, the second current blocking layer 305 is located in the second dielectric layer surface of the electrical layer 304 .
  • the dielectric layer 16 is formed by stacking a first dielectric layer 302 , a first current blocking layer 303 , a second dielectric layer 304 and a second current blocking layer 305 in sequence.
  • the material of the second dielectric layer 304 includes at least one of titanium oxide, barium oxide or lanthanum lutetium oxide. Moreover, the dielectric constant of the material of the second dielectric layer 304 is greater than the dielectric constant of the material of the first dielectric layer 302, which is beneficial to further improve the dielectric constant of the capacitor to improve the electrical performance of the semiconductor structure.
  • the material of the first current blocking layer includes at least one of aluminum oxide, silicon oxide or silicon nitride, and the thickness of the first current blocking layer is 0.1 nm in the direction perpendicular to the surface of the substrate. ⁇ 5nm, eg 0.5nm, 2nm or 4nm.
  • the thickness of the second dielectric layer is 0.1 nm ⁇ 10 nm, such as 0.5 nm, 4 nm or 8 nm, and the thickness of the second current blocking layer is 0.1 nm ⁇ 5 nm , such as 0.5nm, 2nm or 4nm. Controlling the thicknesses of the second dielectric layer and the second current blocking layer within the above-mentioned ranges is beneficial to ensure that the size of the capacitor is small while improving the electrical performance of the semiconductor structure.
  • the crystal structure of the first dielectric layer is tetragonal, which is beneficial to improve the dielectric constant of the first dielectric layer;
  • the dielectric layer used to form the capacitor at least includes a first dielectric whose crystal structure is tetragonal layer, which is beneficial to improve the capacitance of the capacitor.
  • the crystal structure of the lower electrode layer is tetragonal, and the lower electrode layer is used as a seed layer to form the first dielectric layer, so that the crystal structure of the first dielectric layer is also tetragonal.
  • the crystal structure of the first dielectric layer is a tetragonal crystal system, and compared with other crystal structures, the tetragonal crystal system has a relatively high dielectric constant, so it is beneficial to the situation without changing the forming material of the first dielectric layer Next, the dielectric constant of the first dielectric layer is improved; further, the dielectric layer of the capacitor formed subsequently includes the first dielectric layer, which is beneficial to improve the capacitance of the capacitor, thereby improving the electrical performance of the semiconductor structure.
  • a second dielectric layer is formed on the first dielectric layer, and the dielectric constant of the material of the second dielectric layer is greater than the dielectric constant of the material of the first dielectric layer.
  • the dielectric layer of the capacitor formed subsequently is a laminated structure including a first dielectric layer and a second dielectric layer, which is beneficial to improve the structural stability of the capacitor, and because the dielectric constant of the material of the second dielectric layer is greater than The dielectric constant of the material of the first dielectric layer is beneficial to further improve the capacitance of the capacitor.
  • a second dielectric layer is formed on the first dielectric layer; a second current blocking layer is deposited on the surface of the second dielectric layer, and the deposition temperature is greater than or equal to that of the crystal structure in the second dielectric layer converted into a tetragonal system
  • the required crystallization temperature so when the second current blocking layer is formed, the crystal structure of the second dielectric layer can be converted into a tetragonal system without an additional annealing process for the second dielectric layer, which is beneficial to simplify the preparation. Process steps of the second dielectric layer.
  • the crystal structure of the second dielectric layer is a tetragonal crystal system. Compared with other crystal structures, the tetragonal crystal system has a relatively high dielectric constant.
  • the dielectric constant of the second dielectric layer is increased; further, the dielectric layer of the capacitor formed subsequently includes a first dielectric layer, a second dielectric layer and a second current blocking layer, which is beneficial to improve the capacitance of the capacitor , and the second current blocking layer is beneficial to reduce the leakage current in the capacitor, so as to further improve the electrical performance of the semiconductor structure.
  • the semiconductor structure and the manufacturing method thereof provided by the embodiments of the present disclosure are beneficial to increase the dielectric constant of the first dielectric layer, and reduce the leakage current of the first dielectric layer by using the first current blocking layer, so as to improve the subsequent formation of the capacitor
  • the electrical capacity of the semiconductor structure is thus beneficial to improve the electrical properties of the semiconductor structure.

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Abstract

本申请实施例提供一种半导体结构及其制作方法，半导体结构的制作方法包括：提供基底；在所述基底上形成下电极层，所述下电极层的晶体结构包括四方晶系；以所述下电极层为晶种层，在所述下电极层表面形成第一介电层，所述第一介电层的晶体结构包括四方晶系；在所述第一介电层表面形成第一电流阻挡层。

Description

半导体结构及其制作方法
本公开要求在2021年03月09日提交中国专利局、申请号为202110258253.9、发明名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种半导体结构及其制作方法。
背景技术
随着半导体结构中的电容器向小型化和高性能化的方向发展，电容器需要在较小尺寸的情况下具有较高的电容量。目前为提升电容器的电容量，通常通过提升电容器中介电层的材料的介电常数来实现。
然而，介电层的材料的介电常数与该材料自身的晶体结构相关，如何在不改变介电层的材料的情况下，提高介电层的材料的介电常数成为急需解决的问题。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请实施例提供的一种半导体结构及其制作方法。
本申请实施例提供一种半导体结构的制作方法，包括：提供基底；在所述基底上形成下电极层，所述下电极层的晶体结构包括四方晶系；以所述下电极层为晶种层，在所述下电极层表面形成第一介电层，所述第一介电层的晶体结构包括四方晶系；在所述第一介电层表面形成第一电流阻挡层。
本申请实施例还提供一种半导体结构，包括：基底；下电极层，所述下电极层位于所述基底上，且所述下电极层的晶体结构包括四方晶系；第一介电层，所述第一介电层位于所述下电极层表面，且所述第一介电层的晶体结构包括四方晶系；第一电流阻挡层，所述第一电流阻挡层位于所述第一介电 层表面。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本申请的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请一实施例的在基底上形成下电极层的步骤对应的局部剖面结构示意图；
图2为本申请一实施例的在下电极层表面形成第一介电层的步骤对应的局部剖面结构示意图；
图3为本申请一实施例的在第一介电层表面形成第一电流阻挡层的步骤对应的局部剖面结构示意图；
图4为本申请一实施例的在衬底上依次堆叠形成第一牺牲层、中间支撑层、第二牺牲层和顶部支撑层的步骤对应的局部剖面结构示意图；
图5为本申请一实施例的在电容孔的底部和侧壁形成基础下电极层的步骤对应的局部剖面结构示意图；
图6为本申请一实施例的形成基底、在基底上形成下电极层的步骤对应的局部剖面结构示意图；
图7为本申请一实施例的在下电极层表面形成介质层的步骤对应的局部剖面结构示意图；
图8为本申请另一实施例的在第一电流阻挡层表面形成第二介电层的步骤对应的局部剖面结构示意图；
图9为本申请另一实施例的在第二介电层表面沉积第二电流阻挡层的步骤对应的局部剖面结构示意图；
图10为本申请再一实施例的在第一电流阻挡层上形成第二介电层的步骤对应的局部剖面结构示意图；
图11为本申请再一实施例的在第二介电层表面沉积第二电流阻挡层的步骤对应的局部剖面结构示意图。
具体实施方式
由背景技术可知，半导体结构中的电容器的电容量有待提高，电容器中的介电层的介电常数有待提高。
经分析发现，为提高半导体结构中电容器的电容量，通常采用介电常数较高的材料来制作介电层。对于大部分用于形成介电层的材料而言，该材料晶体结构为四方晶系时，相较于其他低级晶族，四方晶系具有相对较高的介电常数。然而，大部分用于形成介电层的材料需要通过退火工艺才能将介电层的晶体结构转化为四方晶系，不利于简化制备电容器的工艺步骤。
在介电层中形成晶种层，促使介电层的晶体结构转化为四方晶系时，由于介电层中存在晶种层，增加了介电层的整体厚度，从而会降低形成的电容器的电容量，也不利于形成尺寸较小的电容器。
本申请实施提供一种半导体结构及其制作方法。其中，下电极层的晶体结构为四方晶系，以下电极层作为晶种层来形成第一介电层，使得第一介电层的晶体结构也为四方晶系，有利于在不改变第一介电层的形成材料的情况下，形成具有更高介电常数的第一介电层，有利于提高半导体结构中电容器的电容量，从而提高半导体结构的电学性能，且无需采用退火工艺形成晶体结构为四方晶系的第一介电层，有利于简化制备第一介电层的工艺步骤。此外，相较于将晶种层设置在介电层中以改变介电层的晶体结构，本技术方案有利于降低介电层的厚度，因而有利于进一步提高后续形成的电容器的电容量。
下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1至图7为本申请一实施例提供的半导体结构的制作方法各步骤对应 的局部剖面结构示意图。其中，图3为图7中区域I的一种剖面结构示意图。
参考图1，提供基底100；在基底100上形成下电极层101。
本实施例中，下电极层101的晶体结构为四方晶系，有利于后续作为形成第一介电层的晶种层，无需额外在第一介电层中形成晶种层，有利于降低第一介电层的厚度，从而有利于提高后续形成的电容器的电容量和实现电容器尺寸小型化。
下电极层101的材料包括氧化钌或者氧化铱中的至少一种。采用氧化钌和氧化铱形成下电极层101，无需通过退火工艺即可形成晶体结构为四方晶系的下电极层101，有利于简化制备下电极层101的工艺步骤。
形成下电极层101的方法包括原子层沉积工艺、化学气相沉积工艺或者物理气相沉积工艺。在一个例子中，采用原子层沉积工艺形成下电极层101，由于原子层沉积工艺是一种可以将物质以单原子膜形式一层一层的镀在基底100表面的方法，则采用原子层沉积工艺形成下电极层101可以保证下电极层101中的原子呈重复且有规律的排列，保证下电极层101的晶体结构为四方晶系。原子层沉积工艺的温度参数为280℃～400℃，有利于形成致密性较高，强度较高的下电极层101。此外，在垂直于基底100表面的方向上，下电极层101的厚度为1nm～30nm，例如5nm、15nm或者25nm。
参考图2，以下电极层101为晶种层，在下电极层101表面形成第一介电层102。
本实施例中，采用外延工艺形成第一介电层102。由于外延工艺有利于形成与下电极层101晶体结构相同的第一介电层102，则无需采用退火工艺，即可形成晶体结构为四方晶系的第一介电层102，有利于简化制备第一介电层102的工艺步骤。在垂直于基底100表面的方向上，第一介电层102的厚度为0.1nm～10nm，例如0.5nm、4nm或者8nm。
在一个例子中，第一介电层102的材料为氧化铪；外延工艺的工艺温度为250℃～600℃。
由于晶体结构为单斜晶系的氧化铪的介电常数为20～25，晶体结构为四方晶系的氧化铪的介电常数为40～60。可见，将晶体结构为四方晶系的下电极层101作为晶种层，通过外延工艺在在下电极层101表面形成晶体结构为四方晶系的第一介电层102，有利于在不改变第一介电层102的形成材料的 情况下，提高第一介电层102本身的介电常数；后续形成的电容器的介质层包括第一介电层102，有利于提高电容器的电容量。
在其他实施例中，第一介电层102的材料包括氧化钽、氧化铪、氧化锆、氧化铌、氧化钛、氧化钡、氧化锶、氧化钇、氧化镧、氧化镨或者钛酸锶钡等电介质材料中的至少一种。
参考图3，在形成第一介电层102之后，还包括：在第一介电层102表面形成第一电流阻挡层103。在垂直于基底100表面的方向上，第一电流阻挡层103的厚度为0.1nm～5nm，例如0.5nm、2nm或者4nm。
第一电流阻挡层103的材料包括氧化铝、氧化硅或者氮化硅中的至少一种。由于氧化铝、氧化硅和氮化硅均为高带隙材料，即第一电流阻挡层103中导带的最低点和价带的最高点的能量之差较大，电子由价带被激发到导带越困难，因此，第一电流阻挡层103的电导率较低，后续形成的电容器的介质层包括第一电流阻挡层103，有利于在提高电容器的介电常数的同时，降低电容器中的泄露电流，以提高电容器的电容量，从而提高半导体结构的电学性能。
形成第一电流阻挡层103的方法包括原子层沉积工艺、化学气相沉积工艺或者物理气相沉积工艺，形成第一电流阻挡层103的工艺温度为200℃～700℃。一个例子中，第一电流阻挡层103的材料为氧化铝，采用原子层沉积工艺形成第一电流阻挡层103，且原子层沉积工艺的工艺温度为200℃～700℃，有利于保证第一电流阻挡层103对第一介电层102中泄漏电流的良好抑制效果，从而有利于提高后续形成的电容器的电学性能。
本实施例中，在形成第一电流阻挡层之后，可以在第一电流阻挡层上直接形成上电极层，以形成电容器。在其他实施例中，在形成第一电流阻挡层之后，还可以在第一电流阻挡层上形成一层介电层，然后在该介电层上直接形成上电极层，以形成电容器。
本实施例中，参考图4至图7，提供基底100和在基底100上形成下电极层的101步骤包括：
参考图4，提供衬底11，在衬底11上依次堆叠形成第一牺牲层12、中间支撑层13、第二牺牲层14和顶部支撑层15。
参考图5，图形化顶部支撑层15、第二牺牲层14、中间支撑层13、第一 牺牲层12和衬底11，以形成贯穿顶部支撑层15、第二牺牲层14、中间支撑层13、第一牺牲层12和部分衬底11的电容孔，电容孔露出衬底11。
在电容孔的底部和侧壁形成基础下电极层111。
结合参考图5和图6，去除部分顶部支撑层15、部分中间支撑层13、部分基础下电极层111、第一牺牲层12和第二牺牲层14，以形成基底100和在基底100上形成下电极层101。
其中，第一牺牲层12和第二牺牲层14被完全去除，以露出下电极层101的外表面，便于后续在下电极层101表面形成第一介电层。
图6为半导体结构的局部剖面结构示意图，图6中未示出去除的部分顶部支撑层15和部分中间支撑层13。图6仅实际示例出了一种类型的基底100，实际上还可以有更多类型的基底，用于在该基底上形成下电极层，以便于后续在该基底上形成电容器。
参考图7，在下电极层101表面形成介质层16。本实施例中，介质层16包括上述形成的第一介电层102(参考图3)和第一电流阻挡层103(参考图3)。在下电极层101表面形成第一介电层102的工艺步骤包括：在下电极层101、中间支撑层13和顶部支撑层15共同构成的结构的表面共形地覆盖第一介电层102；在第一介电层102表面共形地覆盖第一电流阻挡层103。
本实施例中，以下电极层101作为晶种层来形成第一介电层102，使得第一介电层102的晶体结构也为四方晶系，有利于形成具有更高介电常数的第一介电层102；后续形成的电容器的介质层至少包括第一介电层102，有利于提高电容器的电容量，从而有利于提高半导体结构的电学性能。此外，在第一介电层102上表面还可以形成第一电流阻挡层103，以降低第一介电层102中的泄露电流，以进一步地提高半导体结构的电学性能。
本申请又一实施例还提供一种半导体结构的制作方法。以下将结合附图对本申请第二实施例提供的半导体结构的制作方法进行详细说明，与前述实施例相同或者相应的部分，可参考前述实施例的详细描述，在此不再赘述。
图8至图9为本申请又一实施例提供的半导体结构的制作方法各步骤对应的局部剖面结构示意图。需要说明的是，图9为图7中区域I的一种剖面结构示意图。
参考图8，在基底200上依次形成下电极层201、第一介电层202和第一 电流阻挡层203之后，在第一电流阻挡层203表面形成第二介电层204。其中，第一电流阻挡层203有利于降低第一介电层202中的泄露电流，后续形成的电容器的介质层包括第一电流阻挡层203，如此，有利于提高电容器的电学性能。
本实施例中，采用原子层沉积工艺形成第一电流阻挡层203和第二介电层204，且在垂直于基底200表面的方向上，第一电流阻挡层203的厚度为0.1nm～5nm，例如0.5nm、2nm或者4nm，第二介电层204的厚度为0.1nm～10nm，例如0.5nm、4nm或者8nm。
参考图9，在第二介电层204表面沉积第二电流阻挡层205，且沉积采用的工艺温度大于或等于第二介电层204中晶体结构转化为四方晶系所需的结晶温度。
由于沉积第二电流阻挡层205采用的工艺温度大于或等于第二介电层204中晶体结构转化为四方晶系所需的结晶温度，因而在形成第二电流阻挡层205之后，第二介电层204的晶体结构会转化为四方晶系，无需额外通过退火工艺形成晶体结构为四方晶系的第二介电层204，有利于简化制备第二介电层204的工艺步骤。同时，第二介电层204的晶体结构为四方晶系，相对于其他低级晶族，四方晶系具有相对较高的介电常数，如此，有利于在不改变第二介电层204的形成材料的情况下，提高第二介电层204的介电常数；后续形成的电容器的介质层至少包括第一介电层202和第二介电层204，有利于提高电容器的电容量。
此外，在第二电流阻挡层205的材料包括氧化铝、氧化硅或者氮化硅中的至少一种，有利于降低第一介电层202和第二介电层204中的泄露电流，以进一步地提高电容器的电容量，从而提高半导体结构的电学性能。
沉积第二电流阻挡层205的方法包括原子层沉积工艺、化学气相沉积工艺或者物理气相沉积工艺，沉积第二电流阻挡层205的工艺温度为200℃～700℃。
在一个例子中，第二介电层204的材料为氧化锆，在垂直于基底200表面的方向上第二介电层204的厚度为0.1nm～10nm，例如2nm或5nm，采用原子层沉积工艺形成第二电流阻挡层205，第二电流阻挡层205的材料为氧化铝，原子层沉积工艺的工艺温度为200℃～700℃，例如330℃。在形成第 二电流阻挡层205的过程中，第二介电层204的晶体结构会转变为四方晶系，则在形成第二电流阻挡层205之后，第二介电层204的材料为四方晶系的氧化锆。
本实施例中，在形成第二电流阻挡层之后，可以在第二电流阻挡层上直接形成上电极层，以形成电容器。在其他实施例中，在形成第二电流阻挡层之后，还可以在第二电流阻挡层上形成一层介电层，然后在该介电层上直接形成上电极层，以形成电容器。
本实施例中，在形成第二电流阻挡层205时，无需额外的对第二介电层204进行退火工艺，即可使得第二介电层204的晶体结构转化为四方晶系，有利于在提高第二介电层204的介电常数，以提高电容器的电容量的同时，简化制备第二介电层204的工艺步骤。此外，第二电流阻挡层205有利于降低第一介电层202和第二介电层204中的泄露电流，以进一步地提高半导体结构的电学性能。进一步地，通过将电容器中的介质层16做成叠层结构，即介质层16至少包括第一介电层202和第二介电层204，有利于提高电容器的结构稳定性。
本申请另一实施例还提供一种半导体结构的制作方法。以下将结合附图对本申请第三实施例提供的半导体结构的制作方法进行详细说明，需要说明的是，与前述实施例相同或者相应的部分，可参考前述实施例的详细描述，在此不再赘述。
图10至图11为本申请另一实施例提供的半导体结构各步骤对应的局部剖面结构示意图。其中，图10至图11为图7中区域I的两种剖面结构示意图。
参考图10，在基底300上依次形成下电极层301、第一介电层302和第一电流阻挡层303之后，在第一电流阻挡层303上形成第二介电层304，且第二介电层304的材料的介电常数大于第一介电层302的材料的介电常数。在垂直于基底300表面的方向上，第二介电层304的厚度为0.1nm～10nm，例如0.5nm、4nm或者8nm。
在一个例子中，参考图10，介质层16(参考图7)包括依次堆叠形成的第一介电层302、第一电流阻挡层303和第二介电层304。其中，第一电流阻挡层303，有利于降低第一介电层302中的泄露电流；后续形成的电容器包 括第一电流阻挡层303，如此，有利于提高电容器的电学性能。
本实施例中，第二介电层304的材料的介电常数大于第一介电层302的材料的介电常数，后续形成的电容器的介质层16(参考图15)包括第一介电层302和第二介电层304，如此，有利于进一步地提高电容器的电容量。
本实施例中，第二介电层304的材料为氧化钛。氧化钛的介电常数为75～85，由上述第一实施例的描述可知，第一介电层302的介电常数为40～60，则第二介电层304为氧化钛时，第二介电层304的介电常数远大于第一介电层302的介电常数，有利于提高第二介电层304对介质层16(参考图7)整体的介电常数的提升效果。
本实施例中，形成第二介电层304的方法包括原子层沉积工艺、化学气相沉积工艺或者物理气相沉积工艺。在一个例子中，采用原子层沉积工艺形成第二介电层304，且原子层沉积工艺的温度参数为200℃～700℃。
在其他实施例中，第二介电层的材料可以为氧化钛、氧化钡或者氧化镥镧中的至少一种。
在又一个例子中，参考图11，在第一介电层302上依次形成第一电流阻挡层303和第二介电层304之后，还包括：在第二介电层304表面沉积第二电流阻挡层305。由于第二电流阻挡层305的电导率较低，有利于降低第二介电层304和第一介电层302中的泄露电流；后续形成的电容器的介质层16还包括第二电流阻挡层305，以进一步地提高电容器的电容量，从而提高半导体结构的电学性能。
本实施例中，在形成第二电流阻挡层之后，可以在第二电流阻挡层上直接形成上电极层，以形成电容器。在其他实施例中，在形成第二电流阻挡层之后，还可以在第二电流阻挡层上形成一层介电层，然后在该介电层上直接形成上电极层，以形成电容器。
本实施例中，在第一介电层302上还形成第二介电层304，且第二介电层304的材料的介电常数大于第一介电层302的材料的介电常数，则后续形成的电容器的介质层16为包括第一介电层302和第二介电层304的叠层结构，有利于在提高电容器的结构稳定性的同时，进一步地提高电容器的电容量。
相应地，本申请再一实施例还提供一种半导体结构，该半导体结构由上 述任一实施例提供的半导体结构的制作方法制成。
参考图3，半导体结构包括：基底100；下电极层101，下电极层101位于基底100上，且下电极层101的晶体结构包括四方晶系；第一介电层102，第一介电层102位于下电极层101表面，且第一介电层102的晶体结构包括四方晶系，有利于提高第一介电层102的介电常数；第一电流阻挡层103，第一电流阻挡层103位于第一介电层102表面，有利于降低第一介电层102中的泄露电流；进一步地，介质层16用于形成半导体结构中电容器，且介质层16包括第一介电层102和第一电流阻挡层103，如此，有利于提高电容器的电容量，从而有利于提高半导体结构的电学性能。
在垂直于基底100表面的方向上，第一介电层的厚度为0.1～10nm，例如0.5nm、4nm或者8nm。第一介电层102的材料包括氧化钽、氧化铪、氧化锆、氧化铌、氧化钛、氧化钡、氧化锶、氧化钇、氧化镧、氧化镨或者钛酸锶钡等电介质材料中的至少一种。
本实施例中，参考图6，基底100包括：衬底11；中间支撑层13，中间支撑层13位于衬底11的上方，且与衬底11具有间距；顶部支撑层15，顶部支撑层15位于中间支撑层13的上方，且与中间支撑层13具有间距。在垂直于衬底11的方向上，中间支撑层13的厚度为10nm～50nm，顶部支撑层15的厚度为10nm～100nm。
中间支撑层13的材料包括氮化硅或者碳氮化硅中的至少一种，顶部支撑层15的材料与中间支撑层13的材料相同。在其他实施例中，顶部支撑层15的材料与中间支撑层13的材料相也可以不同。
继续参考图6，下电极层101的底部与侧壁围成通孔，且通孔的底部与衬底11相抵接；中间支撑层13与顶部支撑层15均与下电极层101远离通孔的部分侧壁相抵接。
参考图7，介质层16共形地覆盖下电极层101、中间支撑层13和顶部支撑层15共同构成的结构的表面。介质层16至少包括上述的第一介电层102。图6仅实际示例出了一种类型的基底100，实际上还可以有更多类型的基底，用于在该基底上形成下电极层，以便于后续在该基底上形成具有介质层16的电容器。
有关半导体结构中介质层16(参考图7)的具体组成结构，以下将结合 图3、图9、和图11进行说明。
示例一：继续参考图3，介质层16还包括：第一电流阻挡层103，第一电流阻挡层103位于第一介电层102表面，有利于在提高半导体结构中的电容器的介电常数的同时，降低电容器中的泄露电流，以进一步提高电容器的电容量，从而提高半导体结构的电学性能。其中，介质层16由第一介电层102和第一电流阻挡层103依次堆叠构成。
示例二：参考图9，介质层16还包括：第一电流阻挡层203，第一电流阻挡层203位于第一介电层202表面；第二介电层204，第二介电层204位于第一电流阻挡层203表面，第二介电层204的晶体结构包括四方晶系；第二电流阻挡层205，第二电流阻挡层205位于第二介电层204第二介电层表面。进一步地，第二介电层204的材料包括氧化锆。
本实施例中，第二介电层204的晶体结构为四方晶系，有利于在提高半导体结构中电容器的介电常数的同时，通过第一电流阻挡层203降低第一介电层202和通过第二电流阻挡层205降低第二介电层204中的泄露电流，以提高半导体结构的电学性能。其中，介质层16由第一介电层202、第一电流阻挡层203、第二介电层204和第二电流阻挡层205依次堆叠构成。
示例三：参考图11，介质层16还包括：第一电流阻挡层303，第一电流阻挡层303位于第一介电层302表面；第二介电层304，第二介电层304位于第一电流阻挡层303表面，第二介电层304的材料的介电常数大于第一介电层302的材料的介电常数；第二电流阻挡层305，第二电流阻挡层305位于第二介电层304表面。其中，介质层16由第一介电层302、第一电流阻挡层303、第二介电层304和第二电流阻挡层305依次堆叠构成。
第二介电层304的材料包括氧化钛、氧化钡或者氧化镥镧中的至少一种。而且，第二介电层304的材料的介电常数大于第一介电层302的材料的介电常数，有利于进一步地提高电容器的介电常数，以提高半导体结构的电学性能。
在示例一至示例三中，第一电流阻挡层的材料包括氧化铝、氧化硅或者氮化硅中的至少一种，在垂直于基底表面的方向上，第一电流阻挡层的厚度均为0.1nm～5nm，例如0.5nm、2nm或者4nm。
在示例二和示例三中，在垂直于基底表面的方向上，第二介电层的厚度 为0.1nm～10nm，例如0.5nm、4nm或者8nm，第二电流阻挡层的厚度为0.1nm～5nm，例如0.5nm、2nm或者4nm。将第二介电层和第二电流阻挡层的厚度控制在上述范围内，在提高半导体结构的电学性能的同时，有利于保证电容器的尺寸较小。
本实施例中，第一介电层晶体结构为四方晶系，有利于提高第一介电层的介电常数；用于形成电容器的介质层至少包括晶体结构为四方晶系的第一介电层，有利于提高电容器的电容量。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
下电极层的晶体结构为四方晶系，以下电极层作为晶种层来形成第一介电层，使得第一介电层的晶体结构也为四方晶系。其中，第一介电层的晶体结构为四方晶系，相对于其他晶体结构，四方晶系具有相对较高的介电常数，如此，有利于在不改变第一介电层的形成材料的情况下，提高第一介电层的介电常数；进一步地，后续形成的电容器的介质层包括第一介电层，如此，有利于提高电容器的电容量，从而有利于提高半导体结构的电学性能。
在第一介电层上形成第二介电层，且第二介电层的材料的介电常数大于第一介电层的材料的介电常数。其中，后续形成的电容器的介质层为包括第一介电层和第二介电层的叠层结构，有利于提高电容器的结构稳定性，且由于第二介电层的材料的介电常数大于第一介电层的材料的介电常数，有利于进一步地提高电容器的电容量。
在第一介电层上形成第二介电层；在第二介电层表面沉积第二电流阻挡层，且沉积采用的工艺温度大于或等于第二介电层中晶体结构转化为四方晶系所需的结晶温度，因而在形成第二电流阻挡层时，无需额外的对第二介电层进行退火工艺，即可使得第二介电层的晶体结构转化为四方晶系，有利于简化制备第二介电层的工艺步骤。同时，第二介电层的晶体结构为四方晶系，相对于其他晶体结构，四方晶系具有相对较高的介电常数，如此，有利于在不改变第二介电层的形成材料的情况下，提高第二介电层介电常数；进一步地，后续形成的电容器的介质层包括第一介电层、第二介电层和第二电流阻挡层，如此，有利于提高电容器的电容量，且第二电流阻挡层有利于降低电容器中的泄露电流，以进一步地提高半导体结构的电学性能。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、 “一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及其制作方法，有利于提高第一介电层的介电常数，和利用第一电流阻挡层降低第一介电层的泄露电流，以提高后续形成的电容器的电容量，从而有利于提高半导体结构的电学性能。

Claims (14)

  1. 一种半导体结构的制作方法，所述制作方法包括：
    提供基底；
    在所述基底上形成下电极层，所述下电极层的晶体结构包括四方晶系；
    以所述下电极层为晶种层，在所述下电极层表面形成第一介电层，所述第一介电层的晶体结构包括四方晶系；
    在所述第一介电层表面形成第一电流阻挡层。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，采用原子层沉积工艺形成所述下电极层，且所述原子层沉积工艺的温度参数为280℃～400℃。
  3. 根据权利要求1所述的半导体结构的制作方法，其中，采用外延工艺形成所述第一介电层。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，所述第一介电层的材料为氧化铪；所述外延工艺的工艺温度为250℃～600℃。
  5. 根据权利要求1所述的半导体结构的制作方法，所述制作方法还包括：
    在所述第一电流阻挡层上形成第二介电层，且所述第二介电层的材料的介电常数大于所述第一介电层的材料的介电常数。
  6. 根据权利要求5所述的半导体结构的制作方法，其中，所述第二介电层的材料包括氧化钛。
  7. 根据权利要求1所述的半导体结构的制作方法，所述制作方法还包括：在所述第一电流阻挡层上形成第二介电层；在所述第二介电层表面沉积第二电流阻挡层，且所述沉积采用的工艺温度大于或等于所述第二介电层中晶体结构转化为四方晶系所需的结晶温度。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，在形成所述第二电流阻挡层之后，所述第二介电层的材料包括四方晶系的氧化锆；所述第二电流阻挡层的材料包括氧化铝。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，所述沉积采用的工艺温度为200℃～700℃。
  10. 根据权利要求1所述的半导体结构的制作方法，其中，所述第一介 电层的材料包括氧化钽、氧化铪、氧化锆、氧化铌、氧化钛、氧化钡、氧化锶、氧化钇、氧化镧、氧化镨或者钛酸锶钡等电介质材料中的至少一种。
  11. 根据权利要求1所述的半导体结构的制作方法，其中，提供所述基底和在所述基底上形成下电极层的步骤包括：
    提供衬底，在所述衬底上依次堆叠形成第一牺牲层、中间支撑层、第二牺牲层和顶部支撑层；
    图形化所述顶部支撑层、所述第二牺牲层、所述中间支撑层、所述第一牺牲层和所述衬底，以形成贯穿所述顶部支撑层、所述第二牺牲层、所述中间支撑层、所述第一牺牲层和部分所述衬底的电容孔，所述电容孔露出所述衬底；
    在所述电容孔的底部和侧壁形成基础下电极层；
    去除部分所述顶部支撑层、部分所述中间支撑层、部分所述基础下电极层、所述第一牺牲层和所述第二牺牲层，以形成所述基底和在所述基底上形成下电极层。
  12. 一种半导体结构，所述半导体结构包括：
    基底；
    下电极层，所述下电极层位于所述基底上，且所述下电极层的晶体结构包括四方晶系；
    第一介电层，所述第一介电层位于所述下电极层表面，且所述第一介电层的晶体结构包括四方晶系；
    第一电流阻挡层，所述第一电流阻挡层位于所述第一介电层表面。
  13. 根据权利要求12所述的半导体结构，所述半导体结构还包括：第二介电层，所述第二介电层位于所述第一电流阻挡层上，所述第二介电层的晶体结构包括四方晶系，或者所述第二介电层的材料的介电常数大于所述第一介电层的材料的介电常数。
  14. 根据权利要求13所述的半导体结构，所述半导体结构还包括：第二电流阻挡层，所述第二电流阻挡层位于所述第二介电层表面。
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