WO2022188149A1 - 微流控基板、微流控芯片及其制作方法 - Google Patents

微流控基板、微流控芯片及其制作方法 Download PDF

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Publication number
WO2022188149A1
WO2022188149A1 PCT/CN2021/080452 CN2021080452W WO2022188149A1 WO 2022188149 A1 WO2022188149 A1 WO 2022188149A1 CN 2021080452 W CN2021080452 W CN 2021080452W WO 2022188149 A1 WO2022188149 A1 WO 2022188149A1
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Prior art keywords
substrate
conductive
conductive pattern
layer
microfluidic
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PCT/CN2021/080452
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English (en)
French (fr)
Inventor
邓睿君
刘祝凯
丁丁
刘浩男
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京东方科技集团股份有限公司
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Priority to US17/753,101 priority Critical patent/US20230158508A1/en
Priority to PCT/CN2021/080452 priority patent/WO2022188149A1/zh
Priority to EP21929624.1A priority patent/EP4140589A4/en
Priority to CN202180000463.6A priority patent/CN115427150B/zh
Publication of WO2022188149A1 publication Critical patent/WO2022188149A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L7/00—Heating or cooling apparatus; Heat insulating devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L7/00—Heating or cooling apparatus; Heat insulating devices
    • B01L7/52—Heating or cooling apparatus; Heat insulating devices with provision for submitting samples to a predetermined sequence of different temperatures, e.g. for treating nucleic acid samples
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
    • B01L3/50—Containers for the purpose of retaining a material to be analysed, e.g. test tubes
    • B01L3/502—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures
    • B01L3/5027—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip
    • B01L3/502707—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip characterised by the manufacture of the container or its components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
    • B01L3/50—Containers for the purpose of retaining a material to be analysed, e.g. test tubes
    • B01L3/502—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures
    • B01L3/5027—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip
    • B01L3/502761—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip specially adapted for handling suspended solids or molecules independently from the bulk fluid flow, e.g. for trapping or sorting beads, for physically stretching molecules
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N19/00—Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2200/00—Solutions for specific problems relating to chemical or physical laboratory apparatus
    • B01L2200/12—Specific details about manufacturing devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2300/00—Additional constructional details
    • B01L2300/06—Auxiliary integrated devices, integrated components
    • B01L2300/0627—Sensor or part of a sensor is integrated
    • B01L2300/0645—Electrodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2300/00—Additional constructional details
    • B01L2300/08—Geometry, shape and general structure
    • B01L2300/0809—Geometry, shape and general structure rectangular shaped
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2300/00—Additional constructional details
    • B01L2300/08—Geometry, shape and general structure
    • B01L2300/0887—Laminated structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2300/00—Additional constructional details
    • B01L2300/12—Specific details about materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2300/00—Additional constructional details
    • B01L2300/16—Surface properties and coatings
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2300/00—Additional constructional details
    • B01L2300/16—Surface properties and coatings
    • B01L2300/161—Control and use of surface tension forces, e.g. hydrophobic, hydrophilic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2300/00—Additional constructional details
    • B01L2300/16—Surface properties and coatings
    • B01L2300/161—Control and use of surface tension forces, e.g. hydrophobic, hydrophilic
    • B01L2300/165—Specific details about hydrophobic, oleophobic surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2300/00—Additional constructional details
    • B01L2300/18—Means for temperature control
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L2300/00—Additional constructional details
    • B01L2300/18—Means for temperature control
    • B01L2300/1805—Conductive heating, heat from thermostatted solids is conducted to receptacles, e.g. heating plates, blocks
    • B01L2300/1827—Conductive heating, heat from thermostatted solids is conducted to receptacles, e.g. heating plates, blocks using resistive heater
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
    • B01L3/50—Containers for the purpose of retaining a material to be analysed, e.g. test tubes
    • B01L3/508—Containers for the purpose of retaining a material to be analysed, e.g. test tubes rigid containers not provided for above
    • B01L3/5085—Containers for the purpose of retaining a material to be analysed, e.g. test tubes rigid containers not provided for above for multiple samples, e.g. microtitration plates
    • B01L3/50851—Containers for the purpose of retaining a material to be analysed, e.g. test tubes rigid containers not provided for above for multiple samples, e.g. microtitration plates specially adapted for heating or cooling samples

Definitions

  • the present disclosure relates to the field of biological detection, and in particular, to a microfluidic substrate, a microfluidic chip and a manufacturing method thereof.
  • Digital polymerase chain reaction chip technology (dPCR, digital Polymerase Chain Reaction) is a quantitative analysis method that provides digital DNA quantitative information, and has shown significant advantages in many fields since it was proposed.
  • dPCR digital Polymerase chain reaction chip technology
  • the development of the initial dPCR technology was very slow, because if the traditional 96-well plate or 384-well plate was used for PCR amplification.
  • Several multi-well plates are required for simultaneous amplification, which is not only complicated to operate, but also consumes a lot of experimental samples and reagents.
  • microfluidic technology With the emergence and rapid development of microfluidic technology in recent years, the combination of microfluidic technology and dPCR technology has greatly improved the sensitivity and accuracy. So far, a number of companies have successively launched dPCR products. These products have shown great technical advantages and commercial prospects in research fields such as single-cell analysis, early cancer diagnosis and prenatal diagnosis.
  • the present disclosure provides a microfluidic substrate, a microfluidic chip and a manufacturing method thereof.
  • the patterned design of the conductive layer improves the uniformity of heating and reduces the low temperature edge area of the conductive layer.
  • the actual size of the microfluidic chip can be effectively reduced, and the number of reaction chambers per unit area can be increased.
  • a microfluidic substrate includes: a first substrate; a conductive layer on the first substrate; and a confinement layer on a side of the conductive layer away from the first substrate, the confinement layer defining a recess wherein the conductive layer includes a plurality of conductive patterns corresponding to the recessed portion, the plurality of conductive patterns are arranged along a first direction, each conductive pattern extends along a second direction and includes a first end and a second Two ends, the first direction is perpendicular to the second direction; each conductive pattern has a maximum local resistance value at the first end and the second end of the conductive pattern.
  • the conductive layer has a uniform thickness
  • each conductive pattern has a midpoint in the second direction
  • each conductive pattern has a direction along the midpoint at the midpoint. The maximum width in the first direction.
  • each conductive pattern has a minimum width along the first direction at the first and second ends of the conductive pattern.
  • each conductive pattern has a width that varies continuously along the second direction.
  • each conductive pattern has rectilinear sides.
  • each conductive pattern has curvilinear sides.
  • each conductive pattern has a width that varies discontinuously along the second direction.
  • each conductive pattern has an axisymmetric shape with an axis of symmetry parallel to the second direction.
  • each conductive pattern has a minimum thickness at the first and second ends of the conductive pattern.
  • the overall resistance value between the first end and the second end of each conductive pattern decreases as the distance between the conductive pattern and the center of the recess increases.
  • the conductive layer has a uniform thickness, and the width of each conductive pattern in the first direction increases with the distance between the conductive pattern and the center of the recessed portion and increase.
  • the lengths of the plurality of conductive patterns in the second direction are the same.
  • the plurality of conductive patterns form a parallel circuit, and the current path of each conductive pattern is along the second direction.
  • the first substrate is a glass substrate.
  • the material of the conductive layer includes at least one of indium tin oxide and indium zinc oxide.
  • the surface of the recess is hydrophilic.
  • the microfluidic substrate further comprises: a trace located between the conductive layer and the first substrate, and a trace located between the trace and the conductive layer
  • the passivation layer includes a through hole; the conductive layer is electrically connected to the wiring through the through hole.
  • the traces include a Mo-AlNd-Mo alloy layer.
  • a microfluidic chip includes: the microfluidic substrate according to any one of the above embodiments; an opposite substrate located on the side of the confinement layer away from the first substrate; and a substrate located around the recessed portion A frame sealant that defines a chamber.
  • the chamber is a reaction chamber
  • the opposing substrate includes a sample inlet and a sample outlet.
  • a method for fabricating a microfluidic chip includes: providing a first substrate; forming a conductive layer on the first substrate and patterning the conductive layer; forming a confinement layer on a side of the conductive layer facing away from the first substrate, the A defining layer defines a recessed portion, the conductive layer includes a plurality of conductive patterns corresponding to the recessed portion, the plurality of conductive patterns are arranged in a first direction, each conductive pattern extends along a second direction and includes a first end and a second end, the first direction is perpendicular to the second direction; each conductive pattern has a maximum local resistance value at the first end and the second end of the conductive pattern; seals are arranged around the recessed portion a sealant, the sealant defining a cavity; and an opposite substrate is arranged on a side of the defining layer away from the first substrate.
  • FIG. 1 shows a top view of a microfluidic substrate according to an embodiment of the present disclosure
  • FIG. 2A shows a cross-sectional view of the microfluidic substrate shown in FIG. 1 along the line A-A' according to an embodiment of the present disclosure
  • FIG. 2B shows a cross-sectional view of the microfluidic substrate shown in FIG. 1 along the line B-B' according to an embodiment of the present disclosure
  • FIG. 2C shows a cross-sectional view of the microfluidic substrate shown in FIG. 1 along the line B-B' according to another embodiment of the present disclosure
  • FIG. 3 shows a top view of a microfluidic substrate according to another embodiment of the present disclosure
  • FIG. 4 shows a top view of a microfluidic substrate according to yet another embodiment of the present disclosure
  • FIG. 5 shows a cross-sectional view of a microfluidic chip according to an embodiment of the present disclosure.
  • FIG. 6 shows a flowchart of a method for fabricating a microfluidic chip according to an embodiment of the present disclosure.
  • FIG. 1 shows a top view of a microfluidic substrate according to an embodiment of the present disclosure
  • FIG. 2A shows a cross-sectional view of the microfluidic substrate shown in FIG. 1 along the line A-A'
  • FIG. 2B shows FIG. 1 A cross-sectional view of the microfluidic substrate shown along the line B-B'.
  • the shape, size and thickness of each film layer in the drawings do not reflect the actual scale of each film layer, and are only intended to illustrate the present disclosure. As shown in FIGS.
  • the microfluidic substrate 100 includes: a first substrate 101 ; a conductive layer 102 located on the first substrate 101 ; and a conductive layer 102 located away from the first A confinement layer 103 on one side of the substrate 101, the confinement layer 103 defines a recessed portion 104; wherein, the conductive layer 102 includes a plurality of conductive patterns 105 corresponding to the recessed portion 104, the plurality of conductive patterns 105 along the Arranged in a first direction X, each conductive pattern 105 extends along a second direction Y and includes a first end 1051 and a second end 1052, the first direction X being perpendicular to the second direction Y; each conductive pattern 105 The first and second ends of the conductive pattern 105 have the largest local resistance values.
  • local resistance value refers to the resistance value per unit length of each conductive pattern in the length direction (ie, the second direction).
  • the first end and the second end of the conductive pattern have a larger local resistance value than the middle position.
  • the resistance of the conductive layer is designed to improve the uniformity of heating and reduce the low temperature edge area of the conductive layer. Thus, the actual size of the microfluidic chip can be effectively reduced, and the number of reaction chambers per unit area can be increased.
  • the conductive layer 102 has a uniform thickness, and each conductive pattern 105 is in the second direction Y There is a midpoint 106 thereon, and each conductive pattern 105 has a maximum width along the first direction X at the midpoint 106 .
  • each conductive pattern 105 may have a centrosymmetric shape having a center of symmetry along the first direction X at the center of symmetry (ie, the midpoint 106 in the second direction Y). maximum width.
  • the distance between two adjacent conductive patterns 105 may be in the range of 1 ⁇ 200 ⁇ m. Simulation results show that the temperature uniformity in the recessed region is significantly improved after patterning the conductive patterns in both directions.
  • each conductive pattern 105 has a direction along the first direction X at the first end and the second end of the conductive pattern. Minimum width.
  • each conductive pattern 105 has a minimum width along the first direction X at the first end and the second end of the conductive pattern.
  • each conductive pattern 105 has a width that varies continuously along the second direction Y. As shown in FIG. 3, each of the conductive patterns 105 has straight sides. As shown in FIG. 1, each conductive pattern 105 has curved sides.
  • each conductive pattern 105 has a width that varies discontinuously along the second direction Y.
  • each conductive pattern 105 has an axisymmetric shape whose axis of symmetry is parallel to the second direction Y.
  • each conductive pattern 105 may also have a center-symmetric shape.
  • each conductive pattern 105 has a minimum thickness at the first and second ends of the conductive pattern 105 (as indicated by the dashed circles in FIG. 2C ).
  • each conductive pattern 105 may have a shape as shown in FIG. 1 , FIG. 3 or FIG. 4 on the X-Y plane, and each conductive pattern 105 has a minimum thickness at the first end and the second end of the conductive pattern 105 .
  • each conductive pattern 105 may have a rectangular shape in the X-Y plane (ie, have a constant width), and each conductive pattern 105 has a minimum at the first and second ends of the conductive pattern 105 . thickness. Thereby, it can be ensured that each conductive pattern 105 has a maximum local resistance value at the first end and the second end of the conductive pattern 105 .
  • the overall resistance value between the first end and the second end of each conductive pattern 105 increases as the distance between the conductive pattern 105 and the center C of the recess increases. decrease.
  • all resistance value refers to the resistance value between the first end and the second end of each conductive pattern, ie, the resistance across the first end and the second end value.
  • the desired overall resistance value can be obtained by designing the shape of each conductive pattern.
  • the overall resistance value of the conductive pattern can also be determined by measuring at both ends of the conductive pattern in the longitudinal direction.
  • the overall resistance value between the first end and the second end of each conductive pattern decreases as the distance between the conductive pattern and the center of the recess increases. That is, the conductive patterns located at the edges of the recessed portion have a smaller overall resistance value than the conductive patterns located at the center of the recessed portion.
  • the microfluidic substrate provided by the embodiments of the present disclosure, by further designing the resistance of the conductive layer, the uniformity of heating is improved, and the low temperature edge area of the conductive layer is reduced. Thus, the actual size of the microfluidic chip can be effectively reduced, and the number of reaction chambers per unit area can be increased.
  • the conductive layer 102 has a uniform thickness, and the width of each conductive pattern 105 in the first direction X varies with the conductive pattern 105 It increases as the distance from the center C of the recessed portion 104 increases.
  • the plurality of conductive patterns 105 may have the same thickness, and the conductive patterns 105 away from the center C have a larger width. Thereby, a conductive pattern having a desired resistance value can be obtained in a simple design manner.
  • the width of a conductive pattern in a certain direction refers to the maximum width of the conductive pattern in that direction, unless otherwise specified.
  • the lengths of the plurality of conductive patterns 105 in the second direction Y are the same.
  • the projection of the plurality of conductive patterns on the first substrate corresponds to a rectangular reaction chamber. Thereby, uniform heating can be provided over the area of the rectangular reaction chamber.
  • the plurality of conductive patterns 105 form a parallel circuit, and the current path of each conductive pattern 105 is along the second direction Y .
  • trace patterns 107 and conductor plugs 108 may be used such that the plurality of conductive patterns 105 form a parallel circuit.
  • the conductor plug 108 may be connected to an external circuit (not shown) to provide power to the parallel circuit.
  • the present disclosure utilizes a simple parallel circuit structure to provide uniform heating over the area of the reaction chamber.
  • the wiring pattern 107 and the plurality of conductive patterns 105 may be fabricated using the same material.
  • the film layer of the conductive layer 102 may be patterned into the wiring pattern 107 and the plurality of conductive patterns 105 in the same patterning process.
  • the first substrate 101 is a glass substrate.
  • a glass substrate can be used to fabricate a microfluidic substrate and a microfluidic chip. Compared with using a silicon substrate, the manufacturing process is simplified and the process difficulty is reduced.
  • the material of the conductive layer 102 includes at least one of indium tin oxide and indium zinc oxide.
  • the conductive layer is made of indium tin oxide and/or indium zinc oxide to avoid optical interference on detection.
  • the surface of the recessed portion 104 is hydrophilic.
  • the surface of the recessed portion 104 may be subjected to a hydrophilization treatment, or a hydrophilic layer 109 may be vapor-deposited on the surface of the recessed portion 104 to confine the liquid in the recessed portion 104 .
  • the material of the hydrophilic layer 109 may be silicon dioxide, and the embodiment of the present disclosure is not limited thereto.
  • a hydrophobic layer 110 may also be arranged on the surface of the defining layer 103 outside the recess.
  • the material of the hydrophobic layer 110 may be resin or silicon nitride, and the embodiment of the present disclosure is not limited thereto.
  • the microfluidic substrate 100 further includes: a wiring 111 located between the conductive layer 102 and the first substrate 101 , and a wiring 111 located between the conductive layer 102 and the first substrate 101
  • a passivation layer 112 is formed between the traces 111 and the conductive layer 102 , the passivation layer 112 includes a through hole 113 ; the conductive layer 102 is electrically connected to the trace 111 through the through hole 113 .
  • the conductive layer 102 may be electrically connected to the traces 110 via the conductor plugs 108 (shown in FIG. 1 ) disposed in the through holes 112 . With the above arrangement, the conductive layer can be connected to an external circuit. In addition, an insulating layer 114 may also be arranged between the conductive layer 102 and the limiting layer 103 to prevent the conductive layer 102 from being short-circuited.
  • the wire 111 includes a Mo-AlNd-Mo alloy layer.
  • a Mo-AlNd-Mo alloy layer is used to fabricate the traces 111 , which reduces the resistance of the traces 111 , thereby reducing the heat generated on the traces 111 .
  • a microfluidic chip includes the microfluidic substrate described in the above embodiments, so the structure of the microfluidic chip can also refer to the above-mentioned embodiments of the microfluidic substrate and the accompanying drawings. As shown in FIG. 1 and FIG.
  • the microfluidic chip 500 includes: a first substrate 101 ; a conductive layer 102 located on the first substrate 101 ; and a conductive layer 102 located away from the first A confinement layer 103 on one side of the substrate 101, the confinement layer 103 defines a recessed portion 104; wherein, the conductive layer 102 includes a plurality of conductive patterns 105 corresponding to the recessed portion 104, the plurality of conductive patterns 105 along the Arranged in a first direction X, each conductive pattern 105 extends along a second direction Y and includes a first end 1051 and a second end 1052, the first direction X being perpendicular to the second direction Y; each conductive pattern 105 The conductive pattern 105 has the largest local resistance value at the first and second ends; the opposite substrate 115 on the side of the defining layer 103 away from the first substrate 101 ; and the recessed portion A sealant 116 around the periphery of 104 , the sealant 116 defines a cavity
  • the first end and the second end of the conductive pattern have a larger local resistance value than the middle position.
  • the resistance of the conductive layer is designed to improve the uniformity of heating and reduce the low temperature edge area of the conductive layer. Thus, the actual size of the microfluidic chip can be effectively reduced, and the number of reaction chambers per unit area can be increased.
  • the conductive layer 102 has a uniform thickness, and each conductive pattern 105 is in the second direction Y There is a midpoint 106 thereon, and each conductive pattern 105 has a maximum width along the first direction X at the midpoint 106 .
  • each conductive pattern 105 may have a centrosymmetric shape having a center of symmetry along the first direction X at the center of symmetry (ie, the midpoint 106 in the second direction Y). maximum width.
  • the distance between two adjacent conductive patterns 105 may be in the range of 1 ⁇ 200 ⁇ m. Simulation results show that the temperature uniformity in the recessed region is significantly improved after patterning the conductive patterns in both directions.
  • each conductive pattern 105 has a direction along the first direction X at the first end and the second end of the conductive pattern. Minimum width.
  • each conductive pattern 105 has a minimum width along the first direction X at the first end and the second end of the conductive pattern.
  • each conductive pattern 105 has a width that varies continuously along the second direction Y. As shown in FIG. 3, each of the conductive patterns 105 has straight sides. As shown in FIG. 1, each conductive pattern 105 has curved sides.
  • each conductive pattern 105 has a width that varies discontinuously along the second direction Y.
  • each conductive pattern 105 has an axisymmetric shape whose axis of symmetry is parallel to the second direction Y.
  • each conductive pattern 105 may also have a center-symmetric shape.
  • each conductive pattern 105 has a minimum thickness at the first and second ends of the conductive pattern 105 (as indicated by the dashed circles in FIG. 2C ).
  • each conductive pattern 105 may have a shape as shown in FIG. 1 , FIG. 3 or FIG. 4 on the X-Y plane, and each conductive pattern 105 has a minimum thickness at the first end and the second end of the conductive pattern 105 .
  • each conductive pattern 105 may have a rectangular shape in the X-Y plane (ie, have a constant width), and each conductive pattern 105 has a minimum at the first and second ends of the conductive pattern 105 . thickness. Thereby, it can be ensured that each conductive pattern 105 has a maximum local resistance value at the first end and the second end of the conductive pattern 105 .
  • the overall resistance value between the first end and the second end of each conductive pattern 105 increases as the distance between the conductive pattern 105 and the center C of the recess increases. decrease.
  • the overall resistance value between the first end and the second end of each conductive pattern decreases as the distance between the conductive pattern and the center of the recess increases. That is, the conductive patterns located at the edges of the recessed portion have a smaller overall resistance value than the conductive patterns located at the center of the recessed portion.
  • the microfluidic substrate provided by the embodiments of the present disclosure, by further designing the resistance of the conductive layer, the uniformity of heating is improved, and the low temperature edge area of the conductive layer is reduced. Thus, the actual size of the microfluidic chip can be effectively reduced, and the number of reaction chambers per unit area can be increased.
  • the conductive layer 102 has a uniform thickness, and the width of each conductive pattern 105 in the first direction X varies with the conductive pattern 105 It increases as the distance from the center C of the recessed portion 104 increases.
  • the plurality of conductive patterns 105 may have the same thickness, and the conductive patterns 105 away from the center C have a larger width. Thereby, a conductive pattern having a desired resistance value can be obtained in a simple design manner.
  • the lengths of the plurality of conductive patterns 105 in the second direction Y are the same.
  • the projection of the plurality of conductive patterns on the first substrate corresponds to a rectangular reaction chamber. Thereby, uniform heating can be provided over the area of the rectangular reaction chamber.
  • the plurality of conductive patterns 105 form a parallel circuit, and the current path of each conductive pattern 105 is along the second direction Y .
  • trace patterns 107 and conductor plugs 108 may be used such that the plurality of conductive patterns 105 form a parallel circuit.
  • the conductor plug 108 may be connected to an external circuit (not shown) to provide power to the parallel circuit.
  • the present disclosure utilizes a simple parallel circuit structure to provide uniform heating over the area of the reaction chamber.
  • the wiring pattern 107 and the plurality of conductive patterns 105 may be fabricated using the same material.
  • the film layer of the conductive layer 102 may be patterned into the wiring pattern 107 and the plurality of conductive patterns 105 in the same patterning process.
  • the first substrate 101 is a glass substrate.
  • a glass substrate can be used to fabricate a microfluidic substrate and a microfluidic chip. Compared with using a silicon substrate, the manufacturing process is simplified and the process difficulty is reduced.
  • the material of the conductive layer 102 includes at least one of indium tin oxide and indium zinc oxide.
  • the conductive layer is made of indium tin oxide and/or indium zinc oxide to avoid optical interference on detection.
  • the surface of the recessed portion 104 is hydrophilic.
  • the surface of the recessed portion 104 may be subjected to a hydrophilization treatment, or a hydrophilic layer 109 may be vapor-deposited on the surface of the recessed portion 104 to confine the liquid in the recessed portion 104 .
  • the material of the hydrophilic layer 109 may be silicon dioxide, and the embodiment of the present disclosure is not limited thereto.
  • a hydrophobic layer 110 may also be arranged on the surface of the defining layer 103 outside the recess.
  • the material of the hydrophobic layer 110 may be resin or silicon nitride, and the embodiment of the present disclosure is not limited thereto.
  • the microfluidic substrate 100 further includes: a wiring 111 located between the conductive layer 102 and the first substrate 101 , and a wiring 111 located between the conductive layer 102 and the first substrate 101
  • a passivation layer 112 is formed between the traces 111 and the conductive layer 102 , the passivation layer 112 includes a through hole 113 ; the conductive layer 102 is electrically connected to the trace 111 through the through hole 113 .
  • the conductive layer 102 may be electrically connected to the traces 110 via the conductor plugs 108 (shown in FIG. 1 ) disposed in the through holes 112 . With the above arrangement, the conductive layer can be connected to an external circuit. In addition, an insulating layer 114 may also be arranged between the conductive layer 102 and the limiting layer 103 to prevent the conductive layer 102 from being short-circuited.
  • the wire 111 includes a Mo-AlNd-Mo alloy layer.
  • a Mo-AlNd-Mo alloy layer is used to fabricate the traces 111 , which reduces the resistance of the traces 111 , thereby reducing the heat generated on the traces 111 .
  • the chamber 117 is a reaction chamber
  • the opposite substrate 115 includes a sample inlet 119 and a sample outlet 120 .
  • microfluidic chip provided by the embodiments of the present disclosure can be used for dPCR, and a patterned temperature control module is integrated on the chip to achieve efficient, accurate, and uniform temperature control, effectively reducing the chip size, increasing the number of reaction chamber arrays, and avoiding detection results. of inaccuracy.
  • a method for fabricating a microfluidic chip includes: S11 providing a first substrate; S12 forming a conductive layer on the first substrate and patterning the conductive layer; S13 placing the conductive layer away from the first substrate A confinement layer is formed on the bottom side, the confinement layer defines a concave portion, the conductive layer includes a plurality of conductive patterns corresponding to the concave portion, the plurality of conductive patterns are arranged along the first direction, and each conductive pattern is along the A second direction extends and includes a first end and a second end, the first direction being perpendicular to the second direction; each conductive pattern has a maximum local resistance value at the first end and the second end of the conductive pattern ; S14 arranging a sealant around the recessed portion, the sealant defining a cavity; and S15 arranging an opposite substrate on the side of the defining layer away from the first substrate.
  • the resistance of the conductive layer is designed, the uniformity of heating is improved, and the low temperature edge area of the conductive layer is reduced.
  • the actual size of the microfluidic chip can be effectively reduced, and the number of reaction chambers per unit area can be increased.
  • the microfluidic chip 500 may include the microfluidic substrate described in any of the previous embodiments. The steps of the method are briefly described below by taking the microfluidic chip 500 including the microfluidic substrate 100 as an example.
  • Step 701 providing a first substrate 101 .
  • the first substrate 101 may be made of any suitable material, in one example, the first substrate 101 is made of glass.
  • Step 702 forming a conductive film layer on the first substrate 101 at about 240°C.
  • the thicknesses of sequentially deposited on the first substrate 101 are The molybdenum (Mo) layer, the thickness is The aluminum neodymium (AlNd) layer and thickness of molybdenum (Mo) layer to form a conductive film layer.
  • the conductive film layer is patterned, such as exposure, development, etching, etc., to form wirings 111 .
  • Step 703 at about 200° C., deposit a first insulating film layer 112 on the wires 111 , and pattern the first insulating film layer 112 to form a first insulating layer 112 covering the wires 111 .
  • the first insulating layer 112 has a thickness of about SiO2 layer.
  • Step 704 Pattern the first insulating layer 112 to form at least one through hole 113 penetrating the first insulating layer 112 , and the at least one through hole 113 exposes a portion of the wiring 111 .
  • the first insulating layer 112 is etched in a dry etcher to form the through holes 113 .
  • etching for 10s under the conditions of a pressure of about 150mtorr, a power of about 800w, and a volume flow of O 2 of about 400sccm (standard cubic centimeter per minute); under the conditions of a pressure of about 60mtorr and a power of about 800w , CF 4 and O 2 gas volume flow ratio of about 200:50 for 200s etching; under pressure of about 130 mtorr, power of about 800w, O 2 and CF 4 gas volume flow ratio of about 400: 40 Etching for 30 s under the conditions of about 60 mtorr pressure, about 800 w power, and about 200:50 gas volume flow ratio of CF 4 and O 2 for 160 s.
  • Step 705 Deposit a conductive film layer (conductive layer) on the side of the first insulating layer 112 away from the first substrate 101, and then perform the steps of exposing, developing, etching, and stripping the conductive film layer to form a plurality of conductive films.
  • Conductive pattern 105 ie, heater
  • the material of the conductive pattern 105 is ITO.
  • Step 706 depositing a second insulating film layer on a side of the conductive pattern 105 away from the first substrate 101 , and patterning the second insulating film layer to form a second insulating layer 114 at least partially covering the conductive pattern 105 .
  • the material of the second insulating layer 114 is SiO 2 .
  • the second insulating layer 114 includes a sequentially stacked thickness of about SiO 2 layer and thickness is approximately SiN x layer.
  • Step 707 Coating a confinement film layer on the side of the second insulating layer 114 away from the first substrate 101 , and patterning the confinement film layer to form the confinement layer 103 defining the concave portion 104 .
  • the process of forming the defining layer 103 is described as follows: first, under the pressure of 30KPa, spin-coating optical glue on the surface of the second insulating layer 114 away from the first substrate 101 at a speed of 300 rpm, and the spin-coating time About 10 seconds, then the optical glue was cured for 120 seconds at a temperature of 90°C. The above process was repeated twice to obtain a defined film layer.
  • the limiting film layer is exposed through a mask, and then the exposed limiting film layer is developed for 100 seconds with a developing solution, and then etched. At a temperature of 230° C., the etched defining film layer is cured for 30 minutes, and finally a defining layer 103 defining the recessed portion 104 is obtained.
  • the material of the defining layer 103 includes photoresist.
  • the depressions 104 of the defining layer 103 are cylindrical depressions, the bottoms of the depressions 104 are 50 microns in diameter and between 40 and 50 microns in depth.
  • the defining layer 103 may define a plurality of concave portions 104 , and the distance between the centers of two adjacent concave portions 104 is 100 ⁇ m.
  • Step 708 at 200° C., deposit an insulating film layer on the surface of the defining layer 103 away from the first substrate 101 , and perform exposure, development and etching on the insulating film layer to form a patterned layer.
  • the patterned layer was treated with a 0.4% KOH solution for about 15 minutes to hydrophilically modify the patterned layer, thereby forming a hydrophilic layer 109 .
  • the hydrophilic layer 109 covers the surface of the defining layer 103 away from the first substrate 101 and covers the bottom and sidewalls of the recess 104 .
  • the hydrophilic layer 109 has a thickness of about SiO2 layer.
  • Step 709 depositing an insulating film layer on the surface of the hydrophilic layer 109 away from the first substrate 101 , and exposing, developing and etching the insulating film layer to form the first hydrophobic layer 110 .
  • the process of forming the first hydrophobic layer 110 is as follows: in a Plasma Enhanced Chemical Vapor Deposition (PECVD) equipment, the temperature is about 200° C., the power is about 600W, and the pressure is about 1200mtorr , and the distance between the plasma reaction enhanced target in the PECVD equipment and the sample to be deposited is about 1000 mils, into the reaction chamber SiH 4 (volume flow rate of 110sccm), NH 3 (volume flow rate of 700sccm) and N 2 (volume flow rate of 2260 sccm, passage time of 100 seconds) to deposit on the surface of the hydrophilic layer 108 away from the first substrate 101 with a thickness of The SiN x film layer is exposed, developed and etched to form the first hydrophobic layer 110
  • Step 710 Encapsulate the microfluidic substrate 100 that has completed the hydrophilic treatment and the hydrophobic treatment.
  • Step 711 Provide the opposite substrate 115 .
  • the opposing substrate 115 may be made of any suitable material, and in one example, the opposing substrate 115 is made of glass.
  • Step 712 deposit a film layer on the side of the opposite substrate 115 close to the first substrate 101, and process the film layer to form a second hydrophobic layer 118, the second hydrophobic layer 118 having a thickness of about TiO2 layer.
  • the second hydrophobic layer 118 is formed of SiNx .
  • Step 713 Punch holes on the opposite substrate 115 and the second hydrophobic layer 118 to form at least one sample inlet 119 and at least one sample outlet 120 penetrating the opposite substrate 115 and the second hydrophobic layer 118 .
  • the diameter of the at least one sample inlet 119 and the at least one sample outlet 120 is between 0.6 millimeters and 1.2 millimeters.
  • Step 714 The microfluidic substrate 100 and the opposite substrate 115 are cured and encapsulated with a frame sealant, and the interval between the microfluidic substrate 100 and the opposite substrate 115 is defined.
  • the manufacturing method may further include more steps, which may be determined according to actual requirements, which are not limited in the embodiments of the present disclosure.
  • steps which may be determined according to actual requirements, which are not limited in the embodiments of the present disclosure.
  • reference may be made to the descriptions of the microfluidic substrate 100 and the microfluidic chip 500 above, which will not be repeated here.

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Abstract

本公开提供了一种微流控基板、微流控芯片及其制作方法。所述微流控基板包括：第一衬底；位于所述第一衬底上的导电层；以及位于所述导电层背离所述第一衬底一侧的限定层，所述限定层限定凹陷部；其中，所述导电层包括对应于所述凹陷部的多个导电图案，所述多个导电图案沿第一方向排列，每个导电图案沿着第二方向延伸并且包括第一端和第二端，所述第一方向垂直于所述第二方向；每个导电图案在该导电图案的第一端和第二端处具有最大的局部电阻值。

Description

微流控基板、微流控芯片及其制作方法 技术领域
本公开涉及生物检测领域，尤其涉及一种微流控基板、微流控芯片及其制作方法。
背景技术
数字聚合酶链式反应芯片技术(dPCR，digital Polymerase Chain Reaction)是一种提供数字化DNA量化信息的定量分析方法，自提出以来在多个领域展现出了显著优势。但是初期的dPCR技术发展十分缓慢，这是由于如果使用传统的96孔板或者384孔板进行PCR扩增。需要数个多孔板同时进行扩增，不仅操作复杂，且实验样品和试剂的消耗量非常大。随着微流控技术的出现和近年来的高速发展，将微流控技术与dPCR技术结合使得灵敏度和精确度有了很大提高。迄今为止，已有多家公司相继推出了dPCR产品。这些产品已经在单细胞分析、癌症早期诊断和产前诊断等研究领域显示出巨大的技术优势和商业前景。
发明内容
本公开提供了一种微流控基板、微流控芯片及其制作方法。利用对导电层的图案化设计，改善了加热的均匀性，减少了导电层的低温边缘面积。由此，可以有效地减小微流控芯片的实际尺寸，增加单位面积上的反应腔室数量。
根据本公开的一个方面，提供了一种微流控基板。所述微流控基板包括：第一衬底；位于所述第一衬底上的导电层；以及位于所述导电层背离所述第一衬底一侧的限定层，所述限定层限定凹陷部；其中，所述导电层包括对应于所述凹陷部的多个导电图案，所述多个导电图案沿第一方向排列，每个导电图案沿着第二方向延伸并且包括第一端和第二端，所述第一方向垂直于所述第二方向；每个导电图案在该导电图案的第一端和第二端处具有最大的局部电阻值。
可选地，在一些实施例中，所述导电层具有均匀的厚度，每个导电图案在所述第二方向上具有中点，并且每个导电图案在所述中点处具有沿着所述第一方向的最大宽度。
可选地，在一些实施例中，每个导电图案在该导电图案的第一端和第二端处具有沿着所述第一方向的最小宽度。
可选地，在一些实施例中，每个导电图案具有沿着所述第二方向连续地变化的宽度。
可选地，在一些实施例中，每个导电图案具有直线形的侧边。
可选地，在一些实施例中，每个导电图案具有曲线形的侧边。
可选地，在一些实施例中，每个导电图案具有沿着所述第二方向非连续地变化的宽度。
可选地，在一些实施例中，每个导电图案具有轴对称的形状，所述轴对称形状的对称轴平行于所述第二方向。
可选地，在一些实施例中，每个导电图案在该导电图案的第一端和第二端处具有最小厚度。
可选地，在一些实施例中，每个导电图案的第一端和第二端之间的整体电阻值随着该导电图案和所述凹陷部的中心之间距离的增大而减小。
可选地，在一些实施例中，所述导电层具有均匀的厚度，每个导电图案在所述第一方向上的宽度随着该导电图案和所述凹陷部的中心之间距离的增大而增大。
可选地，在一些实施例中，所述多个导电图案在所述第二方向上的长度是相同的。
可选地，在一些实施例中，所述多个导电图案构成并联电路，并且每个导电图案的电流通路沿着所述第二方向。
可选地，在一些实施例中，所述第一衬底是玻璃衬底。
可选地，在一些实施例中，所述导电层的材料包括氧化铟锡和氧化铟锌之至少之一者。
可选地，在一些实施例中，所述凹陷部的表面是亲水性的。
可选地，在一些实施例中，所述微流控基板还包括：位于所述导电层和所述第一衬底之间的走线，以及位于所述走线和所述导电层之间的钝化层，所述钝化层包括通孔；所述导电层经由所述通孔与所述走线电连接。
可选地，在一些实施例中，所述走线包括Mo-AlNd-Mo合金层。
根据本公开的另一方面，提供了一种微流控芯片。所述微流控芯 片包括：如以上任一实施例所述的微流控基板；位于所述限定层背离所述第一衬底的一侧的对置基板；以及位于所述凹陷部周边的封框胶，所述封框胶限定腔室。
可选地，在一些实施例中，所述腔室是反应腔室，所述对置基板包括进样口和出样口。
根据本公开的又一方面，提供了一种微流控芯片的制作方法。所述方法包括：提供第一衬底；在所述第一衬底上形成导电层并图案化所述导电层；在所述导电层背离所述第一衬底一侧形成限定层，所述限定层限定凹陷部，所述导电层包括对应于所述凹陷部的多个导电图案，所述多个导电图案沿第一方向排列，每个导电图案沿着第二方向延伸并且包括第一端和第二端，所述第一方向垂直于所述第二方向；每个导电图案在该导电图案的第一端和第二端处具有最大的局部电阻值；在所述凹陷部周边布置封框胶，所述封框胶限定腔室；以及在所述限定层背离所述第一衬底的一侧布置对置基板。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了根据本公开实施例的微流控基板的俯视图；
图2A示出了根据本公开实施例的如图1所示的微流控基板沿着A-A′线的剖面图；
图2B示出了根据本公开实施例的如图1所示的微流控基板沿着B-B′线的剖面图；
图2C示出了根据本公开另一实施例的如图1所示的微流控基板沿着B-B′线的剖面图；
图3示出了根据本公开另一实施例的微流控基板的俯视图；
图4示出了根据本公开又一实施例的微流控基板的俯视图；
图5示出了根据本公开实施例的微流控芯片的剖面图；以及
图6示出了根据本公开实施例的微流控芯片的制作方法的流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
根据本公开的一个方面，提供了一种微流控基板。图1示出了根据本公开实施例的微流控基板的俯视图；图2A示出了如图1所示的微流控基板沿着A-A′线的剖面图；图2B示出了如图1所示的微流控基板沿着B-B′线的剖面图。附图中各膜层的形状、尺寸和厚度不反映各膜层的真实比例，目的只是示意说明本公开内容。如图1-图4所示，所述微流控基板100包括：第一衬底101；位于所述第一衬底101上的导电层102；以及位于所述导电层102背离所述第一衬底101一侧的限定层103，所述限定层103限定凹陷部104；其中，所述导电层102包括对应于所述凹陷部104的多个导电图案105，所述多个导电图案105沿第一方向X排列，每个导电图案105沿着第二方向Y延伸并且包括第一端1051和第二端1052，所述第一方向X垂直于所述第二方向Y；每个导电图案105在该导电图案105的第一端和第二端处具有最大的局部电阻值。
在本公开的上下文中，“局部电阻值”指的是每个导电图案在长度方向(即，第二方向)上单位长度的电阻值。
在本公开的实施例中，对于单个导电图案来说，该导电图案的第一端和第二端具有比中间位置更大的局部电阻值。根据电阻发热公式P＝I 2R，因此该导电图案的第一端和第二端的发热功率也将大于该导电图案的中间位置的发热功率。根据本公开实施例提供的微流控基板，利用对导电层的电阻进行设计，改善了加热的均匀性，减少了导电层的低温边缘面积。由此，可以有效地减小微流控芯片的实际尺寸，增加单位面积上的反应腔室数量。
可选地，在一些实施例中，如图1、图2A、图2B、图3和图4所示，所述导电层102具有均匀的厚度，每个导电图案105在所述第二方向Y上具有中点106，并且每个导电图案105在所述中点106处具 有沿着所述第一方向X的最大宽度。
例如，每个导电图案105可以具有中心对称的形状，所述中心对称的形状在对称中心(即，在所述第二方向Y上的中点106)处具有沿着所述第一方向X的最大宽度。
两个相邻的导电图案105之间的距离可以在1～200微米的范围内。仿真结果表明，在两个方向上对导电图案进行图案化设计之后，凹陷部区域的温度均匀性得到了显著的改善。
可选地，在一些实施例中，如图1、图3和图4所示，每个导电图案105在该导电图案的第一端和第二端处具有沿着所述第一方向X的最小宽度。
如图1、图3和图4所示，每个导电图案105在该导电图案的第一端和第二端处具有沿着所述第一方向X的最小宽度。
可选地，在一些实施例中，如图1和图3所示，每个导电图案105具有沿着所述第二方向Y连续地变化的宽度。如图3所示，每个导电图案105具有直线形的侧边。如图1所示，每个导电图案105具有曲线形的侧边。
可选地，在一些实施例中，如图4所示，每个导电图案105具有沿着所述第二方向Y非连续地变化的宽度。
可选地，在一些实施例中，如图1、图3和图4所示，每个导电图案105具有轴对称的形状，所述轴对称形状的对称轴平行于所述第二方向Y。类似地，每个导电图案105还可以具有中心对称的形状。
可选地，在一些实施例中，如图2C所示，每个导电图案105在该导电图案105的第一端和第二端处具有最小厚度(如图2C中的虚线圆圈所指示)。
例如，每个导电图案105在X-Y平面上可以具有如图1、图3或图4所示的形状，并且每个导电图案105在该导电图案105的第一端和第二端处具有最小厚度。可替换地，每个导电图案105在X-Y平面上可以具有矩形的形状(即，具有不变的宽度)，并且每个导电图案105在该导电图案105的第一端和第二端处具有最小厚度。由此，可以确保每个导电图案105在该导电图案105的第一端和第二端处具有最大的局部电阻值。
可选地，在一些实施例中，每个导电图案105的第一端和第二端 之间的整体电阻值随着该导电图案105和所述凹陷部的中心C之间距离的增大而减小。
在本公开的上下文中，“整体电阻值”指的是在每个导电图案的第一端和第二端之间的电阻值，即，横跨所述第一端和所述第二端的电阻值。可以通过设计每个导电图案的形状来获得希望的整体电阻值。也可以通过在导电图案的纵向方向上的两端进行测量而确定该导电图案的整体电阻值。
在一些实施例中，每个导电图案的第一端和第二端之间的整体电阻值随着该导电图案和所述凹陷部的中心之间距离的增大而减小。也就是说，相比于位于所述凹陷部中心的导电图案，位于所述凹陷部边缘的导电图案具有更小的整体电阻值。根据电阻发热公式P＝U 2/R，因此远离中心C的导电图案105的发热功率将大于靠近中心C的导电图案105的发热功率。根据本公开实施例提供的微流控基板，利用对导电层的电阻的进一步设计，改善了加热的均匀性，减少了导电层的低温边缘面积。由此，可以有效地减小微流控芯片的实际尺寸，增加单位面积上的反应腔室数量。
可选地，在一些实施例中，如图1和图2B所示，所述导电层102具有均匀的厚度，每个导电图案105在所述第一方向X上的宽度随着该导电图案105和所述凹陷部104的中心C之间距离的增大而增大。
如图1和图2B所示，多个导电图案105可以具有相同的厚度，并且远离中心C的导电图案105具有更大的宽度。由此，可以以简单的设计方式获得具有希望的电阻值的导电图案。
在本公开的上下文中，若无特指，“导电图案在某一方向上的宽度”指的是该导电图案在该方向上的最大宽度。
可选地，在一些实施例中，如图1、图3和图4所示，所述多个导电图案105在所述第二方向Y上的长度是相同的。
利用上述布置，多个导电图案在所述第一衬底上的投影对应于矩形的反应腔室。由此，可以在矩形的反应腔室的面积上提供均匀的加热。
可选地，在一些实施例中，如图1、图3和图4所示，所述多个导电图案105构成并联电路，并且每个导电图案105的电流通路沿着所述第二方向Y。
在一些实施例中，如图1-4所示，可以使用走线图案107和导体插塞108，使得所述多个导电图案105构成并联电路。所述导体插塞108可以连接至外部电路(未示出)，从而向所述并联电路提供电力。由此，本公开利用简单的并联电路结构在反应腔室的面积上提供均匀的加热。可以使用相同的材料来制作所述走线图案107和所述多个导电图案105。例如，可以在同一构图工艺中将导电层102的膜层图案化为所述走线图案107和所述多个导电图案105。
可选地，在一些实施例中，所述第一衬底101是玻璃衬底。
根据本公开实施例，可以使用玻璃衬底制作微流控基板和微流控芯片。相比于使用硅衬底，简化了制作工艺，降低了工艺难度。
可选地，在一些实施例中，所述导电层102的材料包括氧化铟锡和氧化铟锌之至少之一者。
氧化铟锡和氧化铟锌是光学透明的。因此，采用氧化铟锡和/或氧化铟锌制作所述导电层，避免了对检测产生光学干扰。
可选地，在一些实施例中，如图2A所示，所述凹陷部104的表面是亲水性的。
可以对所述凹陷部104的表面执行亲水化处理，或在所述凹陷部104的表面蒸镀亲水层109，从而将液体限定在所述凹陷部104中。所述亲水层109的材料可以是二氧化硅，本公开的实施例不限于此。此外，还可以在所述限定层103的位于所述凹陷部外侧的表面上布置疏水层110。所述疏水层110的材料可以是树脂或氮化硅，本公开的实施例不限于此。
可选地，在一些实施例中，如图2A所示，所述微流控基板100还包括：位于所述导电层102和所述第一衬底101之间的走线111，以及位于所述走线111和所述导电层102之间的钝化层112，所述钝化层112包括通孔113；所述导电层102经由所述通孔113与所述走线111电连接。
本领域技术人员能够理解，所述导电层102可以经由设置在所述通孔112中的导体插塞108(在图1中示出)与所述走线110电连接。利用上述布置，所述导电层可以连接至外部电路。此外，还可以在所述导电层102和所述限定层103之间布置绝缘层114，避免导电层102发生短路。
可选地，在一些实施例中，所述走线111包括Mo-AlNd-Mo合金层。
根据本公开的实施例，采用例如Mo-AlNd-Mo合金层来制作走线111，降低了走线111的电阻，从而减少走线111上产生的热量。
根据本公开的另一方面，提供了一种微流控芯片。所述微流控芯片包括如以上实施例所述的微流控基板，因此所述微流控芯片的结构也可以参考上述微流控基板的实施例以及附图。如图1和图5所示，所述微流控芯片500包括：第一衬底101；位于所述第一衬底101上的导电层102；以及位于所述导电层102背离所述第一衬底101一侧的限定层103，所述限定层103限定凹陷部104；其中，所述导电层102包括对应于所述凹陷部104的多个导电图案105，所述多个导电图案105沿第一方向X排列，每个导电图案105沿着第二方向Y延伸并且包括第一端1051和第二端1052，所述第一方向X垂直于所述第二方向Y；每个导电图案105在该导电图案105的第一端和第二端处具有最大的局部电阻值；位于所述限定层103背离所述第一衬底101的一侧的对置基板115；以及位于所述凹陷部104周边的封框胶116，所述封框胶116限定腔室117。
在本公开的实施例中，对于单个导电图案来说，该导电图案的第一端和第二端具有比中间位置更大的局部电阻值。根据电阻发热公式P＝I 2R，因此该导电图案的第一端和第二端的发热功率也将大于该导电图案的中间位置的发热功率。根据本公开实施例提供的微流控基板，利用对导电层的电阻进行设计，改善了加热的均匀性，减少了导电层的低温边缘面积。由此，可以有效地减小微流控芯片的实际尺寸，增加单位面积上的反应腔室数量。
可选地，在一些实施例中，如图1、图2A、图2B、图3和图4所示，所述导电层102具有均匀的厚度，每个导电图案105在所述第二方向Y上具有中点106，并且每个导电图案105在所述中点106处具有沿着所述第一方向X的最大宽度。
例如，每个导电图案105可以具有中心对称的形状，所述中心对称的形状在对称中心(即，在所述第二方向Y上的中点106)处具有沿着所述第一方向X的最大宽度。
两个相邻的导电图案105之间的距离可以在1～200微米的范围内。 仿真结果表明，在两个方向上对导电图案进行图案化设计之后，凹陷部区域的温度均匀性得到了显著的改善。
可选地，在一些实施例中，如图1、图3和图4所示，每个导电图案105在该导电图案的第一端和第二端处具有沿着所述第一方向X的最小宽度。
如图1、图3和图4所示，每个导电图案105在该导电图案的第一端和第二端处具有沿着所述第一方向X的最小宽度。
可选地，在一些实施例中，如图1和图3所示，每个导电图案105具有沿着所述第二方向Y连续地变化的宽度。如图3所示，每个导电图案105具有直线形的侧边。如图1所示，每个导电图案105具有曲线形的侧边。
可选地，在一些实施例中，如图4所示，每个导电图案105具有沿着所述第二方向Y非连续地变化的宽度。
可选地，在一些实施例中，如图1、图3和图4所示，每个导电图案105具有轴对称的形状，所述轴对称形状的对称轴平行于所述第二方向Y。类似地，每个导电图案105还可以具有中心对称的形状。
可选地，在一些实施例中，如图2C所示，每个导电图案105在该导电图案105的第一端和第二端处具有最小厚度(如图2C中的虚线圆圈所指示)。
例如，每个导电图案105在X-Y平面上可以具有如图1、图3或图4所示的形状，并且每个导电图案105在该导电图案105的第一端和第二端处具有最小厚度。可替换地，每个导电图案105在X-Y平面上可以具有矩形的形状(即，具有不变的宽度)，并且每个导电图案105在该导电图案105的第一端和第二端处具有最小厚度。由此，可以确保每个导电图案105在该导电图案105的第一端和第二端处具有最大的局部电阻值。
可选地，在一些实施例中，每个导电图案105的第一端和第二端之间的整体电阻值随着该导电图案105和所述凹陷部的中心C之间距离的增大而减小。
在一些实施例中，每个导电图案的第一端和第二端之间的整体电阻值随着该导电图案和所述凹陷部的中心之间距离的增大而减小。也就是说，相比于位于所述凹陷部中心的导电图案，位于所述凹陷部边 缘的导电图案具有更小的整体电阻值。根据电阻发热公式P＝U 2/R，因此远离中心C的导电图案105的发热功率将大于靠近中心C的导电图案105的发热功率。根据本公开实施例提供的微流控基板，利用对导电层的电阻的进一步设计，改善了加热的均匀性，减少了导电层的低温边缘面积。由此，可以有效地减小微流控芯片的实际尺寸，增加单位面积上的反应腔室数量。
可选地，在一些实施例中，如图1和图2B所示，所述导电层102具有均匀的厚度，每个导电图案105在所述第一方向X上的宽度随着该导电图案105和所述凹陷部104的中心C之间距离的增大而增大。
如图1和图2B所示，多个导电图案105可以具有相同的厚度，并且远离中心C的导电图案105具有更大的宽度。由此，可以以简单的设计方式获得具有希望的电阻值的导电图案。
可选地，在一些实施例中，如图1、图3和图4所示，所述多个导电图案105在所述第二方向Y上的长度是相同的。
利用上述布置，多个导电图案在所述第一衬底上的投影对应于矩形的反应腔室。由此，可以在矩形的反应腔室的面积上提供均匀的加热。
可选地，在一些实施例中，如图1、图3和图4所示，所述多个导电图案105构成并联电路，并且每个导电图案105的电流通路沿着所述第二方向Y。
在一些实施例中，如图1-4所示，可以使用走线图案107和导体插塞108，使得所述多个导电图案105构成并联电路。所述导体插塞108可以连接至外部电路(未示出)，从而向所述并联电路提供电力。由此，本公开利用简单的并联电路结构在反应腔室的面积上提供均匀的加热。可以使用相同的材料来制作所述走线图案107和所述多个导电图案105。例如，可以在同一构图工艺中将导电层102的膜层图案化为所述走线图案107和所述多个导电图案105。
可选地，在一些实施例中，所述第一衬底101是玻璃衬底。
根据本公开实施例，可以使用玻璃衬底制作微流控基板和微流控芯片。相比于使用硅衬底，简化了制作工艺，降低了工艺难度。
可选地，在一些实施例中，所述导电层102的材料包括氧化铟锡和氧化铟锌之至少之一者。
氧化铟锡和氧化铟锌是光学透明的。因此，采用氧化铟锡和/或氧化铟锌制作所述导电层，避免了对检测产生光学干扰。
可选地，在一些实施例中，如图2A所示，所述凹陷部104的表面是亲水性的。
可以对所述凹陷部104的表面执行亲水化处理，或在所述凹陷部104的表面蒸镀亲水层109，从而将液体限定在所述凹陷部104中。所述亲水层109的材料可以是二氧化硅，本公开的实施例不限于此。此外，还可以在所述限定层103的位于所述凹陷部外侧的表面上布置疏水层110。所述疏水层110的材料可以是树脂或氮化硅，本公开的实施例不限于此。
可选地，在一些实施例中，如图2A所示，所述微流控基板100还包括：位于所述导电层102和所述第一衬底101之间的走线111，以及位于所述走线111和所述导电层102之间的钝化层112，所述钝化层112包括通孔113；所述导电层102经由所述通孔113与所述走线111电连接。
本领域技术人员能够理解，所述导电层102可以经由设置在所述通孔112中的导体插塞108(在图1中示出)与所述走线110电连接。利用上述布置，所述导电层可以连接至外部电路。此外，还可以在所述导电层102和所述限定层103之间布置绝缘层114，避免导电层102发生短路。
可选地，在一些实施例中，所述走线111包括Mo-AlNd-Mo合金层。
根据本公开的实施例，采用例如Mo-AlNd-Mo合金层来制作走线111，降低了走线111的电阻，从而减少走线111上产生的热量。
可选地，在一些实施例中，如图5所示，所述腔室117是反应腔室，所述对置基板115包括进样口119和出样口120。
本公开实施例提供的微流控芯片可用于dPCR，在芯片上集成图案化控温模块，实现高效、精确、均匀控温，有效地缩小了芯片尺寸，增加反应腔室阵列数量，避免检测结果的不准确性。
根据本公开的又一方面，提供了一种微流控芯片的制作方法。如图6所示，所述方法包括：S11提供第一衬底；S12在所述第一衬底上形成导电层并图案化所述导电层；S13在所述导电层背离所述第一衬底 一侧形成限定层，所述限定层限定凹陷部，所述导电层包括对应于所述凹陷部的多个导电图案，所述多个导电图案沿第一方向排列，每个导电图案沿着第二方向延伸并且包括第一端和第二端，所述第一方向垂直于所述第二方向；每个导电图案在该导电图案的第一端和第二端处具有最大的局部电阻值；S14在所述凹陷部周边布置封框胶，所述封框胶限定腔室；以及S15在所述限定层背离所述第一衬底的一侧布置对置基板。
根据本公开实施例提供的微流控基板的制作方法，利用对导电层的电阻进行设计，改善了加热的均匀性，减少了导电层的低温边缘面积。由此，可以有效地减小微流控芯片的实际尺寸，增加单位面积上的反应腔室数量。
下面提供实例，以介绍本公开提供的微流控芯片的制作方法。该微流控芯片500可以包括在前面任一实施例中描述的微流控基板。下面以微流控芯片500包括微流控基板100为例，来简单地描述该方法步骤。
步骤701：提供第一衬底101。第一衬底101可以由任何合适的材料制成，在一个示例中，第一衬底101由玻璃制成。
步骤702：在大约240℃下，在第一衬底101上形成导电膜层。在一个示例中，在第一衬底101上依次沉积厚度为
Figure PCTCN2021080452-appb-000001
的钼(Mo)层、厚度为
Figure PCTCN2021080452-appb-000002
的铝钕(AlNd)层以及厚度为
Figure PCTCN2021080452-appb-000003
的钼(Mo)层以形成导电膜层。对该导电膜层进行图案化，例如曝光、显影、刻蚀等，形成走线111。
步骤703：在大约200℃下，在走线111上沉积第一绝缘膜层112，对该第一绝缘膜层112进行构图，以形成覆盖走线111的第一绝缘层112。在一个示例中，第一绝缘层112为厚度约为
Figure PCTCN2021080452-appb-000004
的SiO 2层。
步骤704：对第一绝缘层112进行构图，以形成贯穿第一绝缘层112的至少一个通孔113，该至少一个通孔113暴露走线111的一部分。在一个示例中，在干刻机中对第一绝缘层112进行刻蚀以形成通孔113。具体的工艺过程描述如下：在压强约为150mtorr、功率约为800w、O 2的体积流量约为400sccm(standard cubic centimeter per minute)的条件下刻蚀10s；在压强约为60mtorr、功率约为800w、CF 4和O 2的气体体积流量比值约为200∶50的条件下刻蚀200s；在压强约为130 mtorr、功率约为800w、O 2和CF 4的气体体积流量比值约为400∶40的条件下刻蚀30s；以及在压强约为60mtorr、功率约为800w、CF 4和O 2的气体体积流量比值约为200∶50的条件下刻蚀160s。
步骤705：在第一绝缘层112远离第一衬底101的一侧沉积一层导电膜层(导电层)，然后对该导电膜层进行曝光、显影、刻蚀、剥离等工序以形成多个导电图案105(即，加热器)。在一个示例中，导电图案105的材料为ITO。
步骤706：导电图案105远离第一衬底101的一侧沉积第二绝缘膜层，对该第二绝缘膜层进行图案化，以形成至少部分地覆盖导电图案105的第二绝缘层114。在一个示例中，第二绝缘层114的材料为SiO 2。在另一个示例中，第二绝缘层114包括依次层叠的厚度约为
Figure PCTCN2021080452-appb-000005
的SiO 2层和厚度约为
Figure PCTCN2021080452-appb-000006
的SiN x层。
步骤707：在第二绝缘层114远离第一衬底101的一侧涂覆限定膜层，对该限定膜层进行图案化，以形成限定有凹陷部104的限定层103。在一个示例中，形成限定层103的工艺过程描述如下：首先在30Kpa压强下，在第二绝缘层114远离第一衬底101的表面以300转/分钟的速度旋涂光学胶，旋涂时间约为10秒，然后在90℃的温度下，对光学胶固化120秒。重复上述过程两次，以得到限定膜层。接着，通过掩模板对限定膜层进行曝光，然后利用显影液对曝光后的限定膜层显影100秒，然后刻蚀。在230℃的温度下，将刻蚀后的限定膜层固化30分钟，最后得到限定凹陷部104的限定层103。限定层103的材料包括光刻胶。在一个示例中，限定层103的凹陷部104为圆柱形凹陷，凹陷部104的底部直径为50微米，深度在40至50微米之间。限定层103可以限定多个凹陷部104，相邻两个凹陷部104的圆心之间的距离为100微米。
步骤708：在200℃下，在限定层103远离第一衬底101的表面上沉积一层绝缘膜层，对该绝缘膜层进行曝光、显影、刻蚀，以形成图案化层。以0.4％的KOH溶液处理该图案化层约15分钟，以对该图案化层进行亲水修饰，从而形成亲水层109。亲水层109覆盖限定层103的远离第一衬底101的表面，并且覆盖凹陷部104的底部和侧壁。在一个示例中，亲水层109为厚度约为
Figure PCTCN2021080452-appb-000007
的SiO 2层。
步骤709：在亲水层109远离第一衬底101的表面上沉积一层绝缘 膜层，对该绝缘膜层进行曝光、显影、刻蚀，以形成第一疏水层110。在一个示例中，形成第一疏水层110的过程如下：在等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)设备中，在温度约为200℃、功率约为600W、压强约为1200mtorr、以及PECVD设备中的等离子体反应增强靶材与待沉积样品之间的距离约为1000mils下，向反应腔室中通入SiH 4(体积流量为110sccm)、NH 3(体积流量为700sccm)以及N 2(体积流量为2260sccm，通入时间为100秒)，以在亲水层108远离第一衬底101的表面上沉积厚度为
Figure PCTCN2021080452-appb-000008
的SiN x膜层，对该SiN x膜层进行曝光、显影、刻蚀，以形成第一疏水层110。
步骤710：对已完成亲水处理和疏水处理的微流控基板100进行封装。
步骤711：提供对置基板115。对置基板115可以由任何合适的材料制成，在一个示例中，对置基板115由玻璃制成。
步骤712：在对置基板115靠近第一衬底101的一面沉积膜层，对该膜层进行处理，以形成第二疏水层118，该第二疏水层118是厚度约为
Figure PCTCN2021080452-appb-000009
的TiO 2层。在一个示例中，该第二疏水层118由SiN x形成。
步骤713：在对置基板115和第二疏水层118上打孔，以形成贯穿对置基板115和第二疏水层118的至少一个进样口119和至少一个出样口120。在一个示例中，至少一个进样口119和至少一个出样口120的直径在0.6毫米至1.2毫米之间。
步骤714：利用封框胶将微流控基板100和对置基板115进行固化封装，并且限定微流控基板100和对置基板115之间的间隔。
需要说明的是，该制造方法还可以包括更多的步骤，这可以根据实际需求而定，本公开的实施例对此不作限制。该制造方法实现的技术效果可以参考上文中关于微流控基板100和微流控芯片500的描述，此处不再赘述。
在本公开的描述中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开而不是要求本公开必须以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施 例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。另外，需要说明的是，本说明书中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此。任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种微流控基板，包括：
    第一衬底；
    位于所述第一衬底上的导电层；以及
    位于所述导电层背离所述第一衬底一侧的限定层，所述限定层限定凹陷部；
    其中，所述导电层包括对应于所述凹陷部的多个导电图案，所述多个导电图案沿第一方向排列，每个导电图案沿着第二方向延伸并且包括第一端和第二端，所述第一方向垂直于所述第二方向；每个导电图案在该导电图案的第一端和第二端处具有最大的局部电阻值。
  2. 如权利要求1所述的微流控基板，其中，所述导电层具有均匀的厚度，每个导电图案在所述第二方向上具有中点，并且每个导电图案在所述中点处具有沿着所述第一方向的最大宽度。
  3. 如权利要求2所述的微流控基板，其中，每个导电图案在该导电图案的第一端和第二端处具有沿着所述第一方向的最小宽度。
  4. 如权利要求2所述的微流控基板，其中，每个导电图案具有沿着所述第二方向连续地变化的宽度。
  5. 如权利要求4所述的微流控基板，其中，每个导电图案具有直线形的侧边。
  6. 如权利要求4所述的微流控基板，其中，每个导电图案具有曲线形的侧边。
  7. 如权利要求2所述的微流控基板，其中，每个导电图案具有沿着所述第二方向非连续地变化的宽度。
  8. 如权利要求1所述的微流控基板，其中，每个导电图案具有轴对称的形状，所述轴对称形状的对称轴平行于所述第二方向。
  9. 如权利要求1所述的微流控基板，其中，每个导电图案在该导电图案的第一端和第二端处具有最小厚度。
  10. 如权利要求1所述的微流控基板，其中，每个导电图案的第一端和第二端之间的整体电阻值随着该导电图案和所述凹陷部的中心之间距离的增大而减小。
  11. 如权利要求1所述的微流控基板，其中，所述导电层具有均匀 的厚度，每个导电图案在所述第一方向上的宽度随着该导电图案和所述凹陷部的中心之间距离的增大而增大。
  12. 如权利要求1-11任一项所述的微流控基板，其中，所述多个导电图案在所述第二方向上的长度是相同的。
  13. 如权利要求1-11任一项所述的微流控基板，其中，所述多个导电图案构成并联电路，并且每个导电图案的电流通路沿着所述第二方向。
  14. 如权利要求1-11任一项所述的微流控基板，其中，所述第一衬底是玻璃衬底。
  15. 如权利要求1-11任一项所述的微流控基板，其中，所述导电层的材料包括氧化铟锡和氧化铟锌之至少之一者。
  16. 如权利要求1-11任一项所述的微流控基板，其中，所述凹陷部的表面是亲水性的。
  17. 如权利要求1-11任一项所述的微流控基板，还包括：位于所述导电层和所述第一衬底之间的走线，以及位于所述走线和所述导电层之间的钝化层，所述钝化层包括通孔；所述导电层经由所述通孔与所述走线电连接。
  18. 如权利要求17所述的微流控基板，其中，所述走线包括Mo-AlNd-Mo合金层。
  19. 一种微流控芯片，包括：
    如权利要求1-18任一项所述的微流控基板；
    位于所述限定层背离所述第一衬底的一侧的对置基板；以及
    位于所述凹陷部周边的封框胶，所述封框胶限定腔室。
  20. 如权利要求19所述的微流控芯片，其中，所述腔室是反应腔室，所述对置基板包括进样口和出样口。
  21. 一种微流控芯片的制作方法，包括：
    提供第一衬底；
    在所述第一衬底上形成导电层并图案化所述导电层；
    在所述导电层背离所述第一衬底一侧形成限定层，所述限定层限定凹陷部，所述导电层包括对应于所述凹陷部的多个导电图案，所述多个导电图案沿第一方向排列，每个导电图案沿着第二方向延伸并且包括第一端和第二端，所述第一方向垂直于所述第二方向；每个导电 图案在该导电图案的第一端和第二端处具有最大的局部电阻值；
    在所述凹陷部周边布置封框胶，所述封框胶限定腔室；以及
    在所述限定层背离所述第一衬底的一侧布置对置基板。
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