WO2022183486A1 - 一种功率半导体模组及制造方法 - Google Patents

一种功率半导体模组及制造方法 Download PDF

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Publication number
WO2022183486A1
WO2022183486A1 PCT/CN2021/079309 CN2021079309W WO2022183486A1 WO 2022183486 A1 WO2022183486 A1 WO 2022183486A1 CN 2021079309 W CN2021079309 W CN 2021079309W WO 2022183486 A1 WO2022183486 A1 WO 2022183486A1
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WIPO (PCT)
Prior art keywords
power semiconductor
conductive
substrate
heat sink
layer
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PCT/CN2021/079309
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English (en)
French (fr)
Inventor
杜若阳
吕镇
Original Assignee
华为数字能源技术有限公司
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Application filed by 华为数字能源技术有限公司 filed Critical 华为数字能源技术有限公司
Priority to EP21928569.9A priority Critical patent/EP4280270A4/en
Priority to CN202180091530.XA priority patent/CN116830248A/zh
Priority to PCT/CN2021/079309 priority patent/WO2022183486A1/zh
Publication of WO2022183486A1 publication Critical patent/WO2022183486A1/zh
Priority to US18/451,912 priority patent/US20230395464A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2089—Modifications to facilitate cooling, ventilating, or heating for power electronics, e.g. for inverters for controlling motor
    • H05K7/20927—Liquid coolant without phase change
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates

Definitions

  • the present application relates to the technical field of power semiconductor modules, and in particular, to a power semiconductor module and a manufacturing method thereof, a motor driver, a powertrain, and a vehicle.
  • Power semiconductor module refers to a semiconductor device that realizes the function of circuit switching, which is usually made of power semiconductor chips through a specific circuit bridge package.
  • power semiconductor chips generally include insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBT), diode (Diode), metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), thyristor, Triode etc.
  • the power semiconductor module is the core device of the motor driver (Motor Control Unit, MCU), and also the most important heating device.
  • MCU Motor Control Unit
  • the heat dissipation capacity of its package plays a decisive role in the performance parameters of the product.
  • the packaging of power semiconductor modules is divided into two structures: single-sided cooling and double-sided cooling.
  • the difference between the two structures is that the heat is mainly transferred from the single surface of the device to the cooling medium in one direction, or the two surfaces of the device are bidirectional. to the cooling medium.
  • the double-sided cooling package has stronger heat dissipation capacity, which helps to give full play to the performance of power semiconductor chips, improve product power density, and reduce product costs.
  • the power semiconductor module of double-sided cooling package usually places the power semiconductor package between two heat sinks, and sets a thermal interface material between the power semiconductor package and the heat sink (thermally conductive silicone grease, graphite film, silicon gels, phase change materials, etc.), the two heat sinks are pressed together by mechanical structures (such as screws, bolts, etc.) to clamp the power semiconductor package and the thermally conductive interface material.
  • a thermal interface material between the power semiconductor package and the heat sink
  • the two heat sinks are pressed together by mechanical structures (such as screws, bolts, etc.) to clamp the power semiconductor package and the thermally conductive interface material.
  • the present application provides a power semiconductor module and a manufacturing method, a motor driver, a powertrain, and a vehicle.
  • a solid heat conduction layer with a fixed function and not easy to fall off is realized between the heat sink and the power semiconductor package, so that all parts of the power semiconductor module can be uniformly stressed, and the assembly process of the power semiconductor module in the motor driver is reduced. risk of stress damage.
  • it can realize the integrated processing of the power semiconductor package and the radiator before the assembly of the motor driver, as well as the helium gas inspection of the power semiconductor module, which avoids the leakage of the radiator during the test of the motor driver. risk of scrapping the machine.
  • an embodiment of the present application provides a power semiconductor module, including at least one heat sink and at least one power semiconductor package;
  • thermally conductive layer the thermally conductive layer is located between the heat sink and the power semiconductor package, the thermally conductive layer is a thermally conductive material with metal bonding wires on the surface; or, the thermally conductive layer is curable silicone grease and the power semiconductor package and the heat sink are both combined with the heat conduction layer to form the power semiconductor module.
  • the thermally conductive layer is a solid thermally conductive layer formed of curable silicone grease, so that the metal bonding wires of the thermally conductive layer are connected to the heat sink and the power Bonding between the semiconductor packages is realized under heating and pressure, so that a bonding force with molecular bonding force is formed between the heat sink, the power semiconductor package and the thermal conductive layer, or the thermal conductive layer is curable
  • the solid heat conduction layer formed by silicone grease, the curable silicone grease forms a solidified heat conduction layer that is embedded with each other when the heat sink and the power semiconductor package are cured.
  • the heat conduction layer between the power semiconductor package and the heat sink has It has a fixed function and is not easy to fall off, which can make the force between the heat sink and the power semiconductor package uniform, and reduce the risk of damage to the power semiconductor module due to stress during the assembly process of the motor driver.
  • the integrated processing of the power semiconductor package and the heat sink can be realized, as well as the helium gas inspection of the power semiconductor module, so that the defective products with air leakage of the heat sink can be screened out in advance, and the qualified power semiconductor modules can be directly applied.
  • the automation level and processing speed of the complete assembly of the motor driver are improved, the yield rate of the secondary processing of the complete machine is improved, and the leakage of the radiator caused by the leakage of the radiator during the helium gas test of the complete machine is avoided. Risk of scrapping the entire motor drive.
  • a bonding force with molecular bonding force or chimeric force is formed between the thermally conductive layer and the heat sink, and between the thermally conductive layer and the power semiconductor package.
  • Molecular bonding force or chimeric force is a strong mutual bonding force, and the molecular bonding force or chimeric force formed between the thermal conductive layer, the heat sink, and the power semiconductor package can firmly fix the heat sink and the power semiconductor package.
  • the heat-conducting layer includes: a metal heat-conducting sheet and the metal bonding wire provided on the surface of the metal heat-conducting sheet.
  • the metal thermal conductive sheet is copper foil, aluminum foil, silver foil or gold foil
  • the metal bonding wire is nano-copper wire, nano-aluminum wire, nano-silver wire or nano-gold Wire.
  • the metal bonding wire will form a molecular bonding force between the metal and the heat sink and the copper layer or aluminum layer on the surface of the power semiconductor package under heating and pressure, which can firmly fix the heat sink and the power semiconductor package.
  • nano-copper wire, nano-aluminum wire, nano-silver wire, nano-gold wire, copper foil, aluminum foil, silver foil or gold foil all have good thermal conductivity, which can greatly improve the heat dissipation capability of power semiconductor modules.
  • the thermally conductive layer further includes: thermally conductive glue, the thermally conductive glue is distributed in the gaps between the adjacent metal bonding wires.
  • the thermally conductive adhesive is conducive to the close adhesion of the thermally conductive layer to the heat sink and the power semiconductor package.
  • the thermal conductive adhesive Under the action, a good fixing effect between the heat sink and the power semiconductor package and the thermal conduction layer can be achieved under the process conditions of lower temperature and lower pressure.
  • the temperature and pressure during heating and pressure treatment with the thermally conductive layer help to improve the production yield of the process.
  • the number of the heat sinks is two, and the two heat sinks are a first heat sink and a second heat sink opposite to each other, and the power semiconductor package is disposed on the
  • the thermal conductive layer is provided between the first heat sink and the second heat sink, and between the power semiconductor package and the first heat sink and the second heat sink.
  • the power semiconductor package is arranged between the first heat sink and the second heat sink to form a power semiconductor module with a double-sided cooling structure, and heat can be bidirectionally transferred from the two surfaces of the power semiconductor package to the first heat sink and the second heat sink device.
  • the double-sided cooling structure has a stronger heat dissipation capacity under the same process conditions, which helps to give full play to the performance of the power semiconductor chip, improve the power density of the product, and reduce the product cost.
  • one end of the first heat sink and the second heat sink are connected by a connecting plate, and the other ends of the first heat sink and the second heat sink are connected by Fastener connection.
  • One end of the first radiator and the second radiator are connected by a connecting plate, and the other end is connected by a fastener.
  • both ends of the first radiator and the second radiator are connected by connecting pipes.
  • the heat dissipation structure formed by connecting the two ends of the first radiator and the second radiator by connecting pipes is suitable for the heat dissipation method of parallel heat dissipation water channels.
  • the first radiator and the second radiator are both provided with heat dissipation water channels, and the heat dissipation water channels in the first radiator and the first heat sink
  • the radiating water channels in the two radiators are connected in series through the connecting plate, and the other ends of the first radiator and the second radiator are respectively provided with a water inlet and a water outlet communicating with the radiating water channels.
  • the heat dissipation water channel in the first radiator is connected with the heat dissipation water channel in the second radiator through the heat dissipation water channel in the connecting plate to form a heat dissipation structure of series heat dissipation water channels.
  • the water inlet and the water outlet are located on the same side of the radiator, and the cooling liquid enters the cooling water channel inside the first radiator from the water inlet to absorb the heat of the first radiator; and then flows into the cooling water channel of the second radiator through the cooling water channel in the connecting plate.
  • the cooling water channel absorbs the heat of the second radiator, and finally flows out from the water outlet to take all the heat away.
  • the first radiator and the second radiator are provided with cooling water channels, and the cooling water channels in the first radiator and the cooling water channels in the second radiator pass through all the cooling channels.
  • the connecting pipes are connected in parallel, one end of the first radiator is provided with a water inlet, and one end of the second radiator is provided with a water outlet on the end away from the water inlet.
  • the radiating water channel inside the first radiator and the radiating water channel inside the second radiator are communicated through a connecting pipe between the first radiator and the second radiator, and the connecting pipe is located at both ends of the two radiators to form a parallel cooling water channel heat dissipation structure.
  • the water inlet and the water outlet are located on both sides of the radiator, respectively.
  • the cooling liquid enters the cooling water channel inside the first radiator from the water inlet.
  • the connecting pipe on the water inlet side enters the water outlet and flows out to take away the heat; another part of the coolant enters the cooling water channel inside the second radiator through the connecting pipe adjacent to the water inlet side and flows along the cooling water channel to absorb the second radiator.
  • the heat enters into the water outlet and flows out to take away the heat.
  • each of the power semiconductor packages includes at least a first substrate, a second substrate, and at least one chip, and the chip is fixed on the first substrate and the second substrate and the at least one chip is electrically connected to the first substrate and the second substrate; a circuit is formed between the chip, the first substrate and the second substrate.
  • the heat conducting layer is disposed between the heat sink and at least one of the first substrate and the second substrate, and is used for transferring the heat generated by the power semiconductor package to the heat sink.
  • the chip includes an IGBT chip and a diode chip.
  • the chip includes a silicon (Si) metal oxide semiconductor field effect transistor (MOSFET) or a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET silicon metal oxide semiconductor field effect transistor
  • SiC silicon carbide metal oxide semiconductor field effect transistor
  • the power semiconductor package further includes: at least one conductive pad, where the conductive pad functions to conduct electricity and support the first substrate and the second substrate.
  • the conductive pad is located between the chip and the first substrate; and two ends of the conductive pad are respectively connected with the chip and the first substrate through a conductive connection layer;
  • the first substrate has a first conductive region and a second conductive region that are insulated from each other and arranged side by side;
  • the second substrate has a third conductive region and a fourth conductive region that are insulated from each other and arranged side by side, the first conductive region is opposite to the third conductive region, and the second conductive region is opposite to the fourth conductive region
  • the conductive area is opposite
  • a portion of the chip is located between the first conductive region and the third conductive region, and a portion of the chip is located between the second conductive region and the fourth conductive region;
  • first conductive region is in conduction with the fourth conductive region, or the second conductive region is in conduction with the third conductive region.
  • the first conductive area and the third conductive area are connected through the chip
  • the second conductive area and the fourth conductive area are connected through the chip
  • the first conductive area and the fourth conductive area are connected, so that the third conductive area,
  • the first conductive region, the fourth conductive region, and the second conductive region are conductive.
  • the second conductive region is electrically connected to the third conductive region, so that the first conductive region, the third conductive region, the second conductive region, and the fourth conductive region form a circuit.
  • both the first substrate and the second substrate are conductive plates
  • the first substrate includes: a first conductive plate and a second conductive plate that are insulated from each other and distributed side by side, the first conductive plate has the first conductive region, and the second conductive plate has the the second conductive region;
  • the second substrate includes a third conductive plate and a fourth conductive plate that are insulated from each other and distributed side by side, the third conductive plate has the third conductive region, and the fourth conductive plate has the first conductive plate.
  • the heat sink and the conductive plate are insulated to avoid conduction between the conductive plate and the heat sink.
  • the first substrate includes a first conductive layer and a first insulating plate, the first conductive layer is located on a side of the first insulating plate facing the chip ;
  • the second substrate includes: a second conductive layer and a second insulating plate, the second conductive layer is located on the side of the second insulating plate facing the chip;
  • first conductive layer includes at least the first conductive region and the second conductive region
  • second conductive layer includes at least the third conductive region and the fourth conductive region.
  • the first insulating plate and the second insulating plate are respectively used to prevent the first conductive layer and the second conductive layer from conducting with the heat sink.
  • the first substrate further includes a first copper layer, the first copper layer plays a role of protection and heat conduction, and the first copper layer is located on the surface of the first insulating plate On the side facing the thermally conductive layer, the first copper layer is used to protect the first insulating plate, prevent the first insulating plate from being broken, and also has a thermal conductivity function;
  • the second substrate further includes a second copper layer, the second copper layer plays the role of protection and heat conduction, the second copper layer is located on the side of the second insulating plate facing the heat conduction layer, and the second copper layer is used for Protect the second insulating plate, prevent the second insulating plate from breaking, and also have the function of heat conduction;
  • the thermally conductive layer is provided between the heat sink and at least one of the first copper layer and the second copper layer.
  • the power semiconductor package further includes a connection terminal, one end of the connection terminal has a first terminal and a second terminal, and one of the first terminal and the second terminal is One of the first and second terminals is electrically connected to the first conductive area, and the other of the first and second terminals is electrically connected to the fourth conductive area, so that the first conductive area is connected to the fourth conductive area.
  • Four conductive regions are turned on;
  • one of the first terminal and the second terminal is electrically connected to the second conductive area, and the other of the first terminal and the second terminal is electrically connected to the third conductive area connecting, so that the second conductive region and the third conductive region are conductive;
  • both the first terminal and the second terminal are electrically connected to the third conductive region or to the fourth conductive region.
  • the power semiconductor package further includes: a first electrode terminal and a second electrode terminal, and one of the first electrode terminal and the second electrode terminal is a positive electrode a terminal, the other of the first electrode terminal and the second electrode terminal is a negative terminal;
  • one of the first electrode terminal and the second electrode terminal is electrically connected to the first conductive area, and the other of the first electrode terminal and the second electrode terminal is electrically connected to the fourth conductive area;
  • one of the first electrode terminal and the second electrode terminal is electrically connected to the second conductive area, and the other of the first electrode terminal and the second electrode terminal is electrically connected to the third conductive area.
  • the power semiconductor package further includes: a first conductive column and a second conductive column, the first conductive column and the second conductive column are respectively located in the first conductive column between the substrate and the second substrate;
  • the second substrate further has a fifth conductive region, and the fifth conductive region is insulated from the third conductive region and the fourth conductive region;
  • Both the first terminal and the second terminal of the connection terminal are electrically connected to the fourth conductive area, and both ends of the first conductive column are respectively connected to the first conductive area and the fourth conductive area the regions are electrically connected, and two ends of the second conductive column are respectively electrically connected to the second conductive region and the fifth conductive region;
  • One of the first electrode terminal and the second electrode terminal is electrically connected to the third conductive area, and the other of the first electrode terminal and the second electrode terminal is electrically connected to the fifth conductive area.
  • the third conductive area, the first conductive area, the fourth conductive area, the second conductive area, and the fifth conductive area form a circuit through the first conductive column and the second conductive column, and form a circuit with the first electrode terminal and the second electrode terminal conductive loop.
  • the power semiconductor package further includes: an encapsulation layer, the first substrate, the second substrate, and the at least one chip are located in the encapsulation layer, through the encapsulation layer
  • the layers fix and seal components such as the first substrate, the second substrate, and the chip to form a power semiconductor package. and at least a partial area of the encapsulation layer opposite to at least one of the first substrate and the second substrate is an exposed area, and at least one of the first substrate and the second substrate faces the heat conduction One side of the layer is exposed at the exposed area. In this way, the blocking of the encapsulation layer is eliminated, and the contact between the substrate and the thermal conductive layer is more closely, which is beneficial to the transfer of heat.
  • the power semiconductor package further includes: a signal terminal, one end of the signal terminal is located in the packaging layer and is electrically connected to the chip, and the other end of the signal terminal is located in the package layer. One end is located outside the encapsulation layer.
  • the power semiconductor package further includes: a bonding wire, one end of the bonding wire is connected to the chip by bonding, and the other end of the bonding wire is connected to the signal The terminal is bonded and connected, so that the chip and the signal terminal are connected;
  • one end of the second substrate is provided with a pad, the other end of the bonding wire is bonded and connected to the pad, and one end of the signal terminal is electrically connected to the pad, so that the chip and the signal terminal are electrically connected. Pass;
  • one end of the second substrate is provided with a pad, the chip is electrically connected to the pad, and one end of the signal terminal is electrically connected to the pad, so that the chip and the signal terminal are electrically connected.
  • an embodiment of the present application provides a motor driver, which includes a capacitor and at least one power semiconductor module described above, wherein electrode terminals of the power semiconductor module are electrically connected to the capacitor.
  • an embodiment of the present application provides a powertrain, including a motor and the above-mentioned motor driver connected to the motor.
  • an embodiment of the present application provides a vehicle, including a wheel, a motor, and the above-mentioned motor driver connected to the motor, and the motor is connected to the wheel through a transmission assembly.
  • an embodiment of the present application provides a method for manufacturing a power semiconductor module, including:
  • An interface material is respectively provided on the top surface and/or the bottom surface of the power semiconductor package, and the interface material is a thermally conductive material with metal bonding wires on the surface, or the interface material is curable silicone grease;
  • the power semiconductor module is formed by pressing the power semiconductor package provided with the interface material and the heat sink for a predetermined time at a predetermined temperature and a predetermined pressure.
  • the power semiconductor package provided with the interface material and the heat sink are subjected to a first preset pressure pretreatment for a first preset time under the conditions of a first preset pressure and a first preset temperature;
  • a second preset time curing process is performed between the pretreated power semiconductor package and the heat sink under the conditions of a second preset pressure and a second preset temperature, so that the curable silicone grease forms a solid thermal conductivity Floor.
  • Curable silicone grease is a viscous liquid material. After pretreatment and curing, a viscous and stable solid heat conduction layer can be formed. The heat sink is firmly packaged and fixed with the power semiconductor to form a power semiconductor module. Cured grease will not liquefy.
  • the method further includes: :
  • Metal plating is formed on the side of the heat sink facing the power semiconductor package, or deoxidation treatment is performed on the side of the heat sink facing the power semiconductor package.
  • the deoxidation treatment exposes the metal element on the top and bottom surfaces of the power semiconductor package, and the metal plating layer is formed on the side of the heat sink facing the power semiconductor package to prevent the generation of the oxide layer, so that the metal bonding wires are respectively connected with the heat sink and the surface of the power semiconductor package.
  • the metal material is bonded under heating and pressure, so that the interface material forms a bonding force with molecular bonding force with the heat sink and the surface of the power semiconductor package respectively.
  • the same side can also be deoxidized to expose the metal element, which can also ensure that the metal material can form a molecular bond between the heat sink and the power semiconductor package. Solid state thermally conductive layer of resultant or interlocking force.
  • FIG. 1 is a schematic diagram of a power semiconductor module provided by an embodiment of the present application.
  • FIG. 2 is a schematic exploded schematic diagram of a partial cross-section of a power semiconductor module provided by an embodiment of the present application
  • 3A is a schematic cross-sectional structural diagram of a thermal conductive layer, a power semiconductor package, a first heat sink, and a second heat sink in a power semiconductor module according to an embodiment of the present application;
  • 3B is a schematic cross-sectional structural diagram of a thermal conductive layer, a power semiconductor package, a first heat sink, and a second heat sink in a power semiconductor module according to an embodiment of the present application;
  • 3C is a schematic cross-sectional view of the power semiconductor module shown in FIG. 2 after being assembled;
  • FIG. 4 is a schematic structural diagram of a power semiconductor package provided by an embodiment of the present application.
  • 5A is a schematic structural diagram of a power semiconductor module according to an embodiment of the present application.
  • 5B is a schematic cross-sectional view along the A-A direction in FIG. 5A;
  • FIG. 6 is a schematic exploded schematic view of a partial cross-section of a power semiconductor module provided by an embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional view of the power semiconductor module shown in FIG. 6 after being assembled
  • FIG. 8 is a schematic exploded schematic diagram of a partial cross-section of a power semiconductor module provided by an embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional view of the power semiconductor module shown in FIG. 8 after being assembled
  • FIG. 10 is a schematic exploded schematic view of a partial cross-section of a power semiconductor module provided by an embodiment of the present application.
  • FIG. 11 is a schematic cross-sectional view of the power semiconductor module shown in FIG. 10 after being assembled.
  • FIG. 12 is a schematic flowchart of a method for manufacturing a power semiconductor package according to an embodiment of the present application.
  • a power semiconductor module of a double-sided cooling package is usually placed between two heat sinks, and the two heat sinks are pressed and connected by a mechanical structure.
  • the disadvantage of pressing the heat sink through the mechanical structure is that it is difficult to ensure that the force is evenly applied to each position of the power semiconductor module.
  • the tightening force near the bolt position is generally greater than that far from the bolt position.
  • Tightening force the tightening force exerted by bolts at different positions is difficult to ensure equal, and it is difficult to ensure that the fixed surface of the heat sink and power semiconductor package is completely flat, and the coating thickness of the thermal interface material itself may also vary. Therefore, Stress is easily generated during the fixing process of the heat sink and the power semiconductor package, and the power semiconductor module is easily damaged during the assembly process of the motor driver.
  • such power semiconductor modules are usually assembled on-site at the same time as the motor driver is assembled, which is not only difficult to assemble, low processing efficiency, and It is impossible to pre-inspect the power semiconductor module, and it is difficult to judge whether the power semiconductor module is damaged during the assembly process. The machine will be at risk of being scrapped.
  • embodiments of the present application provide a power semiconductor module, a motor driver, a powertrain, and a method for manufacturing the power semiconductor module.
  • the power semiconductor module provided by the present application adopts a thermally conductive material with metal bonding wires on the surface or a curable silicone grease, and forms a solid thermal conduction layer with a fixed function and is not easy to fall off between the heat sink and the power semiconductor package.
  • the layer fixes the power semiconductor package and the heat sink, so that the force of each part of the power semiconductor module is uniform, and the risk of stress damage caused by the power semiconductor module during the assembly process of the motor driver is reduced.
  • the power semiconductor module that has passed the inspection can be directly used for the assembly of the motor driver. , to avoid the on-site assembly work of the power semiconductor module during the assembly of the motor driver, and reduce the risk of the motor driver being scrapped due to the leakage of the radiator when the motor driver is tested. Difficulty, improving the automation level and processing speed of the motor driver assembly.
  • the specific structure of the power semiconductor module is described below by taking different embodiments as examples.
  • the power semiconductor module may include at least one heat sink 10 .
  • FIG. 1 includes two heat sinks, which are a first heat sink 11 and a second heat sink, respectively.
  • Two heat sinks 12 as shown in FIG. 1 , the power semiconductor module further includes: at least one power semiconductor package 20 , for example, in FIG.
  • the X direction in FIG. 1 is arranged at intervals between the first heat sink 11 and the second heat sink 12, and each terminal of each power semiconductor package 20 extends from the first heat sink 11 and the first heat sink 11 to the second heat sink along the Y direction and the ⁇ Y direction in FIG. 1 .
  • the space between the two radiators 12 extends outward.
  • the number of power semiconductor packages 20 includes, but is not limited to, three, and may also be two or more.
  • the power semiconductor module further includes: a thermal conductive layer 30 (see FIG. 2 ) located between the heat sink 10 and the power semiconductor package 20 .
  • a thermal conductive layer 30 located between the heat sink 10 and the power semiconductor package 20 .
  • the thermal conductive layer 30 in the Z direction are the second heat sink 12 , the thermal conductive layer 30 , the power semiconductor package 20 , the thermal conductive layer 30 and the first heat sink 11 (refer to FIG. 3C ).
  • FIG. 2 is a partial exploded view of the power semiconductor module shown in FIG. 1 cut along the Y direction in FIG. 1 .
  • the thermally conductive layer 30 is a thermally conductive material having metal bonding wires 32 (see FIG. 3B ) on the surface, or the thermally conductive layer 30 is a solid thermally conductive layer formed of curable silicone grease, the power semiconductor package 20 and the heat sink 10 A bonding force with molecular bonding force or a fitting force is formed with the thermal conductive layer 30 respectively, so that the power semiconductor package 20 and the heat sink 10 constitute a power semiconductor module.
  • the thermally conductive layer 30 is a thermally conductive material with metal bonding wires 33 on the surface; or, the thermally conductive layer is a solid thermally conductive layer formed of curable silicone grease, so that the metal bonding wires 32 of the thermally conductive layer 30 and the heat sink 10 and Bonding between the power semiconductor packages 20 is realized under heating and pressure, so that a bonding force with molecular bonding force is formed between the heat sink, the power semiconductor package and the heat conducting layer, or the heat conducting layer
  • the layer is a solid thermal conduction layer formed of curable silicone grease. When the curable silicone grease is cured between the heat sink and the power semiconductor package, a solid thermal conduction layer that is embedded with each other is formed.
  • the solid thermal conductive layer has a fixed function and is not easy to fall off, which can make the force between the heat sink 10 and the power semiconductor package 20 uniform, and reduce the risk of damage to the power semiconductor module due to stress during the assembly process of the motor driver.
  • the integrated processing of the power semiconductor package 20 and the heat sink 10 and the helium gas inspection of the power semiconductor module can be realized, and the qualified power semiconductor module can be directly applied to the assembly of the motor driver, avoiding the need for the power semiconductor module.
  • the on-site assembly work of the group during the assembly of the motor driver has improved the automation level and processing speed of the motor driver assembly, and reduced the risk of the motor driver being scrapped due to water leakage from the radiator during the whole machine test.
  • the thermally conductive layer 30 is described by taking a thermally conductive material having metal bonding wires 32 (see FIG. 3A ) on the surface as an example.
  • the thermally conductive layer 30 includes: a metal thermally conductive sheet 31 and a device Metal bonding wires 32 on the surface of the metal thermally conductive sheet 31 .
  • the upper and lower surfaces of the metal heat-conducting sheet 31 are provided with metal bonding wires 32 , wherein the metal bonding wires 32 are arranged vertically on the metal heat-conducting sheet 31 , and the adjacent metal bonding wires 32 are arranged vertically. There may be gaps in between.
  • the thermal conductive layer 30 when the thermal conductive layer 30 is located between the heat sink 10 and the power semiconductor package 20, in order to achieve the fixing effect of the thermal conductive layer on the heat sink 10 and the power semiconductor package 20, respectively, the heat sink 10 and the power semiconductor package 20 need to be placed between the heat sink 10 and the power semiconductor package 20.
  • the metal bonding wire 32 Under heating and pressing conditions, the metal bonding wire 32 will be compressed, and the bonding connection with the copper layer or the aluminum layer on the surface of the heat sink 10 and the power semiconductor package 20 will be realized, so that the The metal in the metal bonding wire 32 diffuses into the copper layer or the aluminum layer on the surface of the heat sink 10 and the power semiconductor package 20 , so that a bonding force with molecular bonding force is formed between the thermal conductive layer 30 and the heat sink 10 and the power semiconductor package 20 , so that the heat sink 10 and the power semiconductor package 20 are firmly connected under the action of the thermal conductive layer 30 .
  • the metal heat-conducting sheet 31 may be copper foil, aluminum foil, silver foil or gold foil.
  • the metal heat-conducting sheet 31 may also be other metal foils
  • the metal bonding wire 32 may be nano-copper wire, nano-aluminum wire , silver nanowires or gold nanowires.
  • the metal bonding wire 32 can also be other nano metal wires.
  • the metal thermal conductive sheet 31 is a copper foil and the metal bonding wire 32 is a nano copper wire as an example for description.
  • the heat-conducting layer composed of copper foil and nano-copper wire is also called nano-copper Velcro.
  • the copper in the nano-copper wire diffuses to the surface of the heat sink 10 and the power semiconductor package 20 , and forms a strong molecular bonding force with the heat sink 10 and the copper layer or the aluminum layer on the surface of the power semiconductor package 20 .
  • the heat sink 10 and the power semiconductor package 20 can be firmly fixed.
  • both copper foil and nano-copper wire have good thermal conductivity, which can greatly improve the heat dissipation capability of power semiconductor modules.
  • the nano copper wire growth process may be used to grow the metal bonding wire 32 on the metal thermal conductive sheet 31.
  • the metal bonding wire 32 is a nano copper wire
  • the metal heat-conducting sheet 31 is a copper foil
  • the nano copper wire can be grown on the upper and lower surfaces of the copper foil by chemical vapor deposition method.
  • the thermally conductive layer 30 is a thermally conductive material with metal bonding wires 32 (see FIG. 3A ) on the surface
  • metal bonding wire 32 is bonded to the copper layer or the aluminum layer on the surface of the heat sink 10 and the power semiconductor package 20 , so as to achieve a good fixing effect between the heat sink 10 , the power semiconductor package 20 and the heat conduction layer 30 .
  • the thermally conductive layer 30 further includes: thermally conductive adhesive 33 , and the thermally conductive adhesive 33 is distributed in the gaps between adjacent metal bonding wires 32 .
  • the thermally conductive adhesive 33 facilitates the close adhesion of the thermally conductive layer 33 to the heat sink 10 (eg, the first heat sink 11 and the second heat sink 12 ) and the power semiconductor package 20 .
  • the heat sink 10 and the power semiconductor package 20 and the thermal conductive layer 30 When the thermal conductive layer 30 is fixed under heating and pressurizing conditions, under the action of the thermal conductive adhesive 33, the heat sink 10 and the power semiconductor package 20 and the thermal conductive layer can be realized under the process conditions of lower temperature and lower pressure. Therefore, by providing the thermally conductive adhesive, the temperature and pressure of the heat sink 10 and the power semiconductor package 20 and the thermal conductive layer 30 during heating and pressure treatment are reduced, and the process yield is improved.
  • the thermally conductive adhesive 33 may be in a gel or liquid state, so when the thermally conductive adhesive 33 is distributed between the metal bonding wires 32, the thermally conductive adhesive 33 may be in contact with the metal thermally conductive sheet 31, or, as shown in FIG. 3B It is shown that when the heat or pressure treatment is not performed, the thermally conductive adhesive 33 is distributed between the adjacent metal bonding wires 32, but is not in contact with the metal thermally conductive sheet 21, while the thermally conductive layer 30, the heat sink 10 and the power semiconductor package 20 are heated during the heating process. Or under the action of pressure, finally, the thermally conductive adhesive 30 is in close contact with the metal thermally conductive sheet 21, so as to realize the rapid conduction of heat.
  • the type of the thermally conductive adhesive 33 is not limited, as long as it has a thermal conductivity and can be bonded to the heat sink 10 and the power semiconductor package 20 for fixing.
  • the number of heat sinks 10 may be two, and the two heat sinks 10 are respectively the first heat sink 11 and the second heat sink 12 opposite to each other, and the power semiconductor package 20 is disposed on the first heat sink 10 .
  • a thermally conductive layer 30 is provided between the side of the power semiconductor package 20 facing the first heat sink 11 and the first heat sink 11, and the power semiconductor package 20 faces the second heat sink
  • a thermally conductive layer 30 is also provided between one side of the 12 and the second heat sink 12 .
  • the power semiconductor package 20 is arranged between the first heat sink 11 and the second heat sink 12 to form a power semiconductor module with a double-sided cooling structure, and heat can be bidirectionally transferred from the upper and lower surfaces of the power semiconductor package 20 to the first heat sink 11 and the second radiator 12.
  • the double-sided cooling structure has a stronger heat dissipation capacity under the same process conditions, which helps to give full play to the performance of the power semiconductor chip, improve the power density of the product, and reduce the product cost.
  • a heat sink 10 may also be provided to cool one side of the power semiconductor package 20 .
  • one end of the first heat sink 11 and the second heat sink 12 are connected by a connecting plate 13 , and the other ends of the first heat sink 11 and the second heat sink 12 are connected by a fastener .
  • the other ends of the first heat sink 11 and the second heat sink 12 may also be connected without fasteners.
  • the first radiator 11 , the second radiator 12 and the connecting plate 13 are all provided with communicating cooling water channels 14 .
  • the other ends of the two radiators 12 are respectively provided with a water inlet 111 and a water outlet 121 communicating with the cooling water channel 14 .
  • the cooling water channel 14 inside the first radiator 11 communicates with the cooling water channel 14 inside the second radiator 12 through the cooling water channel (not shown) inside the connecting plate 13 .
  • the water channel 14 constitutes a series heat dissipation water channel.
  • the water inlet 111 and the water outlet 121 may be located on the same side of the radiator 10, and the cooling liquid enters the cooling water channel 14 inside the first radiator 11 through the water inlet 111 to absorb the heat of the first radiator 11;
  • the heat dissipation water channel in the connecting plate 13 flows into the heat dissipation water channel 14 of the second radiator 12, absorbs the heat of the second radiator 12, and finally flows out through the water outlet 121 to take away the heat.
  • the water inlet 111 is provided on the first radiator 11, and the water outlet 121 is provided on the second radiator 12.
  • the water inlet 111 may also be provided on the first radiator 12.
  • the water outlet 121 is provided on the first radiator 11 .
  • the arrangement positions of the water inlet 111 and the water outlet 121 include but are not limited to the positions shown in FIG. 1 .
  • each power semiconductor package 20 includes at least a first substrate 21 , a second substrate 22 and at least one chip.
  • the chip may include an IGBT chip 23 and a diode chip 24, or, in some examples, the chip may also be a silicon (Si) metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) or a carbide Silicon (SiC) Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
  • a circuit is formed between the IGBT chip 23 and the first substrate 21 and the second substrate 22 , a circuit is formed between the diode chip 24 and the first substrate 21 and the second substrate 22 , and a parallel circuit is formed between the IGBT chip 23 and the diode chip 24 .
  • a thermally conductive layer 30 is provided between the heat sink 10 and at least one of the first substrate 21 and the second substrate 22 , and the thermal conductive layer 30 is used to transfer the heat generated by the power semiconductor package 20 to the heat sink 10 .
  • the setting of the chip may refer to the setting manner of the IGBT chip 23 and the diode chip 24 .
  • the following description mainly takes the chip including the IGBT chip 23 and the diode chip 24 as an example for description.
  • the power semiconductor package 20 further includes at least one conductive pad, and the conductive pad is used to electrically connect the chip with the first substrate 21 , for example, see FIG. 2 .
  • the power semiconductor package 20 includes at least one first conductive pad 25 and at least one second conductive pad 26 , and the conductive pads play the role of conducting electricity and supporting the first substrate 21 and the second substrate 22 .
  • the first conductive pad 25 is located between the IGBT chip 23 and the first substrate 21, and two sides of the first conductive pad 25 are respectively connected to the IGBT chip 23 and the first substrate 21 through the conductive connection layer 212;
  • the second conductive pad 26 is located between the diode chip 24 and the first substrate 21 , and two sides of the second conductive pad 26 are respectively connected to the diode chip 24 and the first substrate 21 through the conductive connection layer 212 .
  • the conductive connection layer 212 is a solder layer or a sintered layer with conductive properties.
  • the first substrate 21 has a first conductive region 2106 and a second conductive region 2107 that are insulated from each other and arranged side by side; the second substrate 22 has a mutually insulated and The third conductive region 2206 and the fourth conductive region 2207 are arranged side by side, the first conductive region 2106 is opposite to the third conductive region 2206 , and the second conductive region 2107 is opposite to the fourth conductive region 2207 .
  • a part of the IGBT chip 23 and the diode chip 24 is located between the first conductive region 2106 and the third conductive region 2206 , and another part of the IGBT chip 23 and the diode chip 24 is located between the second conductive region 2107 and the fourth conductive region 2207 .
  • the first conductive region 2106 and the third conductive region 2206 are conducted through the IGBT chip 23 and the diode chip 24, and the second conductive region 2107 and the fourth conductive region 2207 are conducted through the IGBT chip 23 and the diode chip 24.
  • the first conductive region 2106 , the second conductive region 2107 , the third conductive region 2206 and the fourth conductive region 2207 are connected to each other. Therefore, the first conductive region 2106 of the first substrate 21 is connected to the fourth conductive region 2207 of the second substrate 22 .
  • the third conductive region 2206 , the first conductive region 2106 , the fourth conductive region 2207 , and the second conductive region 2107 are turned on, wherein the IGBT chip 23 and the diode chip 24 are connected in parallel.
  • the third conductive region 2206 and the first conductive region 2106 , the fourth conductive region 2207, the second conductive region 2107 and the two electrode terminals form a loop, which can supply power to multiple IGBT chips and multiple diode chips 24 at the same time.
  • the second conductive region 2107 and the third conductive region 2206 can also be conductively connected.
  • the region 2106, the third conductive region 2206, the second conductive region 2107, and the fourth conductive region 2207 are conductive.
  • the first conductive region 2106 and the fourth conductive region 2207 are turned on as an example for description.
  • the conduction mode between the first conductive region 2106 and the fourth conductive region 2207 is described in detail below. .
  • the first substrate 21 includes a first conductive layer 2103 and a first insulating plate 2104 , and the first conductive layer 2103 is located on the first insulating plate 2104 facing the IGBT chip 23 on the side.
  • the second substrate 22 includes: a second conductive layer 2203 and a second insulating plate 2204 .
  • the second conductive layer 2203 is located on the side of the second insulating plate 2204 facing the IGBT chip 23 .
  • the first conductive layer 2103 includes at least a first conductive region 2106 and a second conductive region 2107
  • the second conductive layer 2203 includes at least a third conductive region 2206 and a fourth conductive region 2207 .
  • the first insulating plate 2104 and the second insulating plate 2204 are respectively used to prevent the first conductive layer 2103 and the second conductive layer 2203 from conducting with the heat sink 10 .
  • the first substrate 21 further includes a first copper layer 2105 , the first copper layer 2105 plays a role of protection and heat conduction, and the first copper layer 2105 is located on the first insulating layer.
  • the first insulating board 2104 is located between the first copper layer 2105 and the first conductive layer 2103, and the first copper layer 2105 is used to protect the first insulation
  • the plate 2104 prevents the first insulating plate 2104 from being broken, and has a heat conduction function at the same time.
  • the second substrate 22 further includes a second copper layer 2205.
  • the second copper layer 2205 plays a role of protection and heat conduction.
  • the second copper layer 2205 is located on the side of the second insulating plate facing the heat conduction layer 30.
  • the second insulating plate 2204 is located between the second copper layer 2205 and the second conductive layer 2203 .
  • the second copper layer 2205 is used to protect the second insulating plate 2204 to prevent the second insulating plate 2204 from being broken, and also has a thermal conductivity function.
  • the second insulating plate 2204 and the first insulating plate 2104 can be made of ceramic materials, so that the first insulating plate 2104, the first copper layer 2105 and the first conductive layer 2103 form the first substrate 21, and the second insulating plate 2204, the first
  • the second substrate 22 formed by the two copper layers 2205 and the second conductive layer 2203 is a copper-clad ceramic substrate (Direct Bonding Copper, DBC).
  • the materials of the second insulating plate 2204 and the first insulating plate 2104 include, but are not limited to, ceramic materials, and may also be plates made of other insulating materials.
  • a thermally conductive layer 30 is provided between the heat sink 10 and at least one of the first copper layer 2105 and the second copper layer 2205 .
  • the number of heat sinks 10 is two, then one of the heat sinks 10 (eg, the first heat sink 11 ) and the first copper layer 2105 is provided with a thermal conductive layer 30 , and the other heat sink A thermally conductive layer 30 is also provided between 10 (eg, the second heat sink 12 ) and the second copper layer 2205 .
  • the heat conduction layer 30 is disposed between the heat sink 10 and the first copper layer 2105 or between the heat sink 10 and the second copper layer.
  • the thermal conductive layer 30 is a nano-copper Velcro
  • the copper in the nano-copper wires on the surface of the nano-copper Velcro can reach the first copper layer.
  • 2105 and/or the second copper layer 2205 diffuse and form molecular bonding forces of Cu-Cu metal bonds with the copper in the first copper layer 2105 and/or the second copper layer 2205, so that the thermal conductive layer 30 and the first copper
  • the bonding force between the layer 2105 and/or the second copper layer 2205 is stronger, and delamination is less likely to occur between the thermally conductive layer 30 and the first substrate 21 and/or the second substrate 22, resulting in a reduced thermal conductivity.
  • the power semiconductor package 20 further includes a connection terminal 27 , one end of the connection terminal 27 has a first terminal 2701 and a second terminal 2702 , the first terminal 2701 and the second terminal One of the 2702 is electrically connected to the first conductive area 2106, and the other of the first terminal 2701 and the second terminal 2702 is electrically connected to the fourth conductive area 2207, so that the space between the first conductive area 2106 and the fourth conductive area 2207 is The first terminal 2701 and the second terminal 2702 of the connection terminal 27 are electrically connected.
  • one of the first terminal 2701 and the second terminal 2702 is electrically connected to the second conductive area 2107, and the other of the first terminal 2701 and the second terminal 2702 is electrically connected to the third conductive area 2206, so that the second conductive area is electrically connected
  • the area 2107 and the third conductive area 2206 are electrically connected through the first terminal 2701 and the second terminal 2702 of the connection terminal 27 .
  • the first terminal 2701 is electrically connected to the first conductive region 2106 and the second terminal 2702 is electrically connected to the fourth conductive region 2207 as an example for description.
  • the power semiconductor package 20 further includes a first electrode terminal 28 and a second electrode terminal 29 , and one of the first electrode terminal 28 and the second electrode terminal 29 is a positive terminal , the other of the first electrode terminal 28 and the second electrode terminal 29 is a negative terminal.
  • One of the first electrode terminal 28 and the second electrode terminal 29 is electrically connected to the first conductive area 2106 , and the other of the first electrode terminal 28 and the second electrode terminal 29 is electrically connected to the fourth conductive area 2207 .
  • one of the first electrode terminal 28 and the second electrode terminal 29 is electrically connected to the second conductive region 2107
  • the other of the first electrode terminal 28 and the second electrode terminal 29 is electrically connected to the third conductive region 2206 .
  • the first electrode terminal 28 is a positive terminal and is electrically connected to the third conductive area 2206; the second electrode terminal 29 is a negative terminal and is electrically connected to the second conductive area 2107 as an example for description.
  • the power semiconductor package 20 further includes an encapsulation layer 210, and the first substrate 21, the second substrate 22, at least one IGBT chip 23, and at least one diode chip 24 are located in the encapsulation layer 210, The first substrate 21 , the second substrate 22 , the IGBT chip 23 , the diode chip 24 and other components are encapsulated into a sealed integral structure through the encapsulation layer 210 , so that the chips in the formed power semiconductor package 20 are not easily damaged by water vapor or liquid.
  • the thermal conductive layer 30 is made of nano-copper Velcro
  • the first substrate 21 and the second substrate 22 face the thermal conductive layer 30 on the side of the The encapsulation layer 210 needs to be exposed, so that the nano-copper Velcro is in contact with the copper layers on the surfaces of the first substrate 21 and the second substrate 22 .
  • at least a part of the area of the encapsulation layer 210 opposite to the first substrate 21 and the second substrate 22 is a bare area (for example, a hollow area), so that the first substrate 21 and the second substrate 22 face heat conduction respectively.
  • One side of layer 30 is exposed at the exposed area. In this way, the barrier of the encapsulation layer 210 is eliminated, and the first substrate 21 and the second substrate 22 are in direct contact with the thermally conductive layer 30 respectively, thereby facilitating heat transfer and close bonding with the thermally conductive layer 30 .
  • the number of heat sinks 10 when the number of heat sinks 10 is one, at least part of the surface of the encapsulation layer 210 opposite to the heat sink 10 may be set as an exposed area, for example, the encapsulation layer 210 opposite to the first substrate 21 may be disposed At least a part of the area is set as a bare area, a thermal conductive layer is set between the first substrate 21 and the heat sink 10 , and the area opposite the encapsulation layer 210 and the second substrate 22 is a closed area.
  • the power semiconductor module structure shown in FIG. 2 and FIG. 3C is a partial partial structural view of the power semiconductor module structure.
  • the encapsulation layer 210 is not shown in FIG. 2 and FIG.
  • the encapsulation layer 210 of the module can be referred to as shown in FIG. 4 .
  • the numbers of the IGBT chips 23 and the diode chips 24 include but are not limited to the aforementioned numbers.
  • the power semiconductor package 20 further includes a signal terminal 213 , one end of the signal terminal 213 is located in the packaging layer 210 and is electrically connected to the IGBT chip 23 , and the signal terminal 213 The other end of 213 is located outside the encapsulation layer 210 (see FIG. 4 ).
  • the power semiconductor package 20 further includes a bonding wire 211 , and the bonding wire 211 can be, for example, a wire.
  • the bonding wire 211 can be, for example, a wire.
  • One end of the second substrate 22 is provided with a pad 2209 , one end of the bonding wire 211 and the pad 2209 are electrically connected by bonding, and the other end of the bonding wire 211 and the IGBT chip 23 can also be bonded by bonding
  • One end of the signal terminal 213 is electrically connected to the pad 2209 so that the IGBT chip 23 and the signal terminal 213 are electrically connected.
  • the bonding method is an existing method of connecting the metal wire and the pad, specifically, the metal wire is tightly welded to the pad by heat, pressure or ultrasonic energy.
  • the two ends of the bonding wire 211 and the bonding pad 2209 and the IGBT chip 23 may also be electrically connected in other ways, such as conductive glue or welding.
  • the pads 2209 and the second conductive layer 2203 of the second substrate 22 are spaced apart, so as to ensure that the pads 2209 and the second conductive layer 2203 of the second substrate 22 are mutually insulation.
  • FIG. 5A is another schematic structural diagram of a power semiconductor module provided by an embodiment of the present application.
  • both ends of the first radiator 11 and the second radiator 12 are connected by connecting pipes, for example, as shown in FIG. 5B
  • One end of the first radiator 11 communicates with one end of the second radiator 12 through the connecting pipe 11b
  • the other end of the first radiator 11 communicates with one end of the second radiator 12 through the connecting pipe 11a.
  • the first radiator 11 and the second radiator 12 are provided with cooling water channels 14 (see FIG.
  • the cooling water channels 14 in the first radiator 11 and the second radiator 12 are realized by connecting pipes 11 a and 11 b
  • one end of the first radiator 11 is provided with a water inlet 111
  • one end of the second radiator 12 is provided with a water outlet 121 on one end away from the water inlet 111 .
  • the cooling liquid enters the cooling water channel 14 (see FIG. 6 ) inside the first radiator 11 from the water inlet 111 , and a part of the cooling liquid follows this along the actual surface in FIG. 5B .
  • the line arrow flows in the heat dissipation water channel 14 of the first radiator 11, absorbs the heat of the first radiator 11, and enters the water outlet 121 through the connecting pipe 11a adjacent to the water outlet 121 side and flows out to take away the heat; Following the dashed arrow in FIG. 5B , it enters the cooling water channel 14 inside the second radiator 12 through the connecting pipe 11b on the side adjacent to the water inlet 111 and flows along the cooling water channel 14 (see FIG. 6 ) of the second radiator, absorbing The heat of the second radiator 12 enters the water outlet 121 and flows out to take away the heat.
  • the cooling liquid in the first radiator 11 cools one side of the power semiconductor package 20 and then is discharged from the water outlet 121 , and part of the cooling liquid entered by the water inlet 111 directly enters the second radiator 12 to the other side of the power semiconductor package 20 .
  • the connection pipes 11b and 11a realize the parallel arrangement of the cooling water channels 14 in the two radiators, which achieves a good heat dissipation effect on both sides of the power semiconductor package 20 and ensures that the power semiconductor module has a good heat dissipation capability.
  • FIG. 6 is another schematic structural diagram of the power semiconductor module provided by an embodiment of the application
  • FIG. 7 is a schematic cross-sectional structural diagram of the power semiconductor module shown in FIG. 6 after being assembled.
  • the IGBT chip 23 and the diode chip 24 are assembled in a front-mounted manner, that is, the front side of the IGBT chip 23 and the diode chip 24 face upward, while in the embodiment of the present application, refer to As shown in FIG. 6-FIG. 7, the IGBT chip 23 and the diode chip 24 are assembled by flip-chip method, that is, the front side of the IGBT chip 23 and the diode chip 24 is facing down, and one end of the second substrate 22 is provided with a pad 2209, see As shown in FIG.
  • the IGBT chip 23 is electrically connected to the pad 2209 (eg, by welding), that is, the bonding wire 211 (see FIG. 2 ) is not used for electrical connection between the IGBT chip 23 and the pad 2209 .
  • One end of the signal terminal 213 is electrically connected to the pad 2209 , and finally the conduction between the IGBT chip 23 and the signal terminal 213 is realized.
  • the pads 2209 and the second conductive layer 2203 of the second substrate 22 are spaced apart to ensure that the pads 2209 and the second conductive layer 2203 of the second substrate 22 are insulated from each other.
  • connection method between the IGBT chip 23 , the diode chip 24 and the first conductive pad 25 and the second conductive pad 26 , and other structures are the same as the above-mentioned embodiments.
  • FIG. 8 is another schematic structural diagram of a power semiconductor module provided by an embodiment of the present application, and FIG. 9 shows a schematic structural diagram of each part in FIG. 8 after being assembled.
  • the power semiconductor package 20 further includes: a first conductive column 214 and a second conductive column 215 .
  • the first conductive column 214 and the second conductive pillars 215 are located between the first substrate 21 and the second substrate 22, respectively.
  • the second substrate 22 also has a fifth conductive region 2208.
  • the fifth conductive region 2208 is spaced apart from the third conductive region 2206 and the fourth conductive region 2207 to ensure that the fifth conductive region 2208 and the fourth conductive region 2208 are spaced apart from each other.
  • the third conductive region 2206 and the fourth conductive region 2207 are insulated from each other.
  • the first terminal 2701 and the second terminal 2702 of the wiring terminal 27 are both electrically connected to the fourth conductive area 2207, the two ends of the first conductive column 214 are respectively electrically connected to the fourth conductive area 2207 and the first conductive area 2106, and the second conductive area Two ends of the pillar 215 are electrically connected to the second conductive region 2107 and the fifth conductive region 2208, respectively.
  • the first conductive region 2106 , the second conductive region 2107 , the third conductive region 2206 , the fourth conductive region 2207 and the fifth conductive region 2208 are connected through the first conductive pillar 214 and the second conductive pillar 215 .
  • One of the first electrode terminal 28 and the second electrode terminal 29 is electrically connected to the third conductive area 2206, and the other one of the first electrode terminal 28 and the second electrode terminal 29 is electrically connected to the fifth conductive area 2208.
  • the first electrode terminal 28 is electrically connected to the third conductive region 2206
  • the second electrode terminal 29 is electrically connected to the fifth conductive region 2208.
  • the third conductive region 2206 , the first conductive region 2106 , the fourth conductive region 2207 , the second conductive region 2107 , and the fifth conductive region 2208 are connected to the first electrode through the first conductive column 214 and the second conductive column 215
  • the terminal 28 and the second electrode terminal 29 constitute a conductive loop.
  • FIG. 10 is another schematic structural diagram of a power semiconductor module provided by an embodiment of the present application
  • FIG. 11 is a schematic structural diagram of each part in FIG. 10 after being assembled.
  • the first substrate 21 and the second substrate 22 are both conductive plates.
  • the first substrate 21 and the second substrate 22 may be for copper plate.
  • the first substrate 21 and the second substrate 22 can also be metal conductive plates made of other metal materials with good electrical conductivity and thermal conductivity.
  • the first substrate 21 includes: a first conductive plate 2101 and a second conductive plate 2102 that are insulated from each other and distributed side by side, the first conductive plate 2101 has a first conductive area 2106, and the second conductive plate 2102 has a second conductive area 2107 .
  • the second substrate 22 includes: a third conductive plate 2201 and a fourth conductive plate 2202 that are insulated from each other and distributed side by side, the third conductive plate 2201 has a third conductive region 2206, and the fourth conductive plate 2202 has a fourth conductive region 2207 .
  • the heat sink 10 is insulated from the first substrate 21 and/or the second substrate 22 to avoid conduction between the conductive plates and the heat sink 10 .
  • the thermal conductive layer 30 in order to realize the insulating arrangement between the heat sink 10 (for example, the first heat sink 11 and the second heat sink 12 ) and the first substrate 21 and/or the second substrate 22 , the thermal conductive layer 30 can be selected from the optional
  • the solid heat conduction layer is formed by curing silicone grease.
  • the curable silicone grease is a viscous liquid material. After pretreatment and curing treatment, a viscous and stable solid heat conduction layer can be formed, and the radiator 10 is firmly attached to the power semiconductor package 20.
  • the thermally conductive layer 30 functions to insulate the first heat sink 11 and the second heat sink 12 from the first substrate 21 and the second substrate 22 .
  • the thermal conductive layer in the prior art often uses silicone grease.
  • the silicone grease in the power semiconductor module is non-solid.
  • the curable silicone grease is specifically composed of silicone grease and a polymer film layer on the surface of the silicone grease or a liquid material containing a polymer material, wherein the polymer film
  • the layer or the polymer liquid material has a polymer material that can chemically react with the silicone grease to achieve the purpose of curing, that is, the polymer material is a material that reacts with the silicone grease to achieve a curing effect.
  • the curable silicone grease when the curable silicone grease is placed between the heat sink 10 and the power semiconductor package 20, under the action of heating or pressure, the polymer material in the polymer film layer diffuses into the silicone grease and chemically reacts with the silicone grease. The reaction makes the silicone grease achieve the purpose of curing.
  • the thermal conductive layer 30 is a solid thermal conductive layer formed of curable silicone grease
  • the liquid silicone grease in the curable silicone grease will be filled with In the surface of the power semiconductor package 20 and the surface of the heat sink 10 with fine irregularities
  • the thermal conductive layer 30 and the power semiconductor package 20 and the heat sink 10 (such as the first heat sink 11 or Interlocking force is formed between the second heat sink 12), thereby ensuring a firm and tight combination between the thermal conductive layer 30 and the power semiconductor package 20 and with the heat sink 10, thereby facilitating the rapid conduction of heat and realizing the power semiconductor Timely cooling of the module.
  • the surfaces of the power semiconductor package 20 and the heat sink 10 in contact with the thermal conductive layer 30 may also be roughened, so as to further strengthen the thermal conductive layer 30 and the power semiconductor package 20 and the heat sink 10 fit between.
  • the second substrate 22 is a conductive plate
  • the surface of the second substrate 22 is not provided with the pad 2209
  • the IGBT chip 23 and the signal terminal 213 are connected through the bonding wire 211, for example, the bonding wire 211
  • One end of the wire is electrically connected to the signal terminal 213 by bonding
  • the other end of the bonding wire 211 is electrically connected to the IGBT chip 23 by bonding (see FIG. 11 ), so that the IGBT chip 23 and the signal terminal 213 are electrically connected.
  • Embodiments of the present application further provide a motor driver, including a capacitor and at least one power semiconductor module in any of the above embodiments connected to the capacitor.
  • the capacitor is specifically electrically connected to the first electrode terminal 28 and the second electrode terminal 29 in the power semiconductor module.
  • the structure and working principle of the power semiconductor module can be referred to the description of the above-mentioned embodiment, which is not repeated in the embodiment of the present application.
  • the motor driver provided by the embodiment of the present application by including the above-mentioned power semiconductor module, reduces the risk of stress damage caused by the power semiconductor module during the assembly process of the whole motor driver.
  • the integrated processing of the power semiconductor package and the radiator, as well as the helium gas inspection of the power semiconductor module can be realized before the assembly of the motor driver.
  • the functional semiconductor package and radiator are installed in the whole motor driver first, and then the whole motor driver is tested for helium gas, so that if the radiator leaks, the whole motor driver will be scrapped, which will greatly increase the cost.
  • the power semiconductor module can be tested for helium in advance, so that if the radiator leaks, only the power semiconductor module needs to be replaced, and the whole motor driver will not be scrapped, so the embodiment of the present application In the process, the secondary processing yield of the whole machine is improved.
  • Embodiments of the present application further provide a powertrain, including a motor and the motor driver in Embodiment 6 connected to the motor, wherein the structure and working principle of the power semiconductor module in the motor driver can be referred to the descriptions of the above embodiments, Details are not repeated in the embodiments of the present application.
  • the risk of stress damage caused by the power semiconductor module during the assembly process of the motor driver is reduced. It can realize the integrated processing of the power semiconductor package and the radiator before the assembly of the motor driver, as well as the helium gas inspection of the power semiconductor module, which avoids the leakage of the radiator during the test of the motor driver. risk of obsolescence.
  • An embodiment of the present application further provides a vehicle, including a wheel, a motor, and the motor driver in Embodiment 6 connected to the motor, and the motor is connected to the wheel through a transmission assembly.
  • the vehicle may be an electric vehicle/electric vehicle (EV), a pure electric vehicle (PEV/BEV), a hybrid electric vehicle (HEV), an extended-range electric vehicle (REEV), and a plug-in hybrid electric vehicle (PHEV). ), New Energy Vehicle, etc.
  • EV electric vehicle/electric vehicle
  • PEV/BEV pure electric vehicle
  • HEV hybrid electric vehicle
  • REEV extended-range electric vehicle
  • PHEV plug-in hybrid electric vehicle
  • New Energy Vehicle etc.
  • the risk of stress damage caused by the power semiconductor module during the assembly process of the motor driver is reduced. It can realize the integrated processing of the power semiconductor package and the radiator before the assembly of the motor driver, as well as the helium gas inspection of the power semiconductor module, which avoids the leakage of the radiator during the test of the motor driver. risk of obsolescence.
  • an embodiment of the present application further provides a method for manufacturing a power semiconductor module, including the following steps:
  • S101 Provide at least one power semiconductor package and heat sink
  • S102 respectively disposing interface materials on the top surface and/or bottom surface of the power semiconductor package
  • an interface material may be formed on the top surface of the power semiconductor package 20 , and the interface material may be a thermally conductive material with metal bonding wires on the surface, or the interface material may be curable silicone grease; in this way, the power semiconductor package 20
  • the top surface of the power semiconductor package 20 and the heat sink 10 form an integral structure through the interface material; alternatively, an interface material can be provided on the bottom surface of the power semiconductor package 20, so that the bottom surface of the power semiconductor package 20 and the heat sink 10 form an integral structure through the interface material;
  • the top and bottom surfaces of the power semiconductor package 20 are respectively provided with interface materials, so that the top and bottom surfaces of the power semiconductor package 20 and the heat sink 10 (for example, the first heat sink 11 and the second heat sink 12 in FIG. 1 ) pass through the interface material respectively. form the overall structure.
  • the power semiconductor package 20 provided with the interface material and the heat sink 10 are pressed together at a preset temperature and a preset pressure for a preset time to form a power semiconductor module including:
  • the power semiconductor package 20 provided with the interface material and the heat sink 10 are subjected to a pre-pressing process for a first preset time under the conditions of a first preset pressure and a first preset temperature; wherein, the first preset pressure can be 1MPa-3MPa, the first preset temperature may be 110°C-130°C, and the first preset time may be 15 minutes-25 minutes.
  • the first preset pressure can be 1MPa-3MPa
  • the first preset temperature may be 110°C-130°C
  • the first preset time may be 15 minutes-25 minutes.
  • the pretreated power semiconductor package 20 and the heat sink 10 are subjected to curing treatment for a second preset time under the conditions of a second preset pressure and a second preset temperature, so that the curable silicone grease can be formed separately from the heat dissipation.
  • the second preset pressure may be 4MPa-8MPa
  • the second preset temperature may be 170°C-190°C
  • the second preset time may be 110 minutes-130 minutes.
  • the curable silicone grease can form a viscous and stable solid heat conduction layer, and firmly fix the heat sink 10 and the power semiconductor package 20 to form a power semiconductor module.
  • the interface material is a thermally conductive material with metal bonding wires on the surface, before disposing the interface material on the top surface and the bottom surface of the power semiconductor package 20 respectively, it further includes:
  • Metal plating is formed on the side of the heat sink 10 facing the power semiconductor package 20 , or deoxidation treatment is performed on the side of the heat sink 10 facing the power semiconductor package 20 .
  • the deoxidation treatment exposes the metal element on the top surface and the bottom surface of the power semiconductor package 20, and forming a metal plating layer on the side of the heat sink 10 facing the power semiconductor package 20 can prevent the generation of the oxide layer, so that the metal material can be used in the heat sink 10 and the power semiconductor package.
  • a solid heat conduction layer with molecular bonding force is formed between 20.
  • metal plating layer is not applied to the side of the heat sink 10 facing the power semiconductor package 20 , deoxidation treatment can also be performed on this side to expose the metal element, which can also ensure that the metal material can be between the heat sink 10 and the power semiconductor package 20 .
  • a solid thermal conductive layer with molecular bonding force is formed.

Abstract

本申请提供一种功率半导体模组、电机驱动器、动力总成、车辆以及功率半导体模组的制造方法。通过在所述散热器与所述功率半导体封装之间设置导热层，且导热层为表面具有金属键合线的导热材料；或者，所述导热层为可固化硅脂形成的固态导热层，使得所述功率半导体封装和所述散热器均与所述导热层结合并构成所述功率半导体模组，降低了功率半导体模组在电机驱动器整机装配过程中造成的应力损坏风险。实现了提前对功率半导体模组进行氦气检验，提高了电机驱动器整机二次加工的合格率，避免了电机驱动器在整机氦气测试时因散热器漏气而导致电机驱动器整机报废的风险。

Description

一种功率半导体模组及制造方法 技术领域
本申请涉及功率半导体模组技术领域，特别涉及一种功率半导体模组及制造方法、电机驱动器、动力总成和车辆。
背景技术
功率半导体模组，指实现电路开关功能的半导体器件，通常由功率半导体芯片通过特定的电路桥接封装而成。其中，功率半导体芯片一般包括绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)、二极管(Diode)、金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)、晶闸管、三极管等。功率半导体模组是电机驱动器(Motor Control Unit，MCU)的核心器件，也是最主要的发热器件，其封装的散热能力对产品的性能参数指标起到决定性作用。
目前，功率半导体模组的封装分为单面冷却和双面冷却两种结构，两种结构的区别主要为热量主要由器件的单一表面单向传递至冷却介质，还是由器件的两个表面双向传递至冷却介质。同等工艺条件下双面冷却封装散热能力更强，有助于充分发挥功率半导体芯片性能，提升产品功率密度，降低产品成本。双面冷却封装的功率半导体模组通常是将功率半导体封装放置在两个散热器之间，在功率半导体封装与散热器之间设置导热界面材料(业界较常使用导热硅脂、石墨膜、硅凝胶、相变材料等)，两个散热器通过机械结构(例如螺钉、螺栓等)压紧连接，从而夹紧功率半导体封装和导热界面材料。
然而，采用机械结构压紧散热器，不易保证功率半导体模组各部位受力均匀，使得功率半导体模组在电机驱动器整机装配过程中可能会产生应力而被损坏，造成电机驱动器整机报废。并且导热硅脂在使用一段时间后容易变干脱落，降低功率半导体模组的散热能力。
发明内容
本申请提供一种功率半导体模组及制造方法、电机驱动器、动力总成和车辆。实现了在散热器与功率半导体封装之间形成具有固定功能、且不易脱落的固态导热层，可使功率半导体模组的各部位受力均匀，降低了功率半导体模组在电机驱动器整机装配过程中产生的应力损坏风险。并且能够在电机驱动器整机装配前实现功率半导体封装与散热器的一体化集成加工，以及功率半导体模组的氦气检验，避免了电机驱动器在整机测试时因散热器漏水而导致电机驱动器整机报废的风险。
第一方面，本申请实施例提供一种功率半导体模组，包括至少一个散热器和至少一个功率半导体封装；
还包括：导热层，所述导热层位于所述散热器与所述功率半导体封装之间，所述导热层为表面具有金属键合线的导热材料；或者，所述导热层为可固化硅脂形成的固态导热层；且所述功率半导体封装和所述散热器均与所述导热层结合以构成所述功率半导体模组。
通过将所述导热层配置为表面具有金属键合线的导热材料；或者，所述导热层为可固化硅脂形成的固态导热层，这样导热层的金属键合线与散热器以及所述功率半导体封装之间在加热、加压下实现键合(bond)连接，使得散热器以及所述功率半导体封装与导热层之间形成具有分子键合力的结合力，或者，所述导热层为可固化硅脂形成的固态导热层，可固化硅脂在散热器以及所述功率半导体封装之间固化时形成相互嵌合的固化导热层，这样，功率半导体封装和所述散热器之间的导热层具有固定功能并且不易脱落，能够使散热器与功率半导体封装之间受力均匀，降低功率半导体模组在电机驱动器整机装配过程中因应力产生而导致损坏的风险。同时，可实现功率半导体封装与散热器的一体化集成加工，以及功率半导体模组的氦气检验，这样可以将散热器漏气的不良产品提前筛选出来，检验合格的功率半导体模组可直接应用于电机驱动器整机的装配，提升了电机驱动器整机装配的自动化水平和加工速度，提高了整机二次加工的良率，避免了电机驱动器在整机氦气测试时因散热器漏水而导致电机驱动器整机报废的风险。
在第一方面的一种可能的实现方式中，所述导热层与所述散热器之间，以及所述导热层与所述功率半导体封装之间形成具有分子键合力或嵌合力的结合力。
分子键合力或嵌合力为强相互结合力，导热层与散热器、功率半导体封装之间形成的分子键合力或嵌合力可将散热器牢固的与功率半导体封装进行固定。
在第一方面的一种可能的实现方式中，所述导热层包括：金属导热片和设在所述金属导热片表面的所述金属键合线。
在第一方面的一种可能的实现方式中，所述金属导热片为铜箔、铝箔、银箔或金箔，所述金属键合线为纳米铜线、纳米铝线、纳米银线或纳米金线。
其中，金属键合线会与散热器以及功率半导体封装表面的铜层或铝层之间在加热和加压下形成金属间相互融合的分子键合力，可将散热器牢固的与功率半导体封装固定。同时，纳米铜线、纳米铝线、纳米银线、纳米金线、铜箔、铝箔、银箔或金箔均具有良好的导热性能，可极大提升功率半导体模组的散热能力。
在第一方面的一种可能的实现方式中，所述导热层还包括：导热胶，所述导热胶分布在相邻所述金属键合线之间的间隙中。
通过设置导热胶，导热胶有利于将导热层与散热器以及功率半导体封装实现紧密粘合，这样，散热器以及功率半导体封装与导热层在加热、加压条件下实现固定时，在导热胶的作用下，可以在更低温度和更小压力的工艺条件下即可实现散热器以及功率半导体封装与导热层之间良好的固定作用，所以，通过设置导热胶，降低了散热器以及功率半导体封装与导热层加热、加压处理时的温度和压力，有助于提升工艺的生产良率。
在第一方面的一种可能的实现方式中，所述散热器的数量为两个，两个所述散热器分别为相对的第一散热器和第二散热器，所述功率半导体封装设置于所述第一散热器与所述第二散热器之间，且所述功率半导体封装与所述第一散热器和所述第二散热器之间均设有所述导热层。
将功率半导体封装设置在第一散热器与第二散热器之间，形成具备双面冷却结构的功率半导体模组，热量可由功率半导体封装的两个表面双向传递给第一散热器和第二散热器。相比单面冷却结构，在同等工艺条件下双面冷却结构的散热能力更强，有助于充分发挥功率半导体芯片性能，提升产品功率密度，降低产品成本。
在第一方面的一种可能的实现方式中，所述第一散热器和所述第二散热器的一端通过连接板相连，所述第一散热器和所述第二散热器的另一端通过紧固件连接。
第一散热器和第二散热器的一端通过连接板相连，另一端通过紧固件连接所形成的散热结构适用于串联散热水道的散热方式。
或者，所述第一散热器和所述第二散热器的两端通过连接管相连。
第一散热器和第二散热器的两端通过连接管相连所形成的散热结构适用于并联散热水道的散热方式。
在第一方面的一种可能的实现方式中，所述第一散热器、所述第二散热器的内部均设有散热水道，所述第一散热器内的所述散热水道和所述第二散热器内的所述散热水道通过所述连接板串联，所述第一散热器、所述第二散热器的另一端分别设有与所述散热水道连通的进水口、出水口。
第一散热器内部的散热水道与第二散热器内部的散热水道通过连接板内部的散热水道连通，构成串联散热水道的散热结构。进水口与出水口位于散热器的同侧，冷却液由进水口进入位于第一散热器内部的散热水道，吸收第一散热器的热量；再通过连接板内的散热水道流入第二散热器的散热水道，吸收第二散热器的热量，并最终由出水口流出将所有热量带走。
或者，所述第一散热器、所述第二散热器的内部均设有散热水道，所述第一散热器内的所述散热水道和所述第二散热器内的所述散热水道通过所述连接管并联，所述第一散热器的一端设有进水口、所述第二散热器在远离所述进水口的一端上设有出水口。
第一散热器内部的散热水道与第二散热器内部的散热水道通过位于第一散热器、第二散热器之间的连接管连通，连接管位于两个散热器的两端，构成并联散热水道的散热结构。进水口、出水口分别位于散热器的两侧，冷却液由进水口进入第一散热器内部的散热水道，一部分冷却液顺着此散热水道流动，吸收第一散热器的热量，并通过邻近出水口侧的连接管进入到出水口流出将热量带走；另一部分冷却液通过邻近进水口侧的连接管进入到第二散热器内部的散热水道并顺着此散热水道流动，吸收第二散热器的热量，再进入到出水口流出将热量带走。
在第一方面的一种可能的实现方式中，每个所述功率半导体封装至少包括第一基板、第二基板、至少一个芯片，所述芯片固定在所述第一基板与所述第二基板之间；且所述至少一个芯片与所述第一基板和所述第二基板电连接；使芯片与第一基板、第二基板之间构成电路。
所述散热器与所述第一基板和所述第二基板中的至少一个之间设有所述导热层，用于将功率半导体封装产生的热量传递给散热器。
在第一方面的一种可能的实现方式中，所述芯片包括IGBT芯片和二极管芯片。
或者，所述芯片包括硅(Si)金属氧化物半导体场效应晶体管(MOSFET)或者碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)。
在第一方面的一种可能的实现方式中，所述功率半导体封装还包括：至少一个导电衬垫，导电衬垫起到导电以及支撑第一基板、第二基板的作用。
所述导电衬垫位于芯片和所述第一基板之间；且所述导电衬垫的两端分别通过导电连接层与芯片和所述第一基板相连；
在第一方面的一种可能的实现方式中，所述第一基板具有相互绝缘的且并列排布的第一导电区域和第二导电区域；
所述第二基板具有相互绝缘的且并列排布的第三导电区域和第四导电区域，所述第一导电区域与所述第三导电区域相对，所述第二导电区域与所述第四导电区域相对，
所述芯片的部分位于所述第一导电区域与所述第三导电区域之间，所述芯片的部分位于所述第二导电区域与所述第四导电区域之间；
且所述第一导电区域与所述第四导电区域导通，或者，所述第二导电区域与所述第三导电区域导通。
这样使第一导电区域与第三导电区域之间通过芯片导通，第二导电区域与第四导电区域通过芯片导通，第一导电区域与第四导电区域导通，使第三导电区域、第一导电区域、第四导电区域、第二导电区域导通。
或者，第二导电区域与第三导电区域导通，使第一导电区域、第三导电区域、第二导电区域、第四导电区域构成电路。
在第一方面的一种可能的实现方式中，所述第一基板和所述第二基板均为导电板；
且所述第一基板包括：相互绝缘的且并排分布的第一导电板和第二导电板，所述第一导电板上具有所述第一导电区域，所述第二导电板上具有所述第二导电区域；
所述第二基板包括：相互绝缘的且并排分布的第三导电板和第四导电板，所述第三导电板上具有所述第三导电区域，所述第四导电板上具有所述第四导电区域；
且所述散热器与所述导电板之间绝缘设置，避免导电板与散热器导通。
在第一方面的一种可能的实现方式中，所述第一基板包括第一导电层和第一绝缘板，所述第一导电层位于所述第一绝缘板的朝向所述芯片的一面上；
所述第二基板包括：第二导电层和第二绝缘板，所述第二导电层位于所述第二绝缘板的朝向所述芯片的一面上；
且所述第一导电层至少包括所述第一导电区域和所述第二导电区域，所述第二导电层至少包括所述第三导电区域和所述第四导电区域。
第一绝缘板、第二绝缘板分别用于避免第一导电层、第二导电层与散热器导通。
在第一方面的一种可能的实现方式中，所述第一基板还包括第一铜层，第一铜层起到保护和导热作用，所述第一铜层位于所述第一绝缘板的朝向所述导热层的一面上，第一铜层用于保护第一绝缘板，防止第一绝缘板碎裂，同时兼具导热功能；
所述第二基板还包括第二铜层，第二铜层起到保护和导热作用，所述第二铜层位 于所述第二绝缘板的朝向导热层的一面上，第二铜层用于保护第二绝缘板，防止第二绝缘板碎裂，同时兼具导热功能；
所述散热器与所述第一铜层和所述第二铜层中的至少一个之间设有所述导热层。
在第一方面的一种可能的实现方式中，所述功率半导体封装还包括接线端子，所述接线端子的一端具有第一端子和第二端子，所述第一端子和所述第二端子中的其中一个与所述第一导电区域电连接，所述第一端子和所述第二端子中的另一个与所述第四导电区域电连接，以使所述第一导电区域与所述第四导电区域导通；
或者，所述第一端子和所述第二端子中的其中一个与所述第二导电区电连接，所述第一端子和所述第二端子中的另一个与所述第三导电区域电连接，以使所述第二导电区域和所述第三导电区域导通；
或者，所述第一端子和所述第二端子均与所述第三导电区域或者均与第四导电区域电连接。
在第一方面的一种可能的实现方式中，所述功率半导体封装还包括：第一电极端子和第二电极端子，所述第一电极端子和所述第二电极端子中的其中一个为正极端子，所述第一电极端子和所述第二电极端子中的另一个为负极端子；
所述第一电极端子和第二电极端子中的其中一个与所述第一导电区域电连接，所述第一电极端子和第二电极端子中的另一个与所述第四导电区域电连接；
或者，所述第一电极端子和第二电极端子中的其中一个与第二导电区域电连接，所述第一电极端子和第二电极端子中的另一个与第三导电区域电连接。
在第一方面的一种可能的实现方式中，所述功率半导体封装还包括：第一导电柱和第二导电柱，所述第一导电柱和所述第二导电柱分别位于所述第一基板和所述第二基板之间；
所述第二基板还具有第五导电区域，且所述第五导电区域与所述第三导电区域和所述第四导电区域均绝缘设置；
所述接线端子的所述第一端子和所述第二端子均与所述第四导电区域电连接，所述第一导电柱的两端分别与所述第一导电区域和所述第四导电区域电连接，所述第二导电柱的两端分别与所述第二导电区域和所述第五导电区域电连接；
所述第一电极端子和第二电极端子中的其中一个与第三导电区域电连接，所述第一电极端子和第二电极端子中的另一个与所述第五导电区域电连接。
通过第一导电柱和第二导电柱使第三导电区域、第一导电区域、第四导电区域、第二导电区域、第五导电区域构成电路，并与第一电极端子、第二电极端子构成导电回路。
在第一方面的一种可能的实现方式中，所述功率半导体封装还包括：封装层，所述第一基板、所述第二基板、所述至少一个芯片位于所述封装层内，通过封装层将第一基板、第二基板、芯片等部件固定密封，使之构成功率半导体封装。且所述封装层与所述第一基板以及所述第二基板中的至少一个相对的至少部分区域为裸露区域，所述第一基板与所述第二基板中的至少一个的朝向所述导热层的一面在所述裸露区域处裸露。这样消除了封装层的阻挡，使基板与导热层之间接触更紧密，有利于热量的传递。
在第一方面的一种可能的实现方式中，所述功率半导体封装还包括：信号端子，所述信号端子的一端位于所述封装层内且与所述芯片电连接，所述信号端子的另一端位于所述封装层外。
在第一方面的一种可能的实现方式中，所述功率半导体封装还包括：绑定线，绑定线的一端与所述芯片键合连接，所述绑定线的另一端与所述信号端子键合连接，从而使芯片与信号端子导通；
或者，所述第二基板的一端设有焊盘，所述绑定线的另一端与所述焊盘键合连接，所述信号端子的一端与焊盘电连接，从而使芯片与信号端子导通；
或者，所述第二基板的一端设有焊盘，所述芯片与所述焊盘电连接，所述信号端子的一端与焊盘电连接，从而使芯片与信号端子导通。
第二方面，本申请实施例提供一种电机驱动器，包括电容和至少一个上述任一功率半导体模组，所述功率半导体模组的电极端子与所述电容电连接。
第三方面，本申请实施例提供一种动力总成，包括电机和与所述电机连接的上述电机驱动器。
第四方面，本申请实施例提供一种车辆，包括车轮、电机以及与所述电机连接的上述电机驱动器，所述电机通过传动组件与所述车轮相连。
第五方面，本申请实施例提供一种功率半导体模组的制造方法，包括：
提供至少一个功率半导体封装和散热器；
在所述功率半导体封装的顶面和/或底面分别设置界面材料，所述界面材料为表面具有金属键合线的导热材料，或者，所述界面材料为可固化硅脂；
将设置有所述界面材料的所述功率半导体封装与所述散热器在预设温度和预设压力下压合预设时间，形成所述功率半导体模组。
在第五方面的一种可能的实现方式中，当所述界面材料为可固化硅脂时，所述将设置有所述界面材料的所述功率半导体封装与所述散热器在预设温度和预设压力下压合预设时间，形成所述功率半导体模组，包括：
将设置有所述界面材料的所述功率半导体封装与所述散热器在第一预设压力、第一预设温度条件下进行第一预设时间的压合预处理；
将预处理后的所述功率半导体封装与所述散热器之间在第二预设压力、第二预设温度条件下进行第二预设时间的固化处理，以使可固化硅脂形成固态导热层。
可固化硅脂为具有粘性的液态材料，在经过预处理、固化处理后可形成具有粘性且稳定的固态导热层，将散热器牢固的与功率半导体封装固定，形成功率半导体模组，降低温度后已固化硅脂不会液化。
在第五方面的一种可能的实现方式中，当界面材料为表面具有金属键合线的导热材料时，所述在所述功率半导体封装的顶面和/或底面分别设置界面材料之前还包括：
对所述功率半导体封装的顶面和/或底面进行去氧化处理；
对所述散热器朝向所述功率半导体封装的一面形成金属镀层，或者对所述散热器朝向所述功率半导体封装的一面进行去氧化处理。
去氧化处理使功率半导体封装的顶面、底面露出金属单质，散热器朝向功率半导体封装的一面形成金属镀层可防止氧化层的产生，以便使金属键合线分别与散热器以 及功率半导体封装表面的金属材料在加热、加压下键合，使得界面材料分别与散热器以及功率半导体封装表面形成具有分子键合力的结合力。
若不在散热器朝向功率半导体封装的一面施加金属镀层，也可对此面同样进行去氧化处理，使其露出金属单质，也能保证金属材料能够在散热器以及功率半导体封装之间形成具有分子键合力或嵌合力的固态导热层。
附图说明
图1为本申请一实施例提供的功率半导体模组的示意图；
图2为本申请一实施例提供的功率半导体模组的局部剖面爆炸示意图；
图3A为本申请一实施例提供的功率半导体模组中导热层、功率半导体封装、第一散热器以及第二散热器的剖面结构示意图；
图3B为本申请一实施例提供的功率半导体模组中导热层、功率半导体封装、第一散热器以及第二散热器的剖面结构示意图；
图3C为图2所示的功率半导体模组装配后的的剖面示意图；
图4为本申请一实施例提供的功率半导体封装的结构示意图；
图5A为本申请一实施例提供的功率半导体模组的结构示意图；
图5B为沿着图5A中的A-A方向的剖面示意图；
图6为本申请一实施例提供的功率半导体模组的局部剖面爆炸示意图；
图7为图6所示的功率半导体模组装配后的剖面示意图；
图8为本申请一实施例提供的功率半导体模组的局部剖面爆炸示意图；
图9为图8所示的功率半导体模组装配后的的剖面示意图；
图10为本申请一实施例提供的功率半导体模组的局部剖面爆炸示意图；
图11为图10所示的功率半导体模组装配后的的剖面示意图。
图12为本申请一实施例提供的功率半导体封装的制造方法的流程示意图。
附图标记说明：
10-散热器；11-第一散热器；11a、11b-连接管；111-进水口；12-第二散热器；121-出水口；13-连接板；14-散热水道；20-功率半导体封装；21-第一基板；2101-第一导电板；2102-第二导电板；2103-第一导电层；2104-第一绝缘板；2105-第一铜层；2106-第一导电区域；2107-第二导电区域；22-第二基板；2201-第三导电板；2202-第四导电板；2203-第二导电层；2204-第二绝缘板；2205-第二铜层；2206-第三导电区域；2207-第四导电区域；2208-第五导电区域；2209-焊盘；23-IGBT芯片；24-二极管芯片；25-第一导电衬垫；26-第二导电衬垫；27-接线端子；2701-第一端子；2702-第二端子；28-第一电极端子；29-第二电极端子；210-封装层；211-绑定线；212-导电连接层；213-信号端子；214-第一导电柱；215-第二导电柱；30-导热层；31-金属导热片；32-金属键合线；33-导热胶。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。
现有技术中，双面冷却封装的功率半导体模组通常是将功率半导体封装放置在两个散热器之间，两个散热器通过机械结构压紧连接。然而，通过机械结构压紧散热器的不足在于：不易保证功率半导体模组各位置处受力均匀。例如，采用分布在上下两个散热器之间的多个螺栓，将散热器与功率半导体封装组装而成的功率半导体模组进行固定时，靠近螺栓位置的紧固力一般要大于远离螺栓位置的紧固力，位于不同位置的螺栓所施加的紧固力也难以保证相等，并且散热器、功率半导体封装的固定面难以保证完全平整，以及导热界面材料的涂覆厚度本身也可能存在差异，因此，在散热器与功率半导体封装的固定过程中容易产生应力，容易在电机驱动器整机装配过程中导致功率半导体模组损坏。并且，为了避免导热界面材料损耗失效，此类功率半导体模组通常是在电机驱动器整机装配的同时，对功率半导体模组的各部件进行现场组装，这样不仅组装难度大，加工效率低下，而且无法对功率半导体模组进行预先检验，难以判断功率半导体模组在组装过程中是否存在损坏的情况，若电机驱动器整机测试时，功率半导体模组的散热器因损坏而漏水，则电机驱动器整机将面临报废的风险。
基于此，本申请实施例提供一种功率半导体模组、电机驱动器、动力总成以及功率半导体模组的制造方法。本申请提供的功率半导体模组采用表面具有金属键合线的导热材料或采用可固化硅脂，在散热器与功率半导体封装之间形成具有固定功能、且不易脱落的固态导热层，通过固态导热层将功率半导体封装与散热器固定，可使功率半导体模组各部位受力均匀，降低了功率半导体模组在电机驱动器整机装配过程中造成的应力损坏风险。并且能够在电机驱动器整机装配前实现功率半导体封装与散热器的一体化集成加工，以及功率半导体模组的氦气检验，将检验合格的功率半导体模组整体直接用于电机驱动器整机的装配，避免了功率半导体模组在电机驱动器整机装配时的现场组装工作，降低了电机驱动器在整机测试时，由于散热器漏水而导致电机驱动器整机报废的风险，以及电机驱动器整机的装配难度，提升了电机驱动器整机装配的自动化水平和加工速度。以下分别以不同的实施例为例，对功率半导体模组的具体结构进行介绍。
实施例一
参见图1所示，本申请实施例提供一种功率半导体模组，功率半导体模组可以包括至少一个散热器10，例如，图1中包括两个散热器，分别为第一散热器11和第二散热器12，参见图1所示，功率半导体模组还包括：至少一个功率半导体封装20，例如图1中，功率半导体封装20的数量为三个，三个功率半导体封装20沿着图1中的X方向间隔排布在第一散热器11和第二散热器12之间，各个功率半导体封装20的各个端子沿着图1中的Y方向和-Y方向从第一散热器11和第二散热器12之间向外伸出。当然在一些示例中，功率半导体封装20的数量包括但不限于为三个，还可以为两个或三个以上等。
参见图1和图2所示，功率半导体模组还包括：位于散热器10与功率半导体封装 20之间的导热层30(参见图2)，例如，图1所示的功率半导体模组中，参见图3C所示，在Z方向上分别为第二散热器12、导热层30、功率半导体封装20、导热层30和第一散热器11(参见图3C所示)。
需要说明的是，图2为图1所示的功率半导体模组沿着图1中的Y方向剖开的局部爆炸图。
本申请实施例中，导热层30为表面具有金属键合线32(参见图3B)的导热材料，或者，导热层30为可固化硅脂形成的固态导热层，功率半导体封装20和散热器10分别与导热层30之间形成具有分子键合力或嵌合力的结合力，使得功率半导体封装20和散热器10构成功率半导体模组。
通过将导热层30配置为表面具有金属键合线33的导热材料；或者，所述导热层为可固化硅脂形成的固态导热层，这样导热层30的金属键合线32与散热器10以及所述功率半导体封装20之间在加热、加压下实现键合(bond)连接，使得散热器以及所述功率半导体封装与导热层之间形成具有分子键合力的结合力，或者，所述导热层为可固化硅脂形成的固态导热层，可固化硅脂在散热器以及所述功率半导体封装之间固化时形成相互嵌合的固态导热层，这样，功率半导体封装和所述散热器之间呈固态的导热层具有固定功能并且不易脱落，能够使散热器10与功率半导体封装20之间受力均匀，降低功率半导体模组在电机驱动器整机装配过程中因应力产生而导致损坏的风险。同时，可实现功率半导体封装20与散热器10的一体化集成加工以及功率半导体模组的氦气检验，检验合格的功率半导体模组可直接应用于电机驱动器整机的装配，避免了功率半导体模组在电机驱动器整机装配时的现场组装工作，提升了电机驱动器整机装配的自动化水平和加工速度，降低了电机驱动器在整机测试时因散热器漏水而导致电机驱动器整机报废的风险。
本申请实施例中，导热层30具体以表面具有金属键合线32(参见图3A)的导热材料为例进行说明，例如，参见图3A所示，导热层30包括：金属导热片31和设在金属导热片31表面的金属键合线32。参见图3B所示，金属导热片31的上下两表面均设有金属键合线32，其中，金属键合线32在金属导热片31上呈竖向排布，相邻金属键合线32之间可以具有间隙。
其中，当导热层30位于散热器10和功率半导体封装20之间时，为了实现导热层分别与散热器10和功率半导体封装20的固定作用，所以，需要将散热器10和功率半导体封装20在加热和加压条件下进行处理，在加热和加压条件下，金属键合线32会被压紧，并与散热器10和功率半导体封装20表面的铜层或铝层实现键合连接，使得金属键合线32中金属扩散到散热器10和功率半导体封装20表面的铜层或铝层中，这样，导热层30与散热器10和功率半导体封装20之间形成具有分子键合力的结合力，从而使得散热器10和功率半导体封装20在导热层30的作用下实现牢固相连。
本申请实施例中，金属导热片31可以为铜箔、铝箔、银箔或金箔，当然，金属导热片31还可以为其他金属箔片，金属键合线32可以为纳米铜线、纳米铝线、纳米银线或纳米金线。当然，金属键合线32还可以为其他纳米金属线，本申请实施例中，具体以金属导热片31为铜箔，金属键合线32为纳米铜线为例进行说明。
其中，当金属导热片31为铜箔，金属键合线32为纳米铜线时，铜箔和纳米铜线 组成的导热层也被称为纳米铜魔术贴。这样，纳米铜线中的铜向散热器10、以及功率半导体封装20表面扩散，并与散热器10、以及功率半导体封装20表面的铜层或铝层之间形成结合力较强的分子键合力，可将散热器10与功率半导体封装20牢固的固定。另外，铜箔和纳米铜线均具有良好的导热性能，可极大提升功率半导体模组的散热能力。
其中，金属键合线32在金属导热片31上设置时，可以采用纳米铜线生长工艺在金属导热片31上生长形成金属键合线32，例如，本申请实施例中，当金属键合线32为纳米铜线，金属导热片31为铜箔时，可以通过化学气相沉积法，在铜箔的上下两个表面生长形成纳米铜线。
本申请实施例中，当导热层30为表面具有金属键合线32(参见图3A)的导热材料时，往往需要将散热器10和功率半导体封装20置于高温以及施加较大的压力，以使得金属键合线32与散热器10和功率半导体封装20表面的铜层或铝层实现键合连接，从而达到散热器10以及功率半导体封装20与导热层30之间良好的固定作用。
但是高温和较大的压力使得功率半导体模组的装配难度增加，为此，本申请实施例中，为了降低散热器10、功率半导体封装20与导热层30之间结合所需的温度和压力，参见图3B所示，导热层30还包括：导热胶33，导热胶33分布在相邻金属键合线32之间的间隙中。这样，导热胶33有利于将导热层33与散热器10(例如第一散热器11和第二散热器12)以及功率半导体封装20实现紧密粘合，这样，散热器10以及功率半导体封装20与导热层30在加热、加压条件下实现固定时，在导热胶33的作用下，可以在更低温度和更小压力的工艺条件下,即可实现散热器10以及功率半导体封装20与导热层30之间良好的固定作用，所以，通过设置导热胶，降低了散热器10以及功率半导体封装20与导热层30加热、加压处理时的温度和压力，提升了工艺的良率。
需要说明的是，导热胶33可以为胶状或液态状，所以，导热胶33在金属键合线32之间分布时，导热胶33可以与金属导热片31接触，或者，可以如图3B所示，未加热或加压处理时，导热胶33分布在相邻金属键合线32之间，但未与金属导热片21接触，而在导热层30与散热器10以及功率半导体封装20在加热或加压作用下，最终，导热胶30与金属导热片21紧密接触，从而实现热量的快速传导。
本申请实施例中，导热胶33的种类不作限定，只要具有导热作用且可与散热器10以及功率半导体封装20粘合实现固定的胶水均可选用。
本申请实施例中，参见图1所示，散热器10的数量可以为两个，两个散热器10分别为相对的第一散热器11和第二散热器12，功率半导体封装20设置于第一散热器11与第二散热器12之间，功率半导体封装20朝向第一散热器11的一面与第一散热器11之间设有导热层30，以及，功率半导体封装20朝向第二散热器12的一面与第二散热器12之间也设有导热层30。
将功率半导体封装20设置在第一散热器11与第二散热器12之间，形成具备双面冷却结构的功率半导体模组，热量可由功率半导体封装20的上下两个表面双向传递给第一散热器11和第二散热器12。相比单面冷却结构，在同等工艺条件下双面冷却结构的散热能力更强，有助于充分发挥功率半导体芯片性能，提升产品功率密度，降低 产品成本。
当然，在一些示例中，也可以设置一个散热器10，对功率半导体封装20的单面实现冷却。
本申请实施例中，参见图1所示，第一散热器11和第二散热器12的一端通过连接板13相连，第一散热器11和第二散热器12的另一端通过紧固件连接。当然，在一些示例中，第一散热器11和第二散热器12的另一端也可以不用紧固件进行连接。
在其中一种实施方式中，参见图1-图3C所示，第一散热器11、第二散热器12以及连接板13的内部均设有连通的散热水道14，第一散热器11、第二散热器12的另一端分别设有与散热水道14连通的进水口111、出水口121。
第一散热器11内部的散热水道14与第二散热器12内部的散热水道14通过连接板13内部的散热水道(未示出)连通，第一散热器11和第二散热器12内部的散热水道14构成串联散热水道。
参见图1所示，进水口111与出水口121可以位于散热器10的同侧，冷却液由进水口111进入第一散热器11内部的散热水道14，吸收第一散热器11的热量；再通过连接板13内的散热水道流入第二散热器12的散热水道14，吸收第二散热器12的热量，并最终由出水口121流出将热量带走。
需要说明的是，本申请实施例中，进水口111设在第一散热器11上，出水口121设在第二散热器12上，当然，在一些示例中，进水口111也可以设在第二散热器12上，出水口121设在第一散热器11上。此外，进水口111与出水口121的设置位置包括但不限于图1所示的位置。
在其中一种实施方式中，参见图2、图3C所示，每个功率半导体封装20至少包括第一基板21、第二基板22、至少一个芯片。其中，芯片可以包括IGBT芯片23和二极管芯片24，或者，在一些示例中，芯片还可以为硅(Si)金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)或者碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)。
其中，IGBT芯片23与第一基板21、第二基板22之间构成电路，二极管芯片24与第一基板21、第二基板22之间构成电路，IGBT芯片23与二极管芯片24之间构成并联电路。
本申请实施例中，散热器10与第一基板21和第二基板22中的至少一个之间设有导热层30，导热层30用于将功率半导体封装20产生的热量传递给散热器10。
其中，当芯片为硅金属氧化物半导体场效应晶体管或者碳化硅金属氧化物半导体场效应晶体管时，芯片的设置可参考IGBT芯片23与二极管芯片24的设置方式。
下面描述中主要以芯片包括IGBT芯片23和二极管芯片24为例来进行说明。
在其中一种实施方式中，参见图2-图3C所示，功率半导体封装20还包括至少一个导电衬垫，导电衬垫用于将芯片与第一基板21电连接，例如，参见图2所示，功率半导体封装20包括至少一个第一导电衬垫25和至少一个第二导电衬垫26，导电衬垫起到导电以及支撑第一基板21、第二基板22的作用。
第一导电衬垫25位于IGBT芯片23和第一基板21之间，且第一导电衬垫25的两侧分别通过导电连接层212与IGBT芯片23和第一基板21相连；
第二导电衬垫26位于二极管芯片24和第一基板21之间，且第二导电衬垫26的两侧分别通过导电连接层212与二极管芯片24和第一基板21连接。
本申请实施例中，导电连接层212为具有导电性能的焊料层或烧结层。
在其中一种实施方式中，参见图2-3所示，第一基板21具有相互绝缘的且并列排布的第一导电区域2106和第二导电区域2107；第二基板22具有相互绝缘的且并列排布的第三导电区域2206和第四导电区域2207，第一导电区域2106与第三导电区域2206相对，第二导电区域2107与第四导电区域2207相对。
IGBT芯片23和二极管芯片24的一部分位于第一导电区域2106与第三导电区域2206之间，IGBT芯片23和二极管芯片24的另外一部分位于第二导电区域2107与第四导电区域2207之间。
其中，第一导电区域2106与第三导电区域2206之间通过IGBT芯片23和二极管芯片24导通，第二导电区域2107与第四导电区域2207通过IGBT芯片23和二极管芯片24导通，而为了实现第一导电区域2106、第二导电区域2107、第三导电区域2206和第四导电区域2207导通，所以，第一基板21的第一导电区域2106与第二基板22的第四导电区域2207导通，这样第三导电区域2206、第一导电区域2106、第四导电区域2207、第二导电区域2107导通，其中，IGBT芯片23与二极管芯片24之间为并联。这样，第一基板21中的其中一个导电区域与电极端子的正极电连接，第二基板22中的其中一个导电区域与电极端子的负极电连接后，第三导电区域2206、第一导电区域2106、第四导电区域2207、第二导电区域2107与两个电极端子构成回路，可以同时给多个IGBT芯片和多个二极管芯片24供电。
或者，为了实现第一导电区域2106、第二导电区域2107、第三导电区域2206和第四导电区域2207导通，也可以将第二导电区域2107与第三导电区域2206导通，第一导电区域2106、第三导电区域2206、第二导电区域2107、第四导电区域2207导通。
本申请实施例中，具体是以第一导电区域2106与第四导电区域2207导通为例进行说明，其中，第一导电区域2106与第四导电区域2207之间的导通方式下面进行详细介绍。
在其中一种实施方式中，参见图2-图3C所示，第一基板21包括第一导电层2103和第一绝缘板2104，第一导电层2103位于第一绝缘板2104的朝向IGBT芯片23的一面上。
第二基板22包括：第二导电层2203和第二绝缘板2204，第二导电层2203位于第二绝缘板2204的朝向IGBT芯片23的一面上。
其中，第一导电层2103至少包括第一导电区域2106和第二导电区域2107，第二导电层2203至少包括第三导电区域2206和第四导电区域2207。
第一绝缘板2104、第二绝缘板2204分别用于避免第一导电层2103、第二导电层2203与散热器10导通。
在其中一种实施方式中，参见图2-图3C所示，第一基板21还包括第一铜层2105，第一铜层2105起到保护和导热作用，第一铜层2105位于第一绝缘板2104的朝向导热层30的一面上，例如，参见图3C所示，第一绝缘板2104位于第一铜层2105和第一导电层2103之间，第一铜层2105用于保护第一绝缘板2104，防止第一绝缘板2104 碎裂，同时兼具导热功能。
第二基板22还包括第二铜层2205，第二铜层2205起到保护和导热作用，第二铜层2205位于第二绝缘板的朝向导热层30的一面上，例如，参见图3C所示，第二绝缘板2204位于第二铜层2205和第二导电层2203之间。第二铜层2205用于保护第二绝缘板2204，防止第二绝缘板2204碎裂，同时兼具导热功能。
其中，第二绝缘板2204和第一绝缘板2104可以陶瓷材料，这样第一绝缘板2104、第一铜层2105和第一导电层2103形成的第一基板21，以及第二绝缘板2204、第二铜层2205和第二导电层2203形成的第二基板22均为覆铜陶瓷基板(Direct Bonding Copper，DBC)。
当然，第二绝缘板2204和第一绝缘板2104的材料包括但不限于为陶瓷材料，还可以为其他绝缘材料制成的板材。
散热器10与第一铜层2105和第二铜层2205中的至少一个之间设有导热层30。例如，参见图3C所示，当散热器10的数量为两个时，则其中一个散热器10(例如第一散热器11)与第一铜层2105之间设置导热层30，另一个散热器10(例如第二散热器12)和第二铜层2205之间也设置导热层30。当散热器10的数量为一个时，则散热器10与第一铜层2105之间或散热器10与第二铜层之间设置导热层30。
需要说明的是，设置第一铜层2105和第二铜层2205时，这样当导热层30为纳米铜魔术贴时，这样纳米铜魔术贴表面的纳米铜线中的铜可以向第一铜层2105和/或第二铜层2205扩散，并与第一铜层2105和/或第二铜层2205中的铜形成Cu-Cu金属键的分子键合力，从而使得到导热层30与第一铜层2105和/或第二铜层2205之间的结合力更强，导热层30与第一基板21和/或第二基板22之间不易出现分层而导致导热效果降低的问题。
在其中一种实施方式中，参见图1-4所示，功率半导体封装20还包括接线端子27，接线端子27的一端具有第一端子2701和第二端子2702，第一端子2701和第二端子2702中的其中一个与第一导电区域2106电连接，第一端子2701和第二端子2702中的另一个与第四导电区域2207电连接，这样第一导电区域2106与第四导电区域2207之间通过接线端子27的第一端子2701和第二端子2702导通。
或者，第一端子2701和第二端子2702中的其中一个与第二导电区域2107电连接，第一端子2701和第二端子2702中的另一个与第三导电区域2206电连接，这样第二导电区域2107和第三导电区域2206通过接线端子27的第一端子2701和第二端子2702实现导通。
本申请实施例中，具体以第一端子2701与第一导电区域2106电连接，第二端子2702与第四导电区域2207电连接为例进行说明。
在其中一种实施方式中，参见图2所示，功率半导体封装20还包括第一电极端子28和第二电极端子29，第一电极端子28和第二电极端子29中的其中一个为正极端子，第一电极端子28和第二电极端子29中的另一个为负极端子。
第一电极端子28和第二电极端子29中的其中一个与第一导电区域2106电连接，第一电极端子28和第二电极端子29中的另一个与第四导电区域2207电连接。
或者，第一电极端子28和第二电极端子29中的其中一个与第二导电区域2107 电连接，第一电极端子28和第二电极端子29中的另一个与第三导电区域2206电连接。
本申请实施例中，具体以第一电极端子28为正极端子，且与第三导电区域2206电连接；第二电极端子29为负极端子，且与第二导电区域2107电连接为例进行说明。
在其中一种实施方式中，参见4所示，功率半导体封装20还包括封装层210，第一基板21、第二基板22、至少一个IGBT芯片23、至少一个二极管芯片24位于封装层210内，通过封装层210将第一基板21、第二基板22、IGBT芯片23、二极管芯片24等部件封装为密封的整体结构，使构成的功率半导体封装20中的芯片不易受到水汽或液体的损坏。
其中，导热层30采用纳米铜魔术贴时，为了实现导热层30与功率半导体封装20之间的贴合面产生分子键合力，所以第一基板21和第二基板22朝向导热层30的一面在封装层210处需裸露，使纳米铜魔术贴与第一基板21和第二基板22表面的铜层接触。例如，参见图4所示，封装层210与第一基板21以及第二基板22相对的至少部分区域为裸露区域(例如可以为镂空区域)，这样第一基板21与第二基板22分别朝向导热层30的一面在裸露区域处裸露。这样消除了封装层210的阻挡，使第一基板21和第二基板22分别与导热层30之间直接接触，从而利于热量的传递以及与导热层30紧密结合。
当然，在一些示例中，当散热器10的数量为一个时，可以将封装层210与散热器10相对的一面的至少部分与设置为裸露区域，例如可以将第一基板21相对的封装层210的至少部分区域设置为裸露区域，第一基板21与散热器10之间设置导热层，而封装层210与第二基板22相对的区域为封闭区域。
需要说明的是，图2和图3C示出的功率半导体模组结构为功率半导体模组结构的部分局部结构视图，图2和图3C中未显示封装层210，但是在实际产品中，功率半导体模组的封装层210可以参考图4所示。
本申请实施例中，参见图2所示，第一导电区域2106与第三导电区域2206之间，以及第二导电区域2107与第四导电区域2207之间可以分别具有两个IGBT芯片23和三个二极管芯片24。当然，在一些示例中，IGBT芯片23和二极管芯片24的数量包括但不限于上述个数。
在其中一种实施方式中，参见图1、图2和图4所示，功率半导体封装20还包括信号端子213，信号端子213的一端位于封装层210内且与IGBT芯片23电连接，信号端子213的另一端位于封装层210外(参见图4所示)。
在其中一种实施方式中，参见图2和图3C所示，功率半导体封装20还包括绑定线211，绑定线211例如可以为导线。第二基板22的一端设有焊盘2209，绑定线211的一端与焊盘2209之间通过键合方式实现电连接，绑定线211的另一端与IGBT芯片23之间也可以通过键合方式电连接，信号端子213的一端与焊盘2209电连接，从而使IGBT芯片23与信号端子213导通。
需要说明的是，键合方式为现有的一种将金属线与焊盘之间连接的方式，具体为将金属线利用热、压力或超声波能量使得金属线与焊盘紧密焊合。当然在一些其他示例中，绑定线211的两端与焊盘2209和IGBT芯片23之间也可以采用其他方式电连接，例如通过导电胶水或者熔接方式进行连接。
需要说明的是，参见图3C所示，焊盘2209与第二基板22的第二导电层2203之间间隔开设置，这样确保焊盘2209与第二基板22的第二导电层2203之间相互绝缘。
实施例二
图5A为本申请一实施例提供的功率半导体模组的另一种结构示意图。
本申请实施例与实施例一的区别在于：本申请实施例中，参见图5A所示，第一散热器11和第二散热器12的两端通过连接管相连，例如，参见图5B所示，第一散热器11的一端通过连接管11b与第二散热器12的一端连通，第一散热器11的另一端通过连接管11a与第二散热器12的一端连通。第一散热器11、第二散热器12的内部均设有散热水道14(参见图6)，第一散热器11、第二散热器12中的散热水道14通过连接管11a和连接管11b实现并联，第一散热器11的一端设有进水口111、第二散热器12在远离进水口111的一端上设有出水口121。
冷却时，参见图5B中的箭头所示，冷却液由进水口111进入第一散热器11内部的散热水道14(参见图6所示)，一部分冷却液顺着此沿着图5B中的实线箭头在第一散热器11的散热水道14流动，吸收第一散热器11的热量，并通过邻近出水口121侧的连接管11a进入到出水口121流出将热量带走；另一部分冷却液沿着图5B中的虚线箭头通过邻近进水口111侧的连接管11b进入到第二散热器12内部的散热水道14并沿着第二散热器的散热水道14(参见图6所示)流动，吸收第二散热器12的热量，再进入到出水口121流出将热量带走。
这样第一散热器11内的冷却液对功率半导体封装20的其中一面冷却后从出水口121排出，进水口111进入的部分冷却液直接进入第二散热器12内对功率半导体封装20的另一面冷却，通过连接管11b和连接管11a实现了两个散热器中的散热水道14并联设置，这样实现了对功率半导体封装20两面良好的散热效果，确保了功率半导体模组具有良好的散热能力。
实施例三
图6为本申请一实施例提供的功率半导体模组的另一结构示意图，图7为图6中示出的功率半导体模组装配后的剖面结构示意图。
本申请实施例与上述实施例的区别在于：上述实施例中，IGBT芯片23、二极管芯片24采用正装方式装配，即IGBT芯片23、二极管芯片24的正面朝上，而本申请实施例中，参见图6-图7所示，IGBT芯片23、二极管芯片24采用倒装方式进行装配，即IGBT芯片23、二极管芯片24的正面朝下，其中，第二基板22的一端设有焊盘2209，参见图7所示，IGBT芯片23与焊盘2209电连接(例如采用焊接方式电连接)，即IGBT芯片23与焊盘2209之间未采用绑定线211(参见图2所示)实现电连接。信号端子213的一端与焊盘2209电连接，最终实现IGBT芯片23与信号端子213导通。
本申请实施例中，焊盘2209与第二基板22的第二导电层2203之间隔开设置，确保焊盘2209与第二基板22的第二导电层2203之间相互绝缘设置。
其中，IGBT芯片23、二极管芯片24与第一导电衬垫25、第二导电衬垫26之间的连接方式，以及其他结构均与上述实施例一样，具体可以参考上述实施例，本实施 例不再赘述。
实施例四
图8为本申请一实施例提供的功率半导体模组的另一结构示意图，图9示出了图8中的各个部分装配后的结构示意图。
本申请实施例与上述实施例的区别在于：本申请实施例中，参见图8-图9所示，功率半导体封装20还包括：第一导电柱214和第二导电柱215，第一导电柱214和第二导电柱215分别位于第一基板21和第二基板22之间。
第二基板22还具有第五导电区域2208，参见图8和图9所示，第五导电区域2208与第三导电区域2206和第四导电区域2207均间隔开设置，确保第五导电区域2208与第三导电区域2206和第四导电区域2207之间相互绝缘设置。
接线端子27的第一端子2701和第二端子2702均与第四导电区域2207电连接，第一导电柱214的两端分别与第四导电区域2207和第一导电区域2106电连接，第二导电柱215的两端分别与第二导电区域2107和第五导电区域2208电连接。这样，第一导电区域2106、第二导电区域2107、第三导电区域2206、第四导电区域2207以及第五导电区域2208通过第一导电柱214和第二导电柱215导通。
第一电极端子28和第二电极端子29中的其中一个与第三导电区域2206电连接，第一电极端子28和第二电极端子29中的另一个与第五导电区域2208电连接，例如图8中，第一电极端子28第三导电区域2206电连接，第二电极端子29与第五导电区域2208电连接。
通过第一导电柱214和第二导电柱215使第三导电区域2206、第一导电区域2106、第四导电区域2207、第二导电区域2107、第五导电区域2208导通，并与第一电极端子28、第二电极端子29构成导电回路。
本申请实施例中，其他结构可以参考上述实施例的连接方式，本申请实施例中不再赘述。
实施例五
图10为本申请一实施例提供的功率半导体模组的另一种结构示意图，图11示出了图10中的各个部分装配后的结构示意图。
本申请实施例与上述实施例的区别在于：本申请实施例中，参见图10所示，第一基板21和第二基板22均为导电板，例如，第一基板21和第二基板22可以为铜板。当然，第一基板21和第二基板22也可为其他导电、导热性能较好的金属材料制成的金属导电板。
第一基板21包括：相互绝缘的且并排分布的第一导电板2101和第二导电板2102，第一导电板2101上具有第一导电区域2106，第二导电板2102上具有第二导电区域2107。
第二基板22包括：相互绝缘的且并排分布的第三导电板2201和第四导电板2202，第三导电板2201上具有第三导电区域2206，第四导电板2202上具有第四导电区域2207。
其中，当第一基板21和第二基板22为导电板时，散热器10与第一基板21和/或与第二基板22之间绝缘设置，避免导电板与散热器10导通。
本申请实施例中，为了实现散热器10(例如第一散热器11、第二散热器12)与第一基板21和/或与第二基板22之间绝缘设置，所以，导热层30选用可固化硅脂形成的固态导热层，可固化硅脂为具有粘性的液态材料，在经过预处理、固化处理后可形成具有粘性且稳定的固态导热层，将散热器10牢固的与功率半导体封装20固定，另外，由于硅脂为绝缘材料，所以导热层30起到将第一散热器11、第二散热器12与第一基板21、第二基板22绝缘的作用。
需要说明的是，现有技术中的导热层往往采用硅脂，硅脂与散热器10以及功率半导体封装20之间粘合形成功率半导体模组时，功率半导体模组中的硅脂为非固态状(例如液体或凝胶状)，而本申请实施例中，可固化硅脂具体由硅脂和位于硅脂表面的高分子膜层或者含有高分子材料的液态材料组成，其中，高分子膜层或高分子液体材料中具有可与硅脂发生化学反应而达到固化目的的高分子材料，即，高分子材料为与硅脂发生反应达到固化作用的材料。这样，当可固化硅脂置于散热器10和功率半导体封装20之间后，在加热或加压作用下，高分子膜层中的高分子材料向硅脂中扩散，并与硅脂发生化学反应，使得硅脂达到固化目的。
其中，当导热层30为可固化硅脂形成的固态导热层时，可固化硅脂设置在功率半导体封装20以及与散热器10之间后，可固化硅脂中呈液态状的硅脂会填充在功率半导体封装20以及与散热器10表面细微的凹凸不平的凹坑结构中，这样可固化硅脂固化后，导热层30与功率半导体封装20以及与散热器10(例如第一散热器11或第二散热器12)之间形成相互咬合的嵌合力，从而确保了导热层30与功率半导体封装20以及与散热器10之间牢固且紧密的结合，从而利于热量的快速传导，实现对功率半导体模组的及时散热。
需要说明的是，在一些示例中，也可以将功率半导体封装20和散热器10分别与导热层30接触的一面进行粗糙化处理，从而进一步增强导热层30与功率半导体封装20以及与散热器10之间的嵌合力。
其中，本申请实施例中，由于第二基板22为导电板，所以第二基板22表面不设置焊盘2209，IGBT芯片23与信号端子213通过绑定线211导通，例如，绑定线211的一端与信号端子213通过键合方式电连接，绑定线211的另一端与IGBT芯片23通过键合方式电连接(参见图11所示)，这样IGBT芯片23与信号端子213导通。
实施例六
本申请实施例还提供一种电机驱动器，包括电容和至少一个与电容相连的以上任一实施例中的功率半导体模组。其中，电容具体与功率半导体模组中的第一电极端子28和第二电极端子29电连接。本申请实施例中，功率半导体模组的结构和工作原理可以参考上述实施例的描述，本申请实施例中不再赘述。
本申请实施例提供的电机驱动器，通过包括上述功率半导体模组，降低了功率半导体模组在电机驱动器整机装配过程中造成的应力损坏风险。能够在电机驱动器整机装配前实现功率半导体封装与散热器的一体化集成加工，以及功率半导体模组的氦气 检验，这样可以将散热器漏气的不良产品提前筛选出来，而现有技术中往往将功能半导体封装、散热器先安装到电机驱动器整机中，然后将电机驱动器整机进行氦气检测，这样导致若散热器出现漏气时电机驱动器整机报废，大大增加成本，而本申请实施例中，可以提前对功率半导体模组先进行氦气检测，这样若散热器出现漏气，则只需将功率半导体模组进行替换，不会造成电机驱动器整机报废，所以本申请实施例中，提高了整机二次加工良率。
实施例七
本申请实施例还提供一种动力总成，包括电机和与电机连接的实施例六中的电机驱动器，其中，电机驱动器中的功率半导体模组的结构和工作原理可以参考上述实施例的描述，本申请实施例中不再赘述。
本申请实施例提供的动力总成，通过包括上述功率半导体模组，降低了功率半导体模组在电机驱动器整机装配过程中造成的应力损坏风险。能够在电机驱动器整机装配前实现功率半导体封装与散热器的一体化集成加工，以及功率半导体模组的氦气检验，避免了电机驱动器在整机测试时因散热器漏水而导致电机驱动器整机报废的风险。
实施例八
本申请实施例还提供一种车辆，包括车轮、电机以及与电机连接的实施例六中的电机驱动器，电机通过传动组件与车轮相连。
本申请实施例中，车辆可以为电动车/电动汽车(EV)、纯电动汽车(PEV/BEV)、混合动力汽车(HEV)、增程式电动汽车(REEV)、插电式混合动力汽车(PHEV)、新能源汽车(New Energy Vehicle)等。
其中，电机驱动器中的功率半导体模组的结构和工作原理可以参考上述实施例的描述，本申请实施例中不再赘述。
本申请实施例提供的车辆，通过包括上述功率半导体模组，降低了功率半导体模组在电机驱动器整机装配过程中造成的应力损坏风险。能够在电机驱动器整机装配前实现功率半导体封装与散热器的一体化集成加工，以及功率半导体模组的氦气检验，避免了电机驱动器在整机测试时因散热器漏水而导致电机驱动器整机报废的风险。
实施例九
参见图12所示，本申请实施例还提供了一种功率半导体模组的制造方法，包括如下步骤：
S101：提供至少一个功率半导体封装和散热器；
S102：在功率半导体封装的顶面和/或底面分别设置界面材料；
例如，参见图4所示，可以在功率半导体封装20的顶面界面材料，界面材料可以为表面具有金属键合线的导热材料，或者，界面材料可以为可固化硅脂；这样功率半导体封装20的顶面与散热器10通过界面材料组成整体结构；或者，可以在功率半导体封装20的底面设置界面材料，这样功率半导体封装20的底面与散热器10通过界面材料组成整体结构；或者，可以在功率半导体封装20的顶面和底面分别设置界面材料， 这样功率半导体封装20的顶面和底面分别与散热器10(例如图1中的第一散热器11和第二散热器12)通过界面材料组成整体结构。
S103：将设置有界面材料的功率半导体封装20与散热器10在预设温度和预设压力下压合预设时间，形成功率半导体模组，其中，界面材料在功率半导体封装20与散热器10之间形成呈固态的导热层，其中：
当界面材料为可固化硅脂时，将设置有界面材料的功率半导体封装20与散热器10在预设温度和预设压力下压合预设时间，形成功率半导体模组包括：
将设置有界面材料的功率半导体封装20与散热器10在第一预设压力、第一预设温度的条件下进行第一预设时间的压合预处理；其中，第一预设压力可以为1MPa-3MPa，第一预设温度可以为110℃-130℃，第一预设时间可以为15分钟-25分钟。
将预处理后的功率半导体封装20与散热器10之间在第二预设压力、第二预设温度的条件下进行第二预设时间的固化处理，以使可固化硅脂形成分别与散热器10和功率半导体封装20结合的固态导热层。其中，第二预设压力可以为4MPa-8MPa，第二预设温度可以为170℃-190℃，第二预设时间可以为110分钟-130分钟。
可固化硅脂在经过预处理、固化处理后可形成具有粘性且稳定的固态导热层，将散热器10牢固的与功率半导体封装20固定，形成功率半导体模组。
当界面材料为表面具有金属键合线的导热材料时，在功率半导体封装20的顶面和底面分别设置界面材料之前还包括：
对功率半导体封装20的顶面和/或底面进行去氧化处理；
对散热器10朝向功率半导体封装20的一面形成金属镀层，或者对散热器10朝向功率半导体封装20的一面进行去氧化处理。
去氧化处理使功率半导体封装20的顶面、底面露出金属单质，散热器10朝向功率半导体封装20的一面形成金属镀层可防止氧化层的产生，以便使金属材料能够在散热器10以及功率半导体封装20之间形成具有分子键合力的固态导热层。
若不在散热器10朝向功率半导体封装20的一面施加金属镀层，也可对此面同样进行去氧化处理，使其露出金属单质，也能保证金属材料能够在散热器10以及功率半导体封装20之间形成具有分子键合力的固态导热层。
在本申请实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应作广义理解，例如，可以是固定连接，也可以是通过中间媒介间接相连，可以是两个元件内部的连通或者两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请实施例中的具体含义。
本申请实施例的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。

Claims (26)

  1. 一种功率半导体模组，其特征在于：包括至少一个散热器和至少一个功率半导体封装；
    还包括：导热层，所述导热层位于所述散热器与所述功率半导体封装之间，所述导热层为表面具有金属键合线的导热材料或者由可固化硅脂形成的固态导热层；
    且所述功率半导体封装和所述散热器均与所述导热层结合以构成所述功率半导体模组。
  2. 根据权利要求1所述的功率半导体模组，其特征在于：所述导热层包括：金属导热片和设在所述金属导热片表面的所述金属键合线。
  3. 根据权利要求1或2所述的功率半导体模组，其特征在于：所述金属导热片为铜箔、铝箔、银箔或金箔，所述金属键合线为纳米铜线、纳米铝线、纳米银线或纳米金线。
  4. 根据权利要求1-3任一所述的功率半导体模组，其特征在于：所述导热层还包括：导热胶，所述导热胶分布在相邻所述金属键合线之间的间隙中。
  5. 根据权利要求1-4任一所述的功率半导体模组，其特征在于：所述散热器的数量为两个，两个所述散热器分别为相对的第一散热器和第二散热器，所述功率半导体封装设置于所述第一散热器与所述第二散热器之间，且所述功率半导体封装与所述第一散热器和所述第二散热器之间均设有所述导热层。
  6. 根据权利要求5所述的功率半导体模组，其特征在于：所述第一散热器和所述第二散热器的一端通过连接板相连，所述第一散热器和所述第二散热器的另一端通过紧固件连接；
    或者，所述第一散热器和所述第二散热器的两端通过连接管相连。
  7. 根据权利要求6所述的功率半导体模组，其特征在于：所述第一散热器、所述第二散热器的内部均设有散热水道，所述第一散热器内的所述散热水道和所述第二散热器内的所述散热水道通过所述连接板串联，所述第一散热器、所述第二散热器的另一端分别设有与所述散热水道连通的进水口、出水口；
    或者，所述第一散热器、所述第二散热器的内部均设有散热水道，所述第一散热器内的所述散热水道和所述第二散热器内的所述散热水道通过所述连接管并联，所述第一散热器的一端设有进水口、所述第二散热器在远离所述进水口的一端上设有出水口。
  8. 根据权利要求1-7任一所述的功率半导体模组，其特征在于：每个所述功率半导体封装至少包括第一基板、第二基板、至少一个芯片，所述芯片固定在所述第一基板与所述第二基板之间；
    且所述至少一个芯片与所述第一基板和所述第二基板电连接；
    所述散热器与所述第一基板和所述第二基板中的至少一个之间设有所述导热层。
  9. 根据权利要求8所述的功率半导体模组，其特征在于：所述芯片包括绝缘栅双极型晶体管芯片和二极管芯片；
    或者，所述芯片包括硅金属氧化物半导体场效应晶体管或者碳化硅金属氧化物半 导体场效应晶体管。
  10. 根据权利要求9所述的功率半导体模组，其特征在于，所述功率半导体封装还包括：至少一个导电衬垫，所述导电衬垫位于所述芯片和所述第一基板之间；
    且所述导电衬垫的两端分别通过导电连接层与所述芯片和所述第一基板相连。
  11. 根据权利要求10所述的功率半导体模组，其特征在于：所述第一基板具有相互绝缘的且并列排布的第一导电区域和第二导电区域；
    所述第二基板具有相互绝缘的且并列排布的第三导电区域和第四导电区域，所述第一导电区域与所述第三导电区域相对，所述第二导电区域与所述第四导电区域相对，
    所述芯片的部分位于所述第一导电区域与所述第三导电区域之间，所述芯片的部分位于所述第二导电区域与所述第四导电区域之间；
    且所述第一导电区域与所述第四导电区域导通，或者，所述第二导电区域与所述第三导电区域导通。
  12. 根据权利要求11所述的功率半导体模组，其特征在于：所述第一基板和所述第二基板均为导电板；
    且所述第一基板包括：相互绝缘的且并排分布的第一导电板和第二导电板，所述第一导电板上具有所述第一导电区域，所述第二导电板上具有所述第二导电区域；
    所述第二基板包括：相互绝缘的且并排分布的第三导电板和第四导电板，所述第三导电板上具有所述第三导电区域，所述第四导电板上具有所述第四导电区域；
    且所述散热器与所述导电板之间绝缘设置。
  13. 根据权利要求11所述的功率半导体模组，其特征在于：所述第一基板包括第一导电层和第一绝缘板，所述第一导电层位于所述第一绝缘板的朝向所述芯片的一面上；
    所述第二基板包括：第二导电层和第二绝缘板，所述第二导电层位于所述第二绝缘板的朝向所述芯片的一面上；
    且所述第一导电层至少包括所述第一导电区域和所述第二导电区域，所述第二导电层至少包括所述第三导电区域和所述第四导电区域。
  14. 根据权利要求13所述的功率半导体模组，其特征在于：所述第一基板还包括第一铜层，所述第一铜层位于所述第一绝缘板的朝向所述导热层的一面上；
    所述第二基板还包括第二铜层，所述第二铜层位于所述第二绝缘板的朝向导热层的一面上，所述散热器与所述第一铜层和所述第二铜层中的至少一个之间设有所述导热层。
  15. 根据权利要求11-14任一所述的功率半导体模组，其特征在于：所述功率半导体封装还包括接线端子，所述接线端子的一端具有第一端子和第二端子，所述第一端子和所述第二端子中的其中一个与所述第一导电区域电连接，所述第一端子和所述第二端子中的另一个与所述第四导电区域电连接，以使所述第一导电区域与所述第四导电区域导通；
    或者，所述第一端子和所述第二端子中的其中一个与所述第二导电区电连接，所述第一端子和所述第二端子中的另一个与所述第三导电区域电连接，以使所述第二导电区域和所述第三导电区域导通；
    或者，所述第一端子和所述第二端子均与所述第三导电区域或者均与第四导电区域电连接。
  16. 根据权利要求15所述的功率半导体模组，其特征在于，所述功率半导体封装还包括：第一电极端子和第二电极端子，所述第一电极端子和所述第二电极端子中的其中一个为正极端子，所述第一电极端子和所述第二电极端子中的另一个为负极端子；
    所述第一电极端子和第二电极端子中的其中一个与所述第一导电区域电连接，所述第一电极端子和第二电极端子中的另一个与所述第四导电区域电连接；
    或者，所述第一电极端子和第二电极端子中的其中一个与第二导电区域电连接，所述第一电极端子和第二电极端子中的另一个与第三导电区域电连接。
  17. 根据权利要求16所述的功率半导体模组，其特征在于，所述功率半导体封装还包括：第一导电柱和第二导电柱，所述第一导电柱和所述第二导电柱分别位于所述第一基板和所述第二基板之间；
    所述第二基板还具有第五导电区域，且所述第五导电区域与所述第三导电区域和所述第四导电区域均绝缘设置；
    所述接线端子的所述第一端子和所述第二端子均与所述第四导电区域电连接，所述第一导电柱的两端分别与所述第一导电区域和所述第四导电区域电连接，所述第二导电柱的两端分别与所述第二导电区域和所述第五导电区域电连接；
    所述第一电极端子和第二电极端子中的其中一个与第三导电区域电连接，所述第一电极端子和第二电极端子中的另一个与所述第五导电区域电连接。
  18. 根据权利要求10-17任一所述的功率半导体模组，其特征在于：
    所述功率半导体封装还包括：封装层，所述第一基板、所述第二基板、所述至少一个芯片位于所述封装层内；
    且所述封装层与所述第一基板以及所述第二基板中的至少一个相对的至少部分区域为裸露区域，所述第一基板与所述第二基板中的至少一个的朝向所述导热层的一面在所述裸露区域处裸露。
  19. 根据权利要求18所述的功率半导体模组，其特征在于，所述功率半导体封装还包括：信号端子，所述信号端子的一端位于所述封装层内且与所述芯片电连接，所述信号端子的另一端位于所述封装层外。
  20. 根据权利要求19所述的功率半导体模组，其特征在于，所述功率半导体封装还包括：绑定线，所述绑定线的一端与所述芯片电连接，所述绑定线的另一端与所述信号端子电连接；
    或者，所述第二基板的一端设有焊盘，所述绑定线的另一端与所述焊盘电连接，所述信号端子的一端与焊盘电连接；
    或者，所述第二基板的一端设有焊盘，所述芯片与所述焊盘电连接，所述信号端子的一端与焊盘电连接。
  21. 一种电机驱动器，其特征在于：包括电容和至少一个如权利要求1-20任一所述的功率半导体模组，所述功率半导体模组的电极端子与所述电容电连接。
  22. 一种动力总成，其特征在于：包括电机和与所述电机连接的如权利要求21所述的电机驱动器。
  23. 一种车辆，其特征在于：包括车轮、电机以及与所述电机连接的上述权利要求21所述的电机驱动器，所述电机通过传动组件与所述车轮相连。
  24. 一种功率半导体模组的制造方法，其特征在于：所述方法包括：
    提供至少一个功率半导体封装和散热器；
    在所述功率半导体封装的顶面和/或底面分别设置界面材料，所述界面材料为表面具有金属键合线的导热材料，或者，所述界面材料为可固化硅脂；
    将设置有所述界面材料的所述功率半导体封装与所述散热器在预设温度和预设压力下压合预设时间，形成所述功率半导体模组。
  25. 根据权利要求24所述的功率半导体模组的制造方法，其特征在于，当所述界面材料为可固化硅脂时，所述将设置有所述界面材料的所述功率半导体封装与所述散热器在预设温度和预设压力下压合预设时间，形成所述功率半导体模组，包括：
    将设置有所述界面材料的所述功率半导体封装与所述散热器在第一预设压力、第一预设温度条件下进行第一预设时间的压合预处理；
    将预处理后的所述功率半导体封装与所述散热器之间在第二预设压力、第二预设温度条件下进行第二预设时间的固化处理，以使可固化硅脂形成固态导热层。
  26. 根据权利要求24或25所述的功率半导体模组的制造方法，其特征在于，当所述界面材料为表面具有金属键合线的导热材料时，所述在所述功率半导体封装的顶面和/或底面分别设置界面材料之前还包括：
    对所述功率半导体封装的顶面和/或底面进行去氧化处理；
    对所述散热器朝向所述功率半导体封装的一面形成金属镀层，或者对所述散热器朝向所述功率半导体封装的一面进行去氧化处理。
PCT/CN2021/079309 2021-03-05 2021-03-05 一种功率半导体模组及制造方法 WO2022183486A1 (zh)

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