WO2023221970A1 - 功率模块、电源系统、车辆及光伏系统 - Google Patents

功率模块、电源系统、车辆及光伏系统 Download PDF

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Publication number
WO2023221970A1
WO2023221970A1 PCT/CN2023/094473 CN2023094473W WO2023221970A1 WO 2023221970 A1 WO2023221970 A1 WO 2023221970A1 CN 2023094473 W CN2023094473 W CN 2023094473W WO 2023221970 A1 WO2023221970 A1 WO 2023221970A1
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WIPO (PCT)
Prior art keywords
metal
electrode
power module
metal layer
chip
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Application number
PCT/CN2023/094473
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English (en)
French (fr)
Inventor
郎丰群
李慧
周思展
刘海燕
陈惠斌
吕镇
胡竣富
Original Assignee
华为数字能源技术有限公司
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Publication of WO2023221970A1 publication Critical patent/WO2023221970A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
    • B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
    • B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/327—Means for protecting converters other than automatic disconnection against abnormal temperatures
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
    • H02S40/00—Components or accessories in combination with PV modules, not provided for in groups H02S10/00 - H02S30/00
    • H02S40/30—Electrical components
    • H02S40/32—Electrical components comprising DC/AC inverter means associated with the PV module itself, e.g. AC modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a power module, power supply system, vehicle and photovoltaic system.
  • the electrical connection of the semiconductor chips in the power module is mainly achieved by aluminum wire welding technology.
  • the gate and source of the semiconductor chip are connected to the copper layer on the surface of the substrate through the aluminum wire.
  • the aluminum The number of wires will also increase accordingly. More aluminum wires will increase the parasitic inductance of the power module, and when multiple chips are connected in parallel, the connection of multiple aluminum wires will cause uneven current flow between multiple chips connected in parallel. This will cause uneven heat generation in parallel chips, and local heating will seriously affect the performance of the chip and thus the performance of the power module.
  • This application provides a power module that can reduce parasitic inductance and improve current sharing.
  • the present application provides a power module.
  • the power module includes a first metal-clad substrate, a plurality of chips and a first connecting piece.
  • the first metal-clad substrate includes a first insulating substrate and a A first metal layer on one side of the first insulating substrate, the first metal layer includes a first surface facing away from the first insulating substrate; the chip includes a first electrode and a second electrode, and the plurality of chips are located on The first metal layer is on a side away from the first insulating substrate, and a first electrode of each chip in the plurality of chips is electrically connected to the first metal layer, and at least two of the plurality of chips are The chips are spaced apart along the first direction, and at least two chips among the plurality of chips are spaced apart along the second direction.
  • the second direction and the first direction are both parallel to and intersect the first surface.
  • the first connection piece is located on the side of the plurality of chips away from the first insulating substrate.
  • the first connection piece includes a first body part and a plurality of first contact parts.
  • the second electrode of each chip is in contact with at least one first contact portion, and there is a portion of the first body portion between at least a pair of adjacent first contact portions; the first body portion and the The first metal layer is provided with insulating intervals.
  • the power module includes a plurality of chips arranged along the first direction and along the second direction.
  • the plurality of chips are connected in parallel through a first connecting piece.
  • multiple chips in parallel will generate an inductance.
  • at least one pair of phase There is a part of the first body part between adjacent first contact parts.
  • the connecting piece can also increase the structural reliability of interconnection of multiple chips along the first direction and the second direction to ensure the stability of current transmission.
  • the first body part and the second electrode of the chip are isolated along the thickness direction of the chip, and the first connecting piece includes one or more grooves, The groove protrudes from the first body part toward the first surface, and the bottom of the groove is the first contact part. between the first body part and the second electrode of the chip are isolated from each other, and the groove protrudes from the first body part toward the first surface, so that the first body part is above the second electrode of the chip, so as to improve the electrical insulation between the first body part and the first metal layer.
  • the first connecting piece includes one or more bending structures, and the bending structure includes the first contact portion that is in contact with the second electrode of the chip.
  • the bending structure refers to a structure that is bent toward the first surface. One end of the bending structure away from the first main body protrudes toward the first surface.
  • the first contact portion is the protruding portion.
  • the first contact portion and the second The electrodes are in contact, so that the first body part is located above the second electrode, so as to improve the electrical insulation between the first body part and the first metal layer.
  • the first connecting piece is an integrally formed structure.
  • the one-piece structure can improve the smoothness of current flow, reduce current flow resistance, improve current sharing and reduce inductance, and can also improve the reliability of the first connecting piece.
  • each first contact part is directly connected to the first body part, so that the current flowing out from the second electrode of each chip directly flows into the first body part through the first contact part, strengthening the first direction and the second body part.
  • the connection between multiple chips arranged in different directions improves the consistency of parasitic parameters between parallel chips, thereby optimizing the dynamic current sharing between multiple chips in parallel.
  • the first contact portion is distributed on an edge of the first main body portion.
  • the edge distribution area of the first main body part is large, and more first contact parts can be distributed, thereby allowing more chips to be connected in parallel, thereby increasing the power density of the power module.
  • the power module includes two first chip subgroups spaced apart along the first direction, the first chip subgroup includes at least two chips spaced apart along the second direction, and the first chip subgroup includes at least two chips spaced apart along the second direction.
  • the main body includes a first trunk and a plurality of first branches, the first trunk extends along the second direction, the first branches are located on both sides of the first trunk along the first direction and are connected to the first trunk; in the first direction, the first branches The trunk is located between two adjacent first chip subgroups, the first branch is located between two adjacent first contact portions in the second direction, and the first branch is connected to the two adjacent first contact portions along the second direction. The first contact portion is connected, and the first trunk is electrically connected to the second metal layer.
  • each first chip subgroup has at least two chips
  • the first connecting piece connects the chips in the two first chip subgroups to connect the two first chip subgroups. Chips in a chip subgroup are connected in parallel.
  • the first branch connects the first contact portions on two adjacent chips arranged along the second direction, and at least part of the current coming out of the two first contact portions can flow into the first trunk through the first branch,
  • the first branch is directly connected between the two first contact parts, which can shorten the parallel path of two adjacent chips and improve current sharing.
  • At least part of the first contact portion is spaced apart from the first trunk.
  • the first contact portions on the chips at both ends of the first chip subgroup can be spaced apart from the first trunk, thereby reducing the weight of the first connection piece.
  • the power module further includes a second metal layer, the first metal layer and the second metal layer are located on the same side of the first insulating substrate, and the first metal layer and The second metal layer is spaced apart from its orthogonal projection on the first insulating substrate.
  • the first connecting piece further includes a second contact portion, and the second contact portion is electrically connected to the second metal layer.
  • the combined current in the first body part can flow into the second metal layer through the second contact part.
  • the direction of current flow is in sequence: the input terminal, the first metal layer, the first electrode of the chip, the second electrode of the chip, the first contact part, the first body part, the second contact part, and the second metal layer.
  • the first contact portion adjacent to the second contact portion is also connected to the second contact portion. This allows the current flowing out of the first contact part to flow directly into the second contact part without bypassing, thereby reducing current resistance and shortening the current flow path, thereby reducing inductance.
  • the first contact portion adjacent to the second contact portion is also connected to the first trunk.
  • the first contact part is connected to the first trunk with no gap between the two, so that the current flowing out of the first contact part can flow directly into the first trunk without a bypass, thereby reducing current resistance and shortening the current flow path, thereby reducing inductance.
  • the first contact part is connected to the second contact part and the first trunk, thereby further reducing inductance and improving current sharing.
  • the first contact part, the second contact part and the first body part are an integrally formed structure.
  • the second contact portion is a groove or a bending structure of the first connecting piece protruding from the first body portion to the second metal layer.
  • the one-piece structure improves the reliability of the first connecting piece and reduces the current flow resistance between the first contact part, the second contact part and the first body part, thereby reducing inductance and improving current sharing.
  • the first connecting piece is an integrally formed rectangular sheet structure.
  • the first contact part is a groove or a bending structure protruding from the first body part to the chip
  • the second contact part is a groove or bending structure protruding from the first body part to the second metal layer.
  • the one-piece rectangular sheet structure can make the chips in the two first chip subgroups more closely arranged, improve the current sharing between parallel chips, and effectively reduce parasitic inductance.
  • the power module includes two sets of chipsets arranged in series, namely a first chipset and a second chipset.
  • the first chipset is located on a side of the first metal layer away from the first insulating substrate.
  • the second chipset is located on the side of the second metal layer away from the first insulating substrate.
  • the power module also includes a second connecting piece.
  • the second connecting piece is located on the side of the second chipset away from the first insulating substrate.
  • the second chipset Multiple chips are connected in parallel through the second connecting piece. Two sets of chipsets arranged in series can increase the power density of the power module.
  • the power module further includes a second metal-clad substrate and electronic components, the second metal-clad substrate is located on the first surface, and the electronic components are located on the The side of the second metal-clad substrate is away from the first metal-clad substrate and is electrically connected to the second metal-clad substrate.
  • the electronic components are directly welded to the first metal-clad substrate, an insulating trench needs to be opened on the metal layer of the first metal-clad substrate, and the two ends of the electronic components
  • the electrodes are electrically connected to the metal layers on both sides of the insulating trench. Opening the insulating trench on the first metal-clad substrate will reduce the layout space of the chips, and the first metal-clad substrate is equipped with more chips. Etching grooves in the metal layer on the metal-clad substrate may damage pre-arranged chips or other electronic devices.
  • the electronic components are transferred through the second metal-clad substrate, so that the welding process of the electronic components is simple.
  • the step of opening an insulating trench on the metal layer of the first metal-clad substrate makes the circuit design on the first metal-clad substrate simpler, and can be based on the size of the electronic component and the positions of the two electrodes of the electronic component in advance.
  • An insulating trench is provided on the second metal-clad substrate. The insulating trench is etched on the second metal-clad substrate without affecting the performance of the chip on the first metal-clad substrate.
  • the electronic components are then connected to the second metal-clad substrate.
  • the metal-clad substrate is electrically connected.
  • the chip further includes a third electrode
  • the electronic component is a gate resistor
  • the second metal-clad substrate is located on the first surface
  • the second metal-clad substrate The layer substrate includes a fourth electrode and a fifth electrode arranged at insulating intervals, two ends of the gate resistor are electrically connected to the fourth electrode and the fifth electrode respectively, and the fourth electrode is used to receive a driving current
  • the fifth electrode is electrically connected to the third electrode of the chip through a first conductive line.
  • the second metal-clad substrate is used to transfer the gate resistor, making the process of welding the gate resistor simple.
  • the first metal layer is connected to the first insulating substrate through a metal welding layer;
  • the second metal-clad substrate further includes The second insulating substrate, the fourth electrode and the fifth electrode are attached to the surface of the second insulating substrate.
  • the side of the first insulating substrate facing the chip has two metal layers, and the two metal layers are respectively a metal welding layer and a first metal layer. If the electronic components are directly welded to the first metal-clad substrate, since the electronic components need to carry current, two sixth electrodes and seventh electrodes arranged at insulating intervals need to be provided on the first metal-clad substrate. Part of the fourth metal layer and part of the metal welding layer between the sixth electrode and the seventh electrode are removed through an etching process.
  • the larger size etched along the third direction will increase the aperture of the second trench, or It is said that the larger the size between the sixth electrode and the seventh electrode, and the smaller the size of electronic components (such as gate resistors), they cannot be welded on the sixth electrode and the seventh electrode, or the welding reliability will be poor.
  • the board is connected to an electronic component, wherein the metal on the second metal-clad substrate is directly bonded to the second insulating substrate, so that the formed fourth electrode and fifth electrode are also directly attached to the surface of the second insulating substrate, There is no metal welding layer between the fourth electrode and the fifth electrode and the second insulating substrate.
  • the gap between the fourth electrode and the fifth electrode is The size can be controlled small, which is beneficial to soldering electronic components (such as gate resistors).
  • the first metal-clad substrate is an active metal welding substrate.
  • Active metal welding substrate refers to welding metal layers such as copper or aluminum layers to both sides of the insulating substrate through metal solder.
  • the first metal layer, the second metal layer, and the first end metal can be formed by etching the copper layer. layers, terminal metal layers and other circuits required for power modules.
  • the material of the first insulating substrate in the first metal-clad substrate can be iN or AlN, which makes the welding reliability of the first insulating substrate and the metal plates on both sides stronger and has better thermal conductivity, which can improve the power module. The heat dissipation effect.
  • the second metal-clad substrate is a copper-clad ceramic substrate.
  • the second insulating substrate is an Al 2 O 3 ceramic substrate or an AlN ceramic substrate, and a metal layer (such as copper foil) is directly bonded to the second insulating substrate at high temperature.
  • a metal layer such as copper foil
  • the copper foil is directly bonded to the Al 2 O 3 ceramic substrate at high temperature, and then the copper foil is used to form the fourth electrode and the fifth electrode as needed. There is no electrode between the copper foil and the Al 2 O 3 ceramic substrate.
  • Other metal layers can make the distance between the fourth electrode and the fifth electrode smaller, which is beneficial to welding the gate resistor.
  • the thickness of the first metal layer and the second metal layer is greater than or equal to 0.6 mm.
  • the first metal layer has a higher power density and can quickly transmit current to multiple chips connected in parallel.
  • the value is within the above range, it can also improve the thermal conductivity of the first metal-clad substrate, thereby improving the heat dissipation effect of the power module, allowing the second metal layer to have a higher power density and quickly transmit current to the second chip. Multiple chips connected in parallel in a group. The larger the thickness of the first metal layer and the second metal layer, the better the heat dissipation effect and the greater the power density.
  • the thicker the first metal layer and the second metal layer the greater the thickness will be when etching the insulating trench.
  • the larger the size of the insulation trench the smaller the size of electronic components (such as gate resistors). Welding the electronic components across the trench to the two electrodes will increase the process difficulty. Based on this, when increasing the power density of the power module, By providing a second metal-clad substrate, the process difficulty of welding electronic components can be reduced.
  • the first metal-clad substrate is an insulating metal substrate.
  • the insulating metal substrate includes an insulating resin layer and metal layers located on both sides of the insulating resin layer.
  • the metal layer on one side is etched into a required circuit according to electrical interconnection requirements, including forming a first metal layer and a second metal layer.
  • the metal layer When the metal layer When the thickness of the layer is greater than or equal to 0.6mm, the power module has a higher power density.
  • the second metal-clad layer substrate can be provided to transfer the electronic components to reduce the process difficulty of welding the electronic components.
  • the electronic component is a thermistor
  • the second metal-clad substrate is located on a side of the first metal layer away from the first insulating substrate and adjacent to the chip.
  • the thermistor is used to monitor the temperature of the chip.
  • the second metal-clad substrate and the chip connected to the thermistor are located on the first metal layer, which can improve the accuracy of detecting the temperature of the chip.
  • the power module further includes a heat sink located on a side of the first metal-clad substrate away from the chip, and the heat sink and the first metal-clad substrate A plurality of spaced support components are arranged between the layer substrates.
  • the heat sink can be welded to the side of the first metal-clad substrate away from the chip through the seventh solder. Compared with using thermal conductive silicone to bond the heat sink to the first metal-clad substrate, welding In this way, the thermal conductivity of welding materials is better than that of thermal conductive silica gel.
  • the heat sink and the first metal-clad substrate need to apply pressure, and the support assembly can prevent the seventh solder between the first metal-clad substrate and the heat sink, because The added pressure causes the molten seventh solder to be extruded during welding, and the thickness of the seventh solder is too thin, resulting in failure. effect.
  • the support component may be bonded on the surface of the heat sink facing the first metal-clad substrate, or the support component may be bonded on the surface of the first metal-clad substrate facing the heat sink.
  • the supporting component may be a metal wire or a metal strip.
  • the support component can also be used to control the thickness of the seventh solder, and the thickness of the support component can be designed as needed so that the seventh solder meets the demand.
  • the support assembly includes two parallel support bars, the support bars include at least two support segments, and two adjacent support segments are arranged along the extension direction of the support bars. And the interval is set.
  • the seventh solder is filled between two parallel support bars, the seventh solder is not easily extruded during pressure welding, but bubbles will be generated during high-temperature welding, and if the bubbles do not overflow, they will form pores in the welding layer, affecting the Welding reliability.
  • intervals between support sections By setting intervals between support sections, the overflow of bubbles can be promoted and pores can be reduced.
  • two parallel support bars can be used to enhance the support strength of the first metal-clad substrate and the heat sink.
  • this application provides a power supply system.
  • the power supply system includes a power supply, electrical equipment and a power module as described in any one of the above.
  • the power supply is connected to the input end of the power module.
  • the user is connected to the output end of the power module.
  • the power module is used to convert the direct current output by the power supply into alternating current and transmit the alternating current to the electrical equipment.
  • the power module is a semiconductor device that converts the voltage, current, cycle number, etc. of the DC power output by the power supply. It is the core device of the power supply system for power conversion.
  • the power supply system can be used as the core device for converting DC to AC in the motor control unit of an electric vehicle, outputting DC power as the battery of the electric vehicle, or converting DC power into AC power required for vehicle operation, etc.
  • the present application provides a vehicle, which includes a vehicle body and a power supply system as described above, and the power supply system is installed on the vehicle body.
  • the power supply system includes an inverter.
  • the inverter is provided with a power module and a control circuit.
  • the control circuit is electrically connected to the power module.
  • the control circuit can control the AC power output by the power module to the motor according to the needs of the vehicle. Performance parameters, such as voltage, current, cycle number, frequency, etc.
  • the present application provides a photovoltaic system, which is characterized in that it includes a photovoltaic component and a power module as described in any one of the above, the photovoltaic component is electrically connected to the power module, and the direct current generated by the photovoltaic component Converted into alternating current by the power module.
  • Figure 1 is a schematic structural diagram of a power supply system provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a vehicle provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of a photovoltaic system provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a power module provided by an embodiment of the present application.
  • Figure 5 is a cross-sectional view of a power module provided by an embodiment of the present application.
  • Figure 6 is a cross-sectional view of a chip and a first metal-clad substrate in a power module provided by an embodiment of the present application;
  • Figure 7 is a schematic structural diagram of a power module provided by an embodiment of the present application with the first connecting piece removed;
  • Figure 8 is a schematic structural diagram of the first connecting piece provided by an embodiment of the present application.
  • Figure 9 is a schematic structural diagram of the first connecting piece provided by an embodiment of the present application.
  • Figure 10 is a schematic structural diagram of the first connecting piece provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of the first connecting piece provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of a power module provided by an embodiment of the present application.
  • Figure 13 is a schematic structural diagram of a second connecting piece provided by an embodiment of the present application.
  • Figure 14 is a schematic structural diagram of a power module provided by an embodiment of the present application.
  • Figure 15 is a schematic structural diagram of a power module provided by an embodiment of the present application.
  • Figure 16 is a partial enlarged view of part M in Figure 15 of the present application.
  • Figure 17 is a partial cross-sectional view of a power module provided by an embodiment of the present application.
  • Figure 18 is a schematic structural diagram of the second metal-clad substrate and the first metal-clad substrate in the power module provided by an embodiment of the present application;
  • Figure 19 is a schematic structural diagram of directly welding a gate resistor onto a first metal-clad substrate according to an embodiment of the present application
  • Figure 20 is a partial enlarged view of part N in Figure 15 of the present application.
  • Figure 21 is a partial cross-sectional view of a power module provided by an embodiment of the present application.
  • Figure 22 is a schematic structural diagram of directly welding the thermistor to the first metal-clad substrate according to an embodiment of the present application
  • Figure 23a is a schematic structural diagram of a radiator and support assembly provided by an embodiment of the present application.
  • Figure 23b is a schematic structural diagram of a radiator and support assembly provided by an embodiment of the present application.
  • Figure 24 is a 3D-x-ray diagram of the welding surface between the heat sink and the first metal-clad substrate in the power module provided by an embodiment of the present application;
  • Figure 25 is a flow chart of a manufacturing method of a power module provided by an embodiment of the present application.
  • Figure 26 is a schematic diagram of the process of mounting a chip on a first metal-clad substrate according to an embodiment of the present application
  • Figure 27 is a schematic diagram of the process of mounting a chip on a first metal-clad substrate according to an embodiment of the present application
  • Figure 28 is a schematic structural diagram of a pressurizing head and a chip provided by an embodiment of the present application.
  • Figure 29 is a schematic structural diagram of a welding fixture and a power module provided by an embodiment of the present application.
  • Figure 30 is a schematic structural diagram of a power module provided by an embodiment of the present application.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field-effect transistor.
  • IGBT Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor.
  • the present application provides a power module, which includes a first metal-clad substrate, a plurality of chips and a first connecting piece.
  • the first metal-clad substrate includes a first insulating substrate and a first metal located on one side of the first insulating substrate.
  • the first metal layer includes a first surface facing away from the first insulating substrate;
  • the chip includes a first electrode and a second electrode, and the plurality of chips are located on the first metal layer away from the first one side of the insulating substrate, and the first circuit of each chip in the plurality of chips
  • the pole is electrically connected to the first metal layer, at least two chips among the plurality of chips are spaced apart along the first direction, and at least two chips among the plurality of chips are spaced apart along the second direction, so The second direction and the first direction are both parallel to and intersect the first surface;
  • the first connecting piece is located on a side of the plurality of chips away from the first insulating substrate, and the first connecting piece includes a first body and a plurality of first contact portions, the second electrode of each chip in the plurality of chips is in contact with at least one of the first contact portions, and at least a pair of adjacent first contact portions have a portion of The first main body part is insulatingly spaced from the first metal layer.
  • the first connecting piece disposes part of the first body part between the first contact parts connected to the chip, so that the current flowing out from the second electrode of the chip can directly flow into the first body part through the first contact part, reducing the current flow. path, connecting each chip in parallel through the first connecting piece, which can reduce the winding length when interconnecting the chips, thereby reducing the parasitic inductance of the power module; and the first connecting piece can be connected to each chip, and the third
  • the connecting piece has a wide flow path and low current flow resistance, which can improve the current sharing among the chips of the power module.
  • the power supply system 1 includes a power module 10, a power supply 11 and an electrical device 12.
  • the power supply 11 is connected to the input end 101 of the power module 10.
  • the electrical device 12 and The output end 102 of the power module 10 is connected, and the power module 10 is used to convert the DC power output by the power supply 10 into AC power, and transmit the AC power to the electrical equipment 12 .
  • the power module 10 is a semiconductor device that converts the voltage, current, cycle number, etc. of the DC power output by the power supply 11, and is the core device of the power supply system 1 for power conversion.
  • the power supply system 1 can be used as a core device for converting DC to AC in a motor control unit of an electric vehicle, outputting DC power as a battery of an electric vehicle, or converting DC power into AC power required for vehicle operation, etc.
  • FIG. 2 shows a vehicle 2 according to an embodiment of the present application.
  • the vehicle 2 includes a vehicle body 21 and a power supply system 1 as described above.
  • the power supply system 1 is installed on the vehicle body 21 .
  • the power supply system 1 provides a power source for the vehicle 2.
  • the power supply system 1 in this application has a high power density, and its application in the vehicle 2 can improve the power performance of the vehicle 2.
  • the vehicle 2 includes a car (as shown in Figure 2).
  • the vehicle 2 includes an electric vehicle or a special work vehicle.
  • the electric vehicle includes a two-wheeled, three-wheeled or four-wheeled electric vehicle.
  • the special work vehicle includes various types of electric vehicles.
  • the power source 11 is a battery in the vehicle 2
  • the electrical device 12 is a motor in the vehicle 2
  • the power system 1 includes an inverter (not shown in the figure), the inverter is provided with a power module 10 and a control circuit (not shown in the figure), and the control circuit is electrically connected to the power module 10,
  • the control circuit can control the performance parameters of the AC power output by the power module 10 to the motor according to the needs of the vehicle 2, such as voltage, current, number of cycles, frequency, etc.
  • the power module 10 of the present application can also be used in the photovoltaic system 3.
  • Figure 3 shows the photovoltaic system 3 provided by an embodiment of the present application.
  • the photovoltaic system 3 includes a photovoltaic component 31 and a power module 10.
  • the photovoltaic component 31 and The power module 10 is electrically connected, and the DC power generated by the photovoltaic module 31 is converted into AC power by the power module 10 .
  • the AC power output by the power module 10 is transmitted to electrical equipment, such as base stations, data centers, etc.
  • the photovoltaic component 31 includes at least one photovoltaic panel 32 , and the photovoltaic panel 32 is connected to the power module 10 .
  • the photovoltaic module 31 includes a plurality of photovoltaic panels 32 connected in series. Through the series connection, the direct current of the multiple photovoltaic panels 32 is collected and then connected to the power module 10 through a connector.
  • the photovoltaic system 3 includes an inverter (not shown in the figure), the inverter is provided with a power module 10 and a control circuit (not shown in the figure), and the control circuit is electrically connected to the power module 10,
  • the control circuit can control the performance parameters of the alternating current output by the power module 10 according to the needs of the electrical equipment, such as voltage, current, number of cycles, frequency, etc.
  • FIG. 4 is a schematic structural diagram of the power module 10 provided by an embodiment of the present application.
  • FIG. 5 is a cross-sectional view of the power module 10 provided by an embodiment of the present application.
  • the power module 10 includes a first metal-clad substrate 100, A plurality of chips 200 and a first connecting piece 300, wherein the first metal-clad substrate 100 includes a first insulating substrate 110 and a first metal layer 120 and a second metal layer 130 located on the same side of the first insulating substrate 110.
  • the first metal layer 120 and the second metal layer 130 are located on the same side of the first insulating substrate 110 , and the first metal layer 120 and the second metal layer 130 are insulatingly spaced, wherein the first metal layer 120 includes a first metal layer facing away from the first insulating substrate 110 .
  • Surface 121 The first metal layer 120 and the second metal layer 130 are located on the same side of the first insulating substrate 110 , and the first metal layer 120 and the second metal layer 130 are insulatingly spaced, wherein the first metal layer 120 includes a first metal layer facing away from the first insulating substrate 110 .
  • Surface 121 is insulatingly spaced
  • the chip 200 includes a first electrode 210 and a second electrode 220 (as shown in FIG. 6 ).
  • the multiple chips 200 are located on a side of the first metal layer 120 away from the first insulating substrate 110 , and each of the multiple chips 200
  • the first electrode 210 of one chip 200 is electrically connected to the first metal layer 120.
  • At least two chips 200 of the plurality of chips 200 are arranged at intervals along the first direction X (as shown in FIG. 4).
  • At least two chips 200 are arranged at intervals along the second direction Y, and the second direction Y and the first direction X are both parallel to the first surface 121 and intersect.
  • the first connecting piece 300 is located on a side of the plurality of chips 200 away from the first insulating substrate 110 .
  • the first connecting piece 300 includes a first main body part 310 and a plurality of first contact parts 320 .
  • the first contact portion 320 is electrically connected to the first main body portion 310 , the second electrode 220 of each chip 200 in the plurality of chips 200 is in contact with at least one first contact portion 320 , and at least one pair of adjacent first contact portions 320 is in contact with the first contact portion 320 .
  • the first metal-clad substrate 100 includes a first insulating substrate 110 and metal layers located on both sides of the first insulating substrate 110 .
  • the metal layers on both sides are insulated by the first insulating substrate 110 and located on the same side of the first insulating substrate 110
  • the metal layer includes the first metal layer 120 and the second metal layer 130 .
  • the first metal layer 120 and the second metal layer 130 are located on the same side of the first insulating substrate 110, and the orthographic projections of the first metal layer 120 and the second metal layer 130 on the first insulating substrate 110 are spaced apart, so that the first metal layer 120 and the second metal layer 130 are spaced apart from each other.
  • the layer 120 and the second metal layer 130 are insulatingly spaced.
  • the first metal layer 120 and the second metal layer 130 can be insulated by a first trench 105 (as shown in FIG. 4 ), blocking current transmission between the first metal layer 120 and the second metal layer 130 . ;
  • the first trench 105 may be filled with an insulating medium.
  • the first body part 310 is also electrically connected to the second metal layer 130 for transmitting the current introduced by the first body part 310 to the second metal layer 130 or for passing the current in the second metal layer 130 through the first metal layer 130 .
  • the connecting piece 300 is transferred into the chip 200 .
  • the size and location of the first metal layer 120 and the second metal layer 130 can be set as needed.
  • a plurality of chips 200 are disposed on the first metal layer 120.
  • the first metal layer 120 has a larger area and occupies most of the area of the first metal-clad substrate 100.
  • the second metal layer 130 For connecting the connection terminals of the power module 10, the second metal layer 130 can be disposed at the edge of the first metal-clad substrate 100.
  • the chip 200 includes a first electrode 210 , a second electrode 220 , a third electrode 230 and a chip body 240 .
  • the first electrode 210 , the second electrode 220 and the third electrode 230 are located on the chip body 240 .
  • the chip 200 is a MOSFET
  • the first electrode 210 of the chip 200 is the drain of the MOSFET
  • the second electrode 220 of the chip 200 is the source of the MOSFET
  • the third electrode 230 of the chip 200 is the gate of the MOSFET.
  • the first electrode 210 of the chip 200 is the collector of the IGBT
  • the second electrode 220 of the chip 200 is the emitter of the IGBT
  • the third electrode 230 of the chip 200 is the gate of the IGBT.
  • the third electrode 230 (gate) receives a driving signal
  • conduction between the first electrode 210 (drain) and the second electrode 220 (source) is controlled.
  • the first electrode 210 of the chip 200 is electrically connected to the first metal layer 120 so that the current of the first metal layer 120 can be transmitted to the inside of the chip body 240 through the first electrode 210 and to the second electrode 220 .
  • the first electrode 210 is located on the surface of the chip body 240 adjacent to the first metal layer 120
  • the second electrode 220 is located on the surface of the chip body 240 away from the first metal layer 120
  • the third electrode 230 and the second electrode The chip body 240 is disposed at 220 on a side away from the first metal layer 120 , in which the third electrode 230 and the second electrode 220 are insulated and spaced apart.
  • the material of the chip body 240 is SIC (silicon carbide).
  • SIC can increase the operating frequency of the chip 200 and reduce the volume of the chip 200 while meeting the same operating frequency, so that the first metal-clad substrate 100 can More space can be reserved for installing electronic components of the power module 10 , such as thermistors, gate resistors, etc., and the higher the operating frequency of the chip 200 , the lower the cost of peripheral electronic components of the power module 10 such as capacitors, coils, etc. volume of.
  • the higher the working frequency of the chip 200 and the higher the power the current sharing among the multiple chips 200 in the power module 10 is difficult to control, and there is a risk of causing the power module 10 to fail. For this reason, this application has a method that can improve the power module 10 The first connection piece 300 for current equalization.
  • the first connecting piece 300 in this application includes a first main body part 310 and a plurality of first contact parts 320 electrically connected to the first main body part 310.
  • the multiple chips 200 in the power module 10 pass through the first main body part 310.
  • a connecting piece 300 realizes parallel connection, wherein a pair of adjacent first contact portions 320 refers to two adjacent first contact portions 320, and at least a pair of adjacent first contact portions 320 has a portion of the first body portion between them. 310, so that the current flowing out from the first contact part 320 can directly flow into the first body part 310, reducing the current flow path to reduce the inductance.
  • first body portion 310 there is a portion of the first body portion 310 between each pair of adjacent first contact portions 320, so that the current flowing out of each first contact portion 320 can directly flow into the first body portion 310. Further, Reduce the current flow path to reduce inductance.
  • the first body part 310 there is a part of the first body part 310 between the two first contact parts 320 arranged along the first direction X, which can allow the two first contact parts 320 arranged along the first direction X to flow out.
  • the current flows directly into the first main body part 310, reducing the current flow path.
  • the second electrode of the chip 200a is in contact with the first contact portion 320a
  • the second electrode of the chip 200b is in contact with the first contact portion 320b.
  • the first contact portion 320a and the first contact portion 320b are a pair of adjacent first contact portions.
  • a contact portion with a portion of the first body portion 310 between the first contact portion 320a and the first contact portion 320b, so that the current flowing out of the chip 200a directly flows into the first body portion 310 through the first contact portion 320a, and the chip 200b
  • the outgoing current flows directly into the first body part 310 through the first contact part 320b, thereby reducing the current flow paths of the chip 200a and the chip 200b.
  • the first body portion 310 There is a portion of the first body portion 310 between the two first contact portions 320 arranged along the second direction Y, so that the current flowing out of the two first contact portions 320 arranged along the second direction Y can directly flow into the first In the main body part 310, the current flow path is reduced.
  • the second electrode of the chip 200a is in contact with the first contact portion 320a
  • the second electrode of the chip 200c is in contact with the first contact portion 320c.
  • the first contact portion 320a and the first contact portion 320c are a pair of adjacent third contact portions.
  • a contact portion with a portion of the first body portion 310 between the first contact portion 320a and the first contact portion 320c, so that the current flowing out of the chip 200a directly flows into the first body portion 310 through the first contact portion 320a, and the chip 200c
  • the outgoing current flows directly into the first body part 310 through the first contact part 320c, thereby reducing the current flow path between the chip 200a and the chip 200c.
  • the first body part 310 Since the first body part 310 has a wide circulation path, when the current flowing out of each chip 200 is directly introduced into the first body part 310, the circulation path is short and the parasitic inductance can be reduced. Each chip 200 is connected in parallel to the first connecting piece 300. On the other hand, the distribution of chips 200 is concentrated, which can improve the current sharing among the chips 200 .
  • the power module 10 also includes an input terminal 101 and an output terminal 102 (as shown in FIG. 4 ).
  • the input terminal 101 is used to input current, and the input terminal 101 is electrically connected to the first metal layer 120 .
  • the input terminal 101 inputs current as needed, the current flows into the chip 200 through the first metal layer 120.
  • the first contact portion 320 is used to connect the second electrode to the second electrode 220.
  • the current of the electrode 220 is merged into the first main body part 310.
  • the first main body part 310 is used to transmit the merged current to the second metal layer 130, and flow into the output terminal 102 through the second metal layer 130.
  • 102 flows out of the power module 10 .
  • the current flow directions are: input terminal 101, first metal layer 120, first electrode 210 of chip 200, second electrode 220 of chip 200, first contact portion 320, first body portion 310, second metal layer 130, Output 102.
  • the length of each first contact part 320 needs to be increased to make the first contact
  • the portion 320 is connected to the second metal layer 130, and the length of each first contact portion 320 is increased, so that the wiring of the plurality of first contact portions 320 is increased,
  • the parasitic inductance will be enhanced; multiple chips 200 connected in parallel can only be connected together through the second metal layer 130 , resulting in poor consistency of parasitic parameters of multiple chips 200 and poor current sharing of each chip 200 .
  • the parasitic inductance of the aluminum wire is stronger, and the current sharing performance of the multiple chips 200 connected in parallel is even worse.
  • the same connecting piece is used to connect two or more chips 200 along the second direction Y, and the connecting piece is connected to the second metal layer 130, the parasitic inductance can be reduced compared to the aluminum wire connection method.
  • each chip 200 is connected to a different position on the connecting piece, and the distance between each chip 200 and the second metal layer 130 is different. The current flowing out of the chip 200 farthest from the second metal layer 130 still needs to flow along the second direction.
  • Some connecting pieces on Y adjacent chips 200 increase the current flow resistance of the chips 200 adjacent to the second metal layer 130, which also increases the parasitic inductance, and the current sharing between the parallel chips 200 will also deteriorate.
  • the current does not need to flow through the first contact portion 320 on the second electrode 220 of each chip 200. Since the flow path of the first body portion 310 is wider than the flow path of the current in the first contact portion 320, from each The current flowing out of the second electrode 220 of each chip 200 directly flows into the first main body 310, strengthening the connection between the multiple chips 200 arranged in the first direction X and the second direction Y, and improving the connection between the parallel chips 200. Parasitic parameter consistency, thereby optimizing the dynamic current sharing between multiple chips 200 connected in parallel; and the first connecting piece 300 can also increase the structural reliability of the interconnection of multiple chips 200 along the first direction X and the second direction Y, ensuring Current transfer stability.
  • the first direction X is the length direction of the power module 10
  • the second direction Y is the width direction of the power module 10
  • the first direction X is the width direction of the power module 10
  • the second direction Y is the length direction of the power module 10
  • the first direction X intersects the width direction of the power module 10
  • the second direction Y intersects the length direction of the power module 10 .
  • the first body portion 310 is isolated from the second electrode 220 of the chip 200 along the thickness direction of the chip 200 .
  • the first connecting piece 300 includes one or more
  • the groove 301 protrudes from the first body part 310 toward the first surface 121 , and the bottom of the groove 301 is the first contact part 320 .
  • the thickness direction of the chip 200 is the third direction Z, and the third direction Z perpendicularly intersects the first direction X and the second direction Y.
  • the first body part 310 is isolated from the second electrode 220 of the chip 200 , and the groove 301 protrudes from the first body part 310 toward the first surface 121 , so that the first body part 310 is in the second electrode 220 of the chip 200 above to improve the electrical insulation between the first body part 310 and the first metal layer 120 .
  • the first contact portion 320 may be entirely the bottom of the groove 301 .
  • the peripheral wall of the groove may be complete, that is, the cross-section of the peripheral wall of the groove may be a complete annular structure.
  • the peripheral wall of the groove may also be incomplete, that is, the cross-section of the peripheral wall of the groove may be an open structure, such as the first contact portion 320a or the first contact portion 320a in Figure 4
  • the specific implementation form of the first contact portion 320a or 320b is a groove, but the cross section of the peripheral wall of the groove is a U-shaped structure.
  • the opening structure may also be L-shaped or V-shaped.
  • the first body portion 310 and the second electrode 220 of the chip 200 are isolated along the thickness direction of the chip 200.
  • the first connecting piece 300 includes one or more bending structures 302.
  • the bent structure 302 includes a first contact portion 320 in contact with the second electrode 220 of the chip 200 .
  • the bending structure 302 refers to a structure that is bent toward the first surface 121. One end of the bending structure 302 away from the first main body part 310 is convex toward the first surface 121, and the first contact part 320 is the convex part.
  • a contact portion 320 is in contact with the second electrode 220 so that the first body portion 310 is located above the second electrode 220 to improve the electrical insulation between the first body portion 310 and the first metal layer 120 .
  • the first contact portion 320 may be all the portion where the bent structure 302 contacts the second electrode 220 of the chip 200 . In one embodiment, part of the first contact part 320 may be the bottom of the groove 301 , and part of the first contact part 320 may be the part where the bent structure 302 contacts the second electrode 220 of the chip 200 .
  • the first contact portions 320 are distributed on the edge of the first main body portion 310 .
  • the edge distribution area of the first main body part 310 is large, and more first contact parts 320 can be distributed, thereby allowing more chips 200 to be connected in parallel, thereby increasing the power density of the power module 10 .
  • FIG. 7 is a schematic structural diagram of FIG. 4 with the first connecting piece 300 removed
  • FIG. 8 is a schematic structural diagram of the first connecting piece 300 .
  • the power module 10 includes two first chip subgroups 203 spaced apart along the first direction
  • the chips 200 are spaced apart in the second direction Y.
  • the first main body 310 includes a first trunk 311 and a plurality of first branches 312 (as shown in FIG. 8 ).
  • the first trunk 311 extends along the second direction Y, and the first branches 312 is located on both sides of the first trunk 311 along the first direction X and is connected to the first trunk 311; in the first direction On Y, the first branch 312 is located between two adjacent first contact portions 320, and the first branch 312 is connected to the two adjacent first contact portions 320 along the second direction Y.
  • the first trunk 311 is connected to the first contact portion 320 along the second direction Y.
  • the two metal layers 130 are electrically connected.
  • each first chip subgroup 203 has three chips 200
  • the first connecting piece 300 connects the two first chip subgroups 203 .
  • the chips 200 in the group 203 are connected in parallel to the chips 200 in the two first chip subgroups 203 .
  • the first branch 312 connects the first contact portions 320 on two adjacent chips 200 arranged along the second direction Y. At least part of the current from the two first contact portions 320 can pass through the first branch 312 Merged into the first trunk 311, the first branch 312 is directly connected between the two first contact portions 320, which can shorten the parallel path of the two adjacent chips 200 and improve the current sharing.
  • At least part of the first contact portion 320 is spaced apart from the first trunk 311 .
  • the first contact portions 320 on the chips 200 at both ends of the first chip subgroup 203 can be spaced apart from the first trunk 311 , thereby reducing the weight of the first connecting piece 300 .
  • the first connecting piece 300 further includes a second contact portion 330 .
  • the second contact portion 330 is located on a side of the second metal layer 130 away from the first insulating substrate 110 and is connected to the second contact portion 330 .
  • the metal layer 130 is electrically connected.
  • the second contact portion 330 is located at one end of the first body portion 310 and connected to the first body portion 310 .
  • the second contact portion 330 is located at one end of the first trunk 311 (as shown in FIG. 8 ), and the input end 101 is located on a side of the first trunk 311 away from the second contact portion 330 .
  • the second contact portion 330 and the second metal layer 130 are connected by welding.
  • the current collected by the first body part 310 can flow into the second metal layer 130 through the second contact part 330 .
  • the current flow directions are: input terminal 101, first metal layer 120, first electrode 210 of chip 200, second electrode 220 of chip 200, first contact portion 320, first body portion 310, second contact portion 330, Second metal layer 130.
  • the first contact portion 320 c adjacent to the second contact portion 330 may be spaced apart from the first trunk 311 .
  • the first contact portion 320c adjacent to the second contact portion 330 is also connected to the second contact portion 330 .
  • the first contact portion 320 c is spaced apart from the first trunk 311 by a gap J. In the embodiment shown in FIG.
  • the first contact portion 320 c adjacent to the second contact portion 330 is also connected to the first trunk 311 .
  • the first contact part 320c is connected to the first trunk 311 with no gap between the two, so that the current flowing out of the first contact part 320c can flow directly into the first trunk 311 without bypassing, reducing current resistance and shortening the current flow path. thereby reducing inductance.
  • the first contact part 320c is connected to the second contact part 330 and the first trunk 311 to further reduce the inductance and improve the current sharing performance.
  • the first contact part 320 , the second contact part 330 and the first body part 310 are an integrally formed structure.
  • the first contact part 320 extends from the first body part 310 to the chip. 200 protrudes, and the second contact portion 330 protrudes from the first body portion 310 toward the second metal layer 130 .
  • the first connecting piece 300 is an integrally formed structure.
  • the portion of the first connecting piece 300 located on the side of the chip 200 away from the first insulating substrate 110 protrudes toward the chip 200 to form the first contact portion 320 .
  • the part of the first connecting piece 300 on the side of the metal layer 130 away from the first insulating substrate 110 protrudes toward the first insulating substrate 110 to form a second contact portion 330.
  • the other parts are the first main body part 310 .
  • the first contact part 320, the second contact part 330 and the first main body part 310 are integrally formed structures.
  • the first contact part 320, the second contact part 330 and the first main body part 310 can be formed through a stamping process. Formed by die-casting process. Compared with using other components to connect the first contact part 320, the second contact part 330 and the first main body part 310 to form the first connecting piece 300, the first contact part 320, the second contact part 330 and the first main body part 310 are The one-piece structure can improve the smoothness of current flow, reduce current flow resistance, improve current sharing and reduce inductance. On the other hand, it can improve the reliability of the first connecting piece 300 .
  • the first connecting piece 300 is an integrally formed rectangular sheet structure
  • the first contact portion 320 is a groove or bending structure protruding from the first body portion 310 toward the chip 200.
  • the second contact portion 330 is a groove or a bent structure protruding from the first body portion 310 to the second metal layer 130 .
  • the integrated rectangular sheet structure can make the chips 200 in the two first chip subgroups 203 more closely arranged, improve the current sharing between the parallel chips 200, and effectively reduce the parasitic inductance.
  • the power module 10 includes two sets of chipsets arranged in series, namely a first chipset 201 and a second chipset 202.
  • the first chipset 201 is located on the first metal layer. 120 is on the side away from the first insulating substrate 110
  • the second chipset 202 is located on the side of the second metal layer 130 away from the first insulating substrate 110
  • the power module 10 also includes a second connecting piece 400
  • the second connecting piece 400 is located on the side of the second metal layer 130 away from the first insulating substrate 110.
  • On the side of the second chipset 202 away from the first insulating substrate 110 multiple chips 200 in the second chipset 202 are connected in parallel through the second connecting piece 400 .
  • the second connection piece 400 includes a second connection body 410 and a plurality of third connection structures 420 and fourth connection structures 430 that are electrically connected to the second connection body 410 .
  • the plurality of third connection structures 420 are respectively connected to The plurality of chips 200 in the second chipset 202 are electrically connected, and part of the second connection body 410 is located between two third connection structures 420 arranged along the first direction X. Part of the second connection body 410 is located along the second direction Between the two third connection structures 420 arranged in Y, the second connection body 410 and the second metal layer 130 are insulated and spaced apart, and the fourth connection structure 430 is electrically connected to the output end 102 of the power module 10 .
  • the second connecting piece 400 and the first connecting piece 300 are arranged in opposite directions, and the output terminal 102 and the input terminal 101 are located at the same end of the power module 10 .
  • the second connection body 410 includes a second trunk and a second branch, wherein the structure of the second trunk and the second branch in the second connecting piece 400 is the same as that of the first connecting piece 300 , wherein the above-mentioned third Various implementable ways of a connecting piece 300 are also applicable to the second connecting piece 400, which will not be described again here.
  • the power module 10 further includes a first end metal layer 140 .
  • the first end metal layer 140 is insulated from the first metal layer 120 and the second metal layer 130 .
  • the fourth connection structure 430 passes through the first metal layer 140 .
  • the end metal layer 140 is electrically connected to the output terminal 102 .
  • the fourth connection structure 430 is fixedly connected to the first end metal layer 140 , and the first end metal layer 140 is connected to the output terminal 102 .
  • the flow path direction of the current is: the input terminal 101, the first metal layer 120, the first chipset 201, the first connecting piece 300, the second metal layer 130, the The second chipset 202, the second connecting piece 400, the first end metal layer 140, and the output terminal.
  • Each chip 200 in the first chipset 201 is connected in parallel through the first connecting piece 300
  • each chip 200 in the second chipset 202 is connected in parallel through the second connecting piece 400 .
  • the power module 10 can set the number of chipsets and the number of chips 200 in each chipset as needed.
  • the series or parallel connection between the chipsets can be set as needed.
  • the power module 10 includes two sets of chipsets arranged in series, namely a first chipset 201 and a second chipset 202.
  • the first chipset 201 is located on the first metal layer. 120 is on the side away from the first insulating substrate 110, and the second chipset 202 is located on the side of the second metal layer 130 away from the first insulating substrate 110.
  • the power module 10 also includes a first connecting piece 300 and a second connecting piece 400.
  • a connecting piece 300 is located on the side of the first chipset 201 away from the first insulating substrate 110 .
  • Multiple chips 200 in the first chipset 201 are connected in parallel through the first connecting piece 300 .
  • the second connecting piece 400 is located on the second chipset 202 On the side away from the first insulating substrate 110 , multiple chips 200 in the second chipset 202 are connected in parallel through the second connecting piece 400 .
  • the structure of the first connecting piece 300 adopts the structure of the first connecting piece 300 as shown in FIG. 11 , where the second connecting piece 400 has the same structure as the first connecting piece 300 .
  • the first contact part 320 can be soldered to the second electrode 220 of the chip 200 through the first solder S1
  • the second contact part 330 can be connected to the second metal layer 130 through the second solder S2 .
  • the first solder S1 and the second solder S2 can be selected from at least one of tin solder and lead solder, wherein the tin solder can be selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-component strengthening, SnSb10, and can be selected according to It is necessary to select the materials of the first solder S1 and the second solder S2.
  • the first solder S1 and the second solder S2 may be the same or different.
  • SnSb5 refers to the Sb element containing 5% by weight of the Sn element
  • SnSb8 refers to the Sb element containing 8% by weight of the Sn element
  • SnSb10 refers to the Sn element containing 10% by weight of the Sb element.
  • Sb element, SAC in SAC306 represents the three metal elements Sn, Ag, and Cu, indicating that this product is composed of three metal components: Sn (tin), Ag (silver), and Cu (copper). Among them, 3 It represents 3% Ag, and 05 represents 0.5% Cu.
  • SAC multi-component strengthening also includes other metal components among the three metal components of Sn (tin), Ag (silver), and Cu (copper) to enhance the reliability of the solder.
  • the chip 200 is connected to the first metal layer 120 through the sintering material SJ.
  • the sintered material SJ may be formed of silver paste, copper paste or silver film.
  • the silver paste may include at least one of micrometer silver particle paste (Micrometer silver particle paste) and nanometer silver particle paste (Nanometer silver particle paste).
  • micron silver paste refers to silver paste made using micron silver particles and organic solvents, which is low-cost and safe.
  • the sintered material SJ has high density, the interface of the joined body is firmly joined, and the joint reliability is high.
  • the sintering material SJ of this application can be formed using micrometer silver particle paste.
  • the elastic modulus, coefficient of thermal expansion (CTE), etc. of the sintered material SJ can be adjusted by adding materials to the sintered material SJ.
  • the sintered material SJ includes a host material and a filler filled in the host material; the host material includes at least one of silver paste, copper paste or silver film, and the filler is formed of a material with good adhesion to the host material. , and the thermal expansion coefficient of the filler is smaller than that of the main material, thereby improving the joint reliability of sintering.
  • fillers are added to the micron silver paste to reduce the thermal expansion coefficient of the micron silver paste and reduce the joint stress, thereby improving the joint reliability of silver fired joints.
  • the filler may include nickel (Ni), Ni alloy, copper (Cu), nickel-plated copper, titanium (Ti), Ti alloy, iron (Fe), Fe alloy, Kovar (iron-nickel-cobalt alloy) 4J29) and SiC powder, etc., which are not limited here.
  • the length of the filler can be controlled between 20 ⁇ m and 100 ⁇ m.
  • the size of the filler in the vertical length direction can be controlled between 20nm and 30 ⁇ m.
  • the cross-section along the length direction can be circular, elliptical, polygonal, etc.
  • the first metal layer 120 is generally copper.
  • the first metal layer 120 can be Silver plating means that the first metal layer 120 is covered with a silver plating layer in the area corresponding to the sintered material.
  • the thickness of the silver plating layer can be controlled between 0.1 ⁇ m and 30 ⁇ m. If the bonding performance between the sintered material SJ and the first metal-clad substrate is relatively good, silver plating may not be required.
  • the sintered material is copper paste
  • the first metal-clad substrate 100 does not need to be silver-plated at the sintering site.
  • Figure 15 is a schematic structural diagram of the power module 10 provided in an embodiment of the present application.
  • Figure 16 is a partial enlarged view of part M in Figure 15.
  • the power module 10 further includes a second metal-clad substrate 500 and an electronic component 600 (as shown in FIG. 16 ).
  • the second metal-clad substrate 500 is located on the first metal-clad substrate 100 .
  • the electronic component 600 is located on the side of the second metal-clad substrate 500 away from the first metal-clad substrate 100 and is electrically connected to the second metal-clad substrate 500 .
  • the metal layer of the first metal-clad substrate 100 includes the first metal layer 120, the second metal layer 130 or other metal layers.
  • the second metal-clad substrate 500 may be located on the surface of the first metal layer 120 or the second metal layer 130 .
  • the electronic component 600 is located on the first surface 121 of the first metal layer 120 .
  • the electronic component 600 is located on the second metal layer 130 .
  • the structure of the first connecting piece 300 in FIG. 15 is simplified. The structure is for illustration only.
  • the structure of the first connecting piece 300 and the connection relationship between the first connecting piece 300 and the chip 200 please refer to the relevant descriptions in figures 3 to 14.
  • the size of the electronic component 600 is generally relatively small, if the electronic component 600 is directly welded to the first metal-clad substrate 100, an insulating trench needs to be opened on the metal layer of the first metal-clad substrate 100 to connect the electronic component to the first metal-clad substrate 100.
  • the two electrodes of the device 600 are electrically connected to the metal layers on both sides of the insulation trench. Opening an insulation trench on the first metal-clad substrate 100 will reduce the layout space of the chip 200, and the first metal-clad substrate 100 is provided with If more chips 200 are etched into the metal layer on the first metal-clad substrate 100, the pre-arranged chips 200 or other electronic devices may be damaged.
  • the electronic component 600 is transferred through the second metal-clad substrate 500 , so that the welding process of the electronic component 600 is simple.
  • the step of opening an insulating trench on the metal layer of the first metal-clad substrate 100 can be saved, making the circuit design on the first metal-clad substrate 100 simpler, and can be based on the size and electronics of the electronic component 600 in advance.
  • the positions of the two electrodes of the component 600 are provided with insulating trenches on the second metal-clad substrate 500 , and etching the insulating trenches on the second metal-clad substrate 500 will not affect the first metal-clad substrate 100 .
  • the performance of the chip 200 is determined, and the electronic component 600 is electrically connected to the second metal-clad substrate 500 .
  • the second metal-clad substrate 500 includes a second insulating substrate 510 and metal layers located on both sides of the second insulating substrate 510 .
  • the electronic component 600 is electrically connected to the metal layer on one side of the second insulating substrate 510 .
  • the electronic component 600 is a gate resistor 610 (as shown in FIG. 16 ), the second metal-clad substrate 500 is located on the first surface 121 , and the second metal-clad substrate 500 includes an insulating spacer.
  • the fourth electrode 520 and the fifth electrode 530 are provided, and both ends of the gate resistor 610 are electrically connected to the fourth electrode 520 and the fifth electrode 530 respectively.
  • the fourth electrode 520 is used to receive the driving current, and the fifth electrode 530 passes through the first
  • the conductive wire 710 is electrically connected to the third electrode 230 of the chip 200 .
  • the second metal-clad substrate 500 is used to transfer the gate resistor 610, making the welding process of the gate resistor 610 simple.
  • the fourth electrode 520 and the fifth electrode 530 are part of the metal layer on the second insulating substrate 510, and the insulation part between the fourth electrode 520 and the fifth electrode 530 is set according to the size of the gate resistor 610, so that the fourth There is an insulating distance between the electrode 520 and the fifth electrode 530 .
  • a fourth trench 550 is provided between the fourth electrode 520 and the fifth electrode 530 , and the fourth electrode 520 and the fifth electrode 530 are insulated and separated by the fourth trench 550 .
  • the fourth electrode 520 , the fifth electrode 530 and the fourth trench 550 can be formed through an etching process through the metal layer on one side of the second metal-clad substrate 500 .
  • the power module 10 also includes a second conductive wire 720 and a first connection terminal 731 (as shown in FIG. 15 ).
  • the fourth electrode 520 is connected to the first connection terminal 731 through the second conductive wire 720 .
  • the external control The circuit sends the driving current to the first connection terminal 731. After the fourth electrode 520 receives the driving current, please refer to Figure 15 and Figure 16.
  • the driving current passes through the first connection terminal 731, the second conductive wire 720, the fourth electrode 520, and the gate in sequence.
  • the resistor 610, the fifth electrode 530 and the first conductive line 710 flow into the third electrode 230 of the chip 200.
  • the third electrode 230 can be a gate or a gate.
  • the third electrode 230 can drive the first electrode 230.
  • the electrode 210 and the second electrode 220 are electrically connected.
  • the gate resistor 610 is used to improve the switching performance of the chip 200 and can suppress high-frequency oscillation generated when multiple chips 200 are connected in parallel.
  • the first conductive line 710 is a transmission line, such as an aluminum wire, a copper wire, etc.
  • the second metal-clad substrate 500 also includes a third metal layer 540 located on the side of the second insulating substrate 510 away from the fourth electrode 520 and the fifth electrode 530 .
  • the third metal layer 540 is connected to the second insulating substrate 510 through the third solder S3 .
  • the first metal layer 120 on the surface of the first metal-clad substrate 100 is welded.
  • the third solder S3 can be selected from at least one of tin solder and lead solder, wherein the tin solder can be selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-component strengthening, and SnSb10, wherein the third solder S3 is different from the third solder.
  • the first solder S1 may be the same or different
  • the third solder S3 and the second solder S2 may be the same or different.
  • the gate resistor 610 can be soldered to the fourth electrode 520 and the fifth electrode 530 through a fourth solder S4, wherein the fourth solder S4 can be selected from at least one of tin solder and lead solder, wherein the tin solder can be selected from At least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-element strengthening, and SnSb10, wherein the fourth solder S4 and the first solder S1 may be the same or different, and the third solder S3 and the second solder S2 may be the same or different.
  • the fourth solder S4 can be selected from at least one of tin solder and lead solder, wherein the tin solder can be selected from At least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-element strengthening, and SnSb10, wherein the fourth solder S4 and the first solder S1 may be the same or different, and the third
  • the first connection terminal 731 may be soldered to the terminal metal layer 1010 on the edge of the first metal-clad substrate 100 through the eighth solder S8.
  • the eighth solder S8 can be selected from at least one of tin solder and lead solder, wherein the tin solder can be selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-component strengthening, and SnSb10.
  • the third electrodes 230 of the plurality of chips 200 in the first chipset 201 are connected to the same second metal-clad layer through conductive lines.
  • the gate resistor 610 of the layer substrate 500 is electrically connected. That is, one gate resistor 610 controls the on or off of the first electrode 210 and the second electrode 220 in the plurality of chips 200 .
  • each gate resistor 610 when there are multiple gate resistors 610 and the second metal-clad substrate 500 , and each gate resistor 610 is disposed on the second metal-clad substrate 500 , the third electrode of each chip 200 230 is electrically connected to the gate resistor 610 of one of the second metal-clad substrates 500 through conductive wires. That is, a gate resistor 610 controls the on or off of the first electrode 210 and the second electrode 220 in a chip 200 .
  • the chip 200 is located on the first metal layer 120, and the second metal-clad substrate 500 is welded to the surface of the first metal layer 120, which can make the distribution of components more compact.
  • the second metal-clad substrate 500 can also be welded to the surface of the second metal layer 130 .
  • FIG. 18 is a schematic structural diagram of the first metal-clad substrate 100 and the second metal-clad substrate 500 .
  • the first metal layer 120 and the second metal layer 130 are connected to the first insulating substrate 110 through the metal welding layer SH; in the second metal-clad layer In the substrate 500 , the fourth electrode 520 and the fifth electrode 530 are attached to the surface of the second insulating substrate 510 .
  • the side of the first insulating substrate 110 facing the chip 200 has two metal layers.
  • the two metal layers are the metal soldering layer SH and the third metal layer SH.
  • the electronic component 600 is directly welded to the first metal-clad substrate 100. Since the electronic component 600 needs to carry current, two sixth electrodes 103 and a seventh electrode arranged at insulating intervals need to be provided on the first metal-clad substrate 100.
  • 104 please refer to FIG. 19.
  • a part of the first metal layer 120 is etched as the fourth metal layer 150.
  • the fourth metal layer 150 is insulated from other parts of the first metal layer 120 and is etched on the fourth metal layer 150.
  • the second trench 151 forms the sixth electrode 103 and the seventh electrode 104.
  • part of the fourth metal layer 150 and part of the metal welding layer SH between the sixth electrode 103 and the seventh electrode 104 need to be removed through an etching process.
  • the larger size of Z etching in the third direction will increase the aperture of the second trench 151, or in other words, the larger the size between the sixth electrode 103 and the seventh electrode 104, and the electronic component 600 (such as the gate resistor 610)
  • the size is small and cannot be welded on the sixth electrode 103 and the seventh electrode 104, or the welding reliability will be poor.
  • the electronic component 600 is transferred through the second metal-clad substrate 500 , where the metal on the second metal-clad substrate 500 is directly bonded to the second insulating substrate 510 , so that the second metal-clad substrate 500 is formed.
  • the fourth electrode 520 and the fifth electrode 530 are also directly attached to the surface of the second insulating substrate 510. There is no metal welding layer between the fourth electrode 520 and the fifth electrode 530 and the second insulating substrate 510.
  • the etching grooves are formed to form the third electrode.
  • the four electrodes 520 and the fifth electrode 530 are used, there is no need to etch the metal welding layer, so that the size between the fourth electrode 520 and the fifth electrode 530 can be controlled smaller, which is beneficial to welding the electronic components 600 (such as the gate resistor 610). .
  • the first metal-clad substrate 100 is an active metal welding substrate.
  • the active metal welding substrate refers to welding a metal layer such as a copper layer or an aluminum layer to both sides of the insulating substrate through metal solder.
  • the first metal layer 120, the second metal layer 130, and the first terminal can be formed by etching the copper layer.
  • the circuits required by the power module 10 include the internal metal layer 140 and the terminal metal layer 1010 .
  • the material of the first insulating substrate 110 in the first metal-clad substrate 100 can be Si 3 N 4 or AlN, so that the welding reliability of the first insulating substrate 110 and the metal plates on both sides is stronger and has better thermal conductivity. performance, which can improve the heat dissipation effect of the power module 10.
  • the second metal-clad substrate 500 is a copper-clad ceramic substrate.
  • the second insulating substrate 510 is an Al 2 O 3 ceramic substrate or an AlN ceramic substrate, and a metal layer (such as copper foil) is directly bonded to the second insulating substrate 510 at high temperature.
  • a metal layer such as copper foil
  • the copper foil is directly bonded to the Al 2 O 3 ceramic substrate at high temperature, and then the copper foil is used to form the fourth electrode 520 and the fifth electrode 530 as needed.
  • the copper foil and the Al 2 O 3 ceramic substrate There is no other metal layer in between, so that the distance between the fourth electrode 520 and the fifth electrode 530 can be smaller, which is beneficial to welding the gate resistor 610 .
  • the thickness of the first metal layer 120 and the second metal layer 130 is greater than or equal to 0.6 mm.
  • the first metal layer 120 has a higher power density and can quickly transmit current to multiple chips 200 connected in parallel.
  • the second metal layer 130 When the value of the thickness is within the above range, it can also improve the thermal conductivity of the first metal-clad substrate 100, thereby improving the heat dissipation effect of the power module 10, allowing the second metal layer 130 to have a higher power density and be able to quickly The current is transmitted to the multiple chips 200 connected in parallel in the second chipset 202 .
  • the size of the insulating trench will be larger. Since the size of the electronic component 600 (such as the gate resistor 610) is small, welding the electronic component 600 across the trench to the two electrodes will increase the process difficulty. Based on this, when improving When the power density of the power module 10 is increased, the second metal-clad substrate 500 can be provided to reduce the process difficulty of soldering the electronic components 600 .
  • the thickness of the first metal layer 120 and the second metal layer 130 is greater than or equal to 0.8 mm.
  • the thickness of the first metal layer 120 and the second metal layer 130 is greater than or equal to 1.2 mm.
  • the first metal-clad substrate 100 is an insulating metal substrate.
  • the insulating metal substrate includes an insulating resin layer and metal layers located on both sides of the insulating resin layer.
  • the metal layer on one side is etched into a required circuit according to electrical interconnection requirements, including forming a first metal layer 120 and a second metal layer 130.
  • the thickness of the metal layer is greater than or equal to When the thickness is 0.6 mm, the power module 10 has a higher power density, and the second metal-clad substrate 500 can be provided to transfer the electronic components 600 to reduce the process difficulty of soldering the electronic components 600 .
  • the power module 10 includes two second metal-clad substrates, one of which is used to weld the gate resistor 610, and the other second metal-clad substrate 500 is used to weld the gate resistor 610.
  • the metal layer substrate 500a is used for soldering the thermistor 620.
  • only one second metal-clad substrate may be used for soldering the thermistor 620 .
  • FIG. 20 is a partial enlarged view of part N in FIG. 15
  • FIG. 21 is a cross-sectional view of the part including the thermistor 620 in the power module 10 .
  • the electronic component 600 is a thermistor 620
  • the second metal-clad substrate 500a is located on a side of the second metal layer 130 away from the first insulating substrate 110, and is adjacent to the chip located on the second metal layer 130.
  • the thermistor 620 is used to monitor the temperature of the chip 200 .
  • the electronic component 600 is a thermistor 620
  • the second metal-clad substrate 500a is located on a side of the first metal layer 120 away from the first insulating substrate 110, and is adjacent to the chip located on the first metal layer 120.
  • the thermistor 620 is used to monitor the temperature of the chip 200 . That is to say, the second metal-clad substrate 500 for transferring the thermistor 620 and the chip 200 are located on the same metal layer, for example, both are located on the first metal layer 120 , or both are located on the second metal layer 130 .
  • both the second metal-clad substrate 500 and the chip 200 connected to the thermistor 620 are disposed on other metal layers.
  • the second metal-clad substrate 500a includes a fourth electrode 520a and a fifth electrode 530a that are insulated and spaced apart.
  • the two ends of the thermistor 620 are respectively connected to the fourth electrode 520a and the fourth electrode 520a.
  • the fifth electrode 530a is electrically connected.
  • the power module 10 also includes a second connection terminal 732 and a third connection terminal 733 (as shown in FIG. 20 ).
  • the fourth electrode 520a and the fifth electrode 530a are respectively connected to the second connection terminal 732 and the third connection terminal 733 (as shown in FIG. 20 ).
  • connection terminal 733 is electrically connected, the second connection terminal 732 and the third connection terminal 733 are connected to an external control circuit, and the temperature of the chip 200 is monitored through the thermistor 620 .
  • the thermistor 620 may be a negative temperature coefficient thermistor or a positive temperature coefficient thermistor.
  • the second connection terminal 732 and the third connection terminal 733 can be welded on the terminal metal layer, and the terminal metal layer below each connection terminal is arranged at an insulating distance.
  • the power module 10 further includes a third conductive wire 170 and a fourth conductive wire 180.
  • the fourth electrode 520a and the second connection terminal 732 are connected through the third conductive wire 170.
  • the fifth electrode 530a and the third conductive wire 180 are connected to each other through the third conductive wire 170.
  • the connection terminals 733 are connected through the fourth conductive wire 180 .
  • the third conductive wire 170 and the fourth conductive wire 180 may be aluminum wires or copper wires.
  • the thermistor 620 is disposed on the second metal-clad substrate 500a, and the second metal-clad substrate 500a is disposed on the second metal layer 130, and the thermistor 620 is disposed adjacent to the chip 200, Makes temperature measurement more accurate. If the thermistor 620 is directly welded to the second metal layer 130, the thermistor 620 needs to be welded to the trench between the second metal layer 130 and other metal layers.
  • the power module 10 further includes a second end metal layer 160 . There is a third trench 106 between the second metal layer 130 and the second end metal layer 160 . The terminal is provided on the second metal layer 130 and the second end metal layer 160.
  • Only one end of the thermistor 620 is connected to the second metal layer 130.
  • the chip 200 is located on the second metal layer 130. When the chip 200 generates heat after operation, The temperature of the chip 200 will be directly transmitted to the second metal layer 130, so that the temperature of the second metal layer 130 is close to the temperature of the chip 200.
  • the thermistor 620 When only one end of the thermistor 620 is connected to the second metal layer 130, and the thermistor 620 When the other end is connected to the second end metal layer 160, the second end metal layer 160 and the second metal layer 130 are separated by the third trench 106, so that the heat of the second metal layer 130 cannot be transferred to the second end metal.
  • the temperature difference between the second end metal layer 160 and the second metal layer 130 is larger, so that the temperature of one end of the thermistor 620 connected to the second end metal layer 160 is higher than the temperature of one end connected to the second metal layer 130.
  • the temperature of one end of the thermistor 620 is low, so that the temperature monitoring accuracy of the thermistor 620 as a whole and the chip 200 becomes poor.
  • the second metal-clad substrate 500a is located in the second metal layer 130, and the thermistor 620 is welded to the second metal-clad base. On the board 500a (as shown in FIG. 21), the temperatures of both ends of the thermistor 620 are close to each other, and the second metal-clad substrate 500a is disposed on the first metal layer 120 and adjacent to the chip 200, which can improve the sensitivity of the chip 200. Temperature monitoring accuracy.
  • the accuracy of monitoring the temperature of the chip 200 can also be improved.
  • the thermistor 620 can be welded on the fourth electrode 520a and the fifth electrode 530a through the fifth solder S5, wherein the fifth solder S5 can be selected from at least one of tin solder and lead solder, wherein the tin solder can be selected from At least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-element strengthening, and SnSb10, wherein the fifth solder S5 and the first solder S1 may be the same or different, and the fifth solder S5 and the second solder S2 may be the same or different.
  • the second metal-clad substrate 500a can be soldered on the surface of the first metal layer 120 away from the first insulating substrate 110 through a sixth solder S6, where the sixth solder S6 can be selected from at least one of tin solder and lead solder.
  • the tin solder can be selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-component strengthening, and SnSb10, wherein the sixth solder S6 and the first solder S1 may be the same or different, and the sixth solder S6 and the second solder S2 can be the same or different.
  • the first metal-clad substrate 100 is one of an active metal welding substrate and an insulating metal substrate
  • the second metal-clad substrate 500a is a copper-clad ceramic substrate.
  • the metal layer on the second metal-clad substrate 500 can be used as a signal trace, which is beneficial to improving the flexibility of the circuit distribution of the power module 10 .
  • some circuits can be made of the metal layer on the first metal-clad substrate 100, and some circuits can be made of the metal layer on the second metal-clad substrate 500, making the circuit distribution more flexible.
  • the power module 10 further includes a heat sink 800 .
  • the heat sink 800 is located on a side of the first metal-clad substrate 100 away from the chip 200 .
  • the heat sink 800 and the first metal-clad substrate 100 are A plurality of spaced apart support assemblies 900 are disposed between the layer substrates 100 .
  • the radiator 800 may be a water-cooled radiator, which is not limited here, and is used to dissipate heat from the power module 10 and increase the power density of the power module 10 .
  • the heat sink 800 can be soldered to the side of the first metal-clad substrate 100 away from the chip 200 through the seventh solder S7.
  • the method of covering the metal layer substrate 100 is by welding, and the thermal conductivity of the welding material is better than that of thermally conductive silicone.
  • the first metal-clad substrate 100 includes a fifth metal layer 190 located on a side of the first insulating substrate 110 away from the first metal layer 120 .
  • the heat sink 800 is welded to the fifth metal layer 190 through a seventh solder S7 .
  • the radiator 800 includes a radiator bottom plate 810 and a radiator cover 820.
  • the radiator bottom plate 810 is provided with heat dissipation teeth 811, and a channel is formed between the heat dissipation teeth 811.
  • a cooling medium can flow in the channel, and heat dissipation is achieved through the cooling medium.
  • the heat sink 800 and the first metal-clad substrate 100 need to exert pressure, and the support assembly 900 can prevent the first metal-clad substrate 100 and the heat sink 800 from being connected. Due to the applied pressure, the seventh solder S7 that was melted during welding was extruded, and the thickness of the seventh solder S7 was too thin, resulting in failure.
  • the support component 900 may be bonded to the surface of the heat sink 800 facing the first metal-clad substrate 100 before welding, or the support component 900 may be bonded to the surface of the first metal-clad substrate 100 facing the heat sink 800 .
  • the support component 900 may be a metal wire or a metal strip.
  • the support component 900 can also be used to control the thickness of the seventh solder S7.
  • the thickness of the support component 900 can be designed as needed so that the seventh solder S7 meets the requirements.
  • the support assembly 900 includes two support bars 910 arranged in parallel.
  • the support bars 910 include at least two support segments 911.
  • Two adjacent support segments 911 are along the edges of the support bars 910.
  • the extension direction is arranged and spaced.
  • the seventh solder S7 is filled between the two parallel support bars 910, the seventh solder S7 is not easily extruded during pressure welding, but bubbles will be generated during high-temperature welding, and if the bubbles do not overflow, they will be formed in the welding layer. Porosity affects welding reliability.
  • two parallel support bars 910 can be used to enhance the support strength of the first metal-clad substrate 100 and the heat sink 800 .
  • the support component 900 can be formed by stamping on the surface of the heat sink 800 facing the first metal-clad substrate 100, where the support component is in the shape of a boss, as shown in 900a in Figure 23b as shown; or the support component is in the shape of a point, as shown by 900b in Figure 23b; or the support component is in the shape of a crater, as shown by 900c in Figure 23b.
  • the support assembly 900 may also have other shapes.
  • the boss-shaped, point-shaped or volcano-shaped supporting components 900 on the surface of the heat sink 800 may be one type or a combination of more than one type.
  • there may be one or more boss-shaped, point-shaped or volcano-shaped supporting components 900 may be set as needed.
  • Figure 24 is a 3D-x-ray diagram of the welding surface between the heat sink 800 and the first metal-clad substrate 100 in the power module 10 provided by an embodiment of the present application, wherein ( in Figure 24 The picture a) is a 3D-x-ray picture from the welding surface between the seventh solder S7 and the first metal-clad substrate 100. The picture (b) in Figure 24 is from the view between the seventh solder S7 and the heat sink 800. 3D-x-ray image of the welding surface.
  • the support assembly 900 in the embodiment shown in FIG.
  • SnSb5 solder is used as the seventh solder S7 to connect the heat sink 800 and the first metal-clad substrate 100, and the power module 10 is subjected to a temperature shock experiment.
  • the temperature shock test conditions are: 15 min at -40°C (low temperature), 15 min at 125°C (high temperature), one low temperature and one high temperature count as one cycle, and 1,000 cycles are performed.
  • the seventh solder S7 is selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, SAC multi-component strengthening, lead-based high-temperature solder, SnSb10, peritectic Sn-Sb, and Sn-Sb-X, wherein Lead-based high-temperature solder refers to solder with a lead content of greater than or equal to 85%, which requires a higher temperature to melt. Sn-Sb-X refers to Sn and Sb doped with other elements, such as nickel, bismuth, and copper. During welding, the welding temperature can be set according to the specific material of the seventh solder S7.
  • the value of the welding temperature can be set to be greater than or equal to 300°C; for another example, when using SAC305, the welding temperature can be set. Set the value of the welding temperature to 260°C.
  • each component in the power module 10 and the heat sink 800 are welded through one reflow welding process; or through two reflow welding processes, the first reflow welding process will Each component is soldered on the first metal-clad substrate 100 , and the second reflow soldering process solders the heat sink 800 to the side of the first metal-clad substrate 100 away from the chip 200 .
  • Each component includes a first connecting piece 300, a second connecting piece 400, a thermistor 620, a gate resistor 610 and each connecting terminal.
  • solder material used is selected from at least one of SnSb5, SnSb8, SnSbAg, SAC305, and SAC multi-component strengthening
  • the solders of SnSb5, SnSb8, SnSbAg, SAC305, and SAC multi-component strengthening are medium-temperature solders, and the thermistor 620 can withstand The maximum temperature is 260°C.
  • the first solder S1, the second solder S2, the third solder S3, the fourth solder S4, the fifth solder S5, the sixth solder S6, the seventh solder S7 and the eighth solder S8 can be soldered by one reflow.
  • the process is completed, and the temperature of the reflow soldering process is set to 260°C.
  • solder materials used for the first solder S1, the second solder S2, the third solder S3, the fourth solder S4, the fifth solder S5, the sixth solder S6, and the eighth solder S8 are selected from SnSb5, SAC305, SAC
  • the solder material used for the seventh solder S7 is selected from at least one of lead-based high-temperature solder, SnSb10, peritectic Sn-Sb, and Sn-Sb-X. Since the seventh solder S7 is High-temperature solder needs to be melted at a higher temperature to achieve soldering, and the maximum resistance to soldering temperature of each component is low.
  • the maximum resistance to soldering temperature of the thermistor 620 is 260°C.
  • two reflow soldering processes are required.
  • the temperature of the first reflow soldering process is set to 300°C (or greater than 300°C)
  • the seventh solder S7 is soldered
  • the heat sink 800 is soldered to the side of the first metal-clad substrate 100 away from the chip 200
  • the second secondary reflow Welding process the temperature of the second reflow soldering process is set to 260°C.
  • the first solder S1, the second solder S2, the third solder S3, the fourth solder S4, the fifth solder S5, the sixth solder S6, the eighth solder After the soldering of solder S8 is completed, the first connecting piece 300, thermistor 620, gate electronics 610, first connecting terminal 731 and other components corresponding to each solder are soldered on the first metal-clad substrate 100.
  • the thermistor 620 can select a thermistor with a maximum resistance to soldering temperature greater than 300°C, so that the power module 10 can pass The soldering is completed in one reflow soldering process.
  • the solder materials used for the first solder S1, the second solder S2, the third solder S3, the fourth solder S4, the fifth solder S5, the sixth solder S6, and the eighth solder S8 are selected from Sn-Sb-X,
  • the seventh solder S7 is made of lead-based high-temperature solder, SnSb10, and peritectic Sn-Sb, the soldering temperature of the seventh solder S7 is higher than that of the first solder S1.
  • the soldering temperatures of the second solder S2, the third solder S3, the fourth solder S4, the fifth solder S5, the sixth solder S6, and the eighth solder S8 can be completed using two reflow soldering processes.
  • the temperature settings of the two reflow soldering processes are greater than or equal to 300°C, but the temperatures of the two reflow soldering processes are different.
  • the temperature of the seventh solder S7 during welding is higher than the temperatures of the first solder S1, the second solder S2, the third solder S3, the fourth solder S4, the fifth solder S5, the sixth solder S6 and the eighth solder S8.
  • the welding surface may be inconvenient according to the material to select solder.
  • the present application also provides a method for manufacturing the power module 10 , including step S100 , step S200 , step S300 and step S400 . Detailed steps are described below.
  • step S100 the chip 200 is mounted on one side of the first metal-clad substrate 100 through the sintering material SJ.
  • the first metal-clad substrate 100 is an active metal layer substrate, including a first insulating substrate 110 and a copper layer welded on one side of the first insulating substrate 110, where the first insulating substrate 110 is a SiN ceramic substrate, and the copper layer
  • the thickness is 0.8mm, and the copper layer is etched as needed to form the first metal layer 120, the second metal layer 130, the first end metal layer 140, etc.
  • the thickness of the copper layer can be set as desired.
  • the first metal-clad substrate 100 may also be an insulating metal substrate.
  • the first electrode 210 is located on the side of the chip body 240 facing the first metal layer 120 , where the first electrode 210 includes Ti/Ni/Au, and Ti/Ni/Au refers to Ti , Ni, and Au are welded on one side of the chip body 240 in sequence (as shown in Figure 6).
  • the first electrode 210 may also be Ti/Ni/Ag, Ti/NiV/Ag, Ti/NiV/Au, Ni(P)/Pd/Au, Ni(P)/Pd/Ag, Ni(P )/Au or Ni(P)/Ag, where Ni(P) means that the Ni element is doped with P element, and NiV refers to the alloy of Ni element and V element.
  • the second electrode 220 is Ti/Ni/Au, Ti/Ni/Ag, Ti/NiV/Ag, Ti/NiV/Au, Ni(P)/Pd/Au, Ni(P)/Pd/Ag. , Ni(P)/Au or Ni(P)/Ag.
  • a NiSi layer can also be provided between the first electrode 210 and the chip body 240.
  • the sintering material SJ is copper paste or silver paste
  • the chip 200 can be mounted on the first metal-clad substrate 100 through the following steps:
  • step S101a the sintering material SJ is printed on the first metal-clad substrate.
  • the sintered material SJ can be printed on the corresponding first metal-clad substrate 100 through the scraper 42 using a stencil 41 printing process or a screen printing process. on the sintering area. Because the stencil 41 printing process is lower in cost and simpler to produce than the screen printing process. Therefore, optionally, this application uses a stencil printer The copper paste or silver paste is printed on the corresponding sintering area of the first metal-clad substrate 100 .
  • the sides of the opening 43 of the steel mesh 41 can be set to be narrow at the top and wide at the bottom, an inclined surface or an inclined curved surface, so that the thickness of the sintered material at the edge of the opening 43 is thinner to reduce the edge convexity of the sintered material SJ after printing. to improve the printing quality and reduce the stress risk of the chip 200.
  • the edge of the opening 43 is set to have the same thickness as the middle part, then the sintered material SJ filled in the edge of the opening 43 is thicker.
  • the stencil is taken out after printing is completed, the stencil will The sintered material adjacent to the edge of the opening is pulled up, causing the edge of the sintered material SJ to bulge.
  • the edge of the side opening 43 is set to be narrow at the top and wide at the bottom, so that the sintered material SJ filled at the edge of the opening 43 is reduced, the bulging of the edge of the sintered material SJ can be avoided. The problem.
  • the thickness of the printed copper paste or silver paste can be controlled between 30 ⁇ m and 160 ⁇ m.
  • the specific design can be based on the actual product and is not limited here.
  • the area of the printed copper paste or silver paste can be set larger than the area of the corresponding sintering area on the chip 200 to absorb the alignment error between the chip 200 and the sintering material SJ.
  • the boundary of the copper paste or silver paste can extend 20 ⁇ m to 300 ⁇ m outward from the target boundary (the boundary of the sintering area of the chip under ideal conditions).
  • step S102a the printed sintered material SJ is pre-dried.
  • the purpose of pre-drying the printed copper paste or silver paste is to prevent the sintered material from collapsing during pressure sintering.
  • the sintering material SJ (copper paste or silver paste) printed on the first metal-clad substrate 10 can be processed in an N2 atmosphere at a temperature of 100°C to 180°C. Pre-drying process 5min ⁇ 40min.
  • step S103a the chip 200 is mounted on the sintered material SJ of the first metal-clad substrate 100 and pressed.
  • the chip 200 can be vacuum-adsorbed through the metal suction nozzle 44 first, and then the chip 200 can be sucked up, and then the sintering material SJ (copper paste or silver paste) can be processed through the image recognition system. After aligning, the chip 200 is fixed on the dried sintering material SJ (copper paste or silver paste) and pressed.
  • the chip 200 mounting conditions may be: the temperature is controlled between 100°C and 180°C, the pressure is controlled between 0.1MPa and 10MPa, and the time is controlled between 10ms and 999ms. That is, a pressure of 0.1MPa to 10MPa is applied to the chip 200 mounted on the first metal-clad substrate 100 in an environment with a temperature of 100°C to 180°C for at least 10ms.
  • a silver film may be used as the sintering material.
  • the sintering material SJ is a silver film SJ01
  • the chip 200 can be mounted on the first metal-clad substrate 100 through the following steps:
  • Step S101b adhere the silver film SJ01 on the side of the chip 200 facing the first metal-clad substrate 100 .
  • the chip 200 can be adsorbed through the metal suction nozzle 44 , and the temperature of the metal suction nozzle 44 is 80°C to 200°C. Then press the chip 200 on a large piece of silver film SJ01, apply a pressure of 0.1MPa to 5MPa, and pressurize for a time of 1ms to 10000ms. In this way, the silver film SJ01 under the chip 200 is compressed and semi-sintered, and adheres to the chip 200 . There is a silver film support layer 45 below the silver film SJ01. After the chip 200 is attached to the silver film SJ01, the silver film support layer 45 is removed, and then the silver film SJ01 is attached to the first metal layer 120 or the second metal layer of the first metal-clad substrate 100. on the metal layer 130.
  • the surface of the first metal-clad substrate 100 may be bare copper or silver-plated.
  • silver plating is generally used.
  • the thickness of the silver plating layer is about 0.1-30um, and then the silver film is attached to the silver plating layer.
  • step S102b the chip 200 with the silver film SJ01 adhered is mounted on the first metal-clad substrate 100 and pressed.
  • the chip 200 can be sucked up first by vacuum adsorption, and then the first metal-clad substrate 100 can be aligned through the image recognition system, and then the adhered
  • the chip 200 with the silver film SJ01 is fixed on the first metal-clad substrate 100 and pressed.
  • the chip 200 mounting conditions may be: the temperature is controlled between 100°C and 180°C, the pressure is controlled between 0.1MPa and 10MPa, and the time is controlled between 10ms and 999ms. That is, in an environment with a temperature of 100°C to 180°C, the first metal-clad A pressure of 0.1MPa to 10MPa is applied to the chip 200 on the substrate 100 for at least 10ms.
  • the second electrode 220 and the third electrode 230 in the chip 200 are lower than the part of the chip body 240 around the second electrode 220 and the third electrode 230 , so that between the second electrode 220 and the third electrode 230 A voltage-resistant ring 241 is formed around the third electrode 230 and is higher than the second electrode 220 and the third electrode 230 .
  • the voltage-resistant ring 241 is a part of the chip body 240 .
  • the material of the voltage-resistant ring 241 is SiC.
  • the height of the voltage-resistant ring 241 is It is 10 ⁇ m higher than the height of the second electrode 220 and the third electrode 230 , so that when the chip 200 is pressed, the pressing head 46 contacts the voltage withstanding ring 241 without crushing the second electrode 220 and the third electrode 230 .
  • step S104 is executed.
  • Step S104 perform pressure sintering on the chip 200 mounted on the first metal-clad substrate 100.
  • Pressure sintering refers to applying pressure to the joined body at high temperature, thereby increasing the density of the sintered body, promoting atomic diffusion between the particles of the sintered material and the interface between the sintered material and the joined body, and enhancing the bonding strength and joint reliability.
  • the pressure sintering process used in this application is not limited and can be any known method.
  • the pressure head 46 can be used to perform pressure sintering on the chip 200 mounted on the first metal-clad substrate 10 to sinter the chip 200 under pressure.
  • the parallelism of the pressure head 46 can be set to ⁇ 5 ⁇ m to reduce product warpage after sintering.
  • the sintering conditions for pressure sintering are: the sintering temperature is controlled at 200°C to 300°C, the applied pressure is controlled at 5MPa to 30MPa, and the sintering time is controlled at 1min to 10min.
  • the pressure sintering process can be carried out in an air environment.
  • the chip 200 mounted on the first metal-clad substrate 100 is pressure-sintered in a protective atmosphere or vacuum environment.
  • the protective atmosphere may be a reducing atmosphere or an inert atmosphere.
  • the protective atmosphere may be N2, a mixed gas of N2 and H2, Ar or He, etc., which is not limited here.
  • a removable stress relief film 47 may also be placed between the chip 200 and the pressure head 46 . Therefore, during pressure sintering, the stress relaxation film 47 can avoid direct contact between the pressure head 46 and the chip 200 and reduce damage caused by stress concentration on the chip 200 caused by the pressure head 46 . After the pressure sintering is completed, the stress relaxation film 47 can be removed.
  • the thickness of the stress relaxation film 47 can be set to 50 ⁇ m to 90 ⁇ m, which is not limited here.
  • the stress relaxation film 47 can be an organic film such as Teflon film, which is not limited here.
  • Step S105 Cool the product after pressure sintering.
  • the product after sintering is completed, the product can be cooled in a protective atmosphere and under pressure to control the warpage of the sintering product.
  • cooling can be done by circulating cooling water 48, or nitrogen gas cooling can be used.
  • Step S200 welding various components and the heat sink 800 on one side of the first metal-clad substrate 100.
  • a welding jig 1100 can be used to position various components of the power module 10 and the heat sink 800.
  • the components include the first connecting piece 300, the second connecting piece 400, the thermistor 620, and the gate resistor 610.
  • a lead frame 1000 wherein the lead frame 1000 is used to be cut as needed to form connection terminals, such as the first connection terminal 731, the second connection terminal 732, the third connection terminal 733, etc., and after the welding is completed, the lead frame 1000 is cut off as needed. The excess portion is used to form the first connection terminal 731 , the second connection terminal 732 and the third connection terminal 733 .
  • FIG. 29 is only for illustration and does not represent the structure of the power module 10 and the structural shape of the welding fixture in the specific embodiment.
  • the welding jig 1100 includes an upper jig 1101 and a lower jig 1102.
  • the upper jig 1101 and the lower jig 1102 have positioning holes for mounting the chip 200, placing the electronic components 600 and the first cover of the corresponding solder.
  • the metal layer substrate 100 and the lead frame 1000 are placed between the upper jig 1101 and the lower jig 1102 and positioned as needed.
  • the upper jig 1101 and the lower jig 1102 are pressed together with bolts.
  • a spring groove and a high-temperature spring can be provided on the upper pressure plate, so that the first metal-clad base 100 and the lead frame 1000 can be flattened by the spring force.
  • the heat sink 800 is On the welding surface, the support component 900 is pre-implanted through ultrasonic waves.
  • the support component 900 is a metal wire, such as a copper wire or an aluminum wire. As shown in FIG. 23a, these metal line segments can be used to support the first metal-clad substrate 100, and also promote the escape of bubbles during reflow soldering to avoid the generation of pores and affect the soldering reliability.
  • the heat sink 800, the thermistor 620, the gate resistor 610, the second metal-clad substrate 500 and the lead frame 1000 can be configured with solder materials to achieve one-time reflow soldering or multiple reflow soldering, specifically according to Need to set.
  • Each corresponding solder may be in the form of a solder piece or solder paste.
  • solder when the solder is a solder sheet, formic acid vapor is used for vacuum reflow, and a placement machine is used to place the solder sheet into the corresponding position. Then, the second metal-clad substrate 500, the thermistor 620, the gate resistor 610, the first connecting piece 300, and the lead frame 1000 are placed on the corresponding solder pieces using a patch equipment.
  • the gate resistor 610 and the thermistor 620 can be welded on the second metal-clad substrate 500 , or the second metal-clad substrate 500 can be placed on the solder tabs on the first metal-clad substrate 100 .
  • the solder paste when the solder is solder paste, the solder paste is applied to the location to be soldered through 3D printing or dispensing, and the second metal-clad substrate 500, thermistor 620, gate resistor 610, The first connecting piece 300 and the lead frame 1000 are placed on the corresponding solder paste using patch equipment. Tighten the fixing bolts and put them into a vacuum reflow oven for soldering.
  • Step S300 Form conductive lines between components as needed.
  • conductive wires which are aluminum wires or copper wires.
  • the fourth electrode 520a and the second connection terminal 732 in the second metal-clad substrate 500a under the thermistor 620 are connected through the third conductive wire 170 (as shown in FIG. 20 ), and the fifth electrode 530a and the The three connection terminals 733 are connected through a fourth conductive wire 180 .
  • the fourth electrode 520 and the first connection terminal 731 in the second metal-clad substrate 500 below the gate resistor 610 are connected through a second conductive line 720 (as shown in FIG. 16 ).
  • the first solder S1, the second solder S2, the third solder S3, the fourth solder S4, the fifth solder S5, the sixth solder S6, the seventh solder S7, and the eighth solder S8 are solder pieces, since the shape of the soldering piece is in a solid state, during reflow soldering in step S200, the surface of the product is relatively clean and does not need to be cleaned, and conductive lines can be formed directly.
  • the solder paste when the first solder S1, the second solder S2, the third solder S3, the fourth solder S4, the fifth solder S5, the sixth solder S6, the seventh solder S7, and the eighth solder S8 contain solder paste.
  • the solder paste since the form of the solder paste is in a solid state, during the reflow soldering in step S200, the solder paste will be sputtered onto the surface of the product or metal layers such as the first metal layer 120 and the second metal layer 130, causing the electronic components 600, Other components or metal layers such as the first metal layer 120 and the second metal layer 130 contain solder paste, organic matter or flux in the solder paste, which need to be cleaned before forming conductive lines.
  • Step S400 Form a plastic sealing layer 1200 on the first metal-clad substrate 100 and the component.
  • step S300 the product is put into a plastic mold for plastic sealing, and the first metal-clad substrate 100 and the electronic component 600 are sealed between the plastic seal layer 1200 and the heat sink 800 (as shown in FIG. 30 ).
  • an interface stress reliever is used to enhance the bonding strength of the plastic sealing layer 1200.
  • the interface bonding enhancer can be organic, sprayed or immersed, and dried to form a stress relaxation film.
  • Organic matter containing copper may also be formed on the surface of the metal layer (eg, copper layer) of the first metal-clad substrate 100 to increase the bonding force between the plastic sealing layer 1200 and the metallic copper layer.
  • appropriate module molding can be achieved by selecting and optimizing a suitable material for the molding layer 1200 and improving the molding interface.
  • the plastic sealing material uses a low modulus plastic sealant.
  • the plastic sealing material can be formed from a material with an elastic modulus between 0.5GPa and 20GPa. , such as epoxy plastic sealing materials, etc., are not limited here.
  • the method of manufacturing the power module 10 further includes cutting the lead frame 1000 to form corresponding connection terminals, such as first connection terminals, second connection terminals, and third connection terminals, after the plastic packaging is completed, and cutting the connection terminals. Electroplating to prevent corrosion of connection terminals and increase installation performance and welding wettability.
  • the heat sink 800 includes a heat sink bottom plate 810 and a heat sink cover 820.
  • the heat sink bottom plate 810 can be pre-soldered to the side of the first metal-clad substrate 100 away from the chip 200.
  • the radiator cover 820 is sealed on the radiator bottom plate 810 through the sealing ring 830, and a channel is formed between the radiator bottom plate 810 and the radiator cover 820 for the cooling medium to circulate.
  • the radiator cover 820 and the radiator bottom plate 810 can be welded with solder to seal and weld the radiator cover 820 and the radiator bottom plate 810 .

Abstract

本申请提供一种功率模块、电源系统、车辆及光伏系统，功率模块包括第一覆金属层基板、多个芯片和第一连接片，每一个芯片的第一电极与第一覆金属层基板的第一金属层电连接，第一连接片包括第一主体部和多个第一接触部，多个芯片中每一芯片的第二电极均与至少一个第一接触部相接触，至少一对相邻的第一接触部之间具有部分第一主体部。本申请中从芯片流出的电流可直接通过第一接触部流入第一主体部中，减少电流流通路径，通过第一连接片并联连接各芯片，可降低功率模块的寄生电感和提升功率模块的均流性。

Description

功率模块、电源系统、车辆及光伏系统
本申请要求于2022年5月18日提交中国专利局、申请号为202210542672.X、申请名称为“功率模块、电源系统、车辆及光伏系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，特别涉及一种功率模块、电源系统、车辆及光伏系统。
背景技术
随着电力电子技术的发展，功率模块已经吸引了越来越多的关注。功率模块中的半导体芯片的电气连接主要是靠铝线焊接技术来实现，将半导体芯片的栅极、源极通过铝线与基板表面铜层，但是当功率模块中布局较多个芯片时，铝线的数量也会相应增加，较多的铝线会增加功率模块的寄生电感，并且当多个芯片并联时，多铝线连接会使得并联的多个芯片之间的电流不均匀，电流不均匀会使得并联芯片的发热量不均，局部发热严重会影响芯片的性能，而影响功率模块的性能。
发明内容
本申请提供一种可降低寄生电感和提升均流性的功率模块。
第一方面，本申请提供一种功率模块，所述功率模块包括第一覆金属层基板、多个芯片和第一连接片，所述第一覆金属层基板包括第一绝缘基板和位于所述第一绝缘基板一侧的第一金属层，所述第一金属层包括背离所述第一绝缘基板的第一表面；所述芯片包括第一电极和第二电极，所述多个芯片位于所述第一金属层远离所述第一绝缘基板的一侧，且所述多个芯片中的每一个芯片的第一电极与所述第一金属层电连接，所述多个芯片中的至少两个芯片沿第一方向间隔排布，所述多个芯片中的至少两个芯片沿第二方向间隔排布，所述第二方向与所述第一方向均平行于所述第一表面且相交；所述第一连接片，位于所述多个芯片远离所述第一绝缘基板的一侧，所述第一连接片包括第一主体部和多个第一接触部，所述多个芯片中每一芯片的第二电极均与至少一个所述第一接触部相接触，至少一对相邻的第一接触部之间具有部分所述第一主体部；所述第一主体部与所述第一金属层绝缘间隔设置。
其中，功率模块包括沿第一方向和沿第二方向排布的多个芯片，通过一个第一连接片将多个芯片并联，一般多个芯片并联会产生电感，在本申请中至少一对相邻的第一接触部之间具有部分第一主体部，由于第一主体部的流通路径比第一接触部中电流的流通路径宽，从芯片的第二电极流出来的电流直接汇入第一主体部上，加强第一方向和第二方向排布的多个芯片之间的连通，改善并联芯片间的寄生参数一致性，进而优化并联的多个芯片间的动态均流性；并且第一连接片还可增加多个芯片沿第一方向和第二方向互联的结构可靠性，保证电流传输稳定性。
在一种可能的实现方式中，沿所述芯片的厚度方向，所述第一主体部与所述芯片的第二电极之间相隔离，所述第一连接片包括一个或多个凹槽，所述凹槽自所述第一主体部朝向所述第一表面凸起，且所述凹槽的槽底为所述第一接触部。第一主体部与芯片的第二电极之间 相隔离，且凹槽自第一主体部朝向第一表面凸起，使得第一主体部在芯片的第二电极的上方，以提升第一主体部与第一金属层的电性绝缘性。
在一种可能的实现方式中，所述第一连接片包括一个或多个折弯结构，所述折弯结构包括与所述芯片的第二电极接触的所述第一接触部。其中折弯结构是指朝向第一表面弯折的结构，折弯结构远离第一主体部的一端朝向第一表面凸起，第一接触部为该凸起的部分，第一接触部与第二电极接触，使得第一主体部位于第二电极的上方，以提升第一主体部与第一金属层的电性绝缘性。
在一种可能的实现方式中，所述第一连接片为一体成型结构。一体成型结构可提升电流流通顺畅性，降低电流流通阻力，提升均流性和降低电感，还可提升第一连接片的可靠性。
在一种可能的实现方式中，每一对相邻的第一接触部之间均具有部分所述第一主体部。使得每一个第一接触部均与第一主体部直接连接，使得从每一个芯片的第二电极流出来的电流通过第一接触部直接汇入第一主体部上，加强第一方向和第二方向排布的多个芯片之间的连通，改善并联芯片间的寄生参数一致性，进而优化并联的多个芯片间的动态均流性。
在一种可能的实现方式中，所述第一接触部分布于所述第一主体部的边缘。第一主体部的边缘的分布区域大，可分布更多个第一接触部，进而可并联更多个芯片，提升功率模块的功率密度。
在一种可能的实现方式中，功率模块包括两个沿第一方向间隔排布的第一芯片子组，第一芯片子组中包括至少两个沿第二方向间隔排布的芯片，第一主体部包括第一主干和多个第一分支，第一主干沿第二方向延伸，第一分支沿第一方向位于第一主干的两侧并与第一主干连接；在第一方向，第一主干位于相邻两个第一芯片子组之间，在第二方向上，第一分支位于相邻的两个第一接触部之间，且第一分支与沿第二方向相邻的两个第一接触部连接，第一主干与第二金属层电连接。在本实现方式中，包括两个第一芯片子组，每个第一芯片子组中具有至少两个芯片，第一连接片连接两个第一芯片子组中的芯片，以将两个第一芯片子组中的芯片并联。其中，第一分支将沿第二方向排布的相邻两个芯片上的第一接触部连接，从这两个第一接触部出来的至少部分电流可通过第一分支汇入第一主干，第一分支直接连接在两个第一接触部之间，可缩短相邻的两个芯片的并联路径，提升均流性。
在一种可能的实现方式中，至少部分第一接触部与第一主干相间隔。例如可将第一芯片子组两端的芯片上的第一接触部与第一主干相间隔，可减轻第一连接片的重量。
在一种可能的实现方式中，所述功率模块还包括第二金属层，所述第一金属层和所述第二金属层位于第一绝缘基板的同一侧，且所述第一金属层和所述第二金属层在所述第一绝缘基板上的正投影间隔设置，所述第一连接片还包括第二接触部，第二接触部与所述第二金属层电连接。第一主体部汇流后的电流可通过第二接触部流入第二金属层。电流流动方向依次为：输入端、第一金属层、芯片的第一电极、芯片的第二电极、第一接触部、第一主体部、第二接触部、第二金属层。
在一种可能的实现方式中，邻近第二接触部的第一接触部还与第二接触部连接。使得第一接触部流出的电流直接流入第二接触部，无需绕路，减少电流阻力和缩短电流流通路径，进而减少电感。
在一种可能的实现方式中，邻近第二接触部的第一接触部还与第一主干连接。第一接触部与第一主干相连接，两者之间没有间隙，使得第一接触部流出的电流可直接流入第一主干，无需绕路，减少电流阻力和缩短电流流通路径，进而减少电感。在本实施方式中，第一接触部与第二接触部、第一主干均相连接，进一步减少电感和提升均流性。
在一种可能的实现方式中，第一接触部、第二接触部和第一主体部为一体成型结构。其中第二接触部为第一连接片自第一主体部向第二金属层凸出的凹槽或者折弯结构。一体成型结构提升第一连接片的可靠性，且使得第一接触部、第二接触部和第一主体部之间的电流流通阻力降低，进而可降低电感和提升均流性。
在一种可能的实现方式中，第一连接片为一体成型矩形片状结构。第一接触部自第一主体部向芯片凸出的凹槽或者折弯结构，第二接触部自第一主体部向第二金属层凸出的凹槽或者折弯结构。一体成型矩形片状结构可使两个第一芯片子组中的芯片排布更紧密，提升并联芯片之间的均流性，并且可有效降低寄生电感。
在一种可能的实现方式中，功率模块包括两组串联设置的芯片组，分别为第一芯片组和第二芯片组，第一芯片组位于第一金属层远离第一绝缘基板的一侧，第二芯片组位于第二金属层远离第一绝缘基板的一侧，功率模块还包括第二连接片，第二连接片位于第二芯片组远离第一绝缘基板的一侧，第二芯片组中的多个芯片通过第二连接片并联。两组串联设置的芯片组可提升功率模块的功率密度。
在一种可能的实现方式中，所述功率模块还包括第二覆金属层基板和电子元器件，所述第二覆金属层基板位于所述第一表面上，所述电子元器件位于所述第二覆金属层基板远离所述第一覆金属层基板的一侧，且与所述第二覆金属层基板电连接。
由于电子元器件的尺寸一般比较小，如果直接将电子元器件焊接在第一覆金属层基板上，需要在第一覆金属层基板的金属层上开绝缘沟槽，将电子元器件的两个电极与绝缘沟槽两侧的金属层电连接，在第一覆金属层基板上开绝缘沟槽，会减少芯片的布置空间，并且第一覆金属层基板设有较多的芯片，在第一覆金属层基板上的金属层中蚀刻开槽，可能会损坏预先布置好的芯片或者其他电子器件。在本实现方式中，通过第二覆金属层基板转接电子元器件，使得电子元器件焊接工艺简单，相较于直接将电子元器件焊接在第一覆金属层基板的金属层上，可节省在第一覆金属层基板的金属层上开绝缘沟槽的步骤，使得第一覆金属层基板上的电路设计更简单，可预先根据电子元器件的尺寸和电子元器件的两个电极的位置在第二覆金属层基板上设有绝缘沟槽，在第二覆金属层基板上蚀刻绝缘沟槽，不会影响第一覆金属层基板上的芯片的性能，再将电子元器件与第二覆金属层基板电连接。
在一种可能的实现方式中，所述芯片还包括第三电极，所述电子元器件为门极电阻，所述第二覆金属层基板位于所述第一表面上，所述第二覆金属层基板包括绝缘间隔设置的第四电极和第五电极，所述门极电阻的两端分别与所述第四电极和所述第五电极电连接，所述第四电极用于接收驱动电流，所述第五电极通过第一导电线与所述芯片的第三电极电连接。采用第二覆金属层基板转接门极电阻，使得焊接门极电阻工艺简单。
在一种可能的实现方式中，在所述第一覆金属层基板中，所述第一金属层通过金属焊接层连接在所述第一绝缘基板上；所述第二覆金属层基板还包括第二绝缘基板，所述第四电极和所述第五电极贴合在所述第二绝缘基板的表面上。
在第一覆金属层基板中，沿第三方向，第一绝缘基板朝向芯片的一侧具有两层金属层，两层金属层分别为金属焊接层和第一金属层。如果将电子元器件直接焊接在第一覆金属层基板上，由于电子元器件需要通电流，在第一覆金属层基板上需要设置两个绝缘间隔设置的第六电极和第七电极，需要将第六电极和第七电极之间的部分第四金属层和部分金属焊接层这两层金属层通过蚀刻工艺去掉，沿第三方向蚀刻的尺寸大，会使得第二沟槽的孔径增加，或者说第六电极和第七电极之间的尺寸越大，而电子元器件(例如门极电阻)的尺寸较小，无法焊接在第六电极和第七电极上，或者会使得焊接可靠性差。基于此，通过第二覆金属层基 板转接电子元器件，其中第二覆金属层基板上的金属直接键合在第二绝缘基板上，使得形成的第四电极和第五电极也是直接贴合在第二绝缘基板的表面上，第四电极和第五电极与第二绝缘基板之间没有金属焊接层，在蚀刻开槽形成第四电极和第五电极时不需要蚀刻金属焊接层，使得第四电极和第五电极之间的尺寸可控制的较小，有利于焊接电子元器件(例如门极电阻)。
在一实施方式中，第一覆金属层基板为活性金属焊接基板。活性金属焊接基板是指将铜层或者铝层等金属层通过金属焊料焊接在绝缘基板的两侧表面上，其中可通过蚀刻铜层形成第一金属层、第二金属层、第一端部金属层、端子金属层等功率模块所需要的电路。其中第一覆金属层基板中的第一绝缘基板的材料可为iN或者AlN，使得第一绝缘基板与两侧的金属板焊接可靠性更强，且具有较好的导热性，可提升功率模块的散热效果。
在一实施方式中，第二覆金属层基板为覆铜陶瓷基板。第二绝缘基板为Al2O3陶瓷基板或者AlN陶瓷基板，金属层(例如铜箔)在高温下直接键合到第二绝缘基板上。示例性的，将铜箔在高温下直接键合到Al2O3陶瓷基板上，再将铜箔根据需要形成第四电极和第五电极，在铜箔与Al2O3陶瓷基板之间没有其他金属层，可使第四电极和第五电极之间的间隔尺寸较小，有利于焊接门极电阻。
在一种可能的实现方式中，在第一覆金属层基板中，第一金属层和第二金属层的厚度的取值大于或者等于0.6mm。当第一金属层的厚度的取值在上述范围内时，使得第一金属层具有较高的功率密度，能够快速的将电流传输至并联的多个芯片中，第二金属层的厚度的取值在上述范围时，还可提供第一覆金属层基板的导热能力，进而提升功率模块的散热效果，可使得第二金属层具有较高的功率密度，能够快速的将电流传输至第二芯片组中并联的多个芯片中。第一金属层和第二金属层的厚度的取值越大，使得散热效果越佳，功率密度越大，但是，第一金属层和第二金属层越厚，在蚀刻绝缘沟槽时会使得绝缘沟槽的尺寸越大，由于电子元器件(例如门极电阻)尺寸较小，将电子元器件跨沟槽与两电极焊接会增加工艺难度，基于此，在提升功率模块的功率密度时，可通过设置第二覆金属层基板，降低了焊接电子元器件的工艺难度。
在一种可能的实现方式中，第一覆金属层基板为绝缘金属基板。绝缘金属基板包括绝缘树脂层和位于绝缘树脂层两侧的金属层，其中一侧的金属层按照电气互连要求蚀刻成所需的电路，包括形成第一金属层和第二金属层，当金属层的厚度的取值大于或者等于0.6mm时，使得功率模块具有较高的功率密度，可通过设置第二覆金属层基板来转接电子元器件，来降低焊接电子元器件的工艺难度。
在一种可能的实现方式中，所述电子元器件为热敏电阻，所述第二覆金属层基板位于所述第一金属层远离所述第一绝缘基板的一侧，且邻近所述芯片设置，所述热敏电阻用于监测所述芯片的温度。转接热敏电阻的第二覆金属层基板与芯片位于第一金属层上，可提升检测芯片温度的精确度。
在一种可能的实现方式中，所述功率模块还包括散热器，所述散热器位于所述第一覆金属层基板远离所述芯片的一侧，所述散热器和所述第一覆金属层基板之间设有多个相间隔的支撑组件。为了提高散热效果，散热器可以通过第七焊料焊接在第一覆金属层基板远离芯片的一侧，相较于采用导热硅胶将散热器粘结在第一覆金属层基板的方式，采用焊接的方式，焊接材料的导热效果比导热硅胶效果更好。一般的，在焊接散热器和第一覆金属层基板时需要散热器和第一覆金属层基板施加压力，其中支撑组件可防止第一覆金属层基板和散热器之间的第七焊料，由于加压力导致焊接时熔融的第七焊料被挤出，第七焊料厚度过薄，导致失 效。可在焊接前，将支撑组件键合在散热器朝向第一覆金属层基板的表面上，或者将支撑组件键合在第一覆金属层基板朝向散热器的表面上。其中支撑组件可为金属丝或者金属条。支撑组件还可用于控制第七焊料的厚度，可根据需要设计支撑组件的厚度，以使第七焊料满足需求。
在一种可能的实现方式中，所述支撑组件包括两个平行设置的支撑条，所述支撑条包括至少两个支撑段，相邻两个所述支撑段沿所述支撑条的延伸方向排列且间隔设置。第七焊料填充在两个平行设置的支撑条之间时，第七焊料加压焊接时不容易被挤出，但是在高温焊接时会产生气泡，而气泡不溢出会在焊接层形成气孔，影响焊接可靠度。通过将支撑段之间间隔设置，可促进气泡的溢出，减少气孔。另外，两个平行设置的支撑条能够用于增强对第一覆金属层基板和散热器的支撑强度。
第二方面，本申请提供一种电源系统，所述电源系统包括电源、用电设备以及如上面任一项所述的功率模块，所述电源与所述功率模块的输入端连接，所述用电设备和所述功率模块的输出端连接，所述功率模块用于将所述电源输出的直流电转换为交流电，并将所述交流电传输给所述用电设备。其中，功率模块是将电源输出的直流电的电压、电流、周波数等进行变换的半导体装置，是电源系统进行电力变换的核心装置。例如，该电源系统可以作为电动车的马达控制单元进行直流变换交流的核心装置，作为电动车辆的电池输出直流电，或者将直流电变换为车辆运行所需要的交流电等。
第三方面，本申请提供一种车辆，所述车辆包括车本体和如上面所述的电源系统，所述电源系统安装在所述车本体上。在一些实施方式中，电源系统包括逆变器，逆变器中设有功率模块和控制电路，控制电路与功率模块电连接，控制电路可根据车辆的需要来控制功率模块输出给电机的交流电的性能参数，例如电压、电流、周波数、频率等。
第四方面，本申请提供一种光伏系统，其特征在于，包括光伏组件和如上面任一项所述的功率模块，所述光伏组件与所述功率模块电连接，所述光伏组件产生的直流电通过所述功率模块转换为交流电。
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为了更清楚地说明本申请实施例中的技术方案，下面将对本申请实施例中所需要使用的附图进行说明。
图1是本申请一实施例提供的电源系统的结构示意图；
图2是本申请一实施例提供的车辆的结构示意图；
图3是本申请一实施例提供的光伏系统的结构示意图；
图4是本申请一实施例提供的功率模块的结构示意图；
图5是本申请一实施例提供的功率模块的剖面图；
图6是本申请一实施例提供的功率模块中芯片和第一覆金属层基板的剖面图；
图7是本申请一实施例提供的功率模块去掉第一连接片的结构示意图；
图8是本申请一实施例提供的第一连接片的结构示意图；
图9是本申请一实施例提供的第一连接片的结构示意图；
图10是本申请一实施例提供的第一连接片的结构示意图；
图11是本申请一实施例提供的第一连接片的结构示意图；
图12是本申请一实施例提供的功率模块的结构示意图；
图13是本申请一实施例提供的第二连接片的结构示意图；
图14是本申请一实施例提供的功率模块的结构示意图；
图15是本申请一实施例提供的功率模块的结构示意图；
图16是本申请图15中M部分的局部放大图；
图17是本申请一实施例提供的功率模块的部分剖面图；
图18是本申请一实施例提供的功率模块中第二覆金属层基板和第一覆金属层基板的结构示意图；
图19是本申请一实施例提供的将门极电阻直接焊接第一覆金属层基板上的结构示意图；
图20是本申请图15中N部分的局部放大图；
图21是本申请一实施例提供的功率模块的部分剖面图；
图22是本申请一实施例提供的将热敏电阻直接焊接第一覆金属层基板上的结构示意图；
图23a是本申请一实施例提供的散热器和支撑组件的结构示意图；
图23b是本申请一实施例提供的散热器和支撑组件的结构示意图；
图24是本申请一实施例提供的功率模块中的散热器和第一覆金属层基板之间的焊接面的3D-x-ray图；
图25是本申请一实施例提供的功率模块的制备方法流程图；
图26是本申请一实施例提供的在第一覆金属层基板上贴装芯片的过程示意图；
图27是本申请一实施例提供的在第一覆金属层基板上贴装芯片的过程示意图；
图28是本申请一实施例提供的加压头与芯片的结构示意图；
图29是本申请一实施例提供的焊接治具与功率模块的结构示意图；
图30是本申请一实施例提供的功率模块的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
本文中，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本文中，“上”、“下”等方位术语是相对于附图中的结构示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据结构所放置的方位的变化而相应地发生变化。
为方便理解，下面先对本申请实施例所涉及的英文简写和有关技术术语进行解释和描述。
MOSFET：Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物半导体场效应晶体管。
IGBT：Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管。
本申请提供一种功率模块，包括第一覆金属层基板、多个芯片和第一连接片，第一覆金属层基板包括第一绝缘基板和位于所述第一绝缘基板一侧的第一金属层，所述第一金属层包括背离所述第一绝缘基板的第一表面；所述芯片包括第一电极和第二电极，所述多个芯片位于所述第一金属层远离所述第一绝缘基板的一侧，且所述多个芯片中的每一个芯片的第一电 极与所述第一金属层电连接，所述多个芯片中的至少两个芯片沿第一方向间隔排布，所述多个芯片中的至少两个芯片沿第二方向间隔排布，所述第二方向与所述第一方向均平行于第一表面且相交；第一连接片位于所述多个芯片远离所述第一绝缘基板的一侧，所述第一连接片包括第一主体部和多个第一接触部，所述多个芯片中每一芯片的第二电极均与至少一个所述第一接触部相接触，至少一对相邻的第一接触部之间具有部分所述第一主体部，所述第一主体部与所述第一金属层绝缘间隔设置。第一连接片通过将部分第一主体部设置在与芯片连接的第一接触部之间，使得从芯片第二电极流出的电流可直接通过第一接触部流入第一主体部中，减少电流流通路径，通过第一连接片并联连接各芯片，可使得各芯片之间互连时绕线长减少，进而可降低功率模块的寄生电感；且能够第一连接片与每个芯片均连接，且第一连接片的流通路径宽，电流流通阻力少，可提升功率模块各芯片之间的均流性。
请参阅图1，本申请一实施方式提供一种电源系统1，电源系统1包括功率模块10、电源11以及用电设备12，电源11与功率模块10的输入端101连接，用电设备12和功率模块10的输出端102连接，功率模块10用于将电源10输出的直流电转换为交流电，并将交流电传输给用电设备12。其中，功率模块10是将电源11输出的直流电的电压、电流、周波数等进行变换的半导体装置，是电源系统1进行电力变换的核心装置。例如，该电源系统1可以作为电动车的马达控制单元进行直流变换交流的核心装置，作为电动车辆的电池输出直流电，或者将直流电变换为车辆运行所需要的交流电等。
请参阅图2，图2为本申请一实施方式提供一种车辆2，车辆2包括车本体21和如前所述的电源系统1，电源系统1安装在车本体21上。其中电源系统1为车辆2提供动力源，本申请中的电源系统1具有较高的功率密度，应用在车辆2中可提升车辆2动力性能。其中车辆2包括汽车(如图2所示)，在其他实施方式中，车辆2包括电动车或者专项作业车，电动车包括两轮、三轮或者四轮电动车，专项作业车包括各种具有特定功能的车，例如工程抢险车、洒水车、吸污车、水泥搅拌车、起重车、医疗车。在本实施方式中，电源11为车辆2中的电池，用电设备12为车辆2中的电机。在一些实施方式中，电源系统1包括逆变器(图中未示出)，逆变器中设有功率模块10和控制电路(图中未示出)，控制电路与功率模块10电连接，控制电路可根据车辆2的需要来控制功率模块10输出给电机的交流电的性能参数，例如电压、电流、周波数、频率等。
请参阅图3，本申请的功率模块10还可应用在光伏系统3中，图3为本申请一实施方式提供的光伏系统3，光伏系统3包括光伏组件31和功率模块10，光伏组件31与功率模块10电连接，光伏组件31产生的直流电通过功率模块10转换为交流电。其中，功率模块10输出的交流电传输给用电设备，例如基站、数据中心等。
其中，光伏组件31包括至少一块光伏板32，光伏板32与功率模块10连接。在一实施方式中，光伏组件31包括多块串联连接的光伏板32，通过串联的连接方式，将多块光伏板32的直流电汇集后通过连接器与功率模块10连接。在一些实施方式中，光伏系统3包括逆变器(图中未示出)，逆变器中设有功率模块10和控制电路(图中未示出)，控制电路与功率模块10电连接，控制电路可根据用电设备的需要来控制功率模块10输出的交流电的性能参数，例如电压、电流、周波数、频率等。
下面将结合附图和具体实施方式对本申请所提供的功率模块10进行具体说明。
请参阅图4和图5，图4为本申请一实施方式提供的功率模块10的结构示意图，图5为本申请一实施方式提供的功率模块10的剖面图。功率模块10包括第一覆金属层基板100、 多个芯片200和第一连接片300，其中第一覆金属层基板100包括第一绝缘基板110和位于第一绝缘基板110同一侧的第一金属层120和第二金属层130，第一金属层120和第二金属层130位于第一绝缘基板110的同一侧，且第一金属层120和第二金属层130绝缘间隔设置，其中第一金属层120包括背离第一绝缘基板110的第一表面121。
其中，芯片200包括第一电极210和第二电极220(如图6所示)，多个芯片200位于第一金属层120远离第一绝缘基板110的一侧，且多个芯片200中的每一个芯片200的第一电极210与第一金属层120电连接，多个芯片200中的至少两个芯片200沿第一方向X间隔排布(如图4所示)，多个芯片200中的至少两个芯片200沿第二方向Y间隔排布，第二方向Y与第一方向X均平行于第一表面121且相交。
其中，第一连接片300位于多个芯片200远离第一绝缘基板110的一侧，第一连接片300包括第一主体部310和多个第一接触部320。其中，第一接触部320与第一主体部310电连接，多个芯片200中每一芯片200的第二电极220均与至少一个第一接触部320相接触，至少一对相邻的第一接触部320之间具有部分第一主体部310；第一主体部310与第一金属层120绝缘间隔设置。
其中，第一覆金属层基板100包括第一绝缘基板110和位于第一绝缘基板110两侧的金属层，两侧的金属层通过第一绝缘基板110绝缘设置，位于第一绝缘基板110同一侧的金属层中包括所述的第一金属层120和第二金属层130。
第一金属层120和第二金属层130位于第一绝缘基板110的同一侧，且第一金属层120和第二金属层130在第一绝缘基板110上的正投影间隔设置，使得第一金属层120和第二金属层130绝缘间隔设置。示例性的，第一金属层120和第二金属层130之间可通过第一沟槽105间隔而绝缘(如图4所示)，阻断第一金属层120和第二金属层130电流传输；示例性，为了更好的使第一金属层120和第二金属层130之间绝缘，可在第一沟槽105中填充绝缘介质。其中第一主体部310还与第二金属层130电连接，以用于将第一主体部310汇入的电流传输至第二金属层130，或者将第二金属层130中的电流通过第一连接片300传输至芯片200中。
其中第一金属层120和第二金属层130的尺寸和设置位置可根据需要来设置。在本实施方式中，第一金属层120上设有多个芯片200，一般的，第一金属层120的面积较大，占据第一覆金属层基板100的大部分区域，第二金属层130用于连接功率模块10的连接端子，可将第二金属层130设置在第一覆金属层基板100的边缘位置。
请参阅图6，其中，芯片200包括第一电极210、第二电极220、第三电极230和芯片本体240，第一电极210、第二电极220、第三电极230位于芯片本体240上。当芯片200为MOSFET时，芯片200的第一电极210为MOSFET的漏极，芯片200的第二电极220为MOSFET的源极，芯片200的第三电极230为MOSFET的栅极。当芯片200为IGBT时，芯片200的第一电极210为IGBT的集电极，芯片200的第二电极220为IGBT的发射极，芯片200的第三电极230为IGBT的门极。以芯片200为MOSFET为例，当第三电极230(栅极)接收驱动信号时，控制第一电极210(漏极)与第二电极220(源极)之间导通。在本申请中，芯片200的第一电极210与第一金属层120电连接，使得第一金属层120的电流可通过第一电极210传输至芯片本体240的内部，并传输至第二电极220。在本实施方式中，第一电极210位于芯片本体240邻近第一金属层120的表面，第二电极220位于芯片本体240远离第一金属层120的表面上，其中第三电极230与第二电极220设置的芯片本体240远离第一金属层120的一侧，其中第三电极230与第二电极220绝缘间隔设置。
在一实施方式中，芯片本体240的材料为SIC(碳化硅)，SIC可提高芯片200的工作频率，在满足相同工作频率的情况下可减少芯片200体积，使得第一覆金属层基板100上可预留更多的空间用于安装功率模块10的电子元器件，例如热敏电阻、门极电阻等，并且芯片200的工作频率越高，可降低功率模块10周边电子器件例如电容、线圈等的体积。但是芯片200的工作频率越高功率，功率模块10中多个芯片200之间的均流性不好控制，具有导致功率模块10失效的风险，为此，本申请中设有能够改善功率模块10均流性的第一连接片300。
请继续参阅图4，本申请中的第一连接片300包括第一主体部310和与第一主体部310电连接的多个第一接触部320，功率模块10中的多个芯片200通过第一连接片300实现并联，其中一对相邻的第一接触部320是指相邻的两个第一接触部320，至少一对相邻的第一接触部320之间具有部分第一主体部310，使得从第一接触部320流出的电流可直接流入第一主体部310，减少电流流通路径，以降低电感。在一实施方式中，每一对相邻的第一接触部320之间具有部分第一主体部310，使得从每一个第一接触部320流出的电流均可直接流入第一主体部310，进一步减少电流流通路径，以降低电感。
在一具体实施方式中，沿第一方向X排布的两个第一接触部320之间具有部分第一主体部310，可使得沿第一方向X排布的两个第一接触部320流出的电流直接汇入第一主体部310中，减少电流流通路径。示例性的，芯片200a的第二电极与第一接触部320a接触，芯片200b的第二电极与第一接触部320b接触，第一接触部320a和第一接触部320b为一对相邻的第一接触部，第一接触部320a和第一接触部320b之间具有部分第一主体部310，使得从芯片200a流出的电流通过第一接触部320a直接汇入第一主体部310中，芯片200b流出的电流通过第一接触部320b直接汇入第一主体部310中，减少芯片200a和芯片200b电流流通路径。
沿第二方向Y排布的两个第一接触部320之间具有部分第一主体部310，可使得沿第二方向Y排布的两个第一接触部320流出的电流直接汇入第一主体部310中，减少电流流通路径。示例性的，芯片200a的第二电极与第一接触部320a接触，芯片200c的第二电极与第一接触部320c接触，第一接触部320a和第一接触部320c为一对相邻的第一接触部，第一接触部320a和第一接触部320c之间具有部分第一主体部310，使得从芯片200a流出的电流通过第一接触部320a直接汇入第一主体部310中，芯片200c流出的电流通过第一接触部320c直接汇入第一主体部310中，减少芯片200a和芯片200c电流流通路径。
由于第一主体部310具有较宽的流通路径，当各芯片200流出的电流直接汇入第一主体部310后，流通路径短，可降低寄生电感，每个芯片200并联在第一连接片300上，使得芯片200分布集中，可提升各芯片200之间的均流性。
在本实施方式中，功率模块10还包括输入端101和输出端102(如图4所示)，输入端101用于输入电流，且输入端101与第一金属层120电连接。当输入端101根据需要输入电流后，电流通过第一金属层120流入芯片200中，芯片200中的电流从第一电极210流至第二电极220后，第一接触部320用于将第二电极220的电流汇流至第一主体部310中，第一主体部310用于将汇流后的电流传输至第二金属层130中，并通过第二金属层130流入至输出端102，通过输出端102流出功率模块10。电流流动方向依次为：输入端101、第一金属层120、芯片200的第一电极210、芯片200的第二电极220、第一接触部320、第一主体部310、第二金属层130、输出端102。
如果不设置第一主体部310，将每个芯片200的电流通过第一接触部320直接与第二金属层130连接的方案，需要增加每个第一接触部320的长度，才能使第一接触部320与第二金属层130连接，而增加每个第一接触部320的长度，使得多个第一接触部320的布线增加， 会增强寄生电感；并联的多个芯片200只能通过第二金属层130才能连到一起，使得多个芯片200的寄生参数一致性较差，且各个芯片200的均流性也不好。如果采用铝线连接第一接触部320与第二金属层130，铝线的寄生电感更强，并联的多个芯片200的均流性更差。如果采用同一个连接片连接沿第二方向Y上的两个或者三个以上的芯片200，并将连接片连接第二金属层130，相较于采用铝线连接的方式，可减少寄生电感，但是每个芯片200连接在连接片的不同的位置，每个芯片200与第二金属层130的距离不同，离第二金属层130最远的芯片200流出的电流还需要流经沿第二方向Y相邻的芯片200上的部分连接片，使得邻近第二金属层130的芯片200的电流流通阻力增加，同样会增加寄生电感，且并联芯片200之间的均流性也会变差。
在本申请中，电流无需流经每个芯片200的第二电极220上的第一接触部320，由于第一主体部310的流通路径比第一接触部320中电流的流通路径宽，从每个芯片200的第二电极220流出来的电流直接汇入第一主体部310上，加强第一方向X和第二方向Y排布的多个芯片200之间的连通，改善并联芯片200间的寄生参数一致性，进而优化并联的多个芯片200间的动态均流性；并且第一连接片300还可增加多个芯片200沿第一方向X和第二方向Y互联的结构可靠性，保证电流传输稳定性。
为了节省功率模块10的空间，使得功率模块10上的元器件排布更简洁，在本实施方式中，第一方向X为功率模块10的长度方向，第二方向Y为功率模块10的宽度方向。在一些实施方式中，第一方向X为功率模块10的宽度方向，第二方向Y为功率模块10的长度方向。为了适应功率模块10中元器件的排布，在一些实施方式中，第一方向X与功率模块10的宽度方向相交，第二方向Y与功率模块10的长度方向相交。
请继续参阅图4，在一种可能的实现方式中，沿芯片200的厚度方向，第一主体部310与芯片200的第二电极220之间相隔离，第一连接片300包括一个或多个凹槽301，凹槽301自第一主体部310朝向第一表面121凸起，且凹槽301的槽底为第一接触部320。其中，芯片200的厚度方向为第三方向Z，第三方向Z与第一方向X、第二方向Y均垂直相交。第一主体部310与芯片200的第二电极220之间相隔离，且凹槽301自第一主体部310朝向第一表面121凸起，使得第一主体部310在芯片200的第二电极220的上方，以提升第一主体部310与第一金属层120的电性绝缘性。在一实施方式中，第一接触部320可全部为凹槽301的槽底。
值得注意的是，在一种可能的实现方式下，所述凹槽的周壁可以是完整的，也即所述凹槽的周壁的剖面可以是一个完整的环状结构。在另一种可能的实现方式下，所述凹槽的周壁也可以是不完整的，也即所述凹槽的周壁的剖面是一个开口的结构，如图4中的第一接触部320a或320b所示，该第一接触部320a或320b的具体实现形式均为凹槽，但是该凹槽的周壁的剖面是一个U型结构。应当知道的是，在所述凹槽的周壁的剖面是一个开口结构时，该开口结构具体还可以呈L型或V型等。
在一种可能的实现方式中，沿芯片200的厚度方向，第一主体部310与芯片200的第二电极220之间相隔离，第一连接片300包括一个或多个折弯结构302，折弯结构302包括与芯片200的第二电极220接触的第一接触部320。其中折弯结构302是指朝向第一表面121弯折的结构，折弯结构302远离第一主体部310的一端朝向第一表面121凸起，第一接触部320为该凸起的部分，第一接触部320与第二电极220接触，使得第一主体部310位于第二电极220的上方，以提升第一主体部310与第一金属层120的电性绝缘性。在一实施方式中，第一接触部320可全部为折弯结构302与芯片200的第二电极220接触的部分。在一实施方 式中，部分第一接触部320可为凹槽301的槽底，部分第一接触部320可为折弯结构302与芯片200的第二电极220接触的部分。
在一种可能的实现方式中，第一接触部320分布于第一主体部310的边缘。第一主体部310的边缘的分布区域大，可分布更多个第一接触部320，进而可并联更多个芯片200，提升功率模块10的功率密度。
请结合图4、图7和图8，图7为图4中去除第一连接片300的结构示意图，图8为第一连接片300的结构示意图。在一种可能的实现方式中，功率模块10包括两个沿第一方向X间隔排布的第一芯片子组203(如图7所示)，第一芯片子组203中包括至少两个沿第二方向Y间隔排布的芯片200，第一主体部310包括第一主干311和多个第一分支312(如图8所示)，第一主干311沿第二方向Y延伸，第一分支312沿第一方向X位于第一主干311的两侧并与第一主干311连接；在第一方向X，第一主干311位于相邻两个第一芯片子组203之间，在第二方向Y上，第一分支312位于相邻的两个第一接触部320之间，且第一分支312与沿第二方向Y相邻的两个第一接触部320连接，第一主干311与第二金属层130电连接。
在图4和图7所示的实施方式中，包括两个第一芯片子组203，每个第一芯片子组203中具有三个芯片200，第一连接片300连接两个第一芯片子组203中的芯片200，以将两个第一芯片子组203中的芯片200并联。其中，第一分支312将沿第二方向Y排布的相邻两个芯片200上的第一接触部320连接，从这两个第一接触部320出来的至少部分电流可通过第一分支312汇入第一主干311，第一分支312直接连接在两个第一接触部320之间，可缩短相邻的两个芯片200的并联路径，提升均流性。
在一实施方式中，至少部分第一接触部320与第一主干311相间隔。例如可将第一芯片子组203两端的芯片200上的第一接触部320与第一主干311相间隔，可减轻第一连接片300的重量。
请继续参阅图4，在一实施方式中，第一连接片300还包括第二接触部330，第二接触部330位于第二金属层130远离第一绝缘基板110的一侧，且与第二金属层130电连接，在第二方向Y上，第二接触部330位于第一主体部310的一端且与第一主体部310连接。具体的，第二接触部330位于第一主干311的一端(如图8所示)，其中输入端101位于第一主干311远离第二接触部330的一侧。在一实施方式中，第二接触部330与第二金属层130通过焊接而连接。第一主体部310汇流后的电流可通过第二接触部330流入第二金属层130。电流流动方向依次为：输入端101、第一金属层120、芯片200的第一电极210、芯片200的第二电极220、第一接触部320、第一主体部310、第二接触部330、第二金属层130。
在图4中，为了实现功率模块10中电路的特定设计需要，可将邻近第二接触部330的第一接触部320c与第一主干311相间隔。
请参阅图9，在一种可能的实现方式中，邻近第二接触部330的第一接触部320c还与第二接触部330连接。使得第一接触部320c流出的电流直接流入第二接触部330，无需绕路，减少电流阻力和缩短电流流通路径，进而减少电感。在图9所示的实施方式中，第一接触部320c与第一主干311通过间隙J相间隔。
请参阅图10，在一种可能的实现方式中，邻近第二接触部330的第一接触部320c还与第一主干311连接。第一接触部320c与第一主干311相连接，两者之间没有间隙，使得第一接触部320c流出的电流可直接流入第一主干311，无需绕路，减少电流阻力和缩短电流流通路径，进而减少电感。在本实施方式中，第一接触部320c与第二接触部330、第一主干311均相连接，进一步减少电感和提升均流性。
请继续参阅图8，在一种可能的实现方式中，第一接触部320、第二接触部330和第一主体部310为一体成型结构，第一接触部320自第一主体部310向芯片200凸出，第二接触部330自第一主体部310向第二金属层130凸出。
在本实施方式中，第一连接片300为一体成型结构，位于芯片200远离第一绝缘基板110一侧的部分第一连接片300向芯片200凸设而形成第一接触部320，位于第二金属层130远离第一绝缘基板110一侧的部分第一连接片300向第一绝缘基板110凸设形成第二接触部330，第一连接片300除了第一接触部320、第二接触部330之外的部分为第一主体部310。在本实施方式中，第一接触部320、第二接触部330和第一主体部310为一体成型结构，第一接触部320、第二接触部330和第一主体部310可通过冲压工艺、压铸工艺形成。相较于采用其他部件将第一接触部320、第二接触部330和第一主体部310连接构成第一连接片300，第一接触部320、第二接触部330和第一主体部310为一体成型结构，可提升电流流通顺畅性，降低电流流通阻力，提升均流性和降低电感，另一方面可提升第一连接片300的可靠性。
请参阅图11，在一种可能的实现方式中，第一连接片300为一体成型矩形片状结构，第一接触部320自第一主体部310向芯片200凸出的凹槽或者折弯结构，第二接触部330自第一主体部310向第二金属层130凸出的凹槽或者折弯结构。一体成型矩形片状结构可使两个第一芯片子组203中的芯片200排布更紧密，提升并联芯片200之间的均流性，并且可有效降低寄生电感。
请参阅图12，在一种可能的实现方式中，功率模块10包括两组串联设置的芯片组，分别为第一芯片组201和第二芯片组202，第一芯片组201位于第一金属层120远离第一绝缘基板110的一侧，第二芯片组202位于第二金属层130远离第一绝缘基板110的一侧，功率模块10还包括第二连接片400，第二连接片400位于第二芯片组202远离第一绝缘基板110的一侧，第二芯片组202中的多个芯片200通过第二连接片400并联。
如图13所示，第二连接片400包括第二连接主体410和与第二连接主体410电连接的多个第三连接结构420和第四连接结构430，多个第三连接结构420分别与第二芯片组202中的多个芯片200电连接，部分第二连接主体410位于沿第一方向X排布的两个第三连接结构420之间，部分第二连接主体410位于沿第二方向Y排布的两个第三连接结构420之间，第二连接主体410与第二金属层130绝缘间隔设置，第四连接结构430与功率模块10的输出端102电连接。在本实施方式中，第二连接片400与第一连接片300反向设置，输出端102与输入端101位于功率模块10的同一端。在本实施方式中，第二连接主体410包括第二主干和第二分支，其中第二连接片400中第二主干和第二分支的结构与第一连接片300的结构相同，其中，上述第一连接片300的各种可实现的方式也适用于第二连接片400，在此不再赘述。
在本实施方式中，功率模块10还包括第一端部金属层140，第一端部金属层140与第一金属层120、第二金属层130绝缘间隔设置，第四连接结构430通过第一端部金属层140与输出端102电连接。第四连接结构430固定连接在第一端部金属层140上，第一端部金属层140与输出端102连接。
在本实施方式中，当输入端101输入电流后，电流的流径方向为：输入端101、第一金属层120、第一芯片组201、第一连接片300、第二金属层130、第二芯片组202、第二连接片400、第一端部金属层140、输出端。其中第一芯片组201中的各芯片200通过第一连接片300并联，第二芯片组202中的各芯片200通过第二连接片400并联。
在一些实施方式中，功率模块10可根据需要来设置芯片组的个数，以及设置每个芯片组中芯片200的个数，芯片组之间串联或者并联的方式可根据需要来设置。
请参阅图14，在一种可能的实现方式中，功率模块10包括两组串联设置的芯片组，分别为第一芯片组201和第二芯片组202，第一芯片组201位于第一金属层120远离第一绝缘基板110的一侧，第二芯片组202位于第二金属层130远离第一绝缘基板110的一侧，功率模块10还包括第一连接片300和第二连接片400，第一连接片300位于第一芯片组201远离第一绝缘基板110的一侧，第一芯片组201中的多个芯片200通过第一连接片300并联，第二连接片400位于第二芯片组202远离第一绝缘基板110的一侧，第二芯片组202中的多个芯片200通过第二连接片400并联。在本实施方式中，第一连接片300的结构方式采用如图11所示的第一连接片300的结构方式，其中第二连接片400与第一连接片300的结构相同。
本申请为了说明图12中第一连接片300、第二连接片400和图14所示实施方式中的第一连接片300、第二连接片400的结构的优异性，对图12和图14所示的实施方式进行仿真测试，发现图14所示的功率模块10的寄生电感小于图12所示的功率模块10的寄生电感，这说明书，图14中的第一连接片300和第二连接片400采用一体成型矩形片状结构，可有效提升并联芯片200之间的均流性，并且可有效降低寄生电感。本申请还对图12所示的实施方式中和采用导电线并联各芯片200的方式进行仿真测试，发现图12所示的实施方式可有效提升并联芯片200之间的均流性，并且可有效降低寄生电感。
请继续参阅图5，在一实施方式中，第一接触部320可通过第一焊料S1与芯片200的第二电极220焊接，第二接触部330可通过第二焊料S2与第二金属层130焊接。第一焊料S1和第二焊料S2可选自锡焊料和铅焊料中的至少一种，其中锡焊料可选自SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化、SnSb10中的至少一种，可根据需要来选择第一焊料S1和第二焊料S2的材料，第一焊料S1和第二焊料S2可相同或者不相同。其中，SnSb5是指在Sn元素中含重量百分数为5％的Sb元素，SnSb8是指在Sn元素中含重量百分数为8％的Sb元素，SnSb10是指在Sn元素中含重量百分数为10％的Sb元素，SAC306中的SAC代表的是Sn、Ag、Cu这三个金属元素，表示这个产品是由Sn(锡)、Ag(银)、Cu(铜)三种金属成分组成的，其中，3代表含3％的Ag，05代表含有0.5％的Cu。SAC多元强化在Sn(锡)、Ag(银)、Cu(铜)三种金属成分中还包括其他金属成分，以强化焊料的可靠性。
请继续参阅图5，在一种可能的实现方式中，芯片200通过烧结材料SJ连接在第一金属层120上。示例性的，烧结材料SJ可以由银膏、铜膏或银膜形成。在一具体实施方式中，银膏可以包括微米银膏(Micrometer silver particle paste)和纳米银膏(Nanometer silver particle paste)中至少一种。其中，微米银膏是指使用微米银粒子和有机溶剂制作的银膏，成本低，安全。一般在加压下烧结，烧结材料SJ致密性高，被接合体界面接合牢固，接合可靠性高。
可选的，为了提高烧结接合的可靠性以及降低成本，本申请的烧结材料SJ可以采用微米银膏(Micrometer silver particle paste)形成。
为了提高烧结接合的可靠性，可以通过在烧结材料SJ中增加材料来调节烧结材料SJ的弹性模量、热膨胀系数(CTE)等。示例性的，该烧结材料SJ包括主体材料和填充在主体材料中的填料；其中主体材料包括银膏、铜膏或银膜中的至少一种，该填料由与主体材料接合性好的材料形成，且该填料的热膨胀系数小于主体材料的热膨胀系数，从而提高烧结的接合可靠性。
以主体材料为微米银膏为例，在微米银膏中加入填料来降低微米银膏的热膨胀系数，降低接合应力，从而提高银烧接的接合可靠性。示例性的，填料可以包括镍(Ni)、Ni合金、铜(Cu)、铜镀镍、钛(Ti)、Ti合金、铁(Fe)、Fe合金、可伐合金(Kovar，铁镍钴合金4J29)和SiC粉末等中的至少一种，在此不作限定。
本申请对填料的形状不作限定，示例性的，填料的长度可以控制在20μm～100μm之间， 填料在垂直长度方向的尺寸可以控制在20nm～30μm之间。沿长度方向的横截面可以为圆形，椭圆形，多边形等。
在本申请中，第一金属层120一般为铜，当烧结材料SJ为银膏或银膜时，为了提高烧结材料SJ与第一金属层120的接合性能，第一金属层120在烧结处可以镀银，即第一金属层120在与烧结材料对应的区域覆盖有镀银层。示例性的，镀银层的厚度可以控制在0.1μm～30μm之间。如果烧结材料SJ自身与第一覆金属层基板的接合性能比较好时，也可以不用镀银，例如当烧结材料为铜膏时，第一覆金属层基板100在烧结处不需要镀银。
请结合图5、图15和图16，图15为本申请一实施方式中提供的功率模块10的结构示意图，图16是图15中的M部分的局部放大图。在一种可能的实现方式中，功率模块10还包括第二覆金属层基板500和电子元器件600(如图16所示)，第二覆金属层基板500位于第一覆金属层基板100的金属层的表面上，电子元器件600位于第二覆金属层基板500远离第一覆金属层基板100的一侧，且与第二覆金属层基板500电连接。其中，第一覆金属层基板100的金属层包括第一金属层120、第二金属层130或者其他金属层中。第二覆金属层基板500可位于第一金属层120或者第二金属层130的表面上。在图16所示的实施方式中，电子元器件600位于第一金属层120的第一表面121上。在一些实施方式中，电子元器件600位于第二金属层130上。需要说明的是，为了表示第二覆金属层基板500和电子元器件600的结构关系，在图15中的第一连接片300的结构进行了简化，在图15中的第一连接片300的结构仅用于示意，第一连接片300的结构、以及第一连接片300与芯片200的连接关系请参阅3至图14等图的相关描述。
由于电子元器件600的尺寸一般比较小，如果直接将电子元器件600焊接在第一覆金属层基板100上，需要在第一覆金属层基板100的金属层上开绝缘沟槽，将电子元器件600的两个电极与绝缘沟槽两侧的金属层电连接，在第一覆金属层基板100上开绝缘沟槽，会减少芯片200的布置空间，并且第一覆金属层基板100设有较多的芯片200，在第一覆金属层基板100上的金属层中蚀刻开槽，可能会损坏预先布置好的芯片200或者其他电子器件。在本实施方式中，通过第二覆金属层基板500转接电子元器件600，使得电子元器件600焊接工艺简单，相较于直接将电子元器件600焊接在第一覆金属层基板100的金属层上，可节省在第一覆金属层基板100的金属层上开绝缘沟槽的步骤，使得第一覆金属层基板100上的电路设计更简单，可预先根据电子元器件600的尺寸和电子元器件600的两个电极的位置在第二覆金属层基板500上设有绝缘沟槽，在第二覆金属层基板500上蚀刻绝缘沟槽，不会影响第一覆金属层基板100上的芯片200的性能，再将电子元器件600与第二覆金属层基板500电连接。
其中，第二覆金属层基板500包括第二绝缘基板510和位于第二绝缘基板510两侧的金属层，电子元器件600与第二绝缘基板510一侧的金属层电连接。
在一种可能的实现方式中，电子元器件600为门极电阻610(如图16所示)，第二覆金属层基板500位于第一表面121上，第二覆金属层基板500包括绝缘间隔设置的第四电极520和第五电极530，门极电阻610的两端分别与第四电极520和第五电极530电连接，第四电极520用于接收驱动电流，第五电极530通过第一导电线710与芯片200的第三电极230电连接。采用第二覆金属层基板500转接门极电阻610，使得焊接门极电阻610工艺简单。
其中，第四电极520和第五电极530为第二绝缘基板510上的部分金属层，根据门极电阻610的尺寸来设置第四电极520和第五电极530之间的绝缘部分，使得第四电极520与第五电极530之间绝缘间隔。
示例性的，第四电极520和第五电极530之间具有第四沟槽550，第四电极520与第五电极530通过第四沟槽550绝缘间隔。其中，可通过第二覆金属层基板500一侧表面的金属层通过蚀刻工艺形成第四电极520、第五电极530和第四沟槽550。
在本实施方式中，功率模块10还包括第二导电线720和第一连接端子731(如图15所示)，第四电极520通过第二导电线720与第一连接端子731连接，外部控制电路发送驱动电流至第一连接端子731，第四电极520接收驱动电流后，请结合图15和图16，驱动电流依次经过第一连接端子731、第二导电线720、第四电极520、门极电阻610、第五电极530和第一导电线710流入芯片200的第三电极230，其中，第三电极230可为门极或者栅极，第三电极230接收驱动电流后，能够驱动第一电极210和第二电极220之间导通。门极电阻610用于改善芯片200的开关性能，能够抑制多个芯片200并联时产生的高频振荡。其中第一导电线710为传输线，例如铝线、铜线等。
请参阅图17，第二覆金属层基板500还包括位于第二绝缘基板510远离第四电极520和第五电极530一侧的第三金属层540，第三金属层540通过第三焊料S3与第一覆金属层基板100表面上的第一金属层120焊接。第三焊料S3可选自锡焊料和铅焊料中的至少一种，其中锡焊料可选自SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化、SnSb10中的至少一种，其中第三焊料S3与第一焊料S1可相同或者不相同，第三焊料S3与第二焊料S2可相同或者不相同。
其中，门极电阻610可通过第四焊料S4焊接在第四电极520和第五电极530上，其中第四焊料S4可选自锡焊料和铅焊料中的至少一种，其中锡焊料可选自SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化、SnSb10中的至少一种，其中第四焊料S4与第一焊料S1可相同或者不相同，第三焊料S3与第二焊料S2可相同或者不相同。
其中，第一连接端子731可通过第八焊料S8焊接在第一覆金属层基板100的边缘的端子金属层上1010。第八焊料S8可选自锡焊料和铅焊料中的至少一种，其中锡焊料可选自SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化、SnSb10中的至少一种。
在一实施方式中，当门极电阻610和第二覆金属层基板500分别为一个时，第一芯片组201中的多个芯片200的第三电极230通过导电线与同一个第二覆金属层基板500的门极电阻610电连接。即一个门极电阻610控制多个芯片200中第一电极210和第二电极220的导通或者截止。
在一实施方式中，门极电阻610和第二覆金属层基板500均为多个时，且每个门极电阻610设置在第二覆金属层基板500时，每个芯片200的第三电极230通过导电线与其中一个第二覆金属层基板500的门极电阻610电连接。即一个门极电阻610控制一个芯片200中第一电极210和第二电极220的导通或者截止。
在本实施方式中，芯片200位于第一金属层120上，将第二覆金属层基板500焊接第一金属层120的表面上，可使部件分布更紧凑。在一些实施方式中，第二覆金属层基板500也可以焊接在第二金属层130的表面。
请参阅图18，图18为第一覆金属层基板100和第二覆金属层基板500的结构示意图。在一种可能的实现方式中，在第一覆金属层基板100中，第一金属层120和第二金属层130通过金属焊接层SH连接在第一绝缘基板110上；在第二覆金属层基板500中，第四电极520和第五电极530贴合在第二绝缘基板510的表面上。
在本实施方式中，第一覆金属层基板100中，沿第三方向Z，第一绝缘基板110朝向芯片200的一侧具有两层金属层，两层金属层分别为金属焊接层SH和第一金属层120。如果将 电子元器件600直接焊接在第一覆金属层基板100上，由于电子元器件600需要通电流，在第一覆金属层基板100上需要设置两个绝缘间隔设置的第六电极103和第七电极104，请参阅图19，例如，在第一金属层120中蚀刻一部分作为第四金属层150，第四金属层150与第一金属层120的其他部分绝缘间隔设置，第四金属层150上蚀刻第二沟槽151形成第六电极103和第七电极104，此时需要将第六电极103和第七电极104之间的部分第四金属层150和部分金属焊接层SH通过蚀刻工艺去掉，沿第三方向Z蚀刻的尺寸大，会使得第二沟槽151的孔径增加，或者说第六电极103和第七电极104之间的尺寸越大，而电子元器件600(例如门极电阻610)的尺寸较小，无法焊接在第六电极103和第七电极104上，或者会使得焊接可靠性差。基于此，在本实施方式中，通过第二覆金属层基板500转接电子元器件600，其中第二覆金属层基板500上的金属直接键合在第二绝缘基板510上，使得形成的第四电极520和第五电极530也是直接贴合在第二绝缘基板510的表面上，第四电极520和第五电极530与第二绝缘基板510之间没有金属焊接层，在蚀刻开槽形成第四电极520和第五电极530时不需要蚀刻金属焊接层，使得第四电极520和第五电极530之间的尺寸可控制的较小，有利于焊接电子元器件600(例如门极电阻610)。
在一实施方式中，第一覆金属层基板100为活性金属焊接基板。活性金属焊接基板是指将铜层或者铝层等金属层通过金属焊料焊接在绝缘基板的两侧表面上，其中可通过蚀刻铜层形成第一金属层120、第二金属层130、第一端部金属层140、端子金属层1010等功率模块10所需要的电路。其中第一覆金属层基板100中的第一绝缘基板110的材料可为Si3N4或者AlN，使得第一绝缘基板110与两侧的金属板焊接可靠性更强，且具有较好的导热性，可提升功率模块10的散热效果。
在一实施方式中，第二覆金属层基板500为覆铜陶瓷基板。第二绝缘基板510为Al2O3陶瓷基板或者AlN陶瓷基板，金属层(例如铜箔)在高温下直接键合到第二绝缘基板510上。示例性的，将铜箔在高温下直接键合到Al2O3陶瓷基板上，再将铜箔根据需要形成第四电极520和第五电极530，在铜箔与Al2O3陶瓷基板之间没有其他金属层，可使第四电极520和第五电极530之间的间隔尺寸较小，有利于焊接门极电阻610。
在一种可能的实现方式中，在第一覆金属层基板100中，第一金属层120和第二金属层130的厚度的取值大于或者等于0.6mm。当第一金属层120的厚度的取值在上述范围内时，使得第一金属层120具有较高的功率密度，能够快速的将电流传输至并联的多个芯片200中，第二金属层130的厚度的取值在上述范围时，还可提供第一覆金属层基板100的导热能力，进而提升功率模块10的散热效果，可使得第二金属层130具有较高的功率密度，能够快速的将电流传输至第二芯片组202中并联的多个芯片200中。第一金属层120和第二金属层130的厚度的取值越大，使得散热效果越佳，功率密度越大，但是，第一金属层120和第二金属层130越厚，在蚀刻绝缘沟槽时会使得绝缘沟槽的尺寸越大，由于电子元器件600(例如门极电阻610)尺寸较小，将电子元器件600跨沟槽与两电极焊接会增加工艺难度，基于此，在提升功率模块10的功率密度时，可通过设置第二覆金属层基板500，降低了焊接电子元器件600的工艺难度。
示例性的，第一金属层120和第二金属层130的厚度的取值大于或者等于0.8mm。
示例性的，第一金属层120和第二金属层130的厚度的取值大于或者等于1.2mm。
在一种可能的实现方式中，第一覆金属层基板100为绝缘金属基板。绝缘金属基板包括绝缘树脂层和位于绝缘树脂层两侧的金属层，其中一侧的金属层按照电气互连要求蚀刻成所需的电路，包括形成第一金属层120和第二金属层130，当金属层的厚度的取值大于或者等 于0.6mm时，使得功率模块10具有较高的功率密度，可通过设置第二覆金属层基板500来转接电子元器件600，来降低焊接电子元器件600的工艺难度。
请继续参阅图15，在一种可能的实现方式中，功率模块10包括两个第二覆金属层基板，其中一个第二覆金属层基板500用于焊接门极电阻610，另一个第二覆金属层基板500a用于焊接热敏电阻620。在一些实施方式中，可只采用一个第二覆金属层基板用于焊接热敏电阻620。
请结合图20和图21，图20为图15中N部分的局部放大图，图21为功率模块10中包括热敏电阻620部分的剖面图。在本实施方式中，电子元器件600为热敏电阻620，第二覆金属层基板500a位于第二金属层130远离第一绝缘基板110的一侧，且邻近位于第二金属层130上的芯片200设置，热敏电阻620用于监测芯片200的温度。在一些实施方式中，电子元器件600为热敏电阻620，第二覆金属层基板500a位于第一金属层120远离第一绝缘基板110的一侧，且邻近位于第一金属层120上的芯片200设置，热敏电阻620用于监测芯片200的温度。也就是说用于转接热敏电阻620的第二覆金属层基板500与芯片200位于相同的金属层上，例如均位于第一金属层120上，或者均位于第二金属层130上。在其他实施方式中，各根据功率模块10的设计需要，将转接热敏电阻620的第二覆金属层基板500与芯片200均设置在其他金属层上。
请参阅图20和图21，在本实施方式中，第二覆金属层基板500a包括绝缘间隔设置的第四电极520a和第五电极530a，热敏电阻620的两端分别与第四电极520a和第五电极530a电连接，功率模块10还包括第二连接端子732和第三连接端子733(如图20所示)，第四电极520a和第五电极530a分别与第二连接端子732和第三连接端子733电连接，第二连接端子732和第三连接端子733与外部控制电路连接，通过热敏电阻620来监测芯片200的温度。其中热敏电阻620可以为负温度系数热敏电阻或者正温度系数热敏电阻。其中第二连接端子732和第三连接端子733可焊接在端子金属层上，每个连接端子下方的端子金属层绝缘间隔设置。
在本实施方式中，功率模块10还包括第三导电线170和第四导电线180，第四电极520a和第二连接端子732之间通过第三导电线170连接，第五电极530a和第三连接端子733之间通过第四导电线180连接。其中第三导电线170和第四导电线180可为铝线或者铜线。
在本实施方式中，将热敏电阻620设置第二覆金属层基板500a上，且该第二覆金属层基板500a设置在第二金属层130上，并将热敏电阻620邻近芯片200设置，使得测温更准确。如果直接将热敏电阻620焊接在第二金属层130上，需要将热敏电阻620焊接在第二金属层130和其他金属层之间的沟槽。请参阅图22，示例性的，功率模块10还包括第二端部金属层160，第二金属层130和第二端部金属层160之间具有第三沟槽106，热敏电阻620的两端设置在第二金属层130和第二端部金属层160上，热敏电阻620只有一端与第二金属层130连接，芯片200位于第二金属层130上，当芯片200工作后发热时，芯片200的温度会直接传给第二金属层130，使得第二金属层130的温度与芯片200的温度接近，当热敏电阻620只有一端与第二金属层130连接，而热敏电阻620的另一端与第二端部金属层160连接时，第二端部金属层160与第二金属层130被第三沟槽106间隔，使得第二金属层130的热量无法传递给第二端部金属层160，第二端部金属层160与第二金属层130的温差较大，使得与第二端部金属层160连接的热敏电阻620的一端的温度比与第二金属层130连接的热敏电阻620的一端的温度低，使得热敏电阻620整体对与芯片200的温度监测精度变差。而在本实施方式中，第二覆金属层基板500a位于第二金属层130中，热敏电阻620焊接在第二覆金属层基 板500a上(如图21所示)，热敏电阻620的两端的温度相接近，并且将第二覆金属层基板500a设置在第一金属层120上且邻近芯片200设置，可提升对芯片200温度的监测精度。
应当可以理解的是，当用于转接热敏电阻620的第二覆金属层基板500与芯片200均位于第一金属层120上时，也能够提升对芯片200的温度的监测精度。
其中，热敏电阻620可通过第五焊料S5焊接在第四电极520a和第五电极530a上，其中第五焊料S5可选自锡焊料和铅焊料中的至少一种，其中锡焊料可选自SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化、SnSb10中的至少一种，其中第五焊料S5与第一焊料S1可相同或者不相同，第五焊料S5与第二焊料S2可相同或者不相同。
其中，第二覆金属层基板500a可通过第六焊料S6焊接在第一金属层120背离第一绝缘基板110的表面上，其中第六焊料S6可选自锡焊料和铅焊料中的至少一种，其中锡焊料可选自SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化、SnSb10中的至少一种，其中第六焊料S6与第一焊料S1可相同或者不相同，第六焊料S6与第二焊料S2可相同或者不相同。
在本实施方式中，第一覆金属层基板100为活性金属焊接基板、绝缘金属基板中的一种，第二覆金属层基板500a为覆铜陶瓷基板。
在一些实施方式中，第二覆金属层基板500上的金属层可作为信号走线使用，有利于提升功率模块10线路分布的灵活性。其中，部分线路可采用第一覆金属层基板100上的金属层制成，部分线路可采用第二覆金属层基板500上的金属层制成，使得线路分布更灵活。
请继续参阅图5，在一种可能的实现方式中，功率模块10还包括散热器800，散热器800位于第一覆金属层基板100远离芯片200的一侧，散热器800和第一覆金属层基板100之间设有多个相间隔的支撑组件900。其中散热器800可为水冷散热器，在此不做限定，用于对功率模块10散热，提升功率模块10的功率密度。在本实施方式中，为了提高散热效果，散热器800可以通过第七焊料S7焊接在第一覆金属层基板100远离芯片200的一侧，相较于采用导热硅胶将散热器800粘结在第一覆金属层基板100的方式，采用焊接的方式，焊接材料的导热效果比导热硅胶效果更好。
其中，第一覆金属层基板100包括位于第一绝缘基板110远离第一金属层120一侧的第五金属层190，散热器800通过第七焊料S7与第五金属层190焊接。散热器800包括散热器底板810和散热器盖板820，在散热器底板810上设有散热齿811，散热齿811之间构成通道，通道内可流通冷却介质，通过冷却介质实现散热。
一般的，在焊接散热器800和第一覆金属层基板100时需要散热器800和第一覆金属层基板100施加压力，其中支撑组件900可防止第一覆金属层基板100和散热器800之间的第七焊料S7，由于加压力导致焊接时熔融的第七焊料S7被挤出，第七焊料S7厚度过薄，导致失效。可在焊接前，将支撑组件900键合在散热器800朝向第一覆金属层基板100的表面上，或者将支撑组件900键合在第一覆金属层基板100朝向散热器800的表面上。其中支撑组件900可为金属丝或者金属条。支撑组件900还可用于控制第七焊料S7的厚度，可根据需要设计支撑组件900的厚度，以使第七焊料S7满足需求。
请参阅图23a，在一种可能的实现方式中，支撑组件900包括两个平行设置的支撑条910，支撑条910包括至少两个支撑段911，相邻两个支撑段911沿支撑条910的延伸方向排列且间隔设置。第七焊料S7填充在两个平行设置的支撑条910之间时，第七焊料S7加压焊接时不容易被挤出，但是在高温焊接时会产生气泡，而气泡不溢出会在焊接层形成气孔，影响焊接可靠度。通过将支撑段911之间间隔设置，可促进气泡的溢出，减少气孔。另外，两个平行设置的支撑条910能够用于增强对第一覆金属层基板100和散热器800的支撑强度。
请参阅图23b，在一些实施方式中，可通过在散热器800朝向第一覆金属层基板100的表面通过冲压的方式形成支撑组件900，其中支撑组件呈凸台状，如图23b中的900a所示；或者支撑组件呈点状，如图23b中的900b所示；或者支撑组件呈火山口状，如图23b中的900c所示。在其他实施方式中，支撑组件900还可为其他形状。在一些实施方式中，散热器800表面上的凸台状、点状或者火山状的支撑组件900可以是一种或一种以上组合。在一些实施方式中，凸台状、点状或者火山状的支撑组件900可分别为一个或者多个，具体可根据需要来设置。
请参阅图24，图24为本申请一实施方式提供的功率模块10中的散热器800和第一覆金属层基板100之间的焊接面的3D-x-ray图，其中图24中的(a)图是从第七焊料S7与第一覆金属层基板100之间的焊接面的3D-x-ray图，图24中的(b)图是从第七焊料S7与散热器800之间的焊接面的3D-x-ray图。在本实施方式中，采用图23a所示的实施方式中的支撑组件900，并用SnSb5焊料作为第七焊料S7将散热器800与第一覆金属层基板100上，将功率模块10进行温冲实验，其中温冲实验条件为：在-40℃(低温)下保持15min，在125℃(高温)下保持15min，一次低温和一次高温算一次循环，进行1000次循环。从图24中可以看出，图中边缘角落区域没有呈现白色，说明第七焊料S7与散热器800之间的焊接面没有剥离，第七焊料S7与第一覆金属层基板100之间的焊接面没有剥离，说明采用图23a所示的支撑组件900可提升散热器800和第一覆金属层基板100之间的焊接可靠性。
在一实施方式中，第七焊料S7选自SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化、铅基高温焊料、SnSb10、过包晶Sn-Sb、Sn-Sb-X中的至少一种，其中铅基高温焊料是指含铅量大于或者等于85％的焊料，需要较高的温度才能熔融，其中Sn-Sb-X是指在Sn和Sb中掺杂其他元素，例如镍、铋、铜。在焊接时可根据第七焊料S7的具体材质来设置焊接的温度，例如当采用铅基高温焊料时，可将焊接温度的取值设为大于或者等于300℃；再例如当采用SAC305时，可将焊接温度的取值设为260℃。
在一些实施方式中，为了节省焊接时间和焊接工艺，通过一次回流焊接工艺将功率模块10中的各部品焊接以及将散热器800焊接；或者通过两次回流焊接工艺，第一次回流焊接工艺将各部品焊接在第一覆金属层基板100上，第二次回流焊接工艺将散热器800焊接在第一覆金属层基板100远离芯片200的一侧。其中各部品包括第一连接片300、第二连接片400、热敏电阻620、门极电阻610以及各连接端子。
请继续参阅图5，示例性的，当第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第七焊料S7、第八焊料S8采用的焊料材质选自SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化中至少一种时，由于SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化这些焊料为中温焊料，且热敏电阻620的可承受的最大温度为260℃，第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第七焊料S7、第八焊料S8可通过一次回流焊接工艺完成，且回流焊接工艺的温度设置为260℃。
示例性的，当第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第八焊料S8采用的焊料材质选自SnSb5、SAC305、SAC多元强化中至少一种时，第七焊料S7采用的焊料材质选自铅基高温焊料、SnSb10、过包晶Sn-Sb、Sn-Sb-X中的至少一种时，由于第七焊料S7为高温焊料，需要在较高的温度下才能熔融实现焊接，而各部品最大耐焊接温度较低，例如热敏电阻620的最大耐焊接温度为260℃，此时需要通过两次回流焊接工艺，第一次回流焊接工艺的温度设置为300℃(或者大于300℃)，将第七焊料S7焊接完成，将散热器800焊接在第一覆金属层基板100远离芯片200的一侧，再进行第二次回流 焊接工艺，第二次回流焊接工艺的温度设置为260℃，此时第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第八焊料S8焊接完成，将与各焊料对应的第一连接片300、热敏电阻620、门极电子610、第一连接端子731等部品焊接在第一覆金属层基板100上。
示例性的，当第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第七焊料S7、第八焊料S8采用的焊料材质选自铅基高温焊料、SnSb10、过包晶Sn-Sb、Sn-Sb-X中的至少一种时，热敏电阻620可选择最大耐焊接温度大于300℃的热敏电阻，使得功率模块10可通过一次回流焊接工艺焊接完成。
示例性的，第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第八焊料S8采用的焊料材质选自Sn-Sb-X、SnSb5、SnSb8、SnSbAg、SAC305、SAC多元强化中的至少一种时，第七焊料S7采用铅基高温焊料、SnSb10和过包晶Sn-Sb时，由于第七焊料S7焊接温度大于第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第八焊料S8的焊接温度，可采用两次回流焊接工艺来完成。在本实施例中，两次回流焊接工艺的温度设置大于或者等于300℃，但两次回流焊接工艺的温度不相同。第七焊料S7焊接时的温度大于第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第八焊料S8焊接时的温度。
在一些实施方式中，为了增加第一覆金属层基板100和散热器800之间焊接可靠性，或者为了增加第一覆金属层基板100上各部品的焊接可靠性，可根据各不便焊接表面的材料来选择焊料。
请参阅图25，在一实施方式中，本申请还提供一种功率模块10的制备方法，包括步骤S100、步骤S200、步骤S300和步骤S400。详细步骤如下所述。
步骤S100，在第一覆金属层基板100的一侧通过烧结材料SJ贴装芯片200。
示例性的，第一覆金属层基板100为活性金属层基板，包括第一绝缘基板110和焊接在第一绝缘基板110一侧的铜层，其中第一绝缘基板110为SiN陶瓷基板，铜层的厚度为0.8mm，将铜层根据需要蚀刻形成第一金属层120、第二金属层130、第一端部金属层140等。在一些实施方式中，可根据需要设置铜层的厚度。
可选的，第一覆金属层基板100还可以选择绝缘金属基板。
在芯片200中(如图6所示)，第一电极210位于芯片本体240朝向第一金属层120的一侧，其中第一电极210包括Ti/Ni/Au，Ti/Ni/Au是指Ti、Ni、Au依次焊接在芯片本体240的一侧(如图6所示)。可选的，第一电极210还可为Ti/Ni/Ag、Ti/NiV/Ag、Ti/NiV/Au、Ni(P)/Pd/Au、Ni(P)/Pd/Ag、Ni(P)/Au或Ni(P)/Ag中的一种，其中Ni(P)表示在Ni元素中掺杂P元素，NiV是指Ni元素和V元素的合金。可选的，第二电极220为Ti/Ni/Au、Ti/Ni/Ag、Ti/NiV/Ag、Ti/NiV/Au、Ni(P)/Pd/Au、Ni(P)/Pd/Ag、Ni(P)/Au或Ni(P)/Ag中的一种。
可选的，为了增加芯片200的电气性能，还可以在第一电极210和芯片本体240之间设置NiSi层。
示例性的，当烧结材料SJ为铜膏或银膏时，请参阅图26，可以通过以下步骤将芯片200贴装在第一覆金属层基板100上：
步骤S101a，将烧结材料SJ印刷在第一覆金属层基板上。
在具体实施时，如图26中a步骤和b步骤所示，可以采用钢网41印刷工艺或丝网印刷工艺将烧结材料SJ(银膏)通过刮刀42印刷在第一覆金属层基板100对应的烧结区上。由于钢网41印刷工艺相比丝网印刷工艺成本低、制作简单。因此，可选的，本申请采用钢网印刷工 艺将铜膏或银膏印刷在第一覆金属层基板100对应的烧结区上。
在一实施方式中，可将钢网41的开口43侧面设置成上窄下宽、倾斜面或者倾斜曲面，使得开口43边缘的烧结材料的厚度较薄，以减少印刷后烧结材料SJ的边缘凸起，提高印刷质量，减少芯片200的应力风险，如果将开口43的边缘设置与中间部分等厚，那么开口43边缘填充的烧结材料SJ较厚，当印刷完成后取出钢网时，钢网会将邻近开口边缘的烧结材料拉起，造成烧结材料SJ边缘凸起，如果将边开口43边缘设置为上窄下宽，使得开口43边缘填充的烧结材料SJ减少，可避免烧结材料SJ边缘凸起的问题。
示例性的，印刷的铜膏或银膏的厚度可以控制在30μm～160μm之间，具体可以根据实际产品进行设计，在此不作限定。
在一实施方式中，印刷的铜膏或银膏的面积可以设置为大于芯片200上对应的烧结区的面积，以吸收芯片200与烧结材料SJ的对位误差。铜膏或银膏的边界可以比目标边界(理想状态下芯片的烧结区边界)向外延伸20μm～300μm。
步骤S102a，对印刷后的烧结材料SJ进行预干燥处理。
在具体实施时，对印刷后的铜膏或银膏进行预干燥处理是为了防止加压烧结时压塌烧结材料。
示例性的，如图26中c步骤所示，可以在N2氛围下，采用100℃～180℃的温度对印刷在第一覆金属层基板10上的烧结材料SJ(铜膏或银膏)进行预干燥处理5min～40min。
步骤S103a，将芯片200贴装在第一覆金属层基板100的烧结材料SJ上进行加压。
在具体实施时，如图26中d步骤所示，可以先通过金属吸嘴44真空吸附芯片200，将芯片200吸起，然后通过画像识别系统，对烧结材料SJ(铜膏或银膏)进行对位，之后将芯片200固定在干燥后的烧结材料SJ(铜膏或银膏)上进行加压。
示例性的，芯片200贴装条件可以为：温度控制在100℃～180℃，压力控制在0.1MPa～10MPa，时间控制在10ms～999ms。即在温度为100℃～180℃的环境下对贴装在第一覆金属层基板100上的芯片200上施加0.1MPa～10MPa压力至少10ms。
在一些实施例中，可采用银膜作为烧结材料。
示例性的，当烧结材料SJ为银膜SJ01时，请参阅图27，可以通过以下步骤将芯片200贴装在第一覆金属层基板100上：
步骤S101b，在芯片200面向第一覆金属层基板100一侧粘附银膜SJ01。
在具体实施时，如图27中a步骤所示，可以通过金属吸嘴44吸附芯片200，金属吸嘴44的温度为80℃～200℃。然后将芯片200压在一大块银膜SJ01上，施加0.1MPa～5MPa压力，加压时间1ms～10000ms。这样，芯片200下方的银膜SJ01被压缩和半烧结，粘附在芯片200上。其中银膜SJ01下方具有银膜支撑层45，芯片200贴在银膜SJ01后去除银膜支撑层45，再将银膜SJ01贴在第一覆金属层基板100的第一金属层120或者第二金属层130上。
在一实施方式中，第一覆金属层基板100的表面可以是裸铜，也可以镀银。为了增强接合力，一般镀银，镀银层厚度约0.1-30um，再银膜贴在镀银层上。
步骤S102b，将粘附有银膜SJ01的芯片200贴装在第一覆金属层基板100上进行加压。
在一具体实施方式中，如图27中b步骤所示，可以先通过真空吸附，将芯片200吸起，然后通过画像识别系统，对第一覆金属层基板100进行对位，之后将粘附有银膜SJ01的芯片200固定在第一覆金属层基板100上进行加压。
示例性的，芯片200贴装条件可以为：温度控制在100℃～180℃，压力控制在0.1MPa～10MPa，时间控制在10ms～999ms。即在温度为100℃～180℃的环境下对贴装在第一覆金属 层基板100上的芯片200上施加0.1MPa～10MPa压力至少10ms。
请参阅图28，在一实施方式中，芯片200中的第二电极220和第三电极230比第二电极220和第三电极230周围的部分芯片本体240要低，使得在第二电极220和第三电极230周围形成比第二电极220和第三电极230高的耐压环241，其中耐压环241为芯片本体240的一部分，耐压环241的材质为SiC，耐压环241的高度比第二电极220和第三电极230的高度高10μm，使得在对芯片200加压时，加压头46与耐压环241接触，而不会压坏第二电极220和第三电极230。
当芯片200贴装完成后执行步骤S104。
步骤S104，对贴装在第一覆金属层基板100上的芯片200进行有压烧结。
有压烧结是指在高温下向被接合体施加压力，从而增加被烧结体的密度，促进烧结材料粒子间以及烧结材料和被接合体界面的原子扩散，增强结合强度和接合可靠性。本申请对采用的有压烧结的工艺不作限定，可以为任何公知的方法。
在具体实施时，如图26中的e步骤和图27中的c步骤所示，可以采用加压头46对贴装在第一覆金属层基板10上的芯片200进行有压烧结，以加压头面积为50mm*50mm为例，加压头46的平行度可以设置为≤5μm，以减轻烧结后的产品翘曲。
示例性的，进行有压烧结的烧结条件为：烧结温度控制在200℃～300℃，施加的压力控制在5MPa～30MPa，烧结时间控制在1min～10min。
在具体实施时，有压烧结过程可以在空气环境中进行。为防止产品氧化，在保护性气氛或真空环境中在对贴装在第一覆金属层基板100上的芯片200进行有压烧结。其中保护性气氛可以为还原性气氛，或惰性气氛。示例性的，保护性气氛可以为N2、N2和H2的混合气体，Ar或He等，在此不作限定。
为防止烧结过程加压头46对芯片200的损伤，如图27的e步骤和图26的c步骤中所示，对贴装在第一覆金属层基板100上的芯片200进行有压烧结时，还可以在芯片200与加压头46之间放置可移除的应力缓和膜47。从而在进行有压烧结时，应力缓和膜47可以避免加压头46与芯片200进行直接接触以及降低加压头46对芯片200应力集中造成的损伤。当有压烧结完成后，可以将应力缓和膜47移除。
示例性的，应力缓和膜47的厚度可以设置为50μm～90μm，在此不作限定。
示例性的，应力缓和膜47可以采用特氟龙膜等有机膜，在此不作限定。
步骤S105，对有压烧结后的产品行进冷却。
在一实施方式中，在烧结完成后，可对产品在保护性气氛和加压状态下冷却，以控制烧结后产品的翘曲度。如图26中的f步骤和图27中的d步骤所示，为加强冷却，可以通过循环冷却水48冷却，或者使用氮气冷却。
步骤S200，在第一覆金属层基板100的一侧焊接各部品和散热器800。
在对功率模块10进行焊接前，将各部品和对应的焊料贴在预先设定的位置上，以及将散热器800设置在第一覆金属层基板100的底部。请参阅图29，可将使用焊接治具1100，以定位功率模块10的各部品和散热器800，其中部品包括第一连接片300、第二连接片400、热敏电阻620、门极电阻610或者引线框架1000，其中引线框架1000用于可根据需要切割形成连接端子，例如第一连接端子731、第二连接端子732和第三连接端子733等，当焊接完成后将引线框架1000根据需要切除多余的部分，以形成第一连接端子731、第二连接端子732和第三连接端子733。其中图29仅用于示意，不代表具体实施例中功率模块10的结构和焊接治具的结构形状。
其中，焊接治具1100包括上治具1101和下治具1102，上治具1101和下治具1102上具有定位孔，将贴装有芯片200、放置电子元器件600和对应焊料的第一覆金属层基板100和引线框架1000放置在上治具1101和下治具1102之间，并根据需要定位。为了调节第一覆金属层基板的翘曲度和压保证回流焊接时的引线框架1000的翘曲，上治具1101和下治具1102通过螺栓压紧。示例性的，可通过在上加压板设置弹簧槽和高温弹簧，通过弹簧力能压平第一覆金属层基100和引线框架1000。产品和回流焊接治具1100固定安装好后，放入真空回流炉进行回流焊接。底部回流治具有开孔位置，以便散热器800中散热器底板810上的散热齿811可以放入。
在一实施方式中，为了防止第一覆金属层基板100和散热器800之间的焊料，由于加压力导致回流焊接时熔融焊料被挤出，焊料厚度过薄，导致失效，在散热器800的焊接面上，通过超声波预先植入支撑组件900。示例性的，支撑组件900为金属线断，如铜线或铝线。如图23a所示，这些金属线段既可以用于支撑第一覆金属层基板100，也促进了回流焊接时气泡的逸出，避免产生气孔而影响焊接可靠性。
在一实施方式中，散热器800、热敏电阻620、门极电阻610、第二覆金属层基板500和引线框架1000可设置焊料的材质来实现一次回流焊接或者多次回流焊接，具体可根据需要来设置。其中各对应的焊料的形态可以是焊片或者焊膏。
在一实施方式中，当焊料为焊片时，使用甲酸蒸气真空回流，使用贴片机，将焊片放入相对应的位置。然后，将第二覆金属层基板500、热敏电阻620、门极电阻610、第一连接片300、引线框架1000用贴片设备放置到对应的焊片上。门极电阻610和热敏电阻620可以实现焊接在第二覆金属层基板500上，也可以将第二覆金属层基板500放置到第一覆金属层基板100上的焊片上后。
在一实施方式中，当焊料为焊膏时，通过3D印刷或点胶，将焊膏涂敷在所要焊接的位置上，第二覆金属层基板500、热敏电阻620、门极电阻610、第一连接片300、引线框架1000用贴片设备放置到对应的焊膏上。拧紧固定螺栓，放入真空回流炉中进行焊接。
步骤S300，根据需要在各部品之间形成导电线。
通过导电线实现功率模块10中的内部互连，其中导电线为铝线或者铜线。例如在热敏电阻620下方的第二覆金属层基板500a中的第四电极520a和第二连接端子732之间通过第三导电线170连接(如图20所示)，第五电极530a和第三连接端子733之间通过第四导电线180连接。再例如，门极电阻610下方的第二覆金属层基板500中的第四电极520和第一连接端子731之间通过第二导电线720连接(如图16所示)。
在一实施方式中，当第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第七焊料S7、第八焊料S8为焊片时，由于焊片的形态呈固体状态，在步骤S200回流焊接时，在产品表面比较干净，无需清洗，可直接形成导电线。
在一实施方式中，当第一焊料S1、第二焊料S2、第三焊料S3、第四焊料S4、第五焊料S5、第六焊料S6、第七焊料S7、第八焊料S8为含焊膏时，由于焊膏的形态呈固体状态，在步骤S200回流焊接时，焊膏会溅射到产品表面或者第一金属层120、第二金属层130等金属层上，使得各电子元器件600、其他部品上或者第一金属层120、第二金属层130等金属层具有焊膏、焊膏中的有机物或者助焊剂，需要对其清洗再形成导电线。
步骤S400，在第一覆金属层基板100和部品上形成塑封层1200。
在完成步骤S300后将产品放入塑封模具中进行塑封，将第一覆金属层基板100和电子元器件600密封在塑封层1200和散热器800之间(如图30所示)。
为了增加塑封层1200与功率模块10中的第一覆金属层基板100、电子元器件600等部件以及回流焊接面面的接合性，使用界面应力缓和剂增强塑封层1200的接合强度。界面接合增强剂可以是有机物，可以喷涂，也可以是浸入，经烘干处理形成应力缓和膜。还可以在第一覆金属层基板100的金属层(例如铜层)的表面上形成含有铜的有机物，该有机物与增加塑封层1200和金属铜层的接合力。
在一些实施方式中，可通过选择和优化合适的塑封层1200的材料，塑封界面改良，实现合适的模块塑封。
为了防止塑封料与塑封界面的分层，以提高功率模块的可靠性，塑封料使用低模量的塑封料，示例性的，塑封料可以采用弹性模量在0.5GPa～20GPa之间的材料形成，例如环氧塑封料等，在此不作限定。
在一些实施方式中，功率模块10的制备方法还包括在塑封完成后，对引线框架1000切割形成对应的连接端子，例如第一连接端子、第二连接端子和第三连接端子，并对连接端子电镀，防止连接端子腐蚀，增加安装性能和焊接润湿性。
请继续参阅图30，在一些实施方式中，散热器800包括散热器底板810和散热器盖板820，可先将散热器底板810预先焊接在第一覆金属层基板100远离芯片200的一侧，当完成塑封步骤后再将散热器盖板820通过密封圈830密封在散热器底板810上，散热器底板810和散热器盖板820之间形成通道，以供冷却介质流通。
在一些实施方式中，可将散热器盖板820与散热器底板810通过焊料焊接，以将散热器盖板820与散热器底板810之间密封焊接。
以上对本申请实施例所提供的功率模块、电源系统、车辆及光伏系统进行了详细介绍，本文中应用了具体个例对本申请的原理及实施例进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；对于本领域的一般技术人员，依据本申请的思想，在具体实施例及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

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  1. 一种功率模块，其特征在于，所述功率模块包括：
    第一覆金属层基板，包括第一绝缘基板和位于所述第一绝缘基板一侧的第一金属层，所述第一金属层包括背离所述第一绝缘基板的第一表面；
    多个芯片，所述芯片包括第一电极和第二电极，所述多个芯片位于所述第一金属层远离所述第一绝缘基板的一侧，且所述多个芯片中的每一个芯片的第一电极与所述第一金属层电连接，所述多个芯片中的至少两个芯片沿第一方向间隔排布，所述多个芯片中的至少两个芯片沿第二方向间隔排布，所述第二方向与所述第一方向均平行于所述第一表面且相交；
    第一连接片，位于所述多个芯片远离所述第一绝缘基板的一侧，所述第一连接片包括第一主体部和多个第一接触部，所述多个芯片中每一芯片的第二电极均与至少一个所述第一接触部相接触，至少一对相邻的第一接触部之间具有部分所述第一主体部；所述第一主体部与所述第一金属层绝缘间隔设置。
  2. 根据权利要求1所述的功率模块，其特征在于，沿所述芯片的厚度方向，所述第一主体部与所述芯片的第二电极之间相隔离，所述第一连接片包括一个或多个凹槽，所述凹槽自所述第一主体部朝向所述第一表面凸起，且所述凹槽的槽底为所述第一接触部。
  3. 根据权利要求1或2所述的功率模块，其特征在于，所述第一连接片包括一个或多个折弯结构，所述折弯结构包括与所述芯片的第二电极接触的所述第一接触部。
  4. 根据权利要求1至3任一项所述的功率模块，其特征在于，所述第一连接片为一体成型结构。
  5. 根据权利要求1至4任一项所述的功率模块，其特征在于，每一对相邻的第一接触部之间均具有部分所述第一主体部。
  6. 根据权利要求1至5任一项所述的功率模块，其特征在于，所述第一接触部分布于所述第一主体部的边缘。
  7. 根据权利要求1至6任一项所述的功率模块，其特征在于，所述功率模块还包括第二金属层，所述第一金属层和所述第二金属层位于第一绝缘基板的同一侧，且所述第一金属层和所述第二金属层在所述第一绝缘基板上的正投影间隔设置，所述第一连接片还包括第二接触部，第二接触部与所述第二金属层电连接。
  8. 根据权利要求1-7任一项所述的功率模块，其特征在于，所述功率模块还包括第二覆金属层基板和电子元器件，所述第二覆金属层基板位于所述第一表面上，所述电子元器件位于所述第二覆金属层基板远离所述第一覆金属层基板的一侧，且与所述第二覆金属层基板电连接。
  9. 根据权利要求8所述的功率模块，其特征在于，所述芯片还包括第三电极，所述电子元器件为门极电阻，所述第二覆金属层基板位于所述第一表面上，所述第二覆金属层基板包 括绝缘间隔设置的第四电极和第五电极，所述门极电阻的两端分别与所述第四电极和所述第五电极电连接，所述第四电极用于接收驱动电流，所述第五电极通过第一导电线与所述芯片的第三电极电连接。
  10. 根据权利要求9所述的功率模块，其特征在于，在所述第一覆金属层基板中，所述第一金属层通过金属焊接层连接在所述第一绝缘基板上；所述第二覆金属层基板还包括第二绝缘基板，所述第四电极和所述第五电极贴合在所述第二绝缘基板的表面上。
  11. 根据权利要求8所述的功率模块，其特征在于，所述电子元器件为热敏电阻，所述第二覆金属层基板位于所述第一金属层远离所述第一绝缘基板的一侧，且邻近所述芯片设置，所述热敏电阻用于监测所述芯片的温度。
  12. 根据权利要求1-11任一项所述的功率模块，其特征在于，所述功率模块还包括散热器，所述散热器位于所述第一覆金属层基板远离所述芯片的一侧，所述散热器和所述第一覆金属层基板之间设有多个相间隔的支撑组件。
  13. 根据权利要求12所述的功率模块，其特征在于，所述支撑组件包括两个平行设置的支撑条，所述支撑条包括至少两个支撑段，相邻两个所述支撑段沿所述支撑条的延伸方向排列且间隔设置。
  14. 一种电源系统，其特征在于，所述电源系统包括电源、用电设备，以及如权利要求1-13任一项所述的功率模块，所述电源与所述功率模块的输入端连接，所述用电设备和所述功率模块的输出端连接，所述功率模块用于将所述电源输出的直流电转换为交流电，并将所述交流电传输给所述用电设备。
  15. 一种车辆，其特征在于，所述车辆包括车本体和如权利要求14所述的电源系统，所述电源系统安装在所述车本体上。
  16. 一种光伏系统，其特征在于，包括光伏组件和如权利要求1-13任一项所述的功率模块，所述光伏组件与所述功率模块电连接，所述光伏组件产生的直流电通过所述功率模块转换为交流电。
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CN111540730A (zh) * 2020-04-22 2020-08-14 西安交通大学 基于导电金属夹扣互连的多芯片宽禁带功率模块封装结构
CN115101498A (zh) * 2022-05-18 2022-09-23 华为数字能源技术有限公司 功率模块、电源系统、车辆及光伏系统

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