WO2022181163A1 - 窒化物半導体基板およびその製造方法 - Google Patents

窒化物半導体基板およびその製造方法 Download PDF

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WO2022181163A1
WO2022181163A1 PCT/JP2022/002747 JP2022002747W WO2022181163A1 WO 2022181163 A1 WO2022181163 A1 WO 2022181163A1 JP 2022002747 W JP2022002747 W JP 2022002747W WO 2022181163 A1 WO2022181163 A1 WO 2022181163A1
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layer
nitride semiconductor
single crystal
semiconductor substrate
silicon single
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French (fr)
Japanese (ja)
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慶太郎 土屋
偉峰 曲
芳宏 久保田
和寿 永田
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Shin Etsu Chemical Co Ltd
Shin Etsu Handotai Co Ltd
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Shin Etsu Chemical Co Ltd
Shin Etsu Handotai Co Ltd
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Priority to US18/276,520 priority Critical patent/US20240117525A1/en
Priority to CN202280014723.XA priority patent/CN117015840A/zh
Priority to EP22759205.2A priority patent/EP4299802A4/en
Publication of WO2022181163A1 publication Critical patent/WO2022181163A1/ja
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    • C—CHEMISTRY; METALLURGY
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    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
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    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/06—Joining of crystals
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
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    • H10P14/2901—Materials
    • H10P14/2907—Materials being Group IIIA-VA materials
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    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
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    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
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    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
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    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
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    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
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    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials

Definitions

  • the present invention provides a heat-resistant support substrate in which a core made of nitride ceramics is sealed with a sealing layer; a planarization layer provided on the heat-resistant support substrate; a silicon single crystal layer having a carbon concentration of 1 ⁇ 10 17 atoms/cm 3 or more provided on the planarizing layer; a carbonized layer mainly composed of silicon carbide and having a thickness of 4 to 2000 nm provided on the silicon single crystal layer; Provided is a nitride semiconductor substrate comprising a nitride semiconductor layer provided on the carbide layer.
  • the thickness of the sealing layer is 0.05 to 1.5 ⁇ m
  • the planarization layer may have a thickness of 0.5 to 3.0 ⁇ m.
  • the thickness of the silicon single crystal layer can be 100 to 2000 nm.
  • the thickness of the sealing layer is set to 0.05 to 1.5 ⁇ m
  • the thickness of the flattening layer can be 0.5 to 3.0 ⁇ m.
  • the nitride semiconductor substrate and the method of manufacturing the same of the present invention it is possible to relatively inexpensively and easily obtain a nitride semiconductor substrate in which deterioration of device characteristics is suppressed.
  • the nitride semiconductor layer has good crystallinity, and a high-quality nitride semiconductor substrate with suppressed surface roughness and warpage can be obtained.
  • a planarization layer 8 is laminated on the heat-resistant support substrate 7 .
  • the thickness of the flattening layer 8 is preferably 0.5 to 3.0 ⁇ m, for example. That is, when the thickness of the flattening layer 8 is 0.5 ⁇ m or more, the voids and unevenness generated in the heat-resistant support substrate 7 can be more sufficiently filled.
  • the thickness of the planarization layer 8 is 3.0 ⁇ m or less, it is possible to effectively suppress the occurrence of warping.
  • the planarizing layer 8 preferably contains any one of silicon oxide, silicon oxynitride, and aluminum arsenide.
  • the film formation method is not limited to this, but can be formed by, for example, plasma CVD, LPCVD, or low-pressure MOCVD.
  • the nitride semiconductor layer 4 can be formed on the composite substrate 3 by vapor deposition, for example.
  • FIG. 2 shows a configuration example of the nitride semiconductor layer.
  • the intermediate layer 11 functions as a buffer layer inserted to improve the crystallinity of the device layer 14 and control stress, which will be described later. Since this intermediate layer 11 can be produced by the same equipment, it is desirable that it be made of nitride.
  • a device layer 14 made of a nitride thin film formed by vapor phase epitaxy such as the MOVPE method or sputtering.
  • Nitrides can be, for example, GaN, AlN, InN, AlGaN, InGaN, AlInN, and the like.
  • the nitride semiconductor substrate 20 of the present invention as described above has the silicon single crystal layer and the carbonized layer having the above carbon concentration, the change in resistivity in the silicon single crystal layer is suppressed, and the device characteristics are improved. It is possible to obtain a high-quality nitride semiconductor substrate in which deterioration of the surface is suppressed and surface roughness and warpage are suppressed. Moreover, it can be manufactured relatively cheaply and easily.
  • a heat-resistant support substrate 7 is prepared by forming a sealing layer 6 so as to enclose the produced ceramic core 5 .
  • the film thickness is preferably in the range of 0.05 ⁇ m or more and 1.5 ⁇ m or less.
  • Step of cleaning the surface of the substrate with the Si layer in the furnace The substrate with the Si layer is heated in the reactor to clean the surface of the substrate.
  • the temperature for cleaning can be determined between 1000° C. and 1200° C. in terms of the surface temperature of the substrate with the Si layer.
  • Cleaning is performed after the pressure in the furnace has been reduced, and the pressure in the furnace can be between 200 mbar and 30 mbar (200 hPa and 30 hPa).
  • the furnace can be cleaned for about 10 minutes while hydrogen or nitrogen is supplied.
  • a step of forming a carbonized layer 10 In this step, a raw material hydrocarbon is introduced into the furnace at a specified furnace pressure and substrate temperature, so that the surface of the substrate with the Si layer is carbonized to a thickness of 4 to 2000 nm. A carbonized layer containing silicon as a main component is formed. In this step, the growth is performed at 1200° C. under normal pressure, for example. As a carbon source, CH4 can be used for carbonization, but not limited to this. Thus, a carbonized layer is formed by performing a carbonization treatment in a hydrocarbon atmosphere, such as heat treatment (hydrocarbon atmosphere) or CVD (raw material gas containing hydrocarbon). As a result, a composite substrate 3 is obtained in which the semiconductor layer 2 (the silicon single crystal layer 9 and the carbonized layer 10) is formed on the ceramic wafer 1.
  • a hydrocarbon atmosphere such as heat treatment (hydrocarbon atmosphere) or CVD (raw material gas containing hydrocarbon).
  • Step of growing intermediate layer 11 In this step, at a specified furnace pressure and substrate temperature, a gas serving as a source of raw materials Al, Ga, and N is introduced to grow carbonized layer 10 on composite substrate 3. Then, AlN or Al x Ga 1-x N (0 ⁇ x ⁇ 1) is epitaxially grown. In this process, the growth can be performed at a furnace pressure of 50 mbar (50 hPa) and a substrate temperature of 1120° C., for example. Trimethylaluminum (TMAl) can be used as the Al source, trimethylgallium (TMGa) can be used as the Ga source, and ammonia (NH 3 ) can be used as the N source.
  • TMAl Trimethylaluminum
  • TMGa trimethylgallium
  • NH 3 ammonia
  • the material efficiency of the source gas is taken into consideration, and the ratio of the source materials TMAl and TMGa is adjusted so that the Al/Ga ratio taken into the thin film becomes a set ratio.
  • Set the flow rate For example, AlN can be grown with a TMAl flow rate of 0.24 l/min (240 sccm) and a NH 3 flow rate of 2 l/min (2000 sccm).
  • the carrier gas of TMAl, TMGa, NH3 can be hydrogen, for example. These conditions are examples and are not particularly limited.
  • a step of growing the gallium nitride layer 12 In this step, GaN or Al x Ga 1-x N (0 ⁇ x ⁇ 1) is epitaxially grown. In this process, the growth can be performed at a furnace pressure of 200 mbar (200 hPa) and a substrate temperature of 1120° C., for example. Trimethylgallium (TMGa) can be used as the Ga source, and ammonia (NH 3 ) can be used as the N source. Also, in order to obtain a mixed crystal with a desired Al composition, the material efficiency of the source gas is taken into consideration, and the ratio of the source materials TMAl and TMGa is adjusted so that the Al/Ga ratio taken into the thin film becomes a set ratio. Set the flow rate.
  • the carrier gas of TMAl, TMGa, NH3 can be hydrogen, for example. These conditions are examples and are not particularly limited.
  • a source gas of Al, Ga, and N is introduced into the gallium nitride layer 12 at a specified furnace pressure and substrate temperature.
  • AlN or Al x Ga 1-x N (0 ⁇ x ⁇ 0.3) is epitaxially grown.
  • the growth can be performed at a furnace pressure of 150 mbar (150 hPa) and a substrate temperature of 1120° C., for example.
  • Trimethylaluminum (TMAl) can be used as the Al source
  • trimethylgallium (TMGa) can be used as the Ga source
  • ammonia (NH 3 ) can be used as the N source.
  • the material efficiency of the source gas is taken into consideration, and the ratio of the source materials TMAl and TMGa is adjusted so that the Al/Ga ratio taken into the thin film becomes a set ratio.
  • the carrier gas of TMAl, TMGa, NH3 can be hydrogen, for example.
  • Example 1 A sealing layer (thickness: 0.4 ⁇ m) made of silicon nitride (Si 3 N 4 ) and a planarizing layer made of silicon oxide were formed on a substrate made of AlN ceramics (resistivity: 10 14 ⁇ cm or more) to a thickness of 6 ⁇ m. grown up. After that, it was polished and flattened to a thickness of 2 ⁇ m by CMP polishing, and the surface roughness Ra was set to 0.2 nm.
  • the prepared silicon single crystal substrate was attached to the AlN ceramic substrate on which the sealing layer and the flattening layer were laminated, and a part of the silicon single crystal substrate was peeled off to obtain a silicon single crystal layer (thickness: 300 nm) on the AlN ceramic substrate. was made.
  • the prepared silicon single crystal substrate had a resistivity of 4000 ⁇ cm, a conductivity type of p-type, and a carbon concentration of 3 ⁇ 10 17 atoms/cm 3 .
  • the substrate with the Si layer thus produced was introduced into a heat treatment furnace and heat treated at 1250° C. for 10 seconds to form a carbonized layer with a thickness of 4.5 nm.
  • FIG. 4 shows an observation view of a longitudinal section of the wafer. Meltback etching did not occur, a mirror-like surface was obtained, and the device layer was of high quality.
  • Example 1 A substrate with a Si layer was produced in the same manner as in Example 1, and a carbonized layer was formed with a thickness of 2 nm.
  • An intermediate layer of a superlattice structure made of AlN and AlGaN, a gallium nitride layer serving as a device layer, and an electron supply layer made of AlGaN were grown thereon.
  • Example 2 By the same procedure as in Example 1, a substrate with a Si layer having a silicon single crystal layer with a resistivity of 4000 ⁇ cm and a conductivity type of p-type was produced. Then, without forming a carbide layer on the substrate with the Si layer, an intermediate layer of a superlattice structure composed of AlN and AlGaN, a gallium nitride layer serving as a device layer, and AlGaN were formed on the silicon single crystal layer in the same manner as in Example 1. An electron supply layer was grown.
  • a coplanar waveguide (CPW) was formed on the manufactured substrate, and the high-frequency characteristics of Example 1 and Comparative Example 2 were measured.
  • the high-frequency characteristics the second harmonic and loss, which are typical characteristics, were measured.
  • the second harmonic output wave was -73 dBm with respect to the fundamental frequency output, and the loss was 1.9 dBm/mm.
  • the secondary harmonic output wave was -45 dBm with respect to the fundamental frequency output, and the loss was 5.1 dBm/mm.
  • Example 1 and Comparative Examples 1 and 2 were manufactured so that the resistivity of the silicon single crystal layers was 2000 ⁇ cm or more.
  • the resistivity was measured after epitaxial growth in Example 1, the desired resistivity was obtained, but Comparative Examples 1 and 2 were 12 ⁇ cm and 5 ⁇ cm, respectively, deviating from the desired resistivity. Comparative Examples 1 and 2 are considered to be caused by the diffusion of Al and Ga into the underlying silicon single crystal layer during the growth of the device layer.
  • Example 2 A nitride semiconductor substrate was manufactured in the same manner as in Example 1, except that the thickness of the carbide layer was 4 nm.
  • Example 4 A nitride semiconductor substrate was manufactured in the same manner as in Example 1, except that the carbon concentration in the silicon single crystal substrate (silicon single crystal layer) was set to 1 ⁇ 10 17 atoms/cm 3 .
  • Example 3 A nitride semiconductor substrate was manufactured in the same manner as in Example 1, except that the thickness of the carbide layer was 2500 nm.
  • Example 4 A nitride semiconductor substrate was manufactured in the same manner as in Example 1, except that the carbon concentration in the silicon single crystal substrate (silicon single crystal layer) was set to 5 ⁇ 10 16 atoms/cm 3 .
  • Example 2-4 the wafer surface/longitudinal cross-section appearance, secondary harmonics, and loss are good crystals, and the resistivity of the silicon single crystal layer does not change from the desired resistivity, compared to Example 1.
  • a nitride semiconductor substrate having similarly excellent device characteristics could be obtained.
  • Comparative Example 3 the wafer surface became rough and warped.
  • Comparative Example 4 the resistivity of the silicon single crystal layer deviated from the desired resistivity.
  • the present invention is not limited to the above embodiments.
  • the above embodiment is an example, and any device that has substantially the same configuration as the technical idea described in the claims of the present invention and produces similar effects is the present invention. It is included in the technical scope of the invention.

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PCT/JP2022/002747 2021-02-26 2022-01-26 窒化物半導体基板およびその製造方法 Ceased WO2022181163A1 (ja)

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Application Number Priority Date Filing Date Title
US18/276,520 US20240117525A1 (en) 2021-02-26 2022-01-26 Nitride semiconductor substrate and method for producing the same
CN202280014723.XA CN117015840A (zh) 2021-02-26 2022-01-26 氮化物半导体基板及其制造方法
EP22759205.2A EP4299802A4 (en) 2021-02-26 2022-01-26 NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF

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JP2021029830A JP7549549B2 (ja) 2021-02-26 2021-02-26 窒化物半導体基板およびその製造方法
JP2021-029830 2021-02-26

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