WO2022178914A1 - 一种肖特基二极管及其制备方法 - Google Patents

一种肖特基二极管及其制备方法 Download PDF

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WO2022178914A1
WO2022178914A1 PCT/CN2021/079252 CN2021079252W WO2022178914A1 WO 2022178914 A1 WO2022178914 A1 WO 2022178914A1 CN 2021079252 W CN2021079252 W CN 2021079252W WO 2022178914 A1 WO2022178914 A1 WO 2022178914A1
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layer
drift
sub
doping
drift region
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PCT/CN2021/079252
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English (en)
French (fr)
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张园览
张清纯
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光华临港工程应用技术研发(上海)有限公司
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Publication of WO2022178914A1 publication Critical patent/WO2022178914A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a Schottky diode and a preparation method thereof.
  • Power diode is one of the most commonly used electronic components and the most basic unit of power electronic circuit. Its unidirectional conductivity can be used for rectification, clamping and freewheeling of circuits.
  • the diode in the peripheral circuit mainly plays the role of anti-reaction to prevent the damage of the device caused by the current backflow.
  • Traditional power diodes mainly include Schottky power diodes and PN junction power diodes. Compared with PN junction power diodes, Schottky power diodes utilize metal-semiconductor contacts (gold semi-contacts) to form metal-semiconductor junctions, making their forward turn-on voltages smaller.
  • the Schottky power diode is a unipolar majority carrier conduction mechanism, and its reverse recovery time is ideally zero, and there is no accumulation of excess minority carriers.
  • the technical problem to be solved by the present application is to overcome the problem in the prior art that it cannot be ensured that both the complete pinch-off of the conduction channel at a small reverse bias voltage and the low on-resistance during forward conduction cannot be achieved.
  • a Schottky diode comprising: a semiconductor substrate layer; a drift layer located on the semiconductor substrate layer, the drift layer including a first drift region and a first drift region a second drift region on the side facing away from the semiconductor substrate layer, the doping concentration of the second drift region is greater than the doping concentration of the first drift region; the sub-doping located in part of the second drift region layer, the conductivity type of the sub-doped layer is opposite to that of the drift layer; a plurality of main-doped layers located in the drift layer and distributed at intervals around the sub-doped layer, the main-doped layers The conductivity type is the same as the conductivity type of the sub-doped layer.
  • the doping concentration of the second drift region is 2 to 100 times the doping concentration of the first drift region.
  • the ratio of the thickness of the second drift region to the thickness of the first drift region is 1/100 to 1/10.
  • the doping concentration of the sub-doped layer is lower than the doping concentration of the main doping layer.
  • the doping concentration of the sub-doped layer is 5% to 80% of the doping concentration of the main doping layer.
  • the surface area of the secondary doped layer is 5% to 40% of the surface area of the main doped layer.
  • the longitudinal dimension of the sub-doped layer is 1/10 times to 2 times the longitudinal dimension of the second drift region.
  • the distances between the centers of the sub-doped layers and the centers of the adjacent main-doped layers are equal.
  • the surface shape of the secondary doped layer is the same as that of the main doped layer.
  • the surface shape of the secondary doped layer includes a circle, a square, a rectangle or a hexagon; the surface shape of the main doped layer includes a circle, a square, a rectangle or a hexagon.
  • the present application also provides a method for preparing a Schottky diode, including: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer, the drift layer including a first drift region and a first drift region facing away from all a second drift region on one side of the semiconductor substrate layer, the doping concentration of the second drift region is greater than the doping concentration of the first drift region; a sub-doped layer is formed in part of the second drift region, so The conductivity type of the sub-doped layer is opposite to the conductivity type of the drift layer; a plurality of main doping layers are formed in the drift layer, and a plurality of main doping layers are spaced around the sub-doping layer, and the main doping layers are The conductivity type of the impurity layer is the same as that of the sub-doped layer.
  • the process of forming the sub-doped layer includes an ion implantation process.
  • the method for forming the drift layer includes: forming an initial drift layer on the semiconductor substrate layer; and performing ion implantation on a partial thickness of the initial drift layer, so that the initial drift layer forms the drift layer.
  • the adjacent main doped layers distributed along the circumferential direction of the sub-doped layer under a certain reverse bias voltage, the adjacent main doped layers can overlap or contact. Due to the provision of the sub-doped layer, under a certain reverse bias voltage, a space depletion region of the PN junction will also be formed between the sub-doped layer and the drift region.
  • the space depletion region formed by the sub-doped layer and the drift region and the space depletion region formed by the main doping layer and the drift region protect the Schottky contact region, so that the Schottky contact region is in a more field protection range .
  • the second drift layer with a higher doping concentration can compensate for the sub-doping
  • the increase in the area of the impurity layer has an effect on the channel resistance, resulting in a lower on-channel resistance.
  • the space depletion region of the PN junction formed by the adjacent main-doped layer along the circumferential direction of the sub-doped layer under reverse bias voltage is just right
  • the space depletion region formed by the sub-doped layer and the drift region and the space depletion region formed by the main doping layer and the drift region also completely overlap each other, and the space depletion region laterally occupies the entire active region, making the space consumption
  • the Schottky contact area is fully protected, so that the Schottky contact area is completely in the field protection range, which ensures that the Schottky diode can be completely turned off under a small reverse bias voltage, and the Schottky contact area can be completely turned off.
  • the leakage current of the diode is small. To sum up, it is guaranteed that the Schottky diode can be completely turned off under a small reverse bias voltage, and the low on-resistance during forward conduction can also be guaranteed.
  • the Schottky diode has a reverse voltage withstand capability close to that of a PN diode. Since the doping concentration of the second drift layer is greater than that of the first drift layer, the Schottky diode can be precisely controlled to break down in the region where the sub-doped layer is located during reverse bias, and the breakdown is distributed over the entire area. The source region rather than the field stop region, thus improving the avalanche tolerance of the Schottky diode.
  • a drift layer is formed on the semiconductor substrate layer, and the drift layer includes a first drift region and a first drift region facing away from the semiconductor substrate layer. a second drift region on the side, the doping concentration of the second drift region is greater than the doping concentration of the first drift region; a sub-doped layer is formed in part of the second drift region; in the drift layer A plurality of main doping layers are formed, and the plurality of main doping layers are distributed at intervals around the sub-doping layers; the doping concentration of the sub-doping layers is smaller than that of the main doping layers.
  • the doping concentration of the second drift layer is greater than that of the first drift layer, even if the area of the sub-doping layer is slightly larger, the second drift layer with a higher doping concentration can compensate the sub-doping layer The effect of the increase in the area on the channel resistance makes the on-channel resistance lower.
  • the space depletion region of the PN junction formed by the adjacent main-doped layer along the circumferential direction of the sub-doped layer under reverse bias voltage is just right
  • the space depletion region formed by the sub-doped layer and the drift region and the space depletion region formed by the main doping layer and the drift region also completely overlap each other, and the space depletion region laterally occupies the entire active region, making the space consumption
  • the Schottky contact area is fully protected, so that the Schottky contact area is completely in the field protection range, which ensures that the Schottky diode can be completely turned off under a small reverse bias voltage, and the Schottky contact area can be completely turned off.
  • the leakage current of the diode is small. In summary, it is guaranteed that the Schottky diode can be completely turned off under a small reverse bias voltage, and the low on-resistance during forward conduction can also be guaranteed.
  • 1 is a schematic structural diagram of a Schottky diode
  • FIG. 2 is a schematic structural diagram of a Schottky diode in an embodiment of the present application.
  • Fig. 3 is the top view in Fig. 2;
  • FIG. 4 is a top view of a main doping layer and a sub-doping layer in another embodiment of the present application.
  • FIG. 5 is a top view of a main doping layer and a sub-doping layer in another embodiment of the present application.
  • FIG. 6 is a flowchart of a Schottky diode formation process in another embodiment of the present application.
  • FIG. 7 to 10 are schematic structural diagrams of a process of forming a Schottky diode in an embodiment of the present application.
  • a Schottky diode includes: a semiconductor substrate layer 10; a drift layer 11 located on the semiconductor substrate layer 10; a sub-doped layer 12 located in a part of the drift region 11, the sub-doped layer 12
  • the conductivity type of the layer 12 is opposite to that of the drift layer 11 ; a plurality of main doped layers 13 located in the drift layer 11 and distributed around the sub-doped layer 12 at intervals, the main doped layers 13
  • the conductivity type is the same as that of the sub-doped layer 12 .
  • the purpose of setting the sub-doped layer 12 is to make the space depletion region formed by the sub-doped layer and the drift region partially overlap with the space depletion region formed by the main doping layer and the drift region,
  • the space depletion region formed by the sub-doped layer and the drift region and the space depletion region formed by the main doping layer and the drift region protect the Schottky contact region, so that the Schottky contact region is in a more field protection range.
  • the sub-doped layer 12 has a smaller surface area, and the purpose of this setting is to increase the area of the Schottky contact region, thereby reducing the on-resistance, increasing the current density, and improving the performance of the device.
  • the space of the PN junctions formed along the adjacent main-doped layers in the circumferential direction of the sub-doped layer under reverse bias is depleted in space
  • the space depletion region formed by the sub-doped layer and the drift region and the space depletion region formed by the main doping layer and the drift region have not all overlapped.
  • the Schottky diode cannot be completely turned off under a small reverse bias voltage.
  • an embodiment of the present application provides a Schottky diode, including: a semiconductor substrate layer; a drift layer located on the semiconductor substrate layer, the drift layer including a first drift region and a drift layer located on the first drift region The second drift region on the side facing away from the semiconductor substrate layer, the doping concentration of the second drift region is greater than the doping concentration of the first drift region; the sub-doping located in part of the second drift region impurity layer, the conductivity type of the sub-doped layer is opposite to that of the drift layer; a plurality of main-doped layers located in the drift layer and distributed at intervals around the sub-doped layer, the main-doped layers The conductivity type of the layer is the same as the conductivity type of the sub-doped layer.
  • the Schottky diode can ensure complete pinch-off of the conduction channel when the reverse bias voltage is relatively small, and at the same time can ensure low on-resistance during forward conduction.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect.
  • An embodiment of the present application provides a Schottky diode, with reference to FIG. 2 and FIG. 3 , including:
  • the drift layer 110 located on the semiconductor substrate layer 100, the drift layer 110 includes a first drift region 110A and a second drift region 110B located on the side of the first drift region 110A facing away from the semiconductor substrate layer 100, The doping concentration of the second drift region 110B is greater than the doping concentration of the first drift region 110A;
  • the conductivity type of the sub-doped layer 130 is opposite to that of the drift layer 110;
  • the Schottky diode further includes: a Schottky contact electrode layer 140 on the side of the drift layer 110 facing away from the semiconductor substrate layer 100 ; an ohmic contact on the side of the semiconductor substrate layer 100 facing away from the drift layer electrode layer 150 .
  • the Schottky contact electrode layer 140 is omitted.
  • the Schottky diode is an example of a SiC-based Schottky diode for description.
  • the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions.
  • SiC silicon carbide
  • the new generation of semiconductor devices represented by SiC has higher reverse withstand voltage capability, lower forward conduction loss, faster switching frequency and stronger environmental tolerance, so it is considered as a new technology in the field of power conversion. hope.
  • SiC Schottky diode (SBD) is gradually replacing Si-based devices and becoming the mainstream of the market due to its high frequency and low loss in the medium and high voltage field.
  • the Schottky diode may also be a gallium nitride based Schottky diode. In other embodiments, the Schottky diode may also be a silicon-based Schottky diode. It should be noted that, in this embodiment, the material of the semiconductor substrate layer 100 is not limited.
  • the drift layer 110 is doped with drift ions.
  • the material of the drift layer 110 is silicon carbide doped with drift ions.
  • the conductivity type of the drift layer 110 is N-type. It should be noted that, in other embodiments, the material of the drift layer 110 may also be other materials. In other embodiments, the conductivity type of the drift layer 110 may also be P-type.
  • the drift ions can be silicon ions or phosphorus ions.
  • the thickness of the drift layer 110 is 10 micrometers to 20 micrometers, for example, 10 micrometers, 12 micrometers, 15 micrometers, 18 micrometers or 20 micrometers.
  • the drift layer 110 includes a first drift region 110A and a second drift region 110B.
  • the ratio of the thickness of the second drift region 110B to the thickness of the first drift region 110A is 1/100 to 1/10, such as 1/16, 1/25, 1/50, 1/75, or 1/100. If the ratio of the thickness of the second drift region 110B to the thickness of the first drift region 110A is less than 1/100, the forward resistance of the Schottky diode will increase; if the thickness of the second drift region 110B and the thickness of the first drift region 110A If the thickness ratio is greater than 1/10, the reverse leakage current of the Schottky diode will increase.
  • the doping concentration of the second drift region 110B is 2 times to 100 times, such as 10 times, 2 times, 10 times, 20 times, 50 times, of the doping concentration of the first drift region 110A times, 80 times, or 100 times. If the doping concentration of the second drift region 110B is 100 times higher than the doping concentration of the first drift region 110A, the reverse leakage current of the Schottky diode will increase; if the doping concentration of the second drift region 110B is less than the If the doping concentration of the first drift region 110A is doubled, the on-resistance of the Schottky diode increases.
  • the Schottky diode in this embodiment is a Junction Barrier Schottky (JBS) diode .
  • JBS Junction Barrier Schottky
  • junction barrier Schottky The most important design principle of a junction barrier Schottky is the ability to balance forward and reverse characteristics. When forward biased, the on-resistance should be as small as possible, and the Schottky contact area should be as large as possible; when reverse biased, the reverse breakdown voltage should be as large as possible, and the leakage should be as small as possible. current.
  • the main doping layer 120 is located in the drift layer 110, and the sidewall and bottom of the main doping layer 120 are in contact with the drift layer 110. Under the reverse bias of the Schottky diode, the main doping layer 120 is in contact with the drift layer 110. A space charge region is formed between the drift layer 110 at the bottom of the main doping layer 120, and a space charge region is formed between the main doping layer 120 and the drift layer 110 on the side of the main doping layer 120, so that the main doping layer 120 is adjacent to the main doping layer 120. A space charge region with a larger area can be formed between the drift layers 110 , thereby improving the withstand voltage of the Schottky diode.
  • the main doping layer 120 is only located in a part of the second drift region 110B; in another embodiment, the main doping layer is located in the first drift region and the second drift region, that is, the main doping layer extends from the second drift region into the first drift region. In this embodiment, the main doping layer 120 is located in the second drift region 110B and the bottom surface and the side surface of the main doping layer 120 are both surrounded by the second drift region 110B as an example.
  • the longitudinal dimension of the sub-doped layer 130 is 1/10 to 2 times the longitudinal dimension of the second drift region 110B.
  • the sub-doped layer 130 is only located in the second drift region 110B.
  • the longitudinal dimension of the sub-doped layer 130 is 20% to 100% of the longitudinal dimension of the second drift region.
  • the doping concentration of the doping ions in the main doping layer 120 is selected to be in the range of 2e 18 atom/cm 3 to 8e 18 atom/cm 3 . In one embodiment, the concentration of dopant ions in the main doping layer 120 is 500 times to 1000 times that of the dopant concentration in the first drift region 110A.
  • the adjacent main doped layers 120 are formed
  • the spatially depleted regions of the PN junction can overlap or touch. Since the sub-doped layer 130 is provided, under a certain reverse bias voltage, a space depletion region of the PN junction will also be formed between the sub-doped layer 130 and the drift region.
  • the sub-doping layers 130 and the drift region At least partially overlaps with the space depletion region formed by the main doping layer 120 and the drift region. Therefore, the space depletion region formed by the sub-doped layer 130 and the drift region and the space depletion region formed by the main doping layer 120 and the drift region protect the Schottky contact region, so that the Schottky contact region is completely in the field protection range .
  • the doping concentration of the second drift layer 110B is greater than the doping concentration of the first drift layer 110A, and the sub-doping layer 130 is located in the second drift layer 110B, even if the area of the sub-doping layer 130 is slightly larger,
  • the second drift layer with a higher doping concentration can also compensate the influence of the increase in the area of the sub-doped layer on the on-channel resistance, so that the on-channel resistance is lower.
  • the doping concentration of the second drift layer 110B is relatively large, the space depletion layer caused by the sub-doping layer 130 can be reduced, the area of the conduction channel can be increased, and the carrier concentration of the surface layer can be increased. , which increases the conductivity of the conduction channel, further reduces the conduction resistance, and reduces the forward conduction voltage drop.
  • the space depletion region of the PN junction formed by the adjacent main-doped layer along the circumferential direction of the sub-doped layer under reverse bias voltage is just right
  • the space depletion region formed by the sub-doped layer and the drift region and the space depletion region formed by the main doping layer and the drift region also completely overlap each other, and the space depletion region laterally occupies the entire active region, making the space consumption
  • the Schottky contact area is fully protected, so that the Schottky contact area is completely in the field protection range, which ensures that the Schottky diode can be completely turned off under a small reverse bias voltage, and the Schottky contact area can be completely turned off.
  • the leakage current of the diode is small. In summary, it is guaranteed that the Schottky diode can be completely turned off under a small reverse bias voltage, and the low on-resistance during forward conduction can also be guaranteed.
  • the Schottky contact region refers to a region where the Schottky contact electrode layer is in contact with the drift layer located on the side of the sub-doped layer and the main-doped layer.
  • the doping concentration of the sub-doped layer 130 is lower than the doping concentration of the main doping layer 120 . Since the concentration of the sub-doped layer 130 is smaller than that of the main doping layer 120, the Schottky diode can be precisely controlled to break down in the region where the sub-doped layer 130 is located during reverse bias, and the breakdown is distributed throughout the active rather than the field stop region, thus improving the avalanche tolerance of the Schottky diode.
  • the concentration of the sub-doped layer 130 is lower than that of the main doping layer 120, the width of the depletion layer on the side of the drift layer formed by the sub-doped layer 130 and the drift layer to form a PN junction is reduced, which makes the Schottky diode positive The channel resistance during conduction is further reduced.
  • the doping concentration of the sub-doped layer 130 is 5% to 80% of the doping concentration of the main doping layer 120, such as 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80%. If the doping concentration of the sub-doped layer 130 is too small, the overlapping of reverse vacant charge regions will be insufficient; if the doping concentration of the sub-doped layer 130 is greater than 80% of the doping concentration of the main doping layer 120 , resulting in the inability to precisely control the reverse breakdown region.
  • the surface area of the secondary doping layer 130 is 5% to 40% of the surface area of the main doping layer 120 , such as 5%, 10%, 20%, 30% or 40%.
  • the surface area of the sub-doped layer 130 refers to the top surface of the sub-doped layer 130 exposed by the drift layer.
  • the surface area of the main doping layer 120 refers to the top surface of the main doping layer 120 exposed by the drift layer.
  • the surface area of the sub-doped layer is 0.2 ⁇ m 2 to 2 ⁇ m 2 .
  • the distance between the center of the sub-doped layer 130 and the center of the adjacent main-doped layer 120 is equal, so that the distribution of the sub-doped layer 130 is more uniform, and the reverse breakdown resistance of the Schottky diode can be improved. pressure.
  • the surface shape of the sub-doped layer 130 is the same as that of the main-doped layer 120 .
  • the surface shape of the sub-doped layer 130 includes a circle, a square, a rectangle or a hexagon; the surface shape of the main doping layer 120 includes a circle, a square, a rectangle or a hexagon.
  • the surface shape of the sub-doped layer 130 is a hexagon
  • the surface shape of the main doped layer 120 is a hexagon.
  • the surface shapes of the main doping layer 120a and the sub-doping layer 130a are circular.
  • the surface shapes of the main doping layer 120b and the sub-doping layer 130b are square.
  • the sub-doped layer 130 is more easily fabricated.
  • another embodiment of the present application also provides a method for fabricating a Schottky diode.
  • the method includes the following steps:
  • the drift layer includes a first drift region and a second drift region located on the side of the first drift region facing away from the semiconductor substrate layer, the second drift region is The doping concentration is greater than the doping concentration of the first drift region;
  • S04 forming a plurality of main doping layers in the drift layer, a plurality of main doping layers are spaced around the sub-doping layer, and the conductivity type of the main doping layer is the same as that of the sub-doping layer .
  • a semiconductor substrate layer 100 is provided.
  • a drift layer 110 is formed on the semiconductor substrate layer 100 , and the drift layer 110 includes a first drift region 110A and a second drift region located on the side of the first drift region 110A facing away from the semiconductor substrate layer 100 110B, the doping concentration of the second drift region 110B is greater than the doping concentration of the first drift region 110A.
  • the method for forming the drift layer 110 includes: forming an initial drift layer on the semiconductor substrate layer 100 ; and performing ion implantation on a partial thickness of the initial drift layer, so that the initial drift layer forms the drift layer 110 .
  • a sub-doped layer 130 is formed in part of the second drift region 110B, and the conductivity type of the sub-doped layer 130 is opposite to that of the drift layer 110 ; formed in the drift layer 110 A plurality of main doping layers 120, a plurality of main doping layers 120 are distributed at intervals around the sub-doping layer 130, the conductivity type of the main doping layer 120 is the same as that of the sub-doping layer 130; The doping concentration of the doping layer 130 is lower than the doping concentration of the main doping layer 120 .
  • the process of forming the secondary doping layer 130 includes an ion implantation process; the process of forming the main doping layer 120 includes an ion implantation process.
  • the ion implantation process for forming the sub-doped layer 130 and the ion implantation process for forming the main doping layer 120 are both ion implantation processes using a mask.
  • the main-doped layer 120 is formed; in another embodiment, after the main-doped layer 120 is formed, the sub-doped layer 130 is formed.
  • a Schottky contact electrode layer 140 is formed on the side of the drift layer 110 facing away from the semiconductor substrate layer 100; on the semiconductor substrate layer An ohmic contact electrode layer 150 is formed on the side of 100 facing away from the drift layer.
  • the concentration of the sub-doped layer 130 is smaller than that of the main doping layer 120, the breakdown of the Schottky diode in the region where the sub-doped layer 130 is located during reverse bias can be precisely controlled, and the breakdown distribution The entire active region rather than the field stop region, thus improving the avalanche tolerance of the Schottky diode.
  • the doping concentration of the second drift layer is greater than the doping concentration of the first drift layer, even if the area of the sub-doping layer 130 is slightly larger, the second drift layer 110B with a higher doping concentration can compensate for the sub-doping
  • the increased area of the impurity layer 130 has an effect on the channel resistance, so that the on-channel resistance is lower.
  • the space of the PN junctions formed by the adjacent main-doped layers along the circumferential direction of the sub-doped layer 130 under reverse bias is depleted
  • the space depletion region formed by the sub-doped layer and the drift region and the space depletion region formed by the main doping layer 120 and the drift region 110 also completely overlap each other, and the space depletion region laterally occupies the entire active region.
  • the surface area of the sub-doped layer 130 can be appropriately increased, thus reducing the difficulty of the process of forming the sub-doped layer 130 .

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Abstract

一种肖特基二极管及其制备方法，肖特基二极管包括：半导体衬底层；位于所述半导体衬底层上的漂移层，所述漂移层包括第一漂移区和位于所述第一漂移区背向所述半导体衬底层一侧的第二漂移区，所述第二漂移区的掺杂浓度大于所述第一漂移区的掺杂浓度；位于部分第二漂移区中的副掺杂层，所述副掺杂层的导电类型与所述漂移层的导电类型相反；位于所述漂移层中且围绕所述副掺杂层间隔分布的若干主掺杂层，所述主掺杂层的导电类型与所述副掺杂层的导电类型相同。所述肖特基二极管保证在较小的反向偏压时对导通沟道完全夹断，同时能保证正向导通时具有低的导通电阻。

Description

一种肖特基二极管及其制备方法 技术领域
本申请涉及半导体领域，具体涉及一种肖特基二极管及其制备方法。
背景技术
功率二极管是最常用的电子元器件之一，是电力电子线路最基本的组成单元，它的单向导电性可用于电路的整流、箝位、续流。外围电路中二极管主要起防反作用，防止电流反灌造成器件损坏。传统的功率二极管主要包括肖特基功率二极管和PN结功率二极管。与PN结功率二极管相比，肖特基功率二极管利用金属与半导体接触(金半接触)形成金属半导体结，使得其正向开启电压较小。而且肖特基功率二极管是单极多数载流子导电机制，它的反向恢复时间在理想情况下为零，没有过剩少数载流子的积累。
但是，对于肖特基功率二极管而言，在在较小的反向偏压时对导通沟道的完全夹断和低的正向导通电阻之间存在着合理折衷的考虑，这在一定程度上限制了肖特基功率二极管在高压领域的应用。
发明内容
本申请要解决的技术问题在于克服现有技术中保证无法兼顾在较小的反向偏压时对导通沟道的完全夹断和正向导通时具有低的导通电阻的问题。
为了解决上述技术问题，本申请提供一种肖特基二极管，包括：半导体衬底层；位于所述半导体衬底层上的漂移层，所述漂移层包括第一漂移区和位于所述第一漂移区背向所述半导体衬底层一侧的第二漂移区，所述第二漂移区的掺杂浓度大于所述第一漂移区的掺杂浓度；位于部分所述第 二漂移区中的副掺杂层，所述副掺杂层的导电类型与所述漂移层的导电类型相反；位于所述漂移层中且围绕所述副掺杂层间隔分布的若干主掺杂层，所述主掺杂层的导电类型与所述副掺杂层的导电类型相同。
可选的，所述第二漂移区的掺杂浓度为所述第一漂移区的掺杂浓度的2倍至100倍。
可选的，所述第二漂移区的厚度与所述第一漂移区的厚度的比值为1/100至1/10。
可选的，所述副掺杂层的掺杂浓度小于所述主掺杂层的掺杂浓度。
可选的，所述副掺杂层的掺杂浓度为所述主掺杂层的掺杂浓度的5％至80％。
可选的，所述副掺杂层的表面面积为所述主掺杂层的表面面积的5％至40％。
可选的，所述副掺杂层的纵向尺寸为所述第二漂移区的纵向尺寸的1/10倍至2倍。
可选的，所述副掺杂层的中心分别至相邻的主掺杂层的中心之间的间距相等。
可选的，所述副掺杂层的表面形状与所述主掺杂层的表面形状相同。
可选的，所述副掺杂层的表面形状包括圆形、正方形、矩形或六边形；所述主掺杂层的表面形状包括圆形、正方形、矩形或六边形。
本申请还提供一种肖特基二极管的制备方法，包括：提供半导体衬底层；在所述半导体衬底层上形成漂移层，所述漂移层包括第一漂移区和位于第一漂移区背向所述半导体衬底层一侧的第二漂移区，所述第二漂移区的掺杂浓度大于所述第一漂移区的掺杂浓度；在部分所述第二漂移区中形成副掺杂层，所述副掺杂层的导电类型与所述漂移层的导电类型相反；在 所述漂移层中形成若干主掺杂层，若干主掺杂层围绕所述副掺杂层间隔分布，所述主掺杂层的导电类型与所述副掺杂层的导电类型相同。
可选的，形成所述副掺杂层的工艺包括离子注入工艺。
可选的，形成所述漂移层的方法包括：在所述半导体衬底层上形成初始漂移层；对部分厚度的所述初始漂移层进行离子注入，使得初始漂移层形成所述漂移层。
本申请技术方法具有以下有益效果：
1.本申请技术方案提供的肖特基二极管，对于沿着副掺杂层的周向方向上分布的相邻的主掺杂层，在一定的反向偏压下，该相邻的主掺杂层形成的PN结的空间耗尽区能够交叠或者接触。由于设置了副掺杂层，在一定的反向偏压下，所述副掺杂层和漂移区之间也会形成PN结的空间耗尽区。当在反向偏压下沿着所述副掺杂层的周向方向上相邻的主掺杂层形成的PN结的空间耗尽区刚好接触时，副掺杂层和漂移区形成的空间耗尽区与主掺杂层和漂移区形成的空间耗尽区至少部分相互交叠。因此副掺杂层和漂移区形成的空间耗尽区与主掺杂层和漂移区形成的空间耗尽区保护肖特基接触区，使得所述肖特基接触区处于更多的场保护范围。其次，由于第二漂移层的掺杂浓度大于第一漂移层的掺杂浓度，这样即使副掺杂层的面积做的稍微大一点，掺杂浓度较高的第二漂移层也能够补偿副掺杂层的面积增大对沟道电阻的影响，使得导通沟道电阻较低。由于能增大副掺杂层的面积，因此使得当在反向偏压下沿着所述副掺杂层的周向方向上相邻的主掺杂层形成的PN结的空间耗尽区刚好接触时，副掺杂层和漂移区形成的空间耗尽区与主掺杂层和漂移区形成的空间耗尽区也完全相互交叠，空间耗尽区横向占据整个有源区，使得空间耗尽区充分的保护肖特基接触区，使得所述肖特基接触区完全处于场保护范围，保证了在较小的反向偏压下就能完全关断肖特基二极管，且肖特基二极管的漏电流较小。综上，保证在较小的反向偏压下就能完全关断肖特基二极管，也能保证正向导通时的低 导通电阻。
其次，随着PN结在反向偏压时对导通沟道的耗尽，能够形成连续没有间隔的空间电荷区，从而使肖特基二极管拥有接近PN二极管的反向耐压能力。由于第二漂移层的掺杂浓度大于第一漂移层的掺杂浓度，因此能够精确控制肖特基二级管在反偏时在副掺杂层所在的区域击穿，击穿分布于整个有源区而非场截止区，因此提高了肖特基二极管的雪崩耐量。
2.本申请技术方案提供的肖特基二极管的制备方法，在所述半导体衬底层上形成漂移层，所述漂移层包括第一漂移区和位于第一漂移区背向所述半导体衬底层一侧的第二漂移区，所述第二漂移区的掺杂浓度大于所述第一漂移区的掺杂浓度；在部分所述第二漂移区中形成副掺杂层；在所述漂移层中形成若干主掺杂层，若干主掺杂层围绕所述副掺杂层间隔分布；所述副掺杂层的掺杂浓度小于所述主掺杂层的掺杂浓度。由于第二漂移层的掺杂浓度大于第一漂移层的掺杂浓度，这样即使副掺杂层的面积做的稍微大一点，掺杂浓度较高的第二漂移层也能够补偿副掺杂层的面积增大对沟道电阻的影响，使得导通沟道电阻较低。由于能增大副掺杂层的面积，因此使得当在反向偏压下沿着所述副掺杂层的周向方向上相邻的主掺杂层形成的PN结的空间耗尽区刚好接触时，副掺杂层和漂移区形成的空间耗尽区与主掺杂层和漂移区形成的空间耗尽区也完全相互交叠，空间耗尽区横向占据整个有源区，使得空间耗尽区充分的保护肖特基接触区，使得所述肖特基接触区完全处于场保护范围，保证了在较小的反向偏压下就能完全关断肖特基二极管，且肖特基二极管的漏电流较小。综上，保证在较小的反向偏压下就能完全关断肖特基二极管，也能保证正向导通时的低导通电阻。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图；
图1一种肖特基二极管的结构示意图；
图2是本申请一实施例中的肖特基二极管的结构示意图；
图3是图2中的俯视图；
图4为本申请另一实施例中主掺杂层和副掺杂层的俯视图；
图5为本申请又一实施例中主掺杂层和副掺杂层的俯视图；
图6是本申请另一实施例中肖特基二极管形成过程的流程图；
图7至图10是本申请一实施例中肖特基二极管形成过程的结构示意图。
具体实施方式
一种肖特基二极管，参考图，包括：半导体衬底层10；位于所述半导体衬底层10上的漂移层11；位于部分所述漂移区11中的副掺杂层12，所述副掺杂层12的导电类型与所述漂移层11的导电类型相反；位于所述漂移层11中且围绕所述副掺杂层12间隔分布的若干主掺杂层13，所述主掺杂层13的导电类型与所述副掺杂层12的导电类型相同。
上述肖特基二极管中，设置副掺杂层12的目的是:使得副掺杂层和漂移区形成的空间耗尽区与主掺杂层和漂移区形成的空间耗尽区部分相互交叠，副掺杂层和漂移区形成的空间耗尽区与主掺杂层和漂移区形成的空间耗尽区保护肖特基接触区，使得所述肖特基接触区处于更多的场保护范围。通常，副掺杂层12具有较小的表面面积，这样设置的目的是为了使得肖特基接触区的面积增大，能减少导通电阻，增加电流密度，改善器件的性能。
然而，由于副掺杂层12的表面面积较小，因此当在反向偏压下沿着所述副掺杂层的周向方向上相邻的主掺杂层形成的PN结的空间耗尽区刚好接触时，副掺杂层和漂移区形成的空间耗尽区与主掺杂层和漂移区形成的空间耗尽区还没有全部交叠，副掺杂层12和主掺杂层之间漂移区存在部分区域没有形成空间耗尽层，这样导致肖特基二极管无法在较小的反向偏压下就能完全关断肖特基二极管。
在此基础上，本申请实施例提供一种肖特基二极管，包括：半导体衬底层；位于所述半导体衬底层上的漂移层，所述漂移层包括第一漂移区和位于所述第一漂移区背向所述半导体衬底层一侧的第二漂移区，所述第二漂移区的掺杂浓度大于所述第一漂移区的掺杂浓度；位于部分所述第二漂移区中的副掺杂层，所述副掺杂层的导电类型与所述漂移层的导电类型相反；位于所述漂移层中且围绕所述副掺杂层间隔分布的若干主掺杂层，所述主掺杂层的导电类型与所述副掺杂层的导电类型相同。所述肖特基二极管保证在较小的反向偏压时对导通沟道完全夹断，同时能保证正向导通时具有低的导通电阻。
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
本申请一实施例提供一种肖特基二极管，结合参考图2和图3，包括：
半导体衬底层100；
位于所述半导体衬底层100上的漂移层110，所述漂移层110包括第一漂移区110A和位于所述第一漂移区110A背向所述半导体衬底层100一侧的第二漂移区110B，所述第二漂移区110B的掺杂浓度大于所述第一漂移区110A的掺杂浓度；
位于部分所述第二漂移区110B中的副掺杂层130，所述副掺杂层130的导电类型与所述漂移层110的导电类型相反；
位于所述漂移层110中且围绕所述副掺杂层130间隔分布的若干主掺杂层120，所述主掺杂层120的导电类型与所述副掺杂层130的导电类型相同。
所述肖特基二极管还包括：位于所述漂移层110背向所述半导体衬底层100一侧的肖特基接触电极层140；位于半导体衬底层100背向所述漂移层一侧的欧姆接触电极层150。
需要说明的是，图3中为了方便示意副掺杂层130和主掺杂层120，省去了肖特基接触电极层140。
本实施例中，以所述肖特基二极管为SiC基肖特基二极管为示例进行 说明，相应的，所述半导体衬底层100为掺杂有导电离子的碳化硅(SiC)。基于SiC为代表的新一代半导体器件具有更高的反向耐压能力、更低的正向导通损耗、更快的开关频率和更强的环境耐受能力，因此被认为是电能转换领域的新希望。其中，SiC肖特基二极管(SBD)在中高压领域因其频率高、损耗低等众多优点正逐渐替代Si基器件成为市场的主流。
在其他实施例中，肖特基二极管为还可以为氮化镓基肖特基二极管。在其他实施例中，肖特基二极管为还可以为硅基肖特基二极管。需要说明的是，本实施例中，对于半导体衬底层100的材料不做限制。
本实施例中，所述漂移层110中掺杂有漂移离子。所述漂移层110的材料为掺杂有漂移离子的碳化硅。本实施例中，所述漂移层110的导电类型为N型。需要说明的是说，在其他实施例中，所述漂移层110的材料还可以为其他材料。在其他实施例中，所述漂移层110的导电类型还可以为P型。漂移离子可以为硅离子或磷离子。
在一个实施例中，所述漂移层110的厚度为10微米至20微米，例如为10微米、12微米、15微米、18微米或20微米。
所述漂移层110包括第一漂移区110A和第二漂移区110B。在一个实施例中，第二漂移区110B的厚度与第一漂移区110A的厚度的比值为1/100至1/10，例如1/16,1/25,1/50,1/75,或者1/100。若第二漂移区110B的厚度与第一漂移区110A的厚度的比值小于1/100，则导致肖特基二极管正向导通电阻增加；若第二漂移区110B的厚度与第一漂移区110A的厚度的比值大于1/10，则导致肖特基二极管反向漏电流增大。
在一个实施例中，所述第二漂移区110B的掺杂浓度为所述第一漂移区110A的掺杂浓度的2倍至100倍，如10倍，2倍、10倍、20倍、50倍、80倍、或者100倍。若第二漂移区110B的掺杂浓度大于所述第一漂移区110A的掺杂浓度100倍，则导致肖特基二极管反向漏电流增大；若第二漂移区110B的掺杂浓度小于所述第一漂移区110A的掺杂浓度2倍，则导致 肖特基二极管导通电阻增大。
本实施例中，为了使得肖特基二极管具备较好的反向耐压表现，P-i-N结构被引入肖特基二极管，即本实施例的肖特基二极管为结势垒肖特基(JBS)二极管。通过结势垒肖特基二极管的场控制可以保持较小的肖特基金属与述漂移层110接触表面的电场强度，减小漏电流。
结势垒肖特基最重要的设计原则是平衡正向特性和反向特性的能力。当正向偏压时，应有尽可能小的导通电阻，尽可能大的肖特基接触区；反向偏压时，应有尽可能大的反向击穿电压，尽可能小的漏电流。
本实施例中，主掺杂层120位于漂移层110中，主掺杂层120的侧壁和底部均与漂移层110接触，在肖特基二极管反向偏压下，主掺杂层120与主掺杂层120底部的漂移层110之间形成空间电荷区，主掺杂层120与主掺杂层120侧部的漂移层110之间形成空间电荷区，使得主掺杂层120与相邻的漂移层110之间能形成面积较大的空间电荷区，提高肖特基二极管的耐压性。
在一个实施例中，主掺杂层120仅位于部分第二漂移区110B中；在另一个实施例中，主掺杂层位于第一漂移区和第二漂移区中，也就是主掺杂层自第二漂移区延伸至第一漂移区中。本实施例中，以主掺杂层120位于第二漂移区110B中且主掺杂层120的底面和侧面均被第二漂移区110B包围作为示例。
所述副掺杂层130的纵向尺寸为所述第二漂移区110B的纵向尺寸的1/10至2倍。
本实施例中，所述副掺杂层130仅位于第二漂移区110B中。所述副掺杂层130的纵向尺寸为所述第二漂移区的纵向尺寸的20％至100％。
若主掺杂层120中的掺杂离子的浓度过高，会导致反向漏电流增大；若主掺杂层120的掺杂离子的浓度过低，会导致反向空间电荷区交叠不充分。因此本实施例中，选择主掺杂层120中掺杂离子的掺杂浓度的范围为 2e 18atom/cm 3至8e 18atom/cm 3。在一个实施例中，所述主掺杂层120中的掺杂离子的浓度为所述第一漂移区110A中掺杂浓度的500倍至1000倍。
本实施例中，对于沿着所述副掺杂层130的周向方向上分布的相邻的主掺杂层，在一定的反向偏压下，该相邻的主掺杂层120形成的PN结的空间耗尽区能够交叠或者接触。由于在设置了副掺杂层130，在一定的反向偏压下，所述副掺杂层130和漂移区之间也会形成PN结的空间耗尽区。当在反向偏压下沿着所述副掺杂层130的周向方向上相邻的主掺杂层120形成的PN结的空间耗尽区刚好接触时，副掺杂层130和漂移区形成的空间耗尽区与主掺杂层120和漂移区形成的空间耗尽区至少部分相互交叠。因此副掺杂层130和漂移区形成的空间耗尽区与主掺杂层120和漂移区形成的空间耗尽区保护肖特基接触区，使得所述肖特基接触区完全处于场保护范围。
由于第二漂移层110B的掺杂浓度大于第一漂移层110A的掺杂浓度，而副掺杂层130位于第二漂移层110B中，这样即使副掺杂层130的面积做的稍微大一点，掺杂浓度较高的第二漂移层也能够补偿副掺杂层的面积增大对导通沟道电阻的影响，使得导通沟道电阻较低。具体的，由于第二漂移层110B的掺杂浓度较大，可以减小副掺杂层130引起的空间耗尽层，增大导通沟道的面积，而且增加了表面层的载流子浓度，增大了导通沟道的电导率，导通电阻进一步降低，可使正向导通压降降低。
由于能增大副掺杂层的面积，因此使得当在反向偏压下沿着所述副掺杂层的周向方向上相邻的主掺杂层形成的PN结的空间耗尽区刚好接触时，副掺杂层和漂移区形成的空间耗尽区与主掺杂层和漂移区形成的空间耗尽区也完全相互交叠，空间耗尽区横向占据整个有源区，使得空间耗尽区充分的保护肖特基接触区，使得所述肖特基接触区完全处于场保护范围，保证了在较小的反向偏压下就能完全关断肖特基二极管，且肖特基二极管的漏电流较小。综上，保证在较小的反向偏压下就能完全关断肖特基二极管，也能保证正向导通时的低导通电阻。
其次，随着PN结在反向偏压时对导通沟道的耗尽，能够形成连续没有间隔的空间电荷区，从而使肖特基二极管拥有PN二极管的反向耐压能力。
所述肖特基接触区指的是：肖特基接触电极层与位于副掺杂层和主掺杂层侧部的漂移层接触的区域。
本实施例中，所述副掺杂层130的掺杂浓度小于所述主掺杂层120的掺杂浓度。由于副掺杂层130的浓度小于主掺杂层120的浓度，因此能够精确控制肖特基二级管在反偏时在副掺杂层130所在的区域击穿，击穿分布于整个有源区而非场截止区，因此提高了肖特基二极管的雪崩耐量。其次，由于副掺杂层130的浓度小于主掺杂层120的浓度，因此副掺杂层130和漂移层形成PN结在漂移层侧的耗尽层的宽度降低，这样使得肖特基二极管正向导通时的沟道电阻进一步降低。
在一个具体的实施例中，所述副掺杂层130掺杂浓度为所述主掺杂层120的掺杂浓度的5％至80％，如5％、10％、20％、30％、40％、50％、60％、70％或者80％。若所述副掺杂层130掺杂浓度过小，导致反向空点电荷区交叠不充分；若所述副掺杂层130掺杂浓度大于主掺杂层120的掺杂浓度的80％，导致无法精确控制反向击穿区。
所述副掺杂层130的表面面积为所述主掺杂层120的表面面积的5％至40％，如5％、10％、20％、30％或者40％。
所述副掺杂层130的表面面积指的是漂移层暴露出的副掺杂层130的顶面。所述主掺杂层120的表面面积指的是漂移层暴露出的主掺杂层120顶面。
在一个实施例中，所述副掺杂层的表面面积为0.2μm 2至2μm 2。
所述副掺杂层130的中心分别至相邻的主掺杂层120的中心之间的间距相等，使得副掺杂层130的分布更加均匀，能提高肖特基二极管的反向 击穿耐压。
所述副掺杂层130的表面形状与所述主掺杂层120的表面形状相同。
所述副掺杂层130的表面形状包括圆形、正方形、矩形或六边形；所述主掺杂层120的表面形状包括圆形、正方形、矩形或六边形。
本实施例中，参考图3，所述副掺杂层130的表面形状为六边形，所述主掺杂层120的表面形状为六边形。经过理论计算，六边形的副掺杂层和六边形的主掺杂层120的组合能够在耗尽层完全屏蔽有源区的前提下，保持最大的导通路径，拥有最大的肖特基接触面，最小的串联电阻和电容。
在其他实施例中，参考图4，主掺杂层120a和副掺杂层130a的表面形状为圆形。参考图5，主掺杂层120b和副掺杂层130b的表面形状为正方形。
本实施例中，由于适当增加了副掺杂层130的表面面积，因此使得副掺杂层130更加容易制作得到。
相应的，本申请另一实施例还提供一种肖特基二极管的制备方法，参考图6，包括以下步骤：
S01:提供半导体衬底层；
S02:在所述半导体衬底层上形成漂移层，所述漂移层包括第一漂移区和位于第一漂移区背向所述半导体衬底层一侧的第二漂移区，所述第二漂移区的掺杂浓度大于所述第一漂移区的掺杂浓度；
S03:在部分所述第二漂移区中形成副掺杂层，所述副掺杂层的导电类型与所述漂移层的导电类型相反；
S04:在所述漂移层中形成若干主掺杂层，若干主掺杂层围绕所述副掺杂层间隔分布，所述主掺杂层的导电类型与所述副掺杂层的导电类型相同。
下面参考图7至图10具体介绍本实施例中肖特基二极管形成过程的结 构示意图。
参考图7，提供半导体衬底层100。
参考图8，在所述半导体衬底层100上形成漂移层110，所述漂移层110包括第一漂移区110A和位于第一漂移区110A背向所述半导体衬底层100一侧的第二漂移区110B，所述第二漂移区110B的掺杂浓度大于所述第一漂移区110A的掺杂浓度。
形成所述漂移层110的方法包括：在所述半导体衬底层100上形成初始漂移层；对部分厚度的所述初始漂移层进行离子注入，使得初始漂移层形成所述漂移层110。
参考图9，在部分所述第二漂移区110B中形成副掺杂层130，所述副掺杂层130的导电类型与所述漂移层110的导电类型相反；在所述漂移层110中形成若干主掺杂层120，若干主掺杂层120围绕所述副掺杂层130间隔分布，所述主掺杂层120的导电类型与所述副掺杂层130的导电类型相同；所述副掺杂层130的掺杂浓度小于所述主掺杂层120的掺杂浓度。
形成所述副掺杂层130的工艺包括离子注入工艺；形成所述主掺杂层120的工艺包括离子注入工艺。形成副掺杂层130的离子注入工艺和形成主掺杂层120离子注入工艺均为由掩膜的离子注入工艺。
在一个实施例中，形成副掺杂层130之后，形成主掺杂层120；在另一个实施例中，形成主掺杂层120之后，形成副掺杂层130。
参考图10，形成所述副掺杂层130和主掺杂层120之后，在所述漂移层110背向所述半导体衬底层100的一侧形成肖特基接触电极层140；在半导体衬底层100背向所述漂移层的一侧形成欧姆接触电极层150。
本申请中，由于副掺杂层130的浓度小于主掺杂层120的浓度，因此能够精确控制肖特基二级管在反偏时在副掺杂层130所在的区域击穿，击穿分布于整个有源区而非场截止区，因此提高了肖特基二级管的雪崩耐量。 由于第二漂移层的掺杂浓度大于第一漂移层的掺杂浓度，这样即使副掺杂层130的面积做的稍微大一点，掺杂浓度较高的第二漂移层110B也能够补偿副掺杂层130的面积增大对沟道电阻的影响，使得导通沟道电阻较低。由于能增大副掺杂层130的面积，因此使得当在反向偏压下沿着所述副掺杂层130的周向方向上相邻的主掺杂层形成的PN结的空间耗尽区刚好接触时，副掺杂层和漂移区形成的空间耗尽区与主掺杂层120和漂移区110形成的空间耗尽区也完全相互交叠，空间耗尽区横向占据整个有源区，使得空间耗尽区充分的保护肖特基接触区，使得所述肖特基接触区完全处于场保护范围，保证了在较小的反向偏压下就能完全关断肖特基二极管，且肖特基二极管的漏电流较小。综上，保证在较小的反向偏压下就能完全关断肖特基二极管，也能保证正向导通时的低导通电阻。
本申请中，所述副掺杂层130的表面面积能适当增加，因此使得形成副掺杂层130的工艺难度降低。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请的保护范围之中。

Claims (13)

  1. 一种肖特基二极管，其特征在于，包括：
    半导体衬底层；
    位于所述半导体衬底层上的漂移层，所述漂移层包括第一漂移区和位于所述第一漂移区背向所述半导体衬底层一侧的第二漂移区，所述第二漂移区的掺杂浓度大于所述第一漂移区的掺杂浓度；
    位于部分所述第二漂移区中的副掺杂层，所述副掺杂层的导电类型与所述漂移层的导电类型相反；
    位于所述漂移层中且围绕所述副掺杂层间隔分布的若干主掺杂层，所述主掺杂层的导电类型与所述副掺杂层的导电类型相同。
  2. 根据权利要求1所述的肖特基二极管，其特征在于，所述第二漂移区的掺杂浓度为所述第一漂移区的掺杂浓度的2倍至100倍。
  3. 根据权利要求1所述的肖特基二极管，其特征在于，所述第二漂移区的厚度与所述第一漂移区的厚度的比值为1/100至1/10。
  4. 根据权利要求1所述的肖特基二极管，其特征在于，所述副掺杂层的掺杂浓度小于所述主掺杂层的掺杂浓度。
  5. 根据权利要求4所述的肖特基二极管，其特征在于，所述副掺杂层的掺杂浓度为所述主掺杂层的掺杂浓度的5％至80％。
  6. 根据权利要求1所述的肖特基二极管，其特征在于，所述副掺杂层的表面面积为所述主掺杂层的表面面积的5％至40％。
  7. 根据权利要求1所述的肖特基二极管，其特征在于，所述副掺杂层的纵向尺寸为所述第二漂移区的纵向尺寸的1/10倍至2倍。
  8. 根据权利要求1所述的肖特基二极管，其特征在于，所述副掺杂层的中心分别至相邻的主掺杂层的中心之间的间距相等。
  9. 根据权利要求1所述的肖特基二极管，其特征在于，所述副掺杂层的表面形状与所述主掺杂层的表面形状相同。
  10. 根据权利要求1至9任意一项所述的肖特基二极管，其特征在于，所述副掺杂层的表面形状包括圆形、正方形、矩形或六边形；所述主掺杂 层的表面形状包括圆形、正方形、矩形或六边形。
  11. 一种如权利要求1至10任意一项所述的肖特基二极管的制备方法，其特征在于，包括：
    提供半导体衬底层；
    在所述半导体衬底层上形成漂移层，所述漂移层包括第一漂移区和位于第一漂移区背向所述半导体衬底层一侧的第二漂移区，所述第二漂移区的掺杂浓度大于所述第一漂移区的掺杂浓度；
    在部分所述第二漂移区中形成副掺杂层，所述副掺杂层的导电类型与所述漂移层的导电类型相反；
    在所述漂移层中形成若干主掺杂层，若干主掺杂层围绕所述副掺杂层间隔分布，所述主掺杂层的导电类型与所述副掺杂层的导电类型相同。
  12. 根据权利要求11所述的肖特基二极管的制备方法，其特征在于，形成所述副掺杂层的工艺包括离子注入工艺。
  13. 根据权利要求11所述的肖特基二极管的制备方法，其特征在于，形成所述漂移层的方法包括：在所述半导体衬底层上形成初始漂移层；对部分厚度的所述初始漂移层进行离子注入，使得初始漂移层形成所述漂移层。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115621329B (zh) * 2022-12-19 2023-03-28 深圳腾睿微电子科技有限公司 Jbs的元胞结构及对应的碳化硅器件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090224354A1 (en) * 2008-03-05 2009-09-10 Cree, Inc. Junction barrier schottky diode with submicron channels
CN104347685A (zh) * 2013-07-31 2015-02-11 株式会社东芝 半导体装置
US20170271528A1 (en) * 2016-03-16 2017-09-21 Kabushiki Kaisha Toshiba Semiconductor device
CN109037356A (zh) * 2018-10-15 2018-12-18 无锡新洁能股份有限公司 一种高耐压的碳化硅肖特基二极管及其制造方法
CN111668313A (zh) * 2019-03-08 2020-09-15 株式会社东芝 半导体装置
US20210036165A1 (en) * 2019-08-01 2021-02-04 AZ Power, Inc MERGED PiN SCHOTTKY (MPS) DIODE WITH ENHANCED SURGE CURRENT CAPACITY

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090224354A1 (en) * 2008-03-05 2009-09-10 Cree, Inc. Junction barrier schottky diode with submicron channels
CN104347685A (zh) * 2013-07-31 2015-02-11 株式会社东芝 半导体装置
US20170271528A1 (en) * 2016-03-16 2017-09-21 Kabushiki Kaisha Toshiba Semiconductor device
CN109037356A (zh) * 2018-10-15 2018-12-18 无锡新洁能股份有限公司 一种高耐压的碳化硅肖特基二极管及其制造方法
CN111668313A (zh) * 2019-03-08 2020-09-15 株式会社东芝 半导体装置
US20210036165A1 (en) * 2019-08-01 2021-02-04 AZ Power, Inc MERGED PiN SCHOTTKY (MPS) DIODE WITH ENHANCED SURGE CURRENT CAPACITY

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