WO2022174640A1 - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
WO2022174640A1
WO2022174640A1 PCT/CN2021/131692 CN2021131692W WO2022174640A1 WO 2022174640 A1 WO2022174640 A1 WO 2022174640A1 CN 2021131692 W CN2021131692 W CN 2021131692W WO 2022174640 A1 WO2022174640 A1 WO 2022174640A1
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region
type body
contact
body region
type
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PCT/CN2021/131692
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English (en)
French (fr)
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龚轶
刘磊
刘伟
袁愿林
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苏州东微半导体股份有限公司
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Priority to JP2023501646A priority Critical patent/JP2023533776A/ja
Priority to KR1020237001391A priority patent/KR20230023021A/ko
Priority to US18/016,813 priority patent/US20230275148A1/en
Publication of WO2022174640A1 publication Critical patent/WO2022174640A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • the present application belongs to the technical field of semiconductor devices, and for example, relates to a power semiconductor device.
  • the power semiconductor devices of the related art usually improve the switching speed by reducing the Miller capacitance of the device to reduce the switching loss, but the switching speed is too fast will lead to large voltage oscillation and current oscillation, which makes the electromagnetic interference (EMI) of the power semiconductor device in the application. Electromagnetic Interference, EMI) problem is serious.
  • the present application provides a semiconductor device, so as to reduce the EMI problem generated when the semiconductor device is applied.
  • the present application provides a semiconductor device including:
  • a p-type body region within the semiconductor substrate the p-type body region being in contact with the source metal layer;
  • a p-type pillar located within the semiconductor substrate and below the p-type body region;
  • the semiconductor substrate includes at least one first region, and the region outside the first region is a second region;
  • a first p-type body region contact region is provided in the p-type body region in the first region, and the source metal layer is in contact with the first p-type body region contact region and forms an ohmic contact;
  • the p-type body region in the second region does not form an ohmic contact with the source metal layer.
  • FIG. 1 is a schematic top view of a first embodiment of a semiconductor device provided by the present application.
  • FIG. 2 is a schematic cross-sectional view of the structure shown in FIG. 1 along the AA direction;
  • FIG. 3 is a schematic top view of a second embodiment of the semiconductor device provided by the present application.
  • a power semiconductor device chip includes a cell area and a terminal area, wherein the cell area is a current working area, and the terminal area is set to improve the withstand voltage of the most edge cell in the cell area.
  • the semiconductor device described in the embodiments refers to the cell region in the power semiconductor device chip.
  • FIG. 1 is a schematic plan view of a first embodiment of a semiconductor device provided by the present application
  • FIG. 2 is a schematic cross-sectional view of the structure shown in FIG. 1 along the AA direction.
  • the semiconductor device of the present application includes a semiconductor substrate 10 .
  • the semiconductor substrate 10 is usually a silicon substrate and includes an n-type drain region 11 and an n-type drift region located on the n-type drain region 11 . 12.
  • the p-type body region 20 located in the semiconductor substrate 10 forms a pn junction structure with the p-type body region 20 and the n-type drift region 12 .
  • the cell region of the semiconductor device chip includes several p-type body regions, only six p-type body regions 20 are exemplarily shown in FIG. 1 and FIG. 2 .
  • the n-type source region 21 located in the p-type body region 20 , the p-type body region 20 and the n-type source region 21 are all in contact with the source metal layer 17 .
  • the p-type pillar 13 may be in contact with the p-type body region 20 , so that the p-type pillar is connected to the source voltage; alternatively, the p-type pillar 13 may not be in contact with the p-type body region 20 , namely The p-type pillars 13 are arranged in the air. It should be noted that the p-type pillars 13 can be manufactured and formed by various different processes, and the shapes of the p-type pillars obtained thereby will also be different.
  • the semiconductor substrate 10 includes at least one first region 51 , the number and shape of the first region 51 are not limited in the present application.
  • a first area 51 is exemplarily shown and the first area 51 is a circular structure, and the area outside the first area 51 is defined as the second area.
  • the p-type body region 20 located in the first region 51 is provided with a first p-type body region contact region 22 , and the source metal layer 17 is in contact with the first p-type body region contact region 22 and forms an ohmic contact. Since the doping concentration of the first p-type body region contact region 22 is greater than that of the p-type body region 20 , the first p-type body region contact region 22 improves the contact between the p-type body region 20 and the source metal layer 17 The doping concentration at the first region 51 makes the p-type body region 20 in the first region 51 form an ohmic contact with the source metal layer 17 .
  • a second p-type body region contact region can also be formed in the p-type body region 20 in the second region, but the doping concentration of the second p-type body region contact region is lower than that of the first p-type body region
  • the doping concentration of the contact region 22 is such that an ohmic contact cannot be formed after the second p-type body region contact region is in contact with the source metal layer 17 , or the second p-type body region contact region is in contact with the source metal layer 17 to form an ohmic contact
  • the ohmic contact resistance is large.
  • the semiconductor device of the present application further includes a gate structure, the gate structure includes a gate dielectric layer 14 and a gate 15 , and the gate structure is isolated from the source metal layer 17 by an interlayer insulating layer 16 .
  • the gate structure of the semiconductor device of the present application is a planar gate structure.
  • the gate structure of the semiconductor device of the present application may also be a trench gate structure.
  • the p-type body region 20 in the first region 51 forms ohmic contact with the source metal layer 17 through the first p-type body region contact region 22 , and the p-type body region 20 in the second region is in contact with the source electrode
  • the metal layer 17 does not form an ohmic contact, and the potential of the p-type body region 20 without an ohmic contact is not fixed, resulting in a change in the threshold voltage Vth, and the farther away from the p-type body region 20 with an ohmic contact, the p-type without ohmic contact is formed.
  • the threshold voltage difference of the body region is smaller than the threshold voltage difference between the P-type body region on the side away from the first region and the P-type body region in the first region, so that the semiconductor device of the present application has a gradually varying threshold voltage Vth, and is turned on.
  • the current and voltage are turned off, the current and voltage are not easy to suddenly change, so that the voltage oscillation, current oscillation and EMI problems generated by the semiconductor device during application can be reduced.
  • the reverse recovery characteristics of the device can also be improved.
  • FIG. 3 is a schematic top view of the second embodiment of the semiconductor device provided by the present application.
  • the semiconductor substrate 10 includes six first regions 51 , and the first regions 51 are rectangular.
  • the first regions 51 can be regular shapes such as polygons (for example, triangles, squares, regular polygons, rectangles, parallelograms, trapezoids), circles, ellipses, etc., or irregular shapes, and the shape of the first region 51 is not carried out in this embodiment of the present application.
  • the top view shape of the first region 51 only needs to be a package pattern, for example, a closed pattern formed by connecting straight lines and/or curves end to end in sequence.
  • the second area encloses the first area as an example for description. It should be noted that the relative positional relationship between the first area and the second area is not carried out in this embodiment of the present application. 1 and 3, or the first region surrounds the second region, or the first region and the second region are sequentially arranged along a direction parallel to the plane of the semiconductor substrate.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本申请公开了一种半导体器件，包括：半导体衬底；位于所述半导体衬底内的p型体区，所述p型体区与源极金属层接触；位于所述半导体衬底内且位于所述p型体区下方的p型柱；所述半导体衬底包括至少一个第一区域，所述第一区域外的区域为第二区域；所述第一区域内的所述p型体区内设有第一p型体区接触区，所述源极金属层与所述第一p型体区接触区接触并形成欧姆接触；所述第二区域内的所述p型体区与所述源极金属层未形成欧姆接触。

Description

半导体器件
本申请要求在2021年2月19日提交中国专利局、申请号为202110191691.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于半导体器件技术领域，例如涉及一种功率半导体器件。
背景技术
相关技术的功率半导体器件通常通过降低器件的米勒电容来提高开关速度以减少开关损耗，但是开关速度过快会导致大的电压震荡和电流震荡，这使得功率半导体器件在应用时的电磁干扰(Electromagnetic Interference，EMI)问题严重。
发明内容
本申请提供一种半导体器件，以降低半导体器件在应用时产生的EMI问题。
本申请提供了一种半导体器件，包括：
半导体衬底；
位于所述半导体衬底内的p型体区，所述p型体区与源极金属层接触；
位于所述半导体衬底内且位于所述p型体区下方的p型柱；
所述半导体衬底包括至少一个第一区域，所述第一区域外的区域为第二区域；
所述第一区域内的所述p型体区内设有第一p型体区接触区，所述源极金属层与所述第一p型体区接触区接触并形成欧姆接触；
所述第二区域内的所述p型体区与所述源极金属层未形成欧姆接触。
附图说明
图1是本申请提供的半导体器件的第一个实施例的俯视示意图；
图2是图1所示结构沿AA方向的剖面示意图；
图3是本申请提供的半导体器件的第二个实施例的俯视示意图。
具体实施方式
以下将结合本申请实施例中的附图，完整地描述本申请的技术方案。应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不排除至少一个其它元件或其组合的存在。
本领域的技术人员应该理解，功率半导体器件芯片包括元胞区和终端区，其中，元胞区为电流工作区，终端区设置为提高元胞区中最边缘的元胞的耐压，本申请实施例中所述的半导体器件指的是功率半导体器件芯片中的元胞区。
图1是本申请提供的半导体器件的第一个实施例的俯视示意图，图2是图1所示结构沿AA方向的剖面示意图。如图1和图2所示，本申请的半导体器件包括半导体衬底10，半导体衬底10通常为硅衬底，包括n型漏区11和位于n型漏区11之上的n型漂移区12。位于半导体衬底10内的p型体区20，p型体区20与n型漂移区12形成pn结结构。半导体器件芯片的元胞区包括若干个p型体区，图1和图2中仅示例性的展示出了6个p型体区20。位于p型体区20内的n型源区21，p型体区20和n型源区21均与源极金属层17接触。
位于半导体衬底10内且位于p型体区20下方的p型柱13，p型柱13与n型漂移区12形成pn结结构，并且p型柱13与相邻的n型漂移区12之间形成电荷平衡。如图2所示，p型柱13可以与p型体区20相接触，由此p型柱接源极电压；可选的，p型柱13也可以与p型体区20不接触，即p型柱13浮空设置。需要说明的是，p型柱13可以通过多种不同的工艺制造形成，由此得到的p型柱的形状也会不同。
如图1所示，在半导体衬底10的上表面的俯视面上，半导体衬底10包括至少一个第一区域51，本申请对第一区域51的数量和形状不做限定，图1中仅 示例性的示出了一个第一区域51且第一区域51为圆形结构，将第一区域51外的区域定义为第二区域。
位于第一区域51内的p型体区20内设有第一p型体区接触区22，源极金属层17与第一p型体区接触区22接触并形成欧姆接触。由于第一p型体区接触区22的掺杂浓度大于p型体区20的掺杂浓度，因此第一p型体区接触区22提高了p型体区20与源极金属层17相接触处的掺杂浓度，使得第一区域51内的p型体区20与源极金属层17形成欧姆接触。
第二区域内的p型体区20由于掺杂浓度较低，因此第二区域内的p型体区20与源极金属层17接触后未形成欧姆接触。可选的，也可以在此第二区域内的p型体区20内形成第二p型体区接触区，但是第二p型体区接触区的掺杂浓度低于第一p型体区接触区22的掺杂浓度，使得第二p型体区接触区与源极金属层17接触后也不能形成欧姆接触，或者使得第二p型体区接触区与源极金属层17接触后形成的欧姆接触电阻较大。
如图2所示，本申请的半导体器件还包括栅极结构，栅极结构包括栅介质层14和栅极15，栅极结构通过层间绝缘层16与源极金属层17隔离。图2中，本申请的半导体器件的栅极结构为平面栅结构，可选的，本申请的半导体器件的栅极结构也可以为沟槽栅结构。
本申请的半导体器件，第一区域51内的p型体区20通过第一p型体区接触区22与源极金属层17形成欧姆接触，第二区域内的p型体区20与源极金属层17没有形成欧姆接触，没有形成欧姆接触的p型体区20的电势不固定导致阈值电压Vth会变化，而且距离形成欧姆接触的p型体区20越远的未形成欧姆接触的p型体区20的阈值电压Vth与形成欧姆接触的p型体区的阈值电压Vth差异越大，即在第二区域中，靠近第一区域一侧的P型体区与第一区域中的P型体区的阈值电压差小于远离第一区域一侧的P型体区与第一区域中的P型体区的阈值电压差，由此本申请的半导体器件具有缓变的阈值电压Vth，在开启和关断时，电流和电压不容易突变，从而可以以降低半导体器件在应用时产生的 电压震荡、电流震荡和EMI问题。同时也可改善器件的反向恢复特性。
图3是本申请提供的半导体器件的第二个实施例的俯视示意图，在图3中，半导体衬底10包括6个第一区域51，第一区域51为长方形，可选的，第一区域51可以为多边形(例如三角形、正方形、正多边形、长方形、平行四边形、梯形)、圆形、椭圆形等规则图形，也可以为不规则图形，本申请实施例对第一区域51的形状不进行限定，第一区域51的俯视形状只需为封装图形即可，例如由直线和/或曲线依次首尾连接形成的封闭图形即可。
在图1和图3所示的俯视示意图中，均以第二区域包围第一区域为例进行说明，需要说明的是，本申请实施例对第一区域以及第二区域的相对位置关系不进行限定，可以如图1和图3所示，也可以是第一区域包围第二区域，还可以是第一区域和第二区域沿某一与半导体衬底所在平面平行的方向依次设置。

Claims (9)

  1. 半导体器件，包括：
    半导体衬底；
    位于所述半导体衬底内的p型体区，所述p型体区与源极金属层接触；
    位于所述半导体衬底内且位于所述p型体区下方的p型柱；
    所述半导体衬底包括至少一个第一区域，所述第一区域外的区域为第二区域；
    所述第一区域内的所述p型体区内设有第一p型体区接触区，所述源极金属层与所述第一p型体区接触区接触并形成欧姆接触；
    所述第二区域内的所述p型体区与所述源极金属层未形成欧姆接触。
  2. 如权利要求1所述的半导体器件，其中，所述第一区域的形状包括多边形、圆形或者椭圆形中的至少一种。
  3. 如权利要求1所述的半导体器件，其中，所述第二区域内的所述p型体区内设有第二p型体区接触区，所述第二p型体区接触区的掺杂浓度小于所述第一p型体区接触区的掺杂浓度。
  4. 如权利要求3所述的半导体器件，其中，所述源极金属层与所述第二p型体区接触区接触但未形成欧姆接触。
  5. 如权利要求1所述的半导体器件，还包括位于所述p型体区内的n型源区，所述n型源区与所述源极金属层接触。
  6. 如权利要求1所述的半导体器件，其中，所述p型柱与所述p型体区相接触。
  7. 如权利要求1所述的半导体器件，其中，所述半导体衬底包括n型漏区和位于所述n型漏区之上的n型漂移区，所述p型体区与所述n型漂移区形成pn结结构。
  8. 如权利要求1所述的半导体器件，还包括栅极结构，所述栅极结构包括栅介质层和栅极。
  9. 如权利要求8所述的半导体器件，其中，所述栅极结构为平面栅结构或 者为沟槽栅结构。
PCT/CN2021/131692 2021-02-19 2021-11-19 半导体器件 WO2022174640A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057713A1 (en) * 2007-08-31 2009-03-05 Infineon Technologies Austria Ag Semiconductor device with a semiconductor body
CN102593168A (zh) * 2011-01-17 2012-07-18 英飞凌科技奥地利有限公司 半导体器件和逆导igbt
CN105633127A (zh) * 2015-12-31 2016-06-01 电子科技大学 一种超结mosfet
CN106158927A (zh) * 2016-08-25 2016-11-23 无锡新洁能股份有限公司 一种优化开关特性的超结半导体器件及制造方法
CN109786464A (zh) * 2017-11-15 2019-05-21 英飞凌科技德累斯顿公司 具有缓冲区的半导体器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057713A1 (en) * 2007-08-31 2009-03-05 Infineon Technologies Austria Ag Semiconductor device with a semiconductor body
CN102593168A (zh) * 2011-01-17 2012-07-18 英飞凌科技奥地利有限公司 半导体器件和逆导igbt
CN105633127A (zh) * 2015-12-31 2016-06-01 电子科技大学 一种超结mosfet
CN106158927A (zh) * 2016-08-25 2016-11-23 无锡新洁能股份有限公司 一种优化开关特性的超结半导体器件及制造方法
CN109786464A (zh) * 2017-11-15 2019-05-21 英飞凌科技德累斯顿公司 具有缓冲区的半导体器件

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