WO2022174518A1 - 谐振器件和滤波器 - Google Patents

谐振器件和滤波器 Download PDF

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Publication number
WO2022174518A1
WO2022174518A1 PCT/CN2021/091884 CN2021091884W WO2022174518A1 WO 2022174518 A1 WO2022174518 A1 WO 2022174518A1 CN 2021091884 W CN2021091884 W CN 2021091884W WO 2022174518 A1 WO2022174518 A1 WO 2022174518A1
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Prior art keywords
degrees
wafer substrate
crystal axis
equal
resonant device
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PCT/CN2021/091884
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English (en)
French (fr)
Inventor
龚颂斌
杨岩松
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偲百创(深圳)科技有限公司
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Priority claimed from CN202110194412.3A external-priority patent/CN112803916A/zh
Priority claimed from CN202120382749.2U external-priority patent/CN214256258U/zh
Application filed by 偲百创(深圳)科技有限公司 filed Critical 偲百创(深圳)科技有限公司
Publication of WO2022174518A1 publication Critical patent/WO2022174518A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material

Definitions

  • the present application relates to the field of wireless communication technologies, for example, to a resonant device and a filter.
  • RF filter components have the functions of frequency selection and suppression of interfering signals. Better performance RF filter components can not only improve the sensitivity of the transmitter, reduce the spectrum footprint of the transmitter, but also improve the signal-to-noise ratio of the transceiver and reduce the power consumption of mobile devices in the communication link.
  • the RF filter device is composed of resonant devices.
  • the resonant devices usually include Surface Acoustic Wave (SAW) resonant devices and Bulk Acoustic Wave (BAW) resonant devices.
  • SAW resonant devices and BAW resonant devices have different frequency ranges respectively. technical and cost advantages.
  • SAW Surface Acoustic Wave
  • BAW Bulk Acoustic Wave
  • the SAW resonant device has the advantage of low cost, but the operating frequency of the SAW resonant device is low.
  • the electrode width of the resonant device needs to be adjusted, so that the design of the SAW resonant device cannot take into account the device at the same time.
  • the power threshold, insertion loss, and manufacturing cost of the SAW resonator devices at higher operating frequencies are either excessively expensive or insufficient in performance.
  • the BAW resonant device has advantages in performance and high frequency, the manufacturing process of the BAW resonant device is complicated, which increases the manufacturing cost of the BAW resonant device and is difficult to meet the needs of the consumer electronics market.
  • the present application provides a resonant device and a filter to improve the performance and operating frequency of the resonant device.
  • a resonant device comprising:
  • the piezoelectric layer located on one side of the wafer substrate, the piezoelectric layer includes a piezoelectric single crystal material;
  • an interdigital electrode layer located on the side of the piezoelectric layer away from the wafer substrate;
  • the main positioning edge of the wafer substrate is located in the first direction, and the piezoelectric single crystal material includes a first crystal axis, a second crystal axis and a third crystal axis that are perpendicular to each other; wherein, the first crystal axis is vertical On the wafer substrate, or the first crystal axis is parallel to the wafer substrate and the angle between the first crystal axis and the first direction is less than or equal to 30 degrees, or the first crystal axis is The crystal axis is parallel to the wafer substrate and the angle between the first crystal axis and the first direction is greater than or equal to 60 degrees and less than or equal to 120 degrees; the second crystal axis is parallel to the wafer substrate and the angle between the second crystal axis and the first direction is less than or equal to 60 degrees, or the angle between the second crystal axis and the direction perpendicular to the wafer substrate is greater than or equal to 120 degrees and less than or equal to 135 degrees.
  • FIG. 1 is a schematic structural diagram of a resonant device provided by an embodiment of the present application.
  • FIG. 2 is a top view of a resonant device provided by an embodiment of the present application.
  • FIG. 3 is a cross-sectional view of a resonant device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a piezoelectric single crystal material provided by an embodiment of the present application.
  • FIG. 5 is a cross-sectional view of another resonant device provided by an embodiment of the present application.
  • FIG. 6 is a cross-sectional view of another resonant device provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another resonant device provided by an embodiment of the present application.
  • FIG. 8 is a cross-sectional view of another resonant device provided by an embodiment of the present application.
  • FIG. 9 is a cross-sectional view of another resonant device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another resonant device provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another resonant device provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another resonant device provided by an embodiment of the present application.
  • FIG. 13 is a top view of another resonant device provided by an embodiment of the present application.
  • FIG. 14 is a cross-sectional view of another resonant device provided by an embodiment of the present application.
  • FIG. 15 is a cross-sectional view of another resonant device provided by an embodiment of the present application.
  • FIG. 16 is a top view of another resonant device provided by an embodiment of the present application.
  • 17 is a cross-sectional view of another resonant device provided by an embodiment of the present application.
  • FIG. 18 is a schematic diagram of stress distribution of a resonant device provided by an embodiment of the present application.
  • FIG. 19 is a schematic diagram of the displacement distribution of a resonant device provided by an embodiment of the present application.
  • FIG. 20 is an admittance characteristic curve of a resonant device provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a resonant device provided by an embodiment of the present application.
  • FIG. 1 is a side view of a wafer-level resonant device, wherein FIG. 1 is only a schematic diagram.
  • the wafer substrate 10 and the piezoelectric layer 20 of the wafer-level resonant device are shown, and the wafer-level resonant device may include a plurality of resonant devices 100, and FIG. 1 shows one of the resonant devices 100;
  • FIG. 2 is a FIG. 2 is a top view of a resonant device provided in an embodiment of the present application, and FIG. 2 is a top view of the resonant device 100 in FIG. 1 ;
  • FIG. 3 is a cross-sectional view of a resonant device provided in an embodiment of the present application, and
  • FIG. Fig. 4 is a schematic structural diagram of a piezoelectric single crystal material provided by an embodiment of the present application.
  • the resonant device 100 provided by the embodiment of the present application includes: a wafer substrate 10, a piezoelectric layer 20, and an interdigital electrode layer 30; the piezoelectric layer 20 is located on one side of the wafer substrate 10, and the pressure
  • the electrical layer 20 includes a piezoelectric single crystal material; the interdigitated electrode layer 30 is located on the side of the piezoelectric layer 20 away from the wafer substrate 10 ; the main positioning edge 11 of the wafer substrate 10 is located in the first direction N1, and the piezoelectric single
  • the crystal material includes a first crystal axis X, a second crystal axis Y and a third crystal axis Z that are perpendicular to each other; wherein the first crystal axis X is perpendicular to the wafer substrate 10, or the first crystal axis X is parallel to the wafer substrate Bottom 10 and the included angle between the first crystal axis X and the first direction N1 is less than or equal to 30 degrees, or greater than or equal to 60 degrees and less
  • the wafer substrate 10 can provide functions such as buffering, protection or support for the resonant device 100, and the material of the wafer substrate 10 can be sapphire.
  • a plurality of film layers in the resonant device 100 may be sequentially formed on the wafer substrate 10 to form a wafer-level resonant device including the plurality of resonant devices 100. After the wafer-level resonant device is formed, the The resonant device 100 is obtained by cutting.
  • the piezoelectric layer 20 can be formed on the wafer substrate 10 by bonding, and the piezoelectric layer 20 can be composed of a plurality of piezoelectric single crystal materials arranged according to certain rules. For single crystal materials, under the action of an electric field, mechanical stress will be generated in piezoelectric single crystal materials and corresponding deformation will occur.
  • the interdigital electrode layer 30 may include two groups of interdigital electrodes extending along the second direction N2 , and the two groups of interdigital electrodes form on the piezoelectric layer 20 a pattern of interdigitated metal electrodes similar to fingers of two hands.
  • An electrical signal is input to the two groups of interdigital electrodes in the resonant device 100 to apply a third direction N3 to the piezoelectric layer 20 (the third direction N3 is parallel to the wafer substrate 10 and perpendicular to the extending direction of the interdigital electrodes.
  • the interdigital electrodes can be excited in the piezoelectric layer 20 along the third direction N3
  • the surface acoustic waves propagating in three directions N3, namely longitudinally polarized acoustic waves, are converted into corresponding electrical signals for output to realize filtering.
  • each type of crystal structure corresponds to a crystal axis coordinate system containing three crystal axes.
  • the crystal structure of the trigonal piezoelectric single crystal material shown in FIG. 4 is used as an example for schematic illustration, rather than limiting the type of crystal structure of the piezoelectric single crystal material.
  • the piezoelectric single crystal material shown in FIG. 4 may be any one of lithium niobate and lithium tantalate, and in the crystal structure of the piezoelectric single crystal material, the third crystal axis Z may be located at a longer crystal axis.
  • the midpoint of the body diagonal can be the origin of coordinates, and a plane perpendicular to the third crystal axis Z can be obtained to obtain the planes where the first crystal axis X and the second crystal axis Y are located.
  • the crystal axis direction of the piezoelectric single crystal material in the piezoelectric layer 20 is determined, the orientation of the piezoelectric single crystal material relative to the wafer substrate 10 and the interdigital electrode layer 30 is also determined.
  • the first crystal axis X is perpendicular to the wafer substrate 10, that is, the plane formed by the second crystal axis Y and the third crystal axis Z is parallel to the wafer substrate 10, and the second crystal axis Y
  • the first direction N1 where the main positioning edge 11 of the wafer substrate 10 is located may also be the device direction.
  • the first crystal axis X is set perpendicular to the wafer substrate 10 , and the plane formed by the second crystal axis Y and the third crystal axis Z is arranged with the wafer substrate.
  • the resonator device 100 applies an electric field to the piezoelectric single crystal material through the interdigital electrodes, it can enhance the
  • the piezoelectric effect generated by the piezoelectric layer 20 increases the electromechanical coupling coefficient of the resonant device 100 , so as to enhance the performance of the resonant device 100 and increase the operating frequency of the resonant device 100 .
  • the first crystal axis X may also be parallel to the wafer substrate 10, and the included angle between the first crystal axis X and the main positioning edge 11 of the wafer substrate 10 may be less than or equal to 30 degrees , or the first crystal axis X is parallel to the wafer substrate 10 , and the included angle between the first crystal axis X and the main positioning edge 11 of the wafer substrate 10 is greater than or equal to 60 degrees and less than or equal to 120 degrees.
  • the second crystal axis Y may also be parallel to the wafer substrate 10, and the included angle between the second crystal axis Y and the main positioning edge 11 of the wafer substrate 10 may be less than or equal to 60 degrees, or the second crystal axis Y may be perpendicular to the The included angle with respect to the direction of the wafer substrate 10 is greater than or equal to 120 degrees and less than or equal to 135 degrees.
  • the specific direction of the crystal axis by setting the specific direction of the crystal axis, the specific direction of the piezoelectric single crystal material in the piezoelectric layer 20 can be set.
  • the direction of bonding with the wafer substrate 10 also helps to enhance the piezoelectric effect generated by the piezoelectric layer 20, thereby improving the electromechanical coupling coefficient of the resonant device 100, so as to enhance the performance of the resonant device 100 and improve the work of the resonant device 100. frequency.
  • the technical solutions of the embodiments of the present application through the excitation of the longitudinally polarized surface acoustic wave by the resonator device and the setting of the specific direction of the crystal axis, realize the setting of the specific direction of the piezoelectric single crystal material in the piezoelectric layer, so as to adjust the inside of the resonant device.
  • the effect of geometric shape and structure, due to the anisotropic characteristics of piezoelectric single crystal material, bonding the piezoelectric single crystal material to the wafer substrate in the above-mentioned specific direction helps to enhance the piezoelectricity generated by the piezoelectric layer. effect, thereby improving the electromechanical coupling coefficient of the resonant device and enhancing the performance of the resonant device.
  • the technical solutions of the embodiments of the present application alleviate the problem that the surface acoustic wave resonant device in the related art cannot take into account high performance and low cost, and is beneficial to improve the performance and operating frequency of the resonant device while ensuring the low-cost advantage of the resonant device. , thereby improving the performance of the bandpass filter including the resonant device to meet the requirements of the communication standard of the 5th Generation mobile communication system (5G).
  • 5G 5th Generation mobile communication system
  • the first crystal axis X is set to be perpendicular to the wafer substrate 10 , and the first direction N1 rotates to the second crystal axis Y along the clockwise direction
  • the rotation angle a1 of is greater than or equal to 0 degrees and less than or equal to 60 degrees.
  • the first crystal axis X is perpendicular to the wafer substrate 10, and the positive semi-axis of the first crystal axis X points to the direction in which the piezoelectric layer 20 is away from the wafer substrate 10, and the negative semi-axis of the first crystal axis X (-X) points to the direction in which the piezoelectric layer 20 is close to the wafer substrate 10, or the positive half axis of the first crystal axis X points to the direction in which the piezoelectric layer 20 is close to the wafer substrate 10, and the negative half axis of the first crystal axis X
  • the axis points in the direction of the piezoelectric layer 20 away from the wafer substrate 10 .
  • the rotation angle from the first direction N1 to the second crystal axis Y is greater than or equal to 0 degrees and less than or equal to 60 degrees, which refers to the positive or negative semi-axis (-Y) of the second crystal axis Y
  • the positioning edge 11 of the wafer substrate 10 can be rotated clockwise to any position between 0 degrees and 60 degrees.
  • the specific direction of the crystal axis by setting the specific direction of the crystal axis, the specific direction of the piezoelectric single crystal material in the piezoelectric layer 20 can be set.
  • the direction of bonding with the wafer substrate 10 helps to enhance the piezoelectric effect generated by the piezoelectric layer 20 , thereby improving the electromechanical coupling coefficient of the resonant device 100 to enhance the performance of the resonant device 100 and increase the operating frequency of the resonant device 100 . It is experimentally verified that the electromechanical coupling coefficient of the resonant device 100 provided in this embodiment is as high as about 15%.
  • FIG. 5 is a cross-sectional view of another resonant device provided by an embodiment of the present application, and FIG. 5 is another cross-sectional view obtained by cutting the resonant device 100 shown in FIG. 2 along the section line AA′, wherein FIG. 5 only shows The wafer substrate 10 and the piezoelectric layer 20 of the resonant device 100 are shown;
  • FIG. 6 is a cross-sectional view of another resonant device provided by the embodiment of the present application, and FIG. Another cross-sectional view obtained by cutting, wherein, FIG. 6 only shows the wafer substrate 10 and the piezoelectric layer 20 of the resonant device 100;
  • FIG. 7 is a schematic structural diagram of another resonator device provided by the embodiment of the present application, FIG. 7 is a side view of another wafer-level resonant device, wherein FIG. 7 only shows the wafer substrate 10 and the piezoelectric layer 20 of the wafer-level resonant device.
  • the first crystal axis X is set parallel to the wafer substrate 10, and the angle a2 between the second crystal axis Y and the direction perpendicular to the wafer substrate 10 is greater than or equal to 120 degrees and Less than or equal to 135 degrees, and in the clockwise direction, the rotation angle a3 of the first direction N1 to the first crystal axis X is greater than or equal to 60 degrees and less than or equal to 120 degrees.
  • the rotation angle from the first direction N1 to the first crystal axis X is greater than or equal to 60 degrees and less than or equal to 120 degrees, which means that the first crystal axis X may be located on the surface of the wafer substrate 10 .
  • the positioning edge 11 is rotated clockwise to any position between 60 degrees and 120 degrees.
  • the direction perpendicular to the wafer substrate 10 may be the direction of the dotted line L shown in FIG. 5 and FIG.
  • the angle a2 between the second crystal axis Y and the direction perpendicular to the wafer substrate 10 is greater than or equal to 120 degrees and less than or equal to 135 degrees means that the second crystal axis Y can be located at any position rotated clockwise from the dotted line L to 120 degrees to 135 degrees, and the positive half axis of the second crystal axis Y points to the piezoelectric
  • the side of the layer 20 close to the wafer substrate 10 (as shown in FIG. 5 ), or the positive semi-axis of the second crystal axis Y points to the side of the piezoelectric layer 20 away from the wafer substrate 10 (as shown in FIG. 6 ) .
  • the specific direction of the piezoelectric single crystal material in the piezoelectric layer 20 can be set.
  • the direction of bonding with the wafer substrate 10 helps to enhance the piezoelectric effect generated by the piezoelectric layer 20 , thereby improving the electromechanical coupling coefficient of the resonant device 100 to enhance the performance of the resonant device 100 and increase the operating frequency of the resonant device 100 . It is experimentally verified that the electromechanical coupling coefficient of the resonant device 100 provided in this embodiment is as high as about 10%.
  • FIG. 8 is a cross-sectional view of another resonant device provided by an embodiment of the present application, and FIG. 8 is another cross-sectional view obtained by cutting the resonant device 100 shown in FIG. 2 along the section line AA′, wherein FIG. 8 only shows The wafer substrate 10 and the piezoelectric layer 20 of the resonant device 100 are shown;
  • FIG. 9 is a cross-sectional view of another resonant device provided by the embodiment of the present application, and FIG. Another cross-sectional view obtained by cutting, wherein, FIG. 9 only shows the wafer substrate 10 and the piezoelectric layer 20 of the resonant device 100;
  • FIG. 10 is a schematic structural diagram of another resonator device provided by the embodiment of the present application, FIG. 10 is a side view of another wafer-level resonant device, wherein FIG. 10 only shows the wafer substrate 10 and the piezoelectric layer 20 of the wafer-level resonator device.
  • the first crystal axis X is set parallel to the wafer substrate 10, and the angle a4 between the second crystal axis Y and the direction perpendicular to the wafer substrate 10 is greater than or equal to 30 degrees and less than or equal to 50 degrees, and in the clockwise direction, the rotation angle a5 from the first direction N1 to the first crystal axis X is greater than or equal to -30 degrees and less than or equal to 30 degrees, or greater than or equal to 60 degrees and less than or equal to 120 degrees.
  • the rotation angle a5 from the first direction N1 to the first crystal axis X is greater than or equal to -30 degrees and less than or equal to 30 degrees, or greater than or equal to 60 degrees and less than or equal to 120 degrees, It means that the first crystal axis X can be located at any position between -30 degrees and 30 degrees rotated clockwise from the positioning edge 11 of the wafer substrate 10 , or the first crystal axis X can be located at any position from the wafer substrate 10 The positioning edge 11 is rotated clockwise to any position between 60 degrees and 120 degrees.
  • the direction perpendicular to the wafer substrate 10 may be the direction of the dotted line L shown in FIG. 8 and FIG.
  • the angle a4 between the second crystal axis Y and the direction perpendicular to the wafer substrate 10 is greater than or equal to 30 degrees and less than or equal to 50 degrees means that the second crystal axis Y can be located at any position rotated clockwise from the dotted line L to 30 degrees to 50 degrees, and the positive half axis of the second crystal axis Y points to the piezoelectric
  • the side of the layer 20 away from the wafer substrate 10 (as shown in FIG. 8 ), or the positive semi-axis of the second crystal axis Y points to the side of the piezoelectric layer 20 close to the wafer substrate 10 (as shown in FIG. 9 ) .
  • the specific direction of the piezoelectric single crystal material in the piezoelectric layer 20 can be set.
  • the direction of bonding with the wafer substrate 10 helps to enhance the piezoelectric effect generated by the piezoelectric layer 20 , thereby improving the electromechanical coupling coefficient of the resonant device 100 to enhance the performance of the resonant device 100 and increase the operating frequency of the resonant device 100 . It is experimentally verified that the electromechanical coupling coefficient of the resonant device 100 provided in this embodiment is as high as about 10%.
  • the interdigitated electrode layer 30 is provided to include a plurality of first interdigitated electrodes 310 and a plurality of second interdigitated electrodes 320; the plurality of first interdigitated electrodes 310 are all connected to The bus bars 311 on the first side of the electrode layer 30, and the plurality of first interdigital electrodes 310 extend from the first side of the interdigital electrode layer 30 to the second side of the interdigital electrode layer 30 along the second direction N2.
  • the two sides are located on the opposite sides of the first side; the plurality of second interdigitated electrodes 320 are connected to the bus bars 321 located on the second side of the interdigitated electrode layer 30 , and the plurality of second interdigitated electrodes 320 are connected by the second side extending to the first side along the second direction N2; the vertical projections of the first interdigital electrode 310 and the second interdigital electrode 320 on the piezoelectric layer 20 alternate, and the first interdigital electrode 310 and the second interdigital electrode 320 insulated from each other.
  • the first interdigitated electrodes 310 and the second interdigitated electrodes 320 are both metal electrodes, and the materials of the first interdigitated electrodes 310 and the second interdigitated electrodes 320 may include titanium (Titanium, Ti), silver (Silver, Ag), aluminum (Aluminium, Al), copper (Copper, Cu), copper aluminum alloy (Aluminum copper alloy, AlCu), chromium (Chromium, Cr), ruthenium (Ruthenium, Ru), molybdenum (Molybdenum, Moly) and tungsten (Tungsten, W ), or the material of the first interdigitated electrode 310 and the second interdigitated electrode 320 may also be a combination of the above materials.
  • Each first interdigital electrode 310 is connected to a common electrode, that is, the bus bar 311 on the first side of the interdigital electrode layer 30 ; each second interdigital electrode 320 is connected to a common electrode, that is, the second interdigital electrode layer 30 side bus bar 321.
  • the widths of the plurality of first interdigitated electrodes 310 may be the same or different, and the widths of the plurality of second interdigitated electrodes 320 may also be the same or different.
  • the interdigital electrode layer 30 can apply an electric field in the direction perpendicular to the first interdigital electrode 310 and the second interdigital electrode 320 in the piezoelectric layer 20, that is, the electric field in the third direction N3,
  • the electric field in the third direction N3 is generated in the entire thickness direction of the piezoelectric layer 20, and then the surface acoustic wave propagating along the third direction N3, that is, the longitudinally polarized acoustic wave, is excited, and the surface acoustic wave is converted into a corresponding electrical signal output , for filtering.
  • FIG. 11 is a schematic structural diagram of another resonant device provided by an embodiment of the present application, and FIG. 11 is a side view of another wafer-level resonant device, wherein FIG. 11 only shows the wafer of the wafer-level resonant device Substrate 10 and piezoelectric layer 20;
  • FIG. 12 is a schematic structural diagram of another resonant device provided by an embodiment of the present application, and FIG. 12 is a side view of another wafer-level resonant device, wherein FIG. 12 only shows The wafer substrate 10 and the piezoelectric layer 20 of the wafer-level resonant device. 1 to 4 and FIGS.
  • the included angle a1 between the first direction N1 and the third direction N3 is set to be greater than or equal to -30 degrees and less than or equal to 30 degrees, and the third direction N3 is parallel to The wafer substrate 10 is perpendicular to the second direction N2.
  • the included angle between the first direction N1 and the third direction N3 is greater than or equal to -30 degrees and less than or equal to 30 degrees, which refers to the extension direction ( That is, the angle between the direction of the second direction N2) (that is, the third direction N3) and the main positioning edge 11 of the wafer substrate 10 is ⁇ 30° ⁇ a1 ⁇ 30°, in other words, the surface acoustic wave excited by the resonant device 100
  • the angle between the first direction N1 and the third direction N3 -30° ⁇ a1 ⁇ 30°, it is possible to adjust the direction of the interdigital electrode and the piezoelectric
  • the relative positional relationship between the orientations of the crystal structures of the single crystal material is beneficial to enhance the piezoelectric effect generated by the piezoelectric layer 20 while exciting the surface acoustic wave propagating along the third direction N3, thereby improving the electromechanical coupling of the resonant device 100 coefficient to enhance the performance of the resonant device 100 and increase the operating frequency of the resonant device 100 .
  • FIG. 13 is a top view of another resonant device provided by an embodiment of the present application, and FIG. 13 may be another top view of the resonant device 100 in FIG. 1 .
  • the interdigitated electrode layer 30 further includes a plurality of first dummy interdigitated electrodes 312 and a plurality of second dummy interdigitated electrodes 322 ; the first dummy interdigitated electrodes 312 are located adjacent to the first interdigitated electrodes 312 Between the interdigitated electrodes 310 and connected to the bus bar 311 on the first side, the first dummy interdigitated electrode 312 extends from the first side to the second side along the second direction N2; the second dummy interdigitated electrode 322 is located adjacent to the second side.
  • the second dummy interdigitated electrode 322 extends from the second side to the first side along the second direction N2; the first dummy interdigitated electrode 312, the second The dummy interdigital electrodes 322 , the first interdigitated electrodes 310 and the second interdigitated electrodes 320 are insulated from each other.
  • the material of the first dummy interdigital electrode 312 and the second dummy interdigital electrode 322 may be the same as the material of the first interdigital electrode 310 and the second interdigital electrode 320 .
  • Two dummy interdigital electrodes 322, forming a virtual short heel finger disconnected from the interdigital electrode for example, the first dummy interdigital electrode 312 forms a virtual short heel finger disconnected from the corresponding second interdigital electrode 320, and the second dummy fork
  • the finger electrodes 322 form virtual short heels that are disconnected from the corresponding first interdigital electrodes 310 ), so that the surface acoustic wave excited by the resonant device 100 propagates to the first dummy interdigital electrodes 312 and the second dummy interdigital electrodes 322 Reflection occurs, thereby confining the surface acoustic wave to the interior of the resonant device 100 along the second direction N2, thereby increasing the energy reflectivity of the resonator device 100 and suppressing unwanted spurious responses.
  • FIG. 14 is a cross-sectional view of another resonant device provided by an embodiment of the present application, and FIG. 14 is a cross-sectional view obtained by cutting the resonator device 100 shown in FIG. 13 along the section line bb′. 2 , 13 and 14 , optionally, the resonant device 100 further includes an acoustic reflection grating 330 , the acoustic reflection grating 330 is located on the side of the piezoelectric layer 20 away from the wafer substrate 10 , and the acoustic reflection grating 330 is disposed on the fork
  • the finger electrode layer 30 is on both sides of the second direction N2 and is insulated from the interdigital electrode layer 30; each acoustic reflection grid 330 includes a plurality of metal strips 331 extending along the second direction N2, and the metal strips 331 are in the third direction N3
  • the width W r is greater than 0.25 times the width We of the first interdigital electrode 310 and the second interdigital electrode
  • the material of the acoustic reflection grating 330 may be the same as or different from the material of the first interdigital electrode 310 and the second interdigital electrode 320 .
  • Two ends of the metal strip 331 in the acoustic reflection grid 330 are respectively connected to the bus lines, that is, the bus line 332 and the bus line 333 .
  • the bus bar connecting the first interdigital electrode 310 and the second interdigital electrode 320 may be connected to the bus bar connected to the metal bar 331 in the acoustic reflection grid 330, or may not be connected.
  • FIG. 2 and FIG. 13 show the connection of the interdigital electrodes. The case where the bus bars of the electrodes are not connected to the bus bars connected by the metal bars in the acoustic reflection grid.
  • the surface acoustic wave propagating from the resonator device 100 to the outside of the acoustic reflection gratings 330 on both sides can be reduced, which is helpful for the sound
  • the surface wave is confined to the interior of the resonant device 100 along the third direction N3 , thereby improving the energy conversion efficiency between the electrical energy and the mechanical energy of the resonant device 100 .
  • the distance W g between the interdigital electrode layer 30 and the adjacent metal strips 331 refers to the metal strip 331 closest to the interdigital electrode in the acoustic reflection grid, and the first interdigital finger in the interdigital electrode layer 30 closest to the acoustic reflection grid
  • the spacing between the electrodes 310 or the second interdigitated electrodes 320 FIG. 14 schematically shows the case where the widths of the first interdigitated electrode 310 and the second interdigitated electrode 320 in the third direction N3 are both We, in this embodiment, the width of the metal strip 331 in the third direction N3 is set.
  • the width is 0.25W e ⁇ W r ⁇ 10W e
  • the distance between the interdigitated electrode layer 30 and the adjacent metal strips 331 is 0.2W e ⁇ W g ⁇ 10W e , which helps to weaken the acoustic wave generated by the resonator device 100 through the acoustic reflection grating Diffraction, thereby reducing the surface acoustic wave propagating from the resonator device 100 to the outside of the acoustic reflection gratings 330 on both sides, helping to confine the surface acoustic wave to the interior of the resonator device 100 along the third direction N3, thereby improving the power and energy efficiency of the resonator device 100.
  • FIG. 15 is a cross-sectional view of another resonant device provided by an embodiment of the present application, and FIG. 15 may be another cross-sectional view obtained by cutting the resonant device 100 shown in FIG. 13 along the section line bb'.
  • the resonant device 100 further includes a passivation layer 50 located on the side of the interdigital electrode layer 30 away from the wafer substrate 10 , and the passivation layer 50 covers the interdigitated electrodes Layer 30.
  • the material of the passivation layer 50 may be silicon dioxide (SiO2) or silicon nitride (Silicon Nitride, SiNx).
  • the passivation layer 50 is arranged to cover the interdigital electrode layer 30 to isolate water and oxygen, so as to achieve Protection of the interdigitated electrode layer 30 .
  • the passivation layer 50 is formed on the side of the interdigital electrode layer 30 away from the wafer substrate 10 , the upper surface of the passivation layer 50 on the side away from the wafer substrate 10 can be formed to be flat, or the passivation layer 50 can be The undulations on the upper surface are consistent with the topography of the upper surface of the interdigital electrode layer 30 .
  • FIG. 16 is a top view of another resonant device provided by an embodiment of the present application, and FIG. 16 is another top view of the resonant device 100 in FIG. 1 ;
  • FIG. 17 is a cross-sectional view of another resonant device provided by an embodiment of the present application. 17 is a cross-sectional view obtained by cutting the resonant device 100 shown in FIG. 16 along the section line CC'. 16 and 17 , optionally, the resonant device 100 further includes a metal layer 60 , the metal layer 60 is located on the side of the interdigital electrode layer 30 away from the wafer substrate 10 , and the metal layer 60 covers the first part of the interdigital electrode layer 30 . At least a partial area of the bus bar 311 on one side covers at least a partial area of the bus bar 321 on the second side of the interdigital electrode layer 30 .
  • the material of the metal layer 60 may include titanium (Ti), silver (Ag), aluminum (Al), copper (Cu), copper aluminum alloy (AlCu), chromium (Cr), ruthenium (Ru), molybdenum (Moly) and tungsten Any of (W), or a combination of the above materials.
  • the metal layer 60 to cover at least a part of the bus bar 311 on the first side of the interdigital electrode layer 30 and at least a part of the bus bar 321 on the second side of the interdigital electrode layer 30 . It is helpful to When the surface acoustic wave excited by the resonator device 100 propagates to the metal layer 60, the reflection occurs, so as to confine the surface acoustic wave to the inside of the resonator device 100 along the second direction N2, and at the same time, the metal layer 60 can also be exposed to the packaged resonator device. 100, so that the interdigital electrodes can access electrical signals through the metal layer 60 and the bus bars covered by it.
  • one or more dielectric layers can be arranged between the piezoelectric layer and the wafer substrate to adjust the electromechanical coupling coefficient of the resonant device, thereby improving the performance of the resonant device .
  • the widths of the first interdigitated electrode 310 and the second interdigitated electrode 320 in the third direction N3 are set to 250 nm ⁇ W e ⁇ 1 ⁇ m, so as to adjust the The width of the interdigitated electrodes can adjust the electromechanical coupling coefficient of the resonant device 100 , thereby enhancing the performance of the resonant device 100 and increasing the operating frequency of the resonant device 100 .
  • the total number of the first interdigital electrodes 310 and the second interdigital electrodes 320 is set to be greater than 50, so as to adjust the electromechanical coupling coefficient of the resonant device 100 by adjusting the number of interdigitated electrodes , thereby enhancing the performance of the resonant device 100 and increasing the operating frequency of the resonant device 100 .
  • the total number of metal strips 331 in the acoustic reflection grating 330 is set to be greater than 50, so as to reduce the surface acoustic waves propagating from the resonator device 100 to the outside of the acoustic reflection gratings 330 on both sides, and help limit the surface acoustic waves to The interior of the resonant device 100 is along the third direction N3 , thereby improving the energy conversion efficiency between the electrical energy and the mechanical energy of the resonant device 100 .
  • the overlapping length of the first interdigital electrode 310 and the second interdigital electrode 320 along the second direction N2 is set to be 15 ⁇ m ⁇ L a ⁇ 200 ⁇ m, and the second interdigital electrode 320 and the interdigital electrode 320 overlap with each other.
  • the distance between the bus bars 311 on the first side of the electrode layer 30 (that is, the distance between the first interdigital electrode 310 and the bus bars 321 on the second side of the interdigital electrode layer 30 ) is 250 nm ⁇ L g ⁇ 5 ⁇ m, with The electromechanical coupling coefficient of the resonant device 100 is adjusted, thereby enhancing the performance of the resonant device 100 and increasing the operating frequency of the resonant device 100 .
  • the spacing between the adjacent first interdigitated electrodes 310 and the second interdigitated electrodes 320 in the interdigitated electrode layer 30 is set to be 500 nm ⁇ W pi ⁇ 2 ⁇ m
  • the distance between the interdigitated electrode 310 and the second interdigitated electrode 320 may be the distance between the center of the first interdigitated electrode 310 along the third direction N3 and the center of the adjacent second interdigitated electrode 320 along the third direction N3. distance.
  • the spacing between the first interdigital electrodes 310 and the second interdigital electrodes 320 is set. , so as to increase the operating frequency of the resonant device 100 .
  • the thickness of the first interdigitated electrode 310 and the second interdigitated electrode 320 along the direction perpendicular to the wafer substrate 10 is 500 nm ⁇ T e ⁇ 200 nm, and the piezoelectric layer 20 is far away from
  • the thickness of the passivation layer 50 between the surface of the wafer substrate 10 side and the surface of the passivation layer 50 away from the piezoelectric layer 20 is 100 nm ⁇ T p1 ⁇ 600 nm, and the piezoelectric layer 20 is perpendicular to the wafer substrate.
  • the thickness in the direction of 10 is 300 nm ⁇ T p2 ⁇ 1 ⁇ m, so as to adjust the electromechanical coupling coefficient of the resonant device 100 by adjusting the thickness of the interdigital electrode, the thickness of the passivation layer 50 and the thickness of the piezoelectric layer 20 , thereby enhancing the resonant device 100 performance and increase the operating frequency of the resonant device 100 .
  • FIG. 18 is a schematic diagram of stress distribution of a resonant device provided in an embodiment of the present application.
  • FIG. 18 schematically shows the stress distribution of multiple film layers of the resonator device 100 shown in FIG. 14 under the action of an electric field. 14 and 18 , under the action of the electric field, the mechanical stress generated by the resonator device 100 mainly exists in the piezoelectric layer 20 , the interdigital electrode layer 30 and the passivation layer 50 , and only a small amount of stress exists in the wafer substrate 10 .
  • the second interdigital electrode 320 can be respectively connected with the first interdigital electrodes 310 on both sides in the entire piezoelectric layer 20 .
  • Reverse electric fields E1 and E2 are generated in the thickness direction.
  • the stress generated by the resonator device 100 in the piezoelectric layer 20 reaches an extreme value.
  • the electric field E1 applied in the electrical layer 20 makes the stress generated at the corresponding position of the piezoelectric layer 20 reach a maximum value (close to Max).
  • the electric field E2 of makes the stress generated at the corresponding position of the piezoelectric layer 20 reach a minimum value (close to -Max).
  • FIG. 19 is a schematic diagram of the displacement distribution of a resonant device provided in an embodiment of the present application, and FIG. 19 schematically shows the displacement distribution of multiple film layers of the resonator device 100 shown in FIG. 14 under the action of an electric field. 14 and 19 , the displacement caused by the standing wave generated in the acoustic wave propagation in the resonant device 100 is mainly in the piezoelectric layer 20 , the interdigital electrode layer 30 and the passivation layer 50 , and only a small amount in the wafer substrate 10 displacement.
  • FIG. 20 is an admittance characteristic curve of a resonant device provided in an embodiment of the present application, and FIG. 20 may be an admittance characteristic curve obtained by performing a simulation experiment on the resonant device 100 shown in FIGS. 13 and 14 .
  • the resonant frequency f s of the resonant device 100 provided in the embodiment of the present application is 2.62 GHz
  • the electromechanical coupling coefficient Kt 2 can reach 12%.
  • the solution of this embodiment helps to improve the resonant device 100
  • the electromechanical coupling coefficient and frequency and help to determine the thickness, width, size and position of the interdigital electrodes, and the size and position of the acoustic reflection grating relative to the interdigital electrodes of the corresponding resonator device 100 according to the solution.
  • Alternative structures and dimensions of the resonant device 100 are possible.
  • the embodiment of the present application also provides a filter, the filter includes the resonant device in any of the above embodiments of the present application.
  • the filter provided in the embodiment of the present application includes the resonant device provided in any of the above-mentioned embodiments of the present application, and therefore has corresponding functional modules and effects of the resonant device, and details are not described again.

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Abstract

本文公开了一种谐振器件和滤波器。谐振器件包括晶圆衬底、压电层和叉指电极层；压电层位于晶圆衬底的一侧，包括压电单晶材料；晶圆衬底的主定位边位于第一方向，压电单晶材料包括互相垂直的第一晶轴、第二晶轴和第三晶轴；第一晶轴垂直于晶圆衬底，或者第一晶轴平行于晶圆衬底且第一晶轴与第一方向的夹角小于或等于30度，或者第一晶轴平行于晶圆衬底且第一晶轴与第一方向的夹角大于或等于60度且小于或等于120度；第二晶轴平行于晶圆衬底且第二晶轴与第一方向的夹角小于或等于60度，或者第二晶轴与垂直于晶圆衬底的方向的夹角大于或等于120度且小于或等于135度。

Description

谐振器件和滤波器
本申请要求在2021年02月20日提交中国专利局、申请号为202110194412.3的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及无线通信技术领域，例如涉及一种谐振器件和滤波器。
背景技术
射频滤波器件作为无线通信前端的重要组成部分，具有频率选择及抑制干扰信号的功能。性能较好的射频滤波器件不但可以提高发射器的灵敏度，降低发射器的频谱占用空间，还能提高收发机的信号噪声比，并降低通信链路中移动设备的功耗。
射频滤波器件由谐振器件构成，谐振器件通常包括声表面波(Surface Acoustic Wave，SAW)谐振器件和体声波(Bulk Acoustic Wave，BAW)谐振器件，SAW谐振器件和BAW谐振器件分别具有不同频率范围内的技术和成本优势。为符合移动宽带和高数据率无线应用的需求，通信标准不断向更高频率和更宽带宽发展，相关技术中的SAW谐振器件和BAW谐振器件已无法满足上述标准。
例如，SAW谐振器件具有低成本的优势，但SAW谐振器件的工作频率较低，若要提升SAW谐振器件的工作频率，则需调整谐振器件的电极宽度，使得SAW谐振器件的设计无法同时兼顾器件的功率阈值、插入损耗以及制造成本，进而导致工作频率较高的SAW谐振器件要么成本过高要么性能不足。尽管BAW谐振器件具有性能及高频方面的优势，但BAW谐振器件的制造工艺复杂，增加了BAW谐振器件的制造成本，难以满足消费电子市场的需求。
发明内容
本申请提供一种谐振器件和滤波器，以提高谐振器件的性能与工作频率。
提供了一种谐振器件，包括：
晶圆衬底；
压电层，位于所述晶圆衬底的一侧，所述压电层包括压电单晶材料；
叉指电极层，位于所述压电层远离所述晶圆衬底的一侧；
所述晶圆衬底的主定位边位于第一方向，所述压电单晶材料包括互相垂直的第一晶轴、第二晶轴和第三晶轴；其中，所述第一晶轴垂直于所述晶圆衬底，或者所述第一晶轴平行于所述晶圆衬底且所述第一晶轴与所述第一方向的夹角小于或等于30度，或者所述第一晶轴平行于所述晶圆衬底且所述第一晶轴与所述第一方向的夹角大于或等于60度且小于或等于120度；所述第二晶轴平行于所述晶圆衬底且所述第二晶轴与所述第一方向的夹角小于或等于60度，或者所述第二晶轴与垂直于所述晶圆衬底的方向的夹角大于或等于120度且小于或等于135度。
还提供了一种滤波器，包括上述的谐振器件。
附图说明
图1是本申请实施例提供的一种谐振器件的结构示意图；
图2是本申请实施例提供的一种谐振器件的俯视图；
图3是本申请实施例提供的一种谐振器件的剖视图；
图4是本申请实施例提供的一种压电单晶材料的结构示意图；
图5是本申请实施例提供的另一种谐振器件的剖视图；
图6是本申请实施例提供的另一种谐振器件的剖视图；
图7是本申请实施例提供的另一种谐振器件的结构示意图；
图8是本申请实施例提供的另一种谐振器件的剖视图；
图9是本申请实施例提供的另一种谐振器件的剖视图；
图10是本申请实施例提供的另一种谐振器件的结构示意图；
图11是本申请实施例提供的另一种谐振器件的结构示意图；
图12是本申请实施例提供的另一种谐振器件的结构示意图；
图13是本申请实施例提供的另一种谐振器件的俯视图；
图14是本申请实施例提供的另一种谐振器件的剖视图；
图15是本申请实施例提供的另一种谐振器件的剖视图；
图16是本申请实施例提供的另一种谐振器件的俯视图；
图17是本申请实施例提供的另一种谐振器件的剖视图；
图18是本申请实施例提供的一种谐振器件的应力分布示意图；
图19是本申请实施例提供的一种谐振器件的位移分布示意图；
图20是本申请实施例提供的一种谐振器件的导纳特性曲线。
具体实施方式
下面结合附图和实施例对本申请进行说明。
本申请实施例提供了一种谐振器件，图1是本申请实施例提供的一种谐振器件的结构示意图，图1为一种晶圆级谐振器件的侧视图，其中，图1仅示意性地示出了该晶圆级谐振器件的晶圆衬底10和压电层20，该晶圆级谐振器件可包括多个谐振器件100，图1示出了其中的一个谐振器件100；图2是本申请实施例提供的一种谐振器件的俯视图，图2可为图1中的谐振器件100的俯视图；图3是本申请实施例提供的一种谐振器件的剖视图，图3可为图2所示谐振器件100沿剖线AA’进行剖切得到的剖视图；图4是本申请实施例提供的一种压电单晶材料的结构示意图。
结合图1至图4，本申请实施例提供的谐振器件100包括：晶圆衬底10、压电层20以及叉指电极层30；压电层20位于晶圆衬底10的一侧，压电层20包括压电单晶材料；叉指电极层30，位于压电层20远离晶圆衬底10的一侧；晶圆衬底10的主定位边11位于第一方向N1，压电单晶材料包括互相垂直的第一晶轴X、第二晶轴Y和第三晶轴Z；其中，第一晶轴X垂直于晶圆衬底10，或者第一晶轴X平行于晶圆衬底10且第一晶轴X与第一方向N1的夹角小于或等于30度，或者大于或等于60度且小于或等于120度；第二晶轴Y平行于晶圆衬底10且第二晶轴Y与第一方向N1的夹角小于或等于60度，或者第二晶轴Y与垂直于晶圆衬底10的方向的夹角大于或等于120度且小于或等于135度。
晶圆衬底10能够为谐振器件100提供缓冲、保护或支撑等作用，晶圆衬底10的材料可以是蓝宝石。谐振器件100中的多个膜层可依次形成在晶圆衬底10之上，以形成包括多个谐振器件100的晶圆级谐振器件，在形成晶圆级谐振器件之后，可通过对其进行切割来得到谐振器件100。压电层20可通过键合形成在晶圆衬底10上，压电层20可由多个按一定规则排布的压电单晶材料构成，该压电单晶材料是指具有压电效应的单晶材料，在电场的作用下，压电单晶材料中会产生机械应力并发生相应的形变。
叉指电极层30可包括两组沿第二方向N2延伸的叉指电极，该两组叉指电极在压电层20上形成类似于两只手的手指呈相互交叉状的金属电极图案。向谐振器件100中的两组叉指电极输入电信号，以向压电层20施加第三方向N3(第三方向N3是指平行于晶圆衬底10，并垂直于叉指电极的延伸方向的方向)的电场，使得压电层20的整个厚度方向(垂直于晶圆衬底10的方向)上均产生第三方向N3的电场时，叉指电极可在压电层20中激发沿第三方向N3传播的 声表面波，即纵向极化声波，并将声表面波转换为相应的电信号输出，以实现滤波。
由于晶体结构具有空间排列上的三维周期性，每一类晶体结构对应的包含三个晶轴的晶轴坐标系。本实施例中仅结合图4所示的三方晶系压电单晶材料的晶体结构为例进行示意性说明，而并非是对压电单晶材料的晶体结构种类进行限定。示例性地，图4所示压电单晶材料可以是铌酸锂和钽酸锂中的任一种，该压电单晶材料的晶体结构中，第三晶轴Z可位于晶体较长的体对角线上，体对角线的中点可以是坐标原点，做垂直于第三晶轴Z的平面，可得到第一晶轴X和第二晶轴Y所在的平面。当压电层20中的压电单晶材料的晶轴方向确定时，压电单晶材料相对于晶圆衬底10和叉指电极层30的设置方向也确定。
图1示意性地示出了第一晶轴X垂直于晶圆衬底10，即第二晶轴Y与第三晶轴Z构成的平面与晶圆衬底10平行，并且第二晶轴Y与晶圆衬底10的主定位边11的夹角a1小于或等于60度的情况。其中，晶圆衬底10的主定位边11所在的第一方向N1也可以是器件方向。由于压电单晶材料具有各向异性的特点，本实施例中设置第一晶轴X垂直于晶圆衬底10，第二晶轴Y与第三晶轴Z构成的平面与晶圆衬底10平行，并且第二晶轴Y与晶圆衬底10的主定位边11的夹角a1小于或等于60度，使得谐振器件100通过叉指电极向压电单晶材料施加电场时，能够增强压电层20产生的压电效应，从而提升谐振器件100的机电耦合系数，以增强谐振器件100的性能并提高谐振器件100的工作频率。
在本申请的其他实施方式中，第一晶轴X还可以与晶圆衬底10平行，并且第一晶轴X与晶圆衬底10的主定位边11的夹角可小于或等于30度，或者第一晶轴X与晶圆衬底10平行，并且第一晶轴X与晶圆衬底10的主定位边11的夹角大于或等于60度且小于或等于120度。第二晶轴Y还可以与晶圆衬底10平行，并且第二晶轴Y与晶圆衬底10的主定位边11的夹角可小于或等于60度，或者第二晶轴Y与垂直于晶圆衬底10的方向的夹角大于或等于120度且小于或等于135度。本实施例通过设置晶轴的特定方向，实现了设置压电层20中的压电单晶材料的特定方向，由于压电单晶材料具有各向异性的特点，将压电层20以上述特定方向与晶圆衬底10进行键合，同样有助于增强压电层20产生的压电效应，从而提升谐振器件100的机电耦合系数，以增强谐振器件100的性能并提高谐振器件100的工作频率。
本申请实施例的技术方案，通过谐振器件激发纵向极化声表面波，以及设置晶轴的特定方向，实现了设置压电层中的压电单晶材料的特定方向，以调整谐振器件内部的几何形状与结构的效果，由于压电单晶材料具有各向异性的特点，将压电单晶材料以上述特定方向与晶圆衬底进行键合，有助于增强压电层 产生的压电效应，从而提升谐振器件的机电耦合系数，并增强谐振器件的性能。本申请实施例的技术方案，缓解了相关技术中的声表面波谐振器件无法兼顾高性能与低成本的问题，有利于在保证谐振器件的低成本优势的同时，提高谐振器件的性能与工作频率，进而提高包含该谐振器件的带通滤波器的性能，以满足第五代移动通信系统(the 5th Generation mobile communication system，5G)的通信标准的需求。
结合图1至图4，在上述实施例的基础上，可选地，设置第一晶轴X垂直于晶圆衬底10，并且沿顺时针方向，第一方向N1旋转至第二晶轴Y的旋转角a1大于或等于0度且小于或等于60度。
示例性地，第一晶轴X垂直于晶圆衬底10，且第一晶轴X的正半轴指向压电层20远离晶圆衬底10的方向，第一晶轴X的负半轴(-X)指向压电层20靠近晶圆衬底10的方向，或者第一晶轴X的正半轴指向压电层20靠近晶圆衬底10的方向，第一晶轴X的负半轴指向压电层20远离晶圆衬底10的方向。沿顺时针方向，第一方向N1旋转至第二晶轴Y的旋转角大于或等于0度且小于或等于60度，是指第二晶轴Y的正半轴或负半轴(-Y)可由晶圆衬底10的定位边11顺时针旋转至0度至60度之间的任意位置上。本实施例通过设置晶轴的特定方向，实现了设置压电层20中的压电单晶材料的特定方向，由于压电单晶材料具有各向异性的特点，将压电层以20上述特定方向与晶圆衬底10进行键合，有助于增强压电层20产生的压电效应，从而提升谐振器件100的机电耦合系数，以增强谐振器件100的性能并提高谐振器件100的工作频率。经实验验证，本实施例提供的谐振器件100的机电耦合系数高达15％左右。
图5是本申请实施例提供的另一种谐振器件的剖视图，图5可为图2所示谐振器件100沿剖线AA’进行剖切得到的另一种剖视图，其中，图5仅示出了谐振器件100的晶圆衬底10和压电层20；图6是本申请实施例提供的另一种谐振器件的剖视图，图6可为图2所示谐振器件100沿剖线AA’进行剖切得到的另一种剖视图，其中，图6仅示出了谐振器件100的晶圆衬底10和压电层20；图7是本申请实施例提供的另一种谐振器件的结构示意图，图7为另一种晶圆级谐振器件的侧视图，其中，图7仅示出了该晶圆级谐振器件的晶圆衬底10和压电层20。
结合图4至图7，可选地，设置第一晶轴X平行于晶圆衬底10，第二晶轴Y与垂直于晶圆衬底10的方向的夹角a2大于或等于120度且小于或等于135度，并且沿顺时针方向，第一方向N1旋转至第一晶轴X的旋转角a3大于或等于60度且小于或等于120度。
示例性地，沿顺时针方向，第一方向N1旋转至第一晶轴X的旋转角大于 或等于60度且小于或等于120度，是指第一晶轴X可位于由晶圆衬底10的定位边11顺时针旋转至60度至120度之间的任意位置上。垂直于晶圆衬底10的方向可以是图5和图6所示的虚线L所在的方向，相应地，第二晶轴Y与垂直于晶圆衬底10的方向的夹角a2大于或等于120度且小于或等于135度，是指第二晶轴Y可位于由虚线L顺时针旋转至120度至135度之间的任意位置上，并且第二晶轴Y的正半轴指向压电层20靠近晶圆衬底10的一侧(如图5所示)，或者第二晶轴Y的正半轴指向压电层20远离晶圆衬底10的一侧(如图6所示)。本实施例通过设置晶轴的特定方向，实现了设置压电层20中的压电单晶材料的特定方向，由于压电单晶材料具有各向异性的特点，将压电层20以上述特定方向与晶圆衬底10进行键合，有助于增强压电层20产生的压电效应，从而提升谐振器件100的机电耦合系数，以增强谐振器件100的性能并提高谐振器件100的工作频率。经实验验证，本实施例提供的谐振器件100的机电耦合系数高达10％左右。
图8是本申请实施例提供的另一种谐振器件的剖视图，图8可为图2所示谐振器件100沿剖线AA’进行剖切得到的另一种剖视图，其中，图8仅示出了谐振器件100的晶圆衬底10和压电层20；图9是本申请实施例提供的另一种谐振器件的剖视图，图9可为图2所示谐振器件100沿剖线AA’进行剖切得到的另一种剖视图，其中，图9仅示出了谐振器件100的晶圆衬底10和压电层20；图10是本申请实施例提供的另一种谐振器件的结构示意图，图10为另一种晶圆级谐振器件的侧视图，其中，图10仅示出了该晶圆级谐振器件的晶圆衬底10和压电层20。
结合图4以及图8至图10，可选地，设置第一晶轴X平行于晶圆衬底10，第二晶轴Y与垂直于晶圆衬底10的方向的夹角a4大于或等于30度且小于或等于50度，并且沿顺时针方向，第一方向N1旋转至第一晶轴X的旋转角a5大于或等于-30度且小于或等于30度，或者大于或等于60度且小于或等于120度。
示例性地，沿顺时针方向，第一方向N1旋转至第一晶轴X的旋转角a5大于或等于-30度且小于或等于30度，或者大于或等于60度且小于或等于120度，是指第一晶轴X可位于由晶圆衬底10的定位边11顺时针旋转至-30度至30度之间的任意位置上，或者第一晶轴X可位于由晶圆衬底10的定位边11顺时针旋转至60度至120度之间的任意位置上。垂直于晶圆衬底10的方向可以是图8和图9所示的虚线L所在的方向，相应地，第二晶轴Y与垂直于晶圆衬底10的方向的夹角a4大于或等于30度且小于或等于50度，是指第二晶轴Y可位于由虚线L顺时针旋转至30度至50度之间的任意位置上，并且第二晶轴Y的正半轴指向压电层20远离晶圆衬底10的一侧(如图8所示)，或者第二晶轴Y的正半轴指向压电层20靠近晶圆衬底10的一侧(如图9所示)。本实施例通 过设置晶轴的特定方向，实现了设置压电层20中的压电单晶材料的特定方向，由于压电单晶材料具有各向异性的特点，将压电层20以上述特定方向与晶圆衬底10进行键合，有助于增强压电层20产生的压电效应，从而提升谐振器件100的机电耦合系数，以增强谐振器件100的性能并提高谐振器件100的工作频率。经实验验证，本实施例提供的谐振器件100的机电耦合系数高达10％左右。
参见图2和图3，可选地，设置叉指电极层30包括多个第一叉指电极310和多个第二叉指电极320；多个第一叉指电极310均连接至位于叉指电极层30的第一侧的汇流条311，并且多个第一叉指电极310均由叉指电极层30的第一侧沿第二方向N2向叉指电极层30的第二侧延伸，第二侧位于第一侧的对侧；多个第二叉指电极320均连接至位于叉指电极层30的第二侧的汇流条321，并且多个第二叉指电极320均由第二侧沿第二方向N2向第一侧延伸；第一叉指电极310和第二叉指电极320在压电层20上的垂直投影相交替，并且第一叉指电极310和第二叉指电极320互相绝缘。
第一叉指电极310和第二叉指电极320均为金属电极，第一叉指电极310和第二叉指电极320的材料可包括钛(Titanium，Ti)、银(Silver，Ag)、铝(Aluminium，Al)、铜(Copper，Cu)、铜铝合金(Aluminum copper alloy，AlCu)、铬(Chromium，Cr)、钌(Ruthenium，Ru)、钼(Molybdenum，Moly)和钨(Tungsten，W)中的任一种，或者第一叉指电极310和第二叉指电极320的材质也可以是上述材料的组合。每个第一叉指电极310连接至公共电极，即叉指电极层30的第一侧的汇流条311；每个第二叉指电极320连接至公共电极，即叉指电极层30的第二侧的汇流条321。多个第一叉指电极310的宽度可能相同或不同，多个第二叉指电极320的宽度也可能相同或不同。谐振器件100工作时，第一叉指电极310通过叉指电极层30的第一侧的汇流条311输入电源信号Vin，第二叉指电极320通过叉指电极层30的第二侧的汇流条321输入接地信号GND，以使叉指电极层30能够在压电层20中施加垂直于第一叉指电极310和第二叉指电极320的方向上的电场，即第三方向N3的电场，使得压电层20的整个厚度方向上均产生第三方向N3的电场，进而激发沿第三方向N3传播的声表面波，即纵向极化声波，并将声表面波转换为相应的电信号输出，以实现滤波。
图11是本申请实施例提供的另一种谐振器件的结构示意图，图11为另一种晶圆级谐振器件的侧视图，其中，图11仅示出了该晶圆级谐振器件的晶圆衬底10和压电层20；图12是本申请实施例提供的另一种谐振器件的结构示意图，图12为另一种晶圆级谐振器件的侧视图，其中，图12仅示出了该晶圆级谐振器件的晶圆衬底10和压电层20。结合图1至图4以及图11和图12，可选地，设置第一方向N1与第三方向N3的夹角a1大于或等于-30度且小于或等于30 度，第三方向N3平行于晶圆衬底10，并垂直于第二方向N2。
示例性地，第一方向N1与第三方向N3的夹角大于或等于-30度且小于或等于30度，是指垂直于第一叉指电极310和第二叉指电极320的延伸方向(即第二方向N2)的方向(即第三方向N3)与晶圆衬底10的主定位边11的夹角-30°≤a1≤30°，换言之，也即谐振器件100激发的声表面波的传播方向(第三方向N3)与晶圆衬底10的主定位边11的夹角-30°≤a1≤30°。其中，图1示意性地示出了第一方向N1与第三方向N3的夹角a1＝0°的情况，图11示意性地示出了第一方向N1与第三方向N3的夹角a1＝30°的情况，图12示意性地示出了第一方向N1与第三方向N3的夹角a1＝-30°的情况。由于压电层20在叉指电极施加的电场作用下会产生机械应力并发生相应的形变，进而在压电层20中激发沿第三方向N3传播的声表面波，考虑到压电层20中的压电单晶材料具有各向异性的特点，本实施例通过设置第一方向N1与第三方向N3的夹角-30°≤a1≤30°，实现了调整叉指电极的方向与压电单晶材料的晶体结构朝向之间的相对位置关系，有利于在激发沿第三方向N3传播的声表面波的同时，增强压电层20产生的压电效应，从而提升谐振器件100的机电耦合系数，以增强谐振器件100的性能并提高谐振器件100的工作频率。
图13是本申请实施例提供的另一种谐振器件的俯视图，图13可为图1中的谐振器件100的另一种俯视图。如图13所示，可选地，设置叉指电极层30还包括多个第一虚设叉指电极312和多个第二虚设叉指电极322；第一虚设叉指电极312位于相邻第一叉指电极310之间并连接至第一侧的汇流条311，第一虚设叉指电极312由第一侧沿第二方向N2向第二侧延伸；第二虚设叉指电极322位于相邻第二叉指电极320之间并连接至第二侧的汇流条321，第二虚设叉指电极322由第二侧沿第二方向N2向第一侧延伸；第一虚设叉指电极312、第二虚设叉指电极322、第一叉指电极310和第二叉指电极320互相绝缘。第一虚设叉指电极312和第二虚设叉指电极322的材质可以与第一叉指电极310和第二叉指电极320的材质相同，本实施例通过设置第一虚设叉指电极312和第二虚设叉指电极322，形成与叉指电极断开的虚短跟指(例如第一虚设叉指电极312形成与对应的第二叉指电极320断开的虚短跟指，第二虚设叉指电极322形成与对应的第一叉指电极310断开的虚短跟指)，以使谐振器件100激发的声表面波传播至第一虚设叉指电极312和第二虚设叉指电极322时发生反射，从而将声表面波限制在谐振器件100沿第二方向N2的内部，进而提高谐振器件100的能量反射率并抑制不需要的杂散响应。
图14是本申请实施例提供的另一种谐振器件的剖视图，图14可为图13所示谐振器件100沿剖线bb’进行剖切得到的剖视图。结合图2、图13和图14，可选地，谐振器件100还包括声反射栅330，声反射栅330位于压电层20远离 晶圆衬底10的一侧，声反射栅330设置在叉指电极层30沿第二方向N2的两侧，并与叉指电极层30绝缘；每个声反射栅330包括多个沿第二方向N2延伸的金属条331，金属条331在第三方向N3上的宽度W r大于第一叉指电极310和第二叉指电极320在第三方向N3的宽度W e的0.25倍，并小于第一叉指电极310和第二叉指电极320在第三方向N3的宽度W e的10倍；其中，第三方向N3平行于晶圆衬底10，并垂直于第二方向N2；叉指电极层30与相邻的金属条331的间距W g大于第一叉指电极310和第二叉指电极320在第三方向N3的宽度W e的0.2倍，并小于第一叉指电极310和第二叉指电极320在第三方向N3的宽度W e的10倍。
声反射栅330的材质可以与第一叉指电极310和第二叉指电极320的材质相同或者不同。声反射栅330中的金属条331的两端分别连接总线，即总线332和总线333。连接第一叉指电极310和第二叉指电极320的汇流条，可以与声反射栅330中金属条331连接的总线相连，也可以不连接，图2和图13均示出了连接叉指电极的汇流条不与声反射栅中金属条连接的总线相连的情况。本实施例通过在叉指电极层30的两侧设置声反射栅330，能够基于声波的衍射原理，减少谐振器件100向两侧的声反射栅330外部传播的声表面波，有助于将声表面波限制在谐振器件100沿第三方向N3的内部，进而提高谐振器件100的电能与机械能之间的能量转换效率。
叉指电极层30与相邻的金属条331的间距W g，是指声反射栅中距离叉指电极最近的金属条331，与叉指电极层30中最接近声反射栅的第一叉指电极310或第二叉指电极320之间的间距。图14示意性地示出了第一叉指电极310和第二叉指电极320在第三方向N3的宽度均为W e的情况，本实施例通过设置金属条331在第三方向N3上的宽度0.25W e＜W r＜10W e，且叉指电极层30与相邻的金属条331的间距0.2W e＜W g＜10W e，有助于减弱谐振器件100通过声反射栅产生的声波衍射，从而减少谐振器件100向两侧的声反射栅330外部传播的声表面波，有助于将声表面波限制在谐振器件100沿第三方向N3的内部，进而提高谐振器件100的电能与机械能之间的能量转换效率。
图15是本申请实施例提供的另一种谐振器件的剖视图，图15可为图13所示谐振器件100沿剖线bb’进行剖切得到的另一种剖视图。如图3、图14和图15所示，可选地，谐振器件100还包括位于叉指电极层30远离晶圆衬底10一侧的钝化层50，且钝化层50覆盖叉指电极层30。
钝化层50的材质可以是二氧化硅(Silicon dioxide，SiO2)或者氮化硅(Silicon Nitride，SiNx)，本实施例通过设置钝化层50覆盖叉指电极层30，以隔绝水氧，实现对叉指电极层30的保护。在叉指电极层30远离晶圆衬底10的一侧形成钝 化层50时，可使钝化层50远离晶圆衬底10一侧的上表面形成平面，或者也可以使钝化层50上表面的起伏与叉指电极层30上表面的形貌一致。
图16是本申请实施例提供的另一种谐振器件的俯视图，图16可为图1中的谐振器件100的另一种俯视图；图17是本申请实施例提供的另一种谐振器件的剖视图，图17可为图16所示谐振器件100沿剖线CC’进行剖切得到的一种剖视图。结合图16和图17，可选地，谐振器件100还包括金属层60，金属层60位于叉指电极层30远离晶圆衬底10的一侧，金属层60覆盖叉指电极层30的第一侧的汇流条311的至少部分区域，并覆盖叉指电极层30的第二侧的汇流条321的至少部分区域。
金属层60的材料可包括钛(Ti)、银(Ag)、铝(Al)、铜(Cu)、铜铝合金(AlCu)、铬(Cr)、钌(Ru)、钼(Moly)和钨(W)中的任一种，或者也可以是上述材料的组合。本实施例通过设置金属层60覆盖叉指电极层30的第一侧的汇流条311的至少部分区域，以及覆盖叉指电极层30的第二侧的汇流条321的至少部分区域，有助于使谐振器件100激发的声表面波传播至金属层60时发生反射，从而将声表面波限制在谐振器件100沿第二方向N2的内部，同时，金属层60还可以暴露在完成封装的谐振器件100的表面，以使叉指电极通过金属层60及其覆盖的汇流条接入电信号。
在上述实施例的基础上，可选地，还可以在压电层与晶圆衬底之间设置一层或多层介电层，以调节谐振器件的机电耦合系数，进而改善谐振器件的性能。
结合图13和图14，在上述实施例的基础上，可选地，设置第一叉指电极310和第二叉指电极320在第三方向N3的宽度250nm＜W e＜1μm，以通过调节叉指电极的宽度来调节谐振器件100的机电耦合系数，进而增强谐振器件100的性能并提高谐振器件100的工作频率。
结合图13和图14，可选地，设置第一叉指电极310和第二叉指电极320的总个数大于50，以通过调节叉指电极的个数来调节谐振器件100的机电耦合系数，进而增强谐振器件100的性能并提高谐振器件100的工作频率。可选地，设置声反射栅330中的金属条331的总个数大于50，以减少谐振器件100向两侧的声反射栅330外部传播的声表面波，有助于将声表面波限制在谐振器件100沿第三方向N3的内部，进而提高谐振器件100的电能与机械能之间的能量转换效率。
结合图13和图14，可选地，设置第一叉指电极310和第二叉指电极320沿第二方向N2相交叠的长度15μm＜L a＜200μm，第二叉指电极320与叉指电极层30的第一侧的汇流条311之间的距离(即第一叉指电极310与叉指电极层30的第二侧的汇流条321之间的距离)250nm＜L g＜5μm，以调节谐振器件100的 机电耦合系数，进而增强谐振器件100的性能并提高谐振器件100的工作频率。
结合图13和图14，可选地，设置叉指电极层30中相邻的第一叉指电极310和第二叉指电极320之间的间距500nm＜W pi＜2μm，相邻的第一叉指电极310和第二叉指电极320之间的间距可以是第一叉指电极310沿第三方向N3的中心与相邻的第二叉指电极320沿第三方向N3的中心之间的距离。由于f＝v/(2*W pi)，其中，f为谐振器件100的工作频率，v为谐振器件100中的声表面波传播的波速，因此，在波速不变的情况下，第一叉指电极310和第二叉指电极320之间的间距W pi越小，谐振器件100的工作频率，本实施例通过对第一叉指电极310和第二叉指电极320之间的间距进行设置，以提高谐振器件100的工作频率。
结合图13和图14，可选地，设置第一叉指电极310和第二叉指电极320沿垂直于晶圆衬底10的方向上的厚度500nm＜T e＜200nm，压电层20远离晶圆衬底10一侧的表面与钝化层50远离压电层20一侧的表面之间的钝化层50的厚度100nm＜T p1＜600nm，压电层20沿垂直于晶圆衬底10的方向上的厚度300nm＜T p2＜1μm，以通过调节叉指电极的厚度、钝化层50的厚度和压电层20的厚度来调节谐振器件100的机电耦合系数，进而增强谐振器件100的性能并提高谐振器件100的工作频率。
图18是本申请实施例提供的一种谐振器件的应力分布示意图，图18示意性地示出了在电场的作用下，图14所示谐振器件100的多个膜层的应力分布情况。结合图14和图18，在电场的作用下，谐振器件100产生的机械应力主要存在于压电层20、叉指电极层30和钝化层50中，晶圆衬底10中仅存在少量应力。并且由于第一叉指电极310输入电源信号Vin，第二叉指电极320输入接地信号GND，因此第二叉指电极320可分别与两侧的第一叉指电极310在压电层20的整个厚度方向上产生反向的电场E1和E2，相应地，在压电层20中谐振器件100产生的应力达到极值，例如第二叉指电极320与左侧的第一叉指电极310在压电层20中施加的电场E1使得压电层20相应位置产生的应力达到极大值(接近Max)，第二叉指电极320与右侧的第一叉指电极310在压电层20中施加的电场E2使得压电层20相应位置产生的应力达到极小值(接近-Max)。
图19是本申请实施例提供的一种谐振器件的位移分布示意图，图19示意性地示出了在电场的作用下，图14所示谐振器件100的多个膜层的位移分布情况。结合图14和图19，谐振器件100中的声波传播中产生的驻波引起的位移主要在压电层20、叉指电极层30和钝化层50中，晶圆衬底10中仅存在少量位移。
图20是本申请实施例提供的一种谐振器件的导纳特性曲线，图20可以是对图13和图14所示谐振器件100进行模拟实验得到的导纳特性曲线。如图20所示，本申请实施例提供的谐振器件100的共振频率f s为2.62GHz，机电耦合系 数Kt 2可达到12％，由此可见，本实施例的方案有助于提升谐振器件100的机电耦合系数和频率，并有助于根据该方案对应的谐振器件100的多个膜层的厚度、宽度、叉指电极的尺寸和位置以及声反射栅相对于叉指电极的尺寸和位置确定谐振器件100的可选结构和尺寸。
本申请实施例还提供了一种滤波器，该滤波器包括本申请上述任意实施例中的谐振器件。本申请实施例所提供的滤波器包括本申请上述任意实施例所提供的谐振器件，因此具备谐振器件相应的功能模块和效果，不再赘述。

Claims (10)

  1. 一种谐振器件，包括：
    晶圆衬底；
    压电层，位于所述晶圆衬底的一侧，所述压电层包括压电单晶材料；
    叉指电极层，位于所述压电层远离所述晶圆衬底的一侧；
    所述晶圆衬底的主定位边位于第一方向，所述压电单晶材料包括互相垂直的第一晶轴、第二晶轴和第三晶轴；其中，所述第一晶轴垂直于所述晶圆衬底，或者所述第一晶轴平行于所述晶圆衬底且所述第一晶轴与所述第一方向的夹角小于或等于30度，或者所述第一晶轴平行于所述晶圆衬底且所述第一晶轴与所述第一方向的夹角大于或等于60度且小于或等于120度；所述第二晶轴平行于所述晶圆衬底且所述第二晶轴与所述第一方向的夹角小于或等于60度，或者所述第二晶轴与垂直于所述晶圆衬底的方向的夹角大于或等于120度且小于或等于135度。
  2. 根据权利要求1所述的谐振器件，其中，所述第一晶轴垂直于所述晶圆衬底，并且沿顺时针方向，所述第一方向旋转至所述第二晶轴的旋转角大于或等于0度且小于或等于60度。
  3. 根据权利要求1所述的谐振器件，其中，所述第一晶轴平行于所述晶圆衬底，所述第二晶轴与垂直于所述晶圆衬底的方向的夹角大于或等于120度且小于或等于135度，并且沿顺时针方向，所述第一方向旋转至所述第一晶轴的旋转角大于或等于60度且小于或等于120度。
  4. 根据权利要求1所述的谐振器件，其中，所述第一晶轴平行于所述晶圆衬底，所述第二晶轴与垂直于所述晶圆衬底的方向的夹角大于或等于30度且小于或等于50度，并且沿顺时针方向，所述第一方向旋转至所述第一晶轴的旋转角大于或等于-30度且小于或等于30度，或者所述第一方向旋转至所述第一晶轴的旋转角大于或等于60度且小于或等于120度。
  5. 根据权利要求1所述的谐振器件，其中，所述叉指电极层包括多个第一叉指电极和多个第二叉指电极；
    所述多个第一叉指电极均连接至位于所述叉指电极层的第一侧的汇流条，并且所述多个第一叉指电极均由所述叉指电极层的第一侧沿第二方向向所述叉指电极层的第二侧延伸，所述第二侧位于所述第一侧的对侧；
    所述多个第二叉指电极均连接至位于所述叉指电极层的第二侧的汇流条，并且所述多个第二叉指电极均由所述第二侧沿所述第二方向向所述第一侧延伸；
    所述第一叉指电极和所述第二叉指电极在所述压电层上的垂直投影相交替， 并且所述第一叉指电极和所述第二叉指电极互相绝缘；
    在向所述多个第一叉指电极与所述多个第二叉指电极输入电信号的情况下，所述压电层设置为在垂直于所述晶圆衬底的方向上产生第三方向的电场。
  6. 根据权利要求5所述的谐振器件，其中，所述三方向旋转至所述第一方向的旋转角大于或等于-30度且小于或等于30度，所述第三方向平行于所述晶圆衬底，并垂直于所述第二方向。
  7. 根据权利要求5所述的谐振器件，其中，所述叉指电极层还包括多个第一虚设叉指电极和多个第二虚设叉指电极；
    所述第一虚设叉指电极位于相邻第一叉指电极之间并连接至所述第一侧的汇流条，所述第一虚设叉指电极由所述第一侧沿所述第二方向向所述第二侧延伸；
    所述第二虚设叉指电极位于相邻第二叉指电极之间并连接至所述第二侧的汇流条，所述第二虚设叉指电极由所述第二侧沿所述第二方向向所述第一侧延伸；
    所述第一虚设叉指电极、所述第二虚设叉指电极、所述第一叉指电极和所述第二叉指电极互相绝缘。
  8. 根据权利要求5所述的谐振器件，还包括声反射栅，所述声反射栅位于所述压电层远离所述晶圆衬底的一侧，所述声反射栅设置在所述叉指电极层沿所述第二方向的两侧，并与所述叉指电极层绝缘；
    位于所述叉指电极层沿所述第二方向的每一侧的声反射栅包括多个沿所述第二方向延伸的金属条，所述金属条在所述第三方向上的宽度大于所述第一叉指电极和所述第二叉指电极在所述第三方向的宽度的0.25倍，并小于所述第一叉指电极和所述第二叉指电极在所述第三方向的宽度的10倍；其中，所述第三方向平行于所述晶圆衬底，并垂直于所述第二方向；
    所述叉指电极层与相邻的金属条的间距大于所述第一叉指电极和所述第二叉指电极在所述第三方向的宽度的0.2倍，并小于所述第一叉指电极和所述第二叉指电极在所述第三方向的宽度的10倍。
  9. 根据权利要求5所述的谐振器件，还包括金属层，所述金属层位于所述叉指电极层远离所述晶圆衬底的一侧，所述金属层覆盖所述叉指电极层的第一侧的汇流条的至少部分区域，并覆盖所述叉指电极层的第二侧的汇流条的至少部分区域。
  10. 一种滤波器，包括权利要求1-9中任一项所述的谐振器件。
PCT/CN2021/091884 2021-02-20 2021-05-06 谐振器件和滤波器 WO2022174518A1 (zh)

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