WO2022174443A1 - 一种显示面板、显示装置和显示面板的制作方法 - Google Patents

一种显示面板、显示装置和显示面板的制作方法 Download PDF

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Publication number
WO2022174443A1
WO2022174443A1 PCT/CN2021/077233 CN2021077233W WO2022174443A1 WO 2022174443 A1 WO2022174443 A1 WO 2022174443A1 CN 2021077233 W CN2021077233 W CN 2021077233W WO 2022174443 A1 WO2022174443 A1 WO 2022174443A1
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Prior art keywords
substrate
cathode
display panel
layer
orthographic projection
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PCT/CN2021/077233
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English (en)
French (fr)
Inventor
于池
石博
黄炜赟
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/077233 priority Critical patent/WO2022174443A1/zh
Priority to US17/595,806 priority patent/US20230345776A1/en
Priority to EP21926160.9A priority patent/EP4141949A4/en
Priority to CN202180000267.9A priority patent/CN115280509A/zh
Publication of WO2022174443A1 publication Critical patent/WO2022174443A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H10K71/421—Thermal treatment, e.g. annealing in the presence of a solvent vapour using coherent electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a display device, and a manufacturing method of the display panel.
  • OLED Organic light-emitting diode, organic light-emitting diode
  • OLED display technology has the advantages of high brightness, low power consumption, fast response, high definition, with the development and maturity of OLED (Organic light-emitting diode, organic light-emitting diode) display technology , OLED display devices are more and more popular with users.
  • an embodiment of the present disclosure provides a display panel, including a substrate, the substrate including a display area and a functional area, the functional area including a light-transmitting area, and the light-transmitting area including a plurality of pixel units,
  • the pixel units are capable of emitting white light
  • each of the pixel units includes at least one sub-pixel
  • each of the pixel units further includes a cathode
  • the orthographic projections of a plurality of cathodes on the substrate are separated from each other, and each of the sub-pixels
  • the orthographic projection of the effective light-emitting area on the substrate is located within the range of the orthographic projection of the cathode of the corresponding pixel unit on the substrate
  • the display panel further includes a connection structure, the connection structure is the same as the cathode.
  • the layers are arranged through which the different cathodes are connected.
  • the orthographic projection of the edge of the cathode on the substrate is separated from the orthographic projection of the effective light-emitting area of the corresponding sub-pixel on the substrate, and the edge of the cathode is separated from the anode of the corresponding sub-pixel.
  • the orthographic projections of the substrates overlap.
  • the orthographic projection of the anode of the sub-pixel included in the pixel unit on the substrate is located within the orthographic projection of the cathode of the pixel unit on the substrate.
  • the orthographic projection of the edge of the anode on the substrate coincides with the edge portion of the orthographic projection of the corresponding cathode on the substrate.
  • the positive edge of the cathode is on the substrate.
  • the projection extends along a straight line.
  • edges of the cathode are all chamfered, and the edge chamfer of the cathode is greater than 30 degrees.
  • the plurality of cathodes and the connection structure in the light-transmitting area form a mesh structure
  • the mesh structure includes a plurality of openings, and each opening is surrounded by the cathode and the connection structure, the The materials of the cathode and the connecting structure are the same.
  • the plurality of cathodes are arranged along the first direction to form a cathode row, the multiple rows of cathode rows are arranged along the second direction, the angle between the first direction and the second direction is 80-100 degrees, and two adjacent cathode rows are Displaced in the first direction.
  • the functional area further includes a transition area and a pixel circuit area, the pixel circuit area is arranged around the light-transmitting area, the transition area is arranged between the pixel circuit area and the light-transmitting area, the transition area and the light-transmitting area are
  • the pixel circuit regions share one cathode, and the cathode is a solid figure in the orthographic projection of the substrate on the transition region and the pixel circuit region.
  • the display panel further includes a plurality of arc-shaped windings, the windings extend along the edge of the light-transmitting area, and the windings are connected to the pixel circuit area through the wirings located in the transition area. pixel circuit connection.
  • a semiconductor layer is further included, and in the transition region, the semiconductor layer includes a plurality of redundant patterns, and the redundant patterns are arranged at intervals and arranged in an array.
  • the first gate layer located between the semiconductor layer and the anode layer, the first gate layer includes a plurality of first transition lines located in the transition region, the first transition lines The dimension in the second direction is larger than the dimension in the first direction, a plurality of the first patch cords are arranged along the first direction and are parallel to each other, and the first patch cords are on the substrate
  • the orthographic projection of the redundant pattern on the substrate is separate from the orthographic projection of the redundant pattern on the substrate.
  • the second gate layer located between the first gate layer and the anode layer
  • the second gate layer includes a plurality of second transition lines located in the transition region, so The size of the second patch cord in the second direction is larger than the size in the first direction, and the orthographic projection of the second patch cord on the substrate and the redundant pattern on the substrate
  • the orthographic projection on the substrate and the orthographic projection of the first patch cord on the substrate are all separated, and the difference between the distance between two adjacent first patch cables and the distance between two adjacent second patch cables is The ratio is 0.8-1.2.
  • the interlayer insulating layer located between the second gate layer and the anode layer, in the transition region, the interlayer insulating layer includes a plurality of via holes, each via hole is in the The orthographic projection on the substrate overlaps the orthographic projection of one of the redundant patterns on the substrate.
  • the first metal layer located between the interlayer insulating layer and the anode layer, and in the transition region, the first metal layer includes a plurality of third patch wires, the third The size of the patch cord in the first direction is larger than the size in the second direction, and the orthographic projection of the third patch cord on the substrate is the same as the orthographic projection of the first patch cord on the substrate.
  • the included angle between the projections is 80-100 degrees, and the orthographic projection of the third patch wire on the substrate is separated from the orthographic projection of the redundant pattern on the substrate.
  • the transparent wire layer further includes a transparent wire layer between the first metal layer and the anode layer, and the transparent wire layer includes a transparent wire extending along the first direction and a first redundant wire, The transparent wiring is separated from the first redundant wiring, and the transparent wiring layer further includes a plurality of second redundant wirings extending along the second direction.
  • each anode is connected to a transparent wire through the anode hole, the transparent wire is connected to the pixel circuit disposed in the pixel circuit area, and the first redundant wire is connected to the second redundant wire.
  • the sub-pixels corresponding to each pixel unit include two green sub-pixels, one red sub-pixel and one blue sub-pixel, the two green sub-pixels are arranged along the second direction, and the blue sub-pixels are arranged in the second direction.
  • the effective light emitting area is located between the effective light emitting areas of the two green sub-pixels in the second direction.
  • the center lines of the effective light-emitting areas of the two green sub-pixels along the second direction are substantially coincident, and the effective light-emitting areas of the blue sub-pixels and the red sub-pixels are located at the same center line. side.
  • an embodiment of the present disclosure provides a display device, including the display panel according to any one of the first aspect, wherein a camera is provided in the light-transmitting area.
  • an embodiment of the present disclosure provides a method for fabricating a display panel, for fabricating the display panel according to any one of the first aspects, the method includes a step of forming a cathode, and the step of forming a cathode includes :
  • the use of laser to burn the cathode material layer to pattern the cathode material layer includes:
  • the cathode material layer is burned with a laser, and the cathode material layer is patterned to form an image of the cathode.
  • Each pixel unit in the light-transmitting area of the embodiment of the present disclosure includes a cathode, the orthographic projections of the plurality of cathodes on the substrate are separated from each other, and the orthographic projection of the effective light-emitting area of each sub-pixel on the substrate is located in the corresponding pixel unit.
  • the cathode is in the range of the orthographic projection of the substrate, and the display panel further includes a connection structure, the connection structure and the cathode are arranged in the same layer, and different cathodes are connected through the connection structure.
  • the embodiment of the present disclosure increases the opening area of the cathode layer in the light-transmitting region, which helps to improve the transparency of the light-transmitting region.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a stack of anodes and cathodes in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a stack of anodes and cathodes in yet another embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a stack of anodes and cathodes in yet another embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a stack of anodes and cathodes in yet another embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a stack of anodes and cathodes in yet another embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a stack of anodes and cathodes in yet another embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a stack of anodes and cathodes in yet another embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a stack of anodes and cathodes in yet another embodiment of the present disclosure.
  • connection between the cathode and the connection structure in an embodiment of the present disclosure is a schematic diagram of the connection between the cathode and the connection structure in an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a stack of anodes and cathodes in yet another embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of the connection between the cathode and the wiring in the embodiment shown in FIG. 11;
  • FIG. 13 is a schematic structural diagram of a semiconductor layer in an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a stack of a semiconductor layer and a first gate layer in an embodiment of the present disclosure
  • 15 is a schematic view of a stack of a semiconductor layer, a first gate layer and a second gate layer in an embodiment of the present disclosure
  • 16 is a schematic view of a stack of a semiconductor layer, a first gate layer and a second gate layer in an embodiment of the present disclosure
  • 17 is a schematic diagram of a stack of a semiconductor layer, a first gate layer, a second gate layer and a first metal layer in an embodiment of the present disclosure
  • FIG. 18 is a schematic diagram of a stack of a semiconductor layer, a first gate layer, a second gate layer, a first metal layer, and a first flat layer in an embodiment of the present disclosure
  • FIG. 19 is a schematic diagram of a stack of semiconductor layers, a first gate layer, a second gate layer, a first metal layer, a first planar layer and a transparent wiring in an embodiment of the present disclosure
  • 20 is a schematic diagram of a stack of a semiconductor layer, a first gate layer, a second gate layer, a first metal layer, a first planar layer, a transparent trace and a second planar layer in an embodiment of the present disclosure
  • 21 is a schematic diagram of a stack of a semiconductor layer, a first gate layer, a second gate layer, a first metal layer, a first planar layer, a transparent trace, a second planar layer and an anode in an embodiment of the present disclosure
  • 22 is a stack of a semiconductor layer, a first gate layer, a second gate layer, a first metal layer, a first planar layer, a transparent trace, a second planar layer, an anode, and a pixel definition layer in an embodiment of the present disclosure layer diagram;
  • FIG. 23 is a schematic diagram of a pixel structure of a light-transmitting region in an embodiment of the present disclosure.
  • the present disclosure provides a display panel.
  • the display panel includes a substrate, and the substrate includes a display area 10.
  • the display area 10 includes a plurality of pixel units.
  • the specific structure of the display area 10 please refer to The setting of the display area 10 of the display panel in the related art will not be repeated here.
  • the substrate further includes a functional area, and the functional area includes a light-transmitting area 11 , and the light-transmitting area 11 has higher transparency relative to the display area 10 , so that other components are arranged corresponding to the light-transmitting area 11 .
  • the light-transmitting area 11 may be provided with an under-screen camera.
  • the light-transmitting area 11 is set to be circular or substantially circular to suit the shape of the camera. Since the light-transmitting region 11 has higher transparency, it is helpful to improve the imaging effect.
  • the application range of the light-transmitting area 11 is not limited to this, for example, it can also be applied to a transparent display device, etc., which is not further limited here.
  • the light-transmitting area 11 includes a plurality of pixel units.
  • the pixel units can emit white light.
  • Each pixel unit includes at least one sub-pixel. Please continue to refer to FIG. 1.
  • Each pixel unit also includes a cathode 101. The projections are separated from each other.
  • the display panel further includes a connection structure 101A.
  • the connection structure 101A The cathodes 101 are arranged in the same layer, and different cathodes 101 are connected through the connection structure 101A.
  • the light-emitting unit of the sub-pixel includes a cathode 101, a light-emitting layer, and an anode 102 that are stacked in sequence. More specifically, along the direction from the anode 102 to the cathode 101, the anode 102 and the cathode 101 may include holes that are stacked in sequence. Injection layer, hole transport layer, light emitting layer, electron transport layer and electron injection layer. In some of the embodiments, an electron blocking layer may also be provided between the hole transport layer and the light-emitting layer, and a hole blocking layer may be further provided between the light-emitting layer and the electron transport layer. It should be understood that, under normal circumstances, in order to ensure the display effect, the injected electrons are excessive, and generally, an electron blocking layer needs to be provided, and the hole blocking layer can be omitted.
  • the cathode 101 of the light-emitting unit is usually a whole-surface structure.
  • the anode 102 of the light-emitting unit is patterned, while the cathode 101 of the light-emitting unit is a whole-surface structure.
  • the cathode 101 is not patterned , the cathode 101 not only covers the anode 102, but also covers the area outside the anode 102, and the entire cathode 101 has a certain shielding effect on light, which affects the light transmittance of the structure.
  • the cathode layer is composed of a plurality of independent cathodes 101 obtained by patterning.
  • the black filled figure represents the cathode 101 and the anode 102, that is, the cathode 101 covers the area where the anode 102 is located, and other cathode materials are removed to a certain extent to reduce the occlusion of light and improve the transparency of the light-transmitting area 11, as shown in Figure 10,
  • the cathodes 101 are electrically connected through the connection structure 101A, so as to provide the same common voltage to form a common electrode.
  • the orthographic projection of the effective light-emitting region of each sub-pixel in the light-transmitting region 11 on the substrate to be located within the range of the orthographic projection of the cathode 101 of the corresponding pixel unit on the substrate, it is possible to avoid light emission The normal operation of the unit is affected.
  • the cathode layer is composed of a plurality of cathodes 101, in other areas, because there is no cathode material, the opening area of the cathode 101 layer in the light-transmitting area 11 is increased, which is helpful to improve the The transparency of the light-transmitting area 11 .
  • the orthographic projection of the edge of the cathode 101 on the substrate is separated from the orthographic projection of the effective light-emitting area of the corresponding sub-pixel on the substrate, and the edge of the cathode 101 and the anode 102 of the corresponding sub-pixel are on the substrate
  • the orthographic projections overlap to avoid occupying more space. In this way, under the condition of ensuring the display effect, it is helpful to increase the opening area of the cathode 101 and improve the light transmittance.
  • the orthographic projection of the anode 102 of the sub-pixel included in the pixel unit on the substrate is located within the orthographic projection of the cathode 101 of the pixel unit on the substrate, which can be understood as a plurality of sub-pixels in each pixel unit Corresponding to the same cathode 101, the positions of the sub-pixels of the same pixel unit are relatively close, which helps to increase the opening area of the cathode 101 and improve the light transmittance.
  • the sub-pixels of each pixel can be arranged in different ways.
  • the anodes 102 of the sub-pixels are arranged in different ways.
  • each pixel unit The cathode 101 of each sub-pixel is the effective light-emitting area of the pixel, which improves the applicability to different types of display substrates.
  • the orthographic projection of the edge of the anode 102 on the substrate partially coincides with the edge of the corresponding orthographic projection of the cathode 101 on the substrate.
  • the edge of 101 has an overlapping area, which can reduce the area of the cathode 101 as much as possible, which is helpful to increase the area of the opening area corresponding to the cathode 101 and improve the light transmittance.
  • the orthographic projection of the edge of the cathode 101 on the substrate extends along a straight line in a region outside the region where the orthographic projection of the anode 102 on the substrate coincides with the corresponding orthographic projection of the cathode 101 on the substrate.
  • a part of the edge of the cathode 101 extends along the edge of the anode 102, and another part of the edge extends along a straight line, so as to reduce the area of the cathode 101 and improve the light transmittance of the display substrate.
  • the edge of the cathode 101 is chamfered, and the chamfer of the edge of the cathode 101 is greater than 30 degrees.
  • some positions of the anode 102 may have sharp corners. If the cathode 101 completely extends along the edge of the anode 102 in this area, a sharp corner structure will also be formed. , at the position where the edge of the cathode 101 and the edge of the anode 102 are separated, the cathode 101 may also have sharp corners.
  • the edge of the cathode 101 is inverted. Angle treatment to reduce the possibility of light diffraction.
  • the edge chamfer of the cathode 101 is greater than 30 degrees, which can reduce the possible light diffraction phenomenon.
  • the plurality of cathodes 101 and the connection structure 101A in the light-transmitting region 11 form a mesh structure, and the mesh structure includes a plurality of openings, and each opening is surrounded by the cathodes 101 and the connection structure 101A In this way, the opening area of the light-transmitting region 11 can be increased, thereby improving the light transmittance of the light-transmitting region 11.
  • the cathode 101 and the connection structure 101A are made of the same material, which helps to reduce the cathode 101 and the connection structure. The contact resistance between 101A improves the luminous efficiency.
  • the orthographic projection of the cathode 101 on the substrate and the orthographic projection of the anode 102 on the substrate completely overlap, and correspondingly, the edges thereof also completely overlap.
  • the cathode 101 The number and position of the anodes 102 are in a one-to-one correspondence, and their shapes and sizes are also the same. In this way, the opening area corresponding to the cathodes 101 can be maximized and the light transmittance of the display substrate can be improved.
  • the cathodes 101 corresponding to each anode 102 can also be connected through the connection structure 101A to provide a common voltage.
  • a plurality of cathodes 101 are arranged along a first direction to form a row of cathodes 101 , and a plurality of rows of cathodes 101 are arranged along a second direction.
  • the first direction and the second direction One of them may be the extension direction of the scan lines in the display panel, and the other may be the extension direction of the data lines in the display panel.
  • the first direction is the horizontal direction shown in FIG. 1
  • the second direction is the horizontal direction shown in FIG. is the longitudinal direction shown in Figure 1.
  • the angle between the first direction and the second direction is 80-100 degrees, and two adjacent rows of cathodes 101 are staggered in the first direction. It can be understood that the positions of two adjacent rows of cathodes 101 along the second direction are not aligned It is helpful to increase the number of cathodes 101 in a unit area, improve space utilization, and thus improve the resolution of the display panel.
  • the functional area further includes a transition area 12 and a pixel circuit area 13 , the pixel circuit area 13 is arranged around the light-transmitting area 11 , and the transition area 12 is arranged between the pixel circuit area 13 and the light-transmitting area 13 .
  • the transition region 12 and the pixel circuit region 13 share a cathode 101, and the portion of the cathode 101 in the orthographic projection of the substrate on the transition region 12 and the pixel circuit region 13 is a solid figure. Graphical whole surface structure.
  • the transition area 12 is substantially annular and surrounds the light-transmitting area 11
  • the inner contour of the pixel circuit area 13 is circular
  • the outer contour is an irregular pattern
  • the pixel circuit area 13 surrounds the transition District 12. It should be understood that the edges of the transition region 12 and the pixel circuit region 13 in this embodiment are only used to illustrate the approximate boundary positions between the regions, not the actual boundary structure.
  • the display substrate further includes a semiconductor layer 201, and in the transition region 12, the semiconductor layer 201 includes a plurality of redundant patterns 201A (dummy), and the redundant patterns 201A are arranged at intervals and arranged in an array.
  • a plurality of redundant patterns 201A are further provided, and the redundant patterns 201A are used to assist positioning, so as to assist in improving the accuracy of the exposure positions of the traces.
  • the display panel further includes a plurality of arc-shaped windings 202 , the windings 202 extend along the edge of the light-transmitting area 11 , and the windings 202 pass through the The traces are connected to the pixel circuits located in the pixel circuit region 13 .
  • the light-transmitting area 11 in this embodiment is not provided with a driving circuit, the driving circuits of the pixel units in the light-transmitting area 11 are all arranged in the pixel circuit area 13, and the driving circuits in the pixel circuit area 13 pass through the transition area 12.
  • the traces are connected to the light-emitting units located in the light-transmitting area 11 , which helps to further improve the transparency of the light-transmitting area 11 .
  • the above-mentioned wiring includes a first patch cord 203 and a second patch cord 204 .
  • the display substrate further includes a first gate layer located between the semiconductor layer 201 and the anode 102 layer, and the first gate layer includes a plurality of first turns located in the transition region 12 .
  • Wiring 203, the size of the first patch cord 203 in the second direction is larger than the size in the first direction, a plurality of first patch cords 203 are arranged along the first direction and are parallel to each other, and the first patch cords 203 are arranged on the substrate.
  • the orthographic projection is separate from the orthographic projection of the redundant pattern 201 on the substrate.
  • the first transition wires 203 are located between two adjacent columns of redundant patterns 201 along the second direction, which helps to improve the uniformity of the structure thickness at different positions of the display panel.
  • a second gate layer is further included between the first gate layer and the anode 102 layer, and the second gate layer includes a plurality of second turns located in the transition region 12 .
  • the wiring 204, the second wiring 204 extends along the second direction, the orthographic projection of the second wiring 204 on the substrate and the orthographic projection of the redundant pattern 201 on the substrate, the positive projection of the first wiring 203 on the substrate The projections are all phase-separated.
  • the second patch cords 204 in this embodiment are also arranged between two adjacent columns of redundant patterns 201 along the second direction, and the first patch cords 204 are arranged in the second direction.
  • the wiring 203 and the second transition wiring 204 are located between the redundant patterns 201 in different columns, which helps to improve the uniformity of the thickness of different regions of the display panel.
  • the ratio between the distance between the two adjacent first transition lines 203 and the distance between the two adjacent second transition lines 204 is 0.8-1.2, which helps to further improve the uniformity of the thickness of different regions of the display substrate.
  • the dotted lines in FIG. 15 represent the second patch cords 204 only for indicating the position of the second patch cords 204 , and do not represent the actual structure of the second patch cords 204 .
  • first patch cord 203 and second patch cord 204 are mainly used to realize the electrical connection of the pixel circuit. It should be understood that due to the existence of the light-transmitting area 11, the pixel circuit is spaced in the second direction, as shown in Figure 14 and As shown in FIG. 15 , both ends of the first patch cord 203 and the second patch cord 204 are connected to the winding 202 respectively, and the other end is connected to the pixel circuit.
  • the other side of the light-transmitting area 11 is also provided with a Correspondingly connect the first patch cord 203 and the second patch cord 204 with the winding 202 , in this way, the electrical connection of the pixel circuits located on the opposite sides of the light-transmitting area 11 is realized, and at the same time, wiring is avoided in the light-transmitting area 11 , It is helpful to further improve the transparency of the light-transmitting area 11 .
  • an interlayer insulating layer is further included between the second gate layer and the anode 102 layer, and in the transition region 12 , the interlayer insulating layer includes a plurality of via holes 205 , each via hole 205 is in a lining
  • the orthographic projection on the bottom overlaps the orthographic projection of one redundant pattern 201 on the substrate.
  • a first metal layer is further included between the interlayer insulating layer and the anode 102 layer, and in the transition region 12, the first metal layer includes a plurality of third transition wires 206,
  • the size of the third patch wire 206 in the first direction is larger than the size in the second direction, and the angle between the orthographic projection of the third patch wire 206 on the substrate and the orthographic projection of the first patch wire 206 on the substrate is At 80-100 degrees, the orthographic projection of the third patch 206 on the substrate is separated from the orthographic projection of the redundant pattern 201 on the substrate.
  • the third patch cord 206 is used to realize the connection of the pixel circuits in the first direction.
  • the third patch cord 206 in this embodiment is located between two adjacent rows of redundant patterns 201 along the first direction, which is helpful for Improve the uniformity of display panel thickness.
  • a first flat layer (not marked) may be provided as required.
  • a transparent wire layer is further included between the first metal layer and the anode 102 , and the transparent wire layer includes a transparent wire 207 extending along the first direction and a first redundant wire The wire 208, the transparent wire 207 and the first redundant wire 208 are separated, and the transparent wire layer further includes a plurality of second redundant wires 209 extending along the second direction.
  • each anode 102 is connected to a transparent wire 207 through an anode hole, and the transparent wire 207 is connected to the pixel circuit disposed in the pixel circuit area 13 .
  • the first redundant wire 208 is connected to the second redundant wiring 209 .
  • the first redundant wirings 208 and the second redundant wirings 209 in this embodiment are used to balance the thicknesses of different regions of the display panel, improve the uniformity of the thicknesses of different structures, and help improve the display effect.
  • the display substrate further includes a second flat layer (not marked), so as to improve the flatness of the anode 102 to be fabricated subsequently.
  • the anode 102 is disposed on the side of the second flat layer away from the substrate, and the anode 102 is connected to a transparent wire 207 through the anode hole.
  • a pixel defining layer (not marked) is further provided to define the range of the effective light-emitting area of each pixel.
  • each pixel unit includes a plurality of sub-pixels, and the anodes of the plurality of sub-pixels are separated from each other in the orthographic projection of the substrate.
  • each pixel unit corresponds to The sub-pixels include two green sub-pixels G, one red sub-pixel R and one blue sub-pixel B, the two green sub-pixels G are arranged along the second direction, and the effective light-emitting area of the blue sub-pixel B is located in the second direction. between the effective light-emitting regions of the two green sub-pixels G.
  • the pixel unit in this embodiment includes four sub-pixels, which, for example, may be RGGB (red, green, green, blue) sub-pixels, respectively.
  • the edges of the anode 102 and the edges of the cathodes 101 of the four sub-pixels all have overlapping regions.
  • the center lines of the effective light-emitting regions of the two green sub-pixels G in the second direction are substantially coincident, and the effective light-emitting regions of the blue sub-pixel B and the red sub-pixel R are located on the same side of the center line.
  • the distances from the effective light-emitting area of the blue sub-pixel B to the effective light-emitting areas of the two green sub-pixels G are approximately equal, and the effective light-emitting area of the red sub-pixel R is in the first direction from the blue sub-pixel B.
  • the effective light-emitting areas of the red sub-pixels R do not overlap, and the effective light-emitting areas of the red sub-pixels R overlap the effective light-emitting areas of a green sub-pixel G in the first direction.
  • the effective light-emitting area of the red sub-pixel R is located on the side of the effective light-emitting area of the blue sub-pixel B away from the green sub-pixel G, and some of the anode holes of the blue sub-pixel B are located in the effective light-emitting area of the blue sub-pixel B.
  • the light-emitting region is on one side of the second direction, and the anode holes of some blue sub-pixels B are on the other side.
  • the anode hole of the blue subpixel B is located on the left, and for the pixel unit in the lower right corner, the anode hole of the blue subpixel B is located on the right.
  • An embodiment of the present disclosure provides a method for fabricating a display panel, which is used for fabricating the display panel described in any one of the above.
  • the method includes a step of forming a cathode 101, and the step of forming the cathode 101 includes:
  • the cathode material layer is patterned by laser etching to form a cathode layer, and a plasma air knife is further used to remove residual particles to ensure the quality of the formed cathode pattern.
  • the shape of the orthographic projection of the cathode 101 on the substrate is an asymmetrical figure.
  • the patterning of the cathode 101 can be achieved by pre-shielding an Open mask or an FMM mask (Fine Metal Mask).
  • the formed cathode 101 pattern must be a symmetrical structure, resulting in a reduction in the aperture ratio.
  • the related process requires the use of special cathode materials, and the single-layer transmittance is low, which will also increase the diffraction of light.
  • the cathode 101 is obtained by patterning by laser etching, and the obtained cathode 101 has an asymmetric structure.
  • the asymmetric structure helps to reduce light diffraction and helps to increase the aperture. rate, that is, to increase the transmittance of light.
  • laser etching and patterning can be realized on the basis of conventional cathode 101 materials.
  • conventional cathode 101 materials such as MgAg (magnesium-silver alloy) can be selected, which also helps to control costs.
  • the pixel definition layer can be used as a buffer to reduce the possible influence of the heat generated during the etching process.
  • the step of patterning the cathode material layer by burning the cathode material layer with a laser includes:
  • the cathode material layer is burned with a laser, and the cathode material layer is patterned to form an image of the cathode.
  • the laser etching equipment is used to capture the alignment mark first, and then according to the relative position of the alignment mark and the cathode in the preset drawing, the cathode other than the cathode is The material layer is fired, and the remaining cathode material layer forms a patterned cathode pattern at a designated position.
  • the aperture ratio of the opening area of the other structures is m
  • the aperture ratio of the opening area corresponding to the cathode 101 is n
  • the opening area corresponding to the cathode 101 is located within the opening area of the other structures
  • the light transmittance of the cathode 101 is x.
  • the transmittance without light-blocking layer is C.
  • Tr.1 C*[m*x]
  • Tr.2 C*[(m-n)*x+n* 1].
  • Tr.1 and Tr.2 are the corresponding light transmittances.
  • Tr.2/Tr.1 is approximately equal to 1.77. It can be seen that the light transmittance of the display substrate is The pass rate increased significantly.
  • connection structure 101A and the cathode 101 may be provided in the same layer and material. Specifically, it may be formed at the same time when the cathode 101 is obtained by patterning the material layer of the cathode 101, that is, the cathode 101 and the connection structure 101A pass through once The production of the patterning process helps to save the production cost and production process.
  • the decrease in the transmittance of light of the display substrate may also lead to aggravation of the diffraction of light, which affects the display effect and the imaging effect of the under-screen camera.
  • the cathodes 101 are electrically connected through a connection structure 101A, and the connection structure 101A and the cathodes 101 are formed through different patterning processes respectively.
  • connection structure 101A between the cathodes 101 is a transparent conductive connection structure 101A, and the transparent conductive connection structure 101A is fabricated separately. That is to say, in this embodiment, a patterning process is required to form an independent and insulated cathode 101, and the A single patterning process forms the transparent conductive connection structure 101A connecting the cathode 101 .
  • the material of the transparent conductive connection structure 101A can be a material with high transparency such as ITO (indium tin oxide).
  • ITO indium tin oxide
  • the electrical connection between the cathodes 101 can be realized through the transparent conductive connection structure 101A, which can further improve the light transmittance of the display substrate.
  • the present disclosure also provides a display device.
  • the display device includes the display panel of any one of the above display panel embodiments, and the light-transmitting area 11 is provided with a camera.
  • the display device of the present embodiment includes all the technical solutions of the above-mentioned display panel embodiments, at least all the above-mentioned technical effects can be achieved, which will not be repeated here.

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Abstract

本公开提供一种显示面板、显示装置和显示面板的制作方法。一种显示面板，包括衬底，所述衬底包括显示区和功能区，所述功能区包括透光区，所述透光区包括多个像素单元，所述像素单元能够发出白光，每一所述像素单元包括至少一个子像素，每一所述像素单元还包括阴极，多个阴极在所述衬底的正投影相互分离，每一所述子像素的有效发光区在所述衬底上的正投影位于对应的像素单元的阴极在所述衬底的正投影的范围内，所述显示面板还包括连接结构，所述连接结构与所述阴极同层设置，不同的阴极通过所述连接结构连接。提高了阴极层位于该透光区的开口面积，有助于提高该透光区的透明度。

Description

一种显示面板、显示装置和显示面板的制作方法 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示装置和显示面板的制作方法。
背景技术
OLED(Organic light-emitting diode，有机发光二极管)显示技术具有亮度高、功耗低、响应快、清晰度高等优点，随着OLED(Organic light-emitting diode，有机发光二极管)显示技术的发展和成熟，OLED显示装置越来越受到用户的欢迎。
发明内容
第一方面，本公开实施例提供了一种显示面板，包括衬底，所述衬底包括显示区和功能区，所述功能区包括透光区，所述透光区包括多个像素单元，所述像素单元能够发出白光，每一所述像素单元包括至少一个子像素，每一所述像素单元还包括阴极，多个阴极在所述衬底的正投影相互分离，每一所述子像素的有效发光区在所述衬底上的正投影位于对应的像素单元的阴极在所述衬底的正投影的范围内，所述显示面板还包括连接结构，所述连接结构与所述阴极同层设置，不同的阴极通过所述连接结构连接。
可选的，所述阴极的边缘在所述衬底上的正投影与对应子像素的有效发光区在所述衬底上的正投影分离，且所述阴极的边缘与对应的子像素的阳极在衬底的正投影交叠。
可选的，所述像素单元包括的子像素的阳极在所述衬底上的正投影位于所述像素单元的阴极在所述衬底上的正投影内。
可选的，所述阳极的边缘在所述衬底上的正投影与相对应的阴极在所述衬底上的正投影的边缘部分重合。
可选的，在所述阳极在所述衬底上的正投影与相对应的阴极在所述衬底上的正投影重合区域之外的区域，所述阴极边缘在所述衬底上的正投影沿直 线延伸。
可选的，所述阴极的边缘均进行倒角处理，所述阴极的边缘倒角大于30度。
可选的，所述透光区的多个阴极和连接结构构成网状结构，所述网状结构包括多个开口，每个所述开口由所述阴极和所述连接结构围成，所述阴极和所述连接结构的材料相同。
可选的，所述多个阴极沿第一方向排列构成阴极行，多行阴极行沿第二方向排列，第一方向与第二方向的夹角为80-100度，相邻两个阴极行在所述第一方向上错位设置。
可选的，所述功能区还包括过渡区和像素电路区，所述像素电路区设置于透光区周围，过渡区设置于像素电路区和透光区之间，所述过渡区和所述像素电路区共用一个阴极，所述阴极在衬底的正投影在所述过渡区和所述像素电路区的部分为实心图形。
可选的，所述显示面板还包括多条弧形的绕线，所述绕线沿所述透光区的边缘延伸，所述绕线通过位于过渡区的走线与位于所述像素电路区的像素电路连接。
可选的，还包括半导体层，在所述过渡区，所述半导体层包括多个冗余图案，所述冗余图案间隔设置且呈阵列排布。
可选的，还包括位于所述半导体层和阳极层之间的第一栅极层，所述第一栅极层包括位于所述过渡区的多条第一转接线，所述第一转接线在所述第二方向的上尺寸大于在所述第一方向上的尺寸，多条所述第一转接线沿所述第一方向排列且相互平行，所述第一转接线在所述衬底上的正投影与所述冗余图案在所述衬底上的正投影相分离。
可选的，还包括位于所述第一栅极层和所述阳极层之间的第二栅极层，所述第二栅极层包括位于所述过渡区的多条第二转接线，所述第二转接线在所述第二方向的上尺寸大于在所述第一方向的尺寸，所述第二转接线在所述衬底上的正投影与所述冗余图案在所述衬底上的正投影、所述第一转接线在所述衬底上的正投影均相分离，相邻两条第一转接线之间的距离与相邻两条第二转接线之间的距离之比为0.8-1.2。
可选的，还包括位于第二栅极层和所述阳极层之间的层间绝缘层，在所述过渡区，所述层间绝缘层包括多个过孔，每个过孔在所述衬底上的正投影与一个所述冗余图案在所述衬底上的正投影交叠。
可选的，还包括位于所述层间绝缘层和所述阳极层之间的第一金属层，在所述过渡区，所述第一金属层包括多条第三转接线，所述第三转接线在所述第一方向上的尺寸大于在所述第二方向上的尺寸，所述第三转接线在所述衬底的正投影与所述第一转接线在所述衬底的正投影之间的夹角为80-100度，所述第三转接线在所述衬底上的正投影与所述冗余图案在所述衬底上的正投影相分离。
可选的，还包括位于所述第一金属层和所述阳极层之间的透明导线层，所述透明导线层包括沿所述第一方向延伸的透明走线和第一冗余走线，所述透明走线和所述第一冗余走线相分离，所述透明导线层还包括沿所述第二方向延伸的多条第二冗余走线。
可选的，每个阳极通过阳极孔与一条透明走线连接，透明走线与设置于像素电路区的像素电路连接，第一冗余走线和第二冗余走线连接。
可选的，每个像素单元对应的子像素包括两个绿色子像素、一个红色子像素和一个蓝色子像素，所述两个绿色子像素沿第二方向排列，所述蓝色子像素的有效发光区在第二方向上位于所述两个绿色子像素的有效发光区之间。
可选的，所述两个绿色子像素的有效发光区沿所述第二方向的中心线大致重合，所述蓝色子像素和所述红色子像素的有效发光区位于所述中心线的同一侧。
第二方面，本公开实施例提供了一种显示装置，包括第一方面中任一项所述的显示面板，所述透光区设置有摄像头。
第三方面，本公开实施例提供了一种显示面板的制作方法，用于制作第一方面中任一项所述的显示面板，所述方法包括形成阴极的步骤，所述形成阴极的步骤包括：
形成阴极材料层；
利用激光灼烧阴极材料层，使阴极材料层图形化；
利用等离子风刀去除阴极材料层的残留颗粒。
可选的，所述利用激光灼烧阴极材料层，使阴极材料层图形化，包括：
将包括阴极材料层的显示基板设置于激光刻蚀设备的加工平台；
利用所述激光刻蚀设备捕捉所述显示基板上的对位标记；
根据所述对位标记的位置和阴极的位置，利用激光灼烧阴极材料层，使所述阴极材料层图形化形成阴极的图像。
本公开实施例的透光区中的每一像素单元包括阴极，多个阴极在衬底的正投影相互分离，每一子像素的有效发光区在衬底上的正投影位于对应的像素单元的阴极在衬底的正投影的范围内，显示面板还包括连接结构，连接结构与阴极同层设置，不同的阴极通过连接结构连接。这样，本公开实施例提高了阴极层位于该透光区的开口面积，有助于提高该透光区的透明度。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获取其他的附图。
图1是本公开一实施例中显示基板的结构示意图；
图2是本公开一实施例中阳极和阴极的叠层示意图；
图3是本公开又一实施例中阳极和阴极的叠层示意图；
图4是本公开又一实施例中阳极和阴极的叠层示意图；
图5是本公开又一实施例中阳极和阴极的叠层示意图；
图6是本公开又一实施例中阳极和阴极的叠层示意图；
图7是本公开又一实施例中阳极和阴极的叠层示意图；
图8是本公开又一实施例中阳极和阴极的叠层示意图；
图9是本公开又一实施例中阳极和阴极的叠层示意图；
图10是本公开一实施例中阴极和连接结构的连接示意图；
图11是本公开又一实施例中阳极和阴极的叠层示意图；
图12是图11所示实施例中阴极和走线的连接示意图；
图13是本公开一实施例中半导体层的结构示意图；
图14是本公开一实施例中半导体层和第一栅极层的叠层示意图；
图15是本公开一实施例中半导体层、第一栅极层和第二栅极层的叠层示意图；
图16是本公开一实施例中半导体层、第一栅极层和第二栅极层的叠层示意图；
图17是本公开一实施例中半导体层、第一栅极层、第二栅极层和第一金属层的叠层示意图；
图18是本公开一实施例中半导体层、第一栅极层、第二栅极层和第一金属层、第一平坦层的叠层示意图；
图19是本公开一实施例中半导体层、第一栅极层、第二栅极层、第一金属层、第一平坦层和透明走线的叠层示意图；
图20是本公开一实施例中半导体层、第一栅极层、第二栅极层、第一金属层、第一平坦层、透明走线和第二平坦层的叠层示意图；
图21是本公开一实施例中半导体层、第一栅极层、第二栅极层、第一金属层、第一平坦层、透明走线、第二平坦层和阳极的叠层示意图；
图22是本公开一实施例中半导体层、第一栅极层、第二栅极层、第一金属层、第一平坦层、透明走线、第二平坦层、阳极和像素界定层的叠层示意图；
图23是本公开一实施例中透光区的像素结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本公开保护的范围。
本公开提供了一种显示面板。
如图1所示，在一个实施例中，该显示面板包括衬底，衬底包括显示区10，在其中一些实施例中，显示区10包括多个像素单元，显示区10的具体 结构可参考相关技术中显示面板的显示区10设置，此处不再赘述。
该衬底还包括功能区，该功能区包括透光区11，该透光区11相对于显示区10具有更高的透明度，以便对应该透光区11设置其他元器件。
示例性的，该透光区11可以设置屏下摄像头，相应的，本实施例中将透光区11设置为了圆形或大致为圆形，以适应摄像头的形状。由于透光区11具有更高的透明度，因此，有助于提高成像效果。显然，该透光区11的应用范围并不局限于此，例如，还可以应用于透明显示装置等，此处不做进一步限定。
透光区11包括多个像素单元，像素单元能够发出白光，每一像素单元包括至少一个子像素，请继续参阅图1，每一像素单元还包括阴极101，多个阴极101在衬底的正投影相互分离。
每一子像素的有效发光区在衬底上的正投影位于对应的像素单元的阴极101在衬底的正投影的范围内，如图10所示，显示面板还包括连接结构101A，连接结构101A与阴极101同层设置，不同的阴极101通过连接结构101A连接。
子像素的发光单元包括依次层叠设置的阴极101、发光层和阳极102，更为具体的，沿由阳极102到阴极101的方向上，阳极102和阴极101之间可以包括依次层叠设置的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层。在其中一些实施例中，空穴传输层和发光层之间还可以设置电子阻挡层，发光层和电子传输层之间还可以设置空穴阻挡层。应当理解的是，通常情况下，为了确保显示效果，所注入的电子是过量的，一般来说，需要设置电子阻挡层，而可以省略空穴阻挡层。
应当理解的是，发光单元的阴极101通常是整面的结构。请参阅图1，示例性的，在显示区10，发光单元的阳极102经过图形化，而发光单元的阴极101位整面的结构，换句话说，在显示区10，阴极101未经过图形化，阴极101不仅覆盖阳极102，还覆盖阳极102之外的区域，而整面的阴极101对于光线具有一定的遮挡效果，影响结构的光线的透过率。
本实施例中，在透光区11，阴极层是由经过图形化获得的多个独立的阴极101构成的，请继续参阅图1，在透光区11，黑色填充的图形代表阴极101 和阳极102的叠层结构，即阴极101覆盖阳极102所在的区域，其他的阴极材料被一定程度上的去除，以降低对于光线的遮挡，实现提高该透光区11的透明度，如图10所示，各阴极101之间通过连接结构101A电连接，从而提供相同的公共电压，以形成公共电极。
这样，本公开实施例通过控制透光区11中每一子像素的有效发光区在衬底上的正投影位于对应的像素单元的阴极101在衬底的正投影的范围内，避免了对发光单元的正常工作造成影响，同时，由于阴极层是由多个阴极101构成的，在其他区域由于不存在阴极的材料，提高了阴极101层位于该透光区11的开口面积，有助于提高该透光区11的透明度。
在其中一些实施例中，阴极101的边缘在衬底上的正投影与对应子像素的有效发光区在衬底上的正投影分离，阴极101的边缘与对应的子像素的阳极102在衬底的正投影交叠，避免了占用更多的空间，这样，在保证显示效果的情况下，有助于提高阴极101的开口面积，提高透光率。
在其中一些实施例中，像素单元包括的子像素的阳极102在衬底上的正投影位于像素单元的阴极101在衬底上的正投影内，可以理解为，每一像素单元的多个子像素对应同一阴极101设置，而同一像素单元的多个子像素之间的位置较为接近，有助于提高阴极101的开口面积，提高透光率。
如图2至图9所示，本实施例中，每一像素的子像素可以以不同的方式排列，相应的，子像素的阳极102以不同的方式排列，针对不同排列方式，每一像素单元的各子像素的阴极101该像素的有效发光区，提高了对于不同类型的显示基板的适用性。
在其中一些实施例中，阳极102的边缘在衬底上的正投影与相对应的阴极101在衬底上的正投影的边缘部分重合。
可以理解为，沿着垂直于衬底的方向观察，一个像素单元的阴极101的一部分边缘与该像素单元包括的子像素的阳极102的一部分边缘是重叠的。这样，由于阳极102在衬底上的正投影位于阴极101在衬底上的正投影的范围之内，能够保证电子的注入效果，不会对显示效果造成影响，同时，通过控制阳极102和阴极101的边缘存在重叠区域，能够尽可能的减少阴极101的面积，有助于提高阴极101对应的开口区域的面积，提高光线透过率。
在其中一些实施例中，在阳极102在衬底上的正投影与相对应的阴极101在衬底上的正投影重合区域之外的区域，阴极101边缘在衬底上的正投影沿直线延伸。
可以理解为，阴极101的一部分边缘沿着阳极102的边缘延伸，另一部分边缘沿着直线延伸，以减少阴极101的面积，提高显示基板的光线透过率。
在其中一些实施例中，阴极101的边缘均进行倒角处理，阴极101的边缘倒角大于30度。
如图2、图3、图7和图8所示，阳极102的某些位置可能存在尖角，阴极101如果在该区域完全沿着阳极102的边缘延伸，则同样会形成尖角结构，此外，在阴极101的边缘与阳极102的边缘相分离的位置，也可能使阴极101产生尖角。
相关技术人员在实现本公开的技术方案的过程中发现，尖角结构可能会加重光线的衍射，影响显示效果和屏下摄像头的成像效果，因此，本实施例中对于阴极101的边缘均进行倒角处理，以降低出现光线衍射的可能性。在其中一些实施例中，阴极101的边缘倒角大于30度，能够降低可能出现的光线衍射现象。
如图10所示，在其中一些实施例中，透光区11的多个阴极101和连接结构101A构成网状结构，网状结构包括多个开口，每个开口由阴极101和连接结构101A围成，能够提高透光区11的开口面积，从而提高该透光区11的透光率，在其中一些实施例中，阴极101和连接结构101A的材料相同，有助于降低阴极101和连接结构101A之间的接触电阻，提高发光效率。
如图11所示，在其中一些实施例中，阴极101在衬底上的正投影和阳极102在衬底上的正投影完全重叠，相应的，其边缘也完全重叠，可以理解为，阴极101和阳极102的数量和位置均是一一对应的，其形状和尺寸也均是相同的，这样，能够最大程度的提高阴极101对应的开口面积，提高显示基板的光线透过率。
如图12所示，与每一阳极102对应的阴极101也可以均通过连接结构101A相连，以提供公共电压。
如图1所示，在其中一些实施例中，多个阴极101沿第一方向排列构成 阴极101行，多行阴极101行沿第二方向排列，本实施例中，第一方向和第二方向中的一个可以是显示面板中扫描线的延伸方向，另一个可以是显示面板中数据线的延伸方向，示例性的，本实施例中，第一方向为图1中所示横向，第二方向为图1中所示纵向。第一方向与第二方向的夹角为80-100度，相邻两个阴极101行在第一方向上错位设置，可以理解为，相邻两行阴极101沿第二方向上的位置不是对齐的，有助于提高单位面积内的阴极101数量，提高空间利用率，从而提高显示面板的分辨率。
如图1所示，在其中一些实施例中，功能区还包括过渡区12和像素电路区13，像素电路区13设置于透光区11周围，过渡区12设置于像素电路区13和透光区11之间，过渡区12和像素电路区13共用一个阴极101，阴极101在衬底的正投影在过渡区12和像素电路区13的部分为实心图形，这里，实心图形指的是未经过图形化的整面结构。
如图1所示，本实施例中，过渡区12大致呈环形，且环绕透光区11，像素电路区13的内部轮廓为圆形，外部轮廓为不规则的图形，像素电路区13环绕过渡区12。应当理解的是，本实施例中过渡区12以及像素电路区13的边缘仅用于示例性说明各区域之间的大致界线位置，并非实际的分界结构。
请同时参阅图1和图13，在其中一些实施例中，该显示基板还包括半导体层201，在过渡区12，半导体层201包括多个冗余图案201A(dummy)，冗余图案201A间隔设置且呈阵列排布。本实施例中进一步设置了多个冗余图案201A，该冗余图案201A用于辅助定位，以辅助提高走线的曝光位置的准确程度。
请同时参阅图1和图14，在其中一些实施例中，显示面板还包括多条弧形的绕线202，绕线202沿透光区11的边缘延伸，绕线202通过位于过渡区12的走线与位于像素电路区13的像素电路连接。
可以理解为，本实施例中的透光区11未设置驱动电路，透光区11中的像素单元的驱动电路均设置于像素电路区13，像素电路区13中的驱动电路通过位于过渡区12的走线与位于透光区11中的发光单元连接，有助于进一步提高透光区11的透明度。
如图14和图15所示，上述走线包括第一转接线203和第二转接线204。
如图14所示，在其中一些实施例中，显示基板还包括位于半导体层201和阳极102层之间的第一栅极层，第一栅极层包括位于过渡区12的多条第一转接线203，第一转接线203在第二方向的上尺寸大于在第一方向上的尺寸，多条第一转接线203沿第一方向排列且相互平行，第一转接线203在衬底上的正投影与冗余图案201在衬底上的正投影相分离。
如图14所示，可以理解为，第一转接线203位于沿第二方向的相邻两列冗余图案201之间，这样，有助于提高显示面板不同位置结构厚度的均匀性。
如图15所示，在其中一些实施例中，还包括位于第一栅极层和阳极102层之间的第二栅极层，第二栅极层包括位于过渡区12的多条第二转接线204，第二转接线204沿第二方向延伸，第二转接线204在衬底上的正投影与冗余图案201在衬底上的正投影、第一转接线203在衬底上的正投影均相分离。
如图15所示，与第一转接线203的设置方式类似，本实施例中的第二转接线204同样设置于沿第二方向的相邻两列冗余图案201之间，且第一转接线203和第二转接线204位于不同列冗余图案201之间，有助于提高显示面板不同区域厚度的均匀程度。相邻两条第一转接线203之间的距离与相邻两条第二转接线204之间的距离之比为0.8-1.2，有助于进一步提高显示基板不同区域厚度的均匀程度。
应当理解的是，图15中用虚线表示第二转接线204仅用于区表明第二转接线204的位置，并不代表第二转接线204的实际结构。
上述第一转接线203和第二转接线204主要用于实现像素电路的电连接，应当理解的是，由于透光区11的存在，导致像素电路在第二方向上存在间隔，如图14和图15所示，第一转接线203和第二转接线204的两端分别与绕线202相连，另一端与像素电路相连，沿第二方向上，位于透光区11另一侧同样设置有与绕线202对应连接第一转接线203和第二转接线204，这样，实现了位于透光区11相对两侧的像素电路的电连接，同时，避免在透光区11内设置走线，有助于进一步提高透光区11的透明度。
在其中一些实施例中，还包括位于第二栅极层和阳极102层之间的层间绝缘层，在过渡区12，层间绝缘层包括多个过孔205，每个过孔205在衬底上的正投影与一个冗余图案201在衬底上的正投影交叠。通过控制层间绝缘 层的过孔205位置和冗余图案201的正投影交叠，有助于提高显示面板厚度的均匀性。
如图17所示，在其中一些实施例中，还包括位于层间绝缘层和阳极102层之间的第一金属层，在过渡区12，第一金属层包括多条第三转接线206，第三转接线206在第一方向上的尺寸大于在第二方向上的尺寸，第三转接线206在衬底的正投影与第一转接线206在衬底的正投影之间的夹角为80-100度，第三转接线206在衬底上的正投影与冗余图案201在衬底上的正投影相分离。与第一转接线203和第二转接线204的功能类似，第三转接线206用于实现像素电路在第一方向上的连接。
本实施例中，与第一转接线203和第二转接线204的设置方式类似，本实施例中第三转接线206位于沿第一方向相邻两行冗余图案201之间，有助于提高显示面板厚度的均匀性。
如图18所示，在第一金属层远离衬底的一侧，可以根据需要设置第一平坦层(未标识)。
如图19所示，在其中一些实施例中，还包括位于第一金属层和阳极102之间的透明导线层，透明导线层包括沿第一方向延伸的透明走线207和第一冗余走线208，透明走线207和第一冗余走线208相分离，透明导线层还包括沿第二方向延伸的多条第二冗余走线209。
如图19所示，在其中一些实施例中，每个阳极102通过阳极孔与一条透明走线207连接，透明走线207与设置于像素电路区13的像素电路连接，第一冗余走线208和第二冗余走线209连接。
本实施例中的第一冗余走线208和第二冗余走线209用于平衡显示面板不同区域的厚度，提高不同结构厚度的均匀性，有助于提高显示效果。
如图20所示，该显示基板还包括第二平坦层(未标识)，以提高后续制作的阳极102的平坦程度。
如图21所示，阳极102设置于第二平坦层远离衬底的一侧，阳极102通过阳极孔与一条透明走线207连接。
如图22所示，在阳极远离衬底的一侧，还设置有像素界定层(未标识)，以界定各像素的有效发光区的范围。
如图23所示，在其中一些实施例中，每个像素单元每个像素单元包括多个子像素，多个子像素的阳极在衬底的正投影相互分离，示例性的，每一像素单元对应的子像素包括两个绿色子像素G、一个红色子像素R和一个蓝色子像素B，两个绿色子像素G沿第二方向排列，蓝色子像素B的有效发光区在第二方向上位于两个绿色子像素G的有效发光区之间。
本实施例中的像素单元包括四个子像素，示例性的，可以分别是RGGB(红、绿、绿、蓝)子像素。阳极102的边缘和这四个子像素的阴极101的边缘均存在重叠区域。
在其中一些实施例中，两个绿色子像素G的有效发光区沿第二方向的中心线大致重合，蓝色子像素B和红色子像素R的有效发光区位于中心线的同一侧。
在第二方向上，蓝色子像素B的有效发光区到两个绿色子像素G的有效发光区的距离大致相等，红色子像素R的有效发光区在第一方向上与蓝色子像素B的有效发光区没有交叠，红色子像素R的有效发光区在第一方向上一个绿色子像素G的有效发光区有交叠。
在第二方向上，红色子像素R的有效发光区位于蓝色子像素B的有效发光区远离绿色子像素G的一侧，部分蓝色子像素B的阳极孔位于蓝色子像素B的有效发光区在第二方向的一侧，部分蓝色子像素B的阳极孔位于另一侧。
如图24所示，对于左上角的像素单元来说，蓝色子像素B的阳极孔位于左侧，而对于右下角的像素单元来说，蓝色子像素B的阳极孔位于右侧。
本公开实施例提供了一种显示面板的制作方法，用于制作以上任一项所述的显示面板，所述方法包括形成阴极101的步骤，所述形成阴极101的步骤包括：
形成阴极材料层；
利用激光灼烧阴极材料层，使阴极材料层图形化；
利用等离子风刀去除阴极材料层的残留颗粒。
本实施例中，通过激光刻蚀的方式将阴极材料层图形化，形成阴极层，并进一步利用等离子风刀去除残留颗粒，以确保形成的阴极图形的质量。
在其中一些实施例中，阴极101在衬底上的正投影的形状为非对称图形。
本公开的相关技术人员在实现本公开的技术方案的过程中发现，可以通过Open mask(开放式掩膜)或者FMM mask(精细金属掩模板)预先遮挡实现阴极101的图形化。然而受到所使用的张网的限制，形成的阴极101图形必须为对称结构，导致开口率降低，相关工艺需要使用特殊的阴极的材料，单层透过率较低，还会加重光线的衍射。
本实施例中，阴极101通过激光刻蚀图形化获得，且获得的阴极101为非对称结构，相对于对称的阴极101来说，非对称结构有助于降低光线衍射，且有助于提高开口率，也就是提高光线的透过率。此外，采用激光刻蚀图形化，可以在常规的阴极101材料的基础上实现，例如可以选择MgAg(镁银合金)等常规阴极101材料，也有助于控制成本。
应当理解的是，激光灼烧刻蚀会产生较多的热量，实施时，可以通过像素界定层作为缓冲，降低刻蚀过程中产生的热量可能造成的影响。
在其中一些实施例中，利用激光灼烧阴极材料层，使阴极材料层图形化的步骤，包括：
将包括阴极材料层的显示基板设置于激光刻蚀设备的加工平台；
利用所述激光刻蚀设备捕捉所述显示基板上的对位标记；
根据所述对位标记的位置和阴极的位置，利用激光灼烧阴极材料层，使所述阴极材料层图形化形成阴极的图像。
本实施例中，在阴极材料层图形化形成阴极的过程中，首先利用激光刻蚀设备捕捉对位标记，然后根据预设的图纸中对位标记和阴极的相对位置，对阴极之外的阴极材料层进行灼烧，剩余的阴极材料层在指定的位置形成图形化的阴极图形。
以其他结构的开口区域的开口率为m，阴极101对应的开口区域的开口率为n，且阴极101对应的开口区域位于其他结构的开口区域范围之内，阴极101的光线透过率为x，无挡光层透过率为C。
在阴极101未图形化时，光线透过率Tr.1＝C*[m*x]，当阴极101图形化之后，光线透过率Tr.2＝C*[(m-n)*x+n*1]。其中，Tr.1和Tr.2为相应的光线透过率。进一步可以得到Tr.2/Tr.1＝1+(1-x)n/(mx)。
在一个实施例中，示例性的，m＝92.35％，n＝86.78％，x＝55％为例，经过 计算，Tr.2/Tr.1约等于1.77，由此可见，显示基板的光线透过率显著增加。
在其中一些实施例中，连接结构101A可以与阴极101同层同材料设置，具体的，可以是在将阴极101材料层图形化获得阴极101的时候同时形成，即阴极101和连接结构101A通过一次构图工艺制作，有助于节约生产成本和生产工艺。
技术人员在实现本公开的技术方案的过程中发现，受到加工工艺等因素的影响，与阴极101同层同材料设置的连接结构101A的宽度需大于5微米，经过进一步研究发现，该方案会导致显示基板的光线的透过率降低，还可能导致光线的衍射加重，影响显示效果和屏下摄像头的成像效果。
在另外一些实施例中，各阴极101通过连接结构101A电连接，连接结构101A和阴极101分别通过不同的构图工艺形成。
本实施例中，阴极101之间的连接结构101A为透明导电连接结构101A，透明导电连接结构101A单独制作，也就是说，本实施例中需要一次构图工艺形成独立且绝缘的阴极101，还需要一次构图工艺形成连接阴极101的透明导电连接结构101A。
透明导电连接结构101A的材料可以选择ITO(氧化铟锡)等具有较高透明度的材料，通过透明导电连接结构101A实现阴极101之间的电连接，能够进一步提高显示基板的光线的透过率。
本公开还提供了一种显示装置。
在一个实施例中，该显示装置包括以上显示面板实施例中任一项的显示面板，透光区11设置有摄像头。
由于本实施例的显示装置包括上述显示面板实施例的全部技术方案，因此至少能实现上述全部技术效果，此处不再赘述。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (22)

  1. 一种显示面板，包括衬底，所述衬底包括显示区和功能区，所述功能区包括透光区，所述透光区包括多个像素单元，所述像素单元能够发出白光，每一所述像素单元包括至少一个子像素，每一所述像素单元还包括阴极，多个阴极在所述衬底的正投影相互分离，每一所述子像素的有效发光区在所述衬底上的正投影位于对应的像素单元的阴极在所述衬底的正投影的范围内，所述显示面板还包括连接结构，所述连接结构与所述阴极同层设置，不同的阴极通过所述连接结构连接。
  2. 根据权利要求1所述的显示面板，其中，所述阴极的边缘在所述衬底上的正投影与对应子像素的有效发光区在所述衬底上的正投影分离，且所述阴极的边缘与对应的子像素的阳极在衬底的正投影交叠。
  3. 根据权利要求1所述的显示面板，其中，所述像素单元包括的子像素的阳极在所述衬底上的正投影位于所述像素单元的阴极在所述衬底上的正投影内。
  4. 根据权利要求3所述的显示面板，其中，所述阳极的边缘在所述衬底上的正投影与相对应的阴极在所述衬底上的正投影的边缘部分重合。
  5. 根据权利要求4所述的显示面板，其中，在所述阳极在所述衬底上的正投影与相对应的阴极在所述衬底上的正投影重合区域之外的区域，所述阴极边缘在所述衬底上的正投影沿直线延伸。
  6. 根据权利要求5所述的显示面板，其中，所述阴极的边缘均进行倒角处理，所述阴极的边缘倒角大于30度。
  7. 根据权利要求1至6中任一项所述的显示面板，其中，所述透光区的多个阴极和连接结构构成网状结构，所述网状结构包括多个开口，每个所述开口由所述阴极和所述连接结构围成，所述阴极和所述连接结构的材料相同。
  8. 根据权利要求7所述的显示面板，其中，所述多个阴极沿第一方向排列构成阴极行，多行阴极行沿第二方向排列，第一方向与第二方向的夹角为80-100度，相邻两个阴极行在所述第一方向上错位设置。
  9. 根据权利要求8所述的显示面板，其中，所述功能区还包括过渡区和 像素电路区，所述像素电路区设置于透光区周围，过渡区设置于像素电路区和透光区之间，所述过渡区和所述像素电路区共用一个阴极，所述阴极在衬底的正投影在所述过渡区和所述像素电路区的部分为实心图形。
  10. 根据权利要求9所述的显示面板，其中，所述显示面板还包括多条弧形的绕线，所述绕线沿所述透光区的边缘延伸，所述绕线通过位于过渡区的走线与位于所述像素电路区的像素电路连接。
  11. 根据权利要求10所述的显示面板，其中，还包括半导体层，在所述过渡区，所述半导体层包括多个冗余图案，所述冗余图案间隔设置且呈阵列排布。
  12. 根据权利要求11所述的显示面板，其中，还包括位于所述半导体层和阳极层之间的第一栅极层，所述第一栅极层包括位于所述过渡区的多条第一转接线，所述第一转接线在所述第二方向的上尺寸大于在所述第一方向上的尺寸，多条所述第一转接线沿所述第一方向排列且相互平行，所述第一转接线在所述衬底上的正投影与所述冗余图案在所述衬底上的正投影相分离。
  13. 根据权利要求12所述的显示面板，其中，还包括位于所述第一栅极层和所述阳极层之间的第二栅极层，所述第二栅极层包括位于所述过渡区的多条第二转接线，所述第二转接线在所述第二方向的上尺寸大于在所述第一方向的尺寸，所述第二转接线在所述衬底上的正投影与所述冗余图案在所述衬底上的正投影、所述第一转接线在所述衬底上的正投影均相分离，相邻两条第一转接线之间的距离与相邻两条第二转接线之间的距离之比为0.8-1.2。
  14. 根据权利要求13所述的显示面板，其中，还包括位于第二栅极层和所述阳极层之间的层间绝缘层，在所述过渡区，所述层间绝缘层包括多个过孔，每个过孔在所述衬底上的正投影与一个所述冗余图案在所述衬底上的正投影交叠。
  15. 根据权利要求14所述的显示面板，其中，还包括位于所述层间绝缘层和所述阳极层之间的第一金属层，在所述过渡区，所述第一金属层包括多条第三转接线，所述第三转接线在所述第一方向上的尺寸大于在所述第二方向上的尺寸，所述第三转接线在所述衬底的正投影与所述第一转接线在所述衬底的正投影之间的夹角为80-100度，所述第三转接线在所述衬底上的正投 影与所述冗余图案在所述衬底上的正投影相分离。
  16. 根据权利要求15所述的显示面板，其中，还包括位于所述第一金属层和所述阳极层之间的透明导线层，所述透明导线层包括沿所述第一方向延伸的透明走线和第一冗余走线，所述透明走线和所述第一冗余走线相分离，所述透明导线层还包括沿所述第二方向延伸的多条第二冗余走线。
  17. 根据权利要求16所述的显示面板，其中，每个阳极通过阳极孔与一条透明走线连接，透明走线与设置于像素电路区的像素电路连接，第一冗余走线和第二冗余走线连接。
  18. 根据权利要求1所述的显示面板，其中，每个像素单元对应的子像素包括两个绿色子像素、一个红色子像素和一个蓝色子像素，所述两个绿色子像素沿第二方向排列，所述蓝色子像素的有效发光区在第二方向上位于所述两个绿色子像素的有效发光区之间。
  19. 根据权利要求18所述的显示面板，其中，所述两个绿色子像素的有效发光区沿所述第二方向的中心线大致重合，所述蓝色子像素和所述红色子像素的有效发光区位于所述中心线的同一侧。
  20. 一种显示装置，包括权利要求1至19中任一项所述的显示面板，所述透光区设置有摄像头。
  21. 一种显示面板的制作方法，用于制作权利要求1至19中任一项所述的显示面板，所述方法包括形成阴极的步骤，所述形成阴极的步骤包括：
    形成阴极材料层；
    利用激光灼烧阴极材料层，使阴极材料层图形化；
    利用等离子风刀去除阴极材料层的残留颗粒。
  22. 根据权利要求21所述的方法，其中，所述利用激光灼烧阴极材料层，使阴极材料层图形化，包括：
    将包括阴极材料层的显示基板设置于激光刻蚀设备的加工平台；
    利用所述激光刻蚀设备捕捉所述显示基板上的对位标记；
    根据所述对位标记的位置和阴极的位置，利用激光灼烧阴极材料层，使所述阴极材料层图形化形成阴极的图像。
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