WO2022170672A1 - 阵列基板、背光模组及显示面板 - Google Patents

阵列基板、背光模组及显示面板 Download PDF

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Publication number
WO2022170672A1
WO2022170672A1 PCT/CN2021/083842 CN2021083842W WO2022170672A1 WO 2022170672 A1 WO2022170672 A1 WO 2022170672A1 CN 2021083842 W CN2021083842 W CN 2021083842W WO 2022170672 A1 WO2022170672 A1 WO 2022170672A1
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WIPO (PCT)
Prior art keywords
conductive pads
conductive
wire
conductive pad
type
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Ceased
Application number
PCT/CN2021/083842
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English (en)
French (fr)
Inventor
赵斌
李艳
肖军城
李吉
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Priority to US17/289,301 priority Critical patent/US20240038946A1/en
Publication of WO2022170672A1 publication Critical patent/WO2022170672A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a backlight module and a display panel.
  • Micro-Light Emitting Diode has developed into one of the hot spots of future display technology, and the current liquid crystal display panel (Liquid Compared with Crystal Display (LCD) and Organic Light Emitting Diode (OLED) display devices, they have the advantages of fast response, high color gamut, high resolution, and low energy consumption, but they have many technical difficulties and complex technologies, especially It is its key technology mass transfer technology, light-emitting diode (Light Emitting Diode)
  • the miniaturization of Emitting Diode (LED) particles has become a technical bottleneck, and the sub-millimeter light-emitting diode (Mini-LED), as the product of the combination of Micro-LED and the backplane, has the characteristics of high contrast ratio and high color rendering performance comparable to OLED.
  • the cost of LCD is slightly higher, only about 60% of that of OLED, and it is easier to implement than OLED, so Mini-LED has become a hot spot for major panel manufacturers.
  • FIG. 1 it is a schematic plan view of a driver chip bound to a backplane and connected to a Mini-LED in a conventional technology.
  • Each driver chip 1 includes a first pin VCC, a second pin VSS, a third pin Di, a fourth pin Out and a fifth pin GND, and the backplane is provided with a first signal line 2, a second pin The signal line 3 , the third signal line 4 , the fourth signal line 5 and the power supply line 6 , wherein the first signal line 2 is electrically connected to the first pin VCC on each driver chip 1 to transmit the carrier signal to the The driver chip 1, the second signal line 3 is electrically connected to the second pin VSS on each driver chip 1, and the third signal line 4 is electrically connected to the third pins Di and The fourth pin Out is used to realize signal transmission between the two driver chips 1.
  • the fourth signal line 5 is electrically connected to the fifth pin GND in each driver chip 1 to input the ground signal, and one end of the LED is connected to The fourth pin Out, the other end of the LED is connected to the power line 6 , and the third signal line 4 and the second signal line 3 overlap.
  • the purpose of the present application is to provide an array substrate, a backlight module and a display panel to solve the problem of overlapping between signal lines electrically connected to a driving chip in the conventional technology.
  • a backlight module comprising:
  • a substrate comprising at least two first bonding regions
  • a first wire disposed on the substrate, and connected to at least two of the first conductive pads located in the first bonding area;
  • a second wire disposed on the substrate, and connected to the two second conductive pads respectively located in the two first bonding regions;
  • a driving chip connected to the first conductive pad and the second conductive pad of the first bonding area
  • the two second conductive pads connected by the second wires are located on the same side of the first wires.
  • a display panel comprising:
  • a substrate comprising at least two first bonding regions
  • a first wire disposed on the substrate, and connected to at least two of the first conductive pads located in the first bonding area;
  • a second wire disposed on the substrate, and connected to the two second conductive pads respectively located in the two first bonding regions;
  • a driving chip connected to the first conductive pad and the second conductive pad of the first bonding area
  • the two second conductive pads connected by the second wires are located on the same side of the first wires.
  • An array substrate comprising:
  • a substrate comprising at least two first bonding regions
  • a first wire disposed on the substrate, and connected to at least two of the first conductive pads located in the first bonding area;
  • a second wire disposed on the substrate, and connected to the two second conductive pads respectively located in the two first bonding areas;
  • the two second conductive pads connected by the second wires are located on the same side of the first wires.
  • the present application provides an array substrate, a backlight module and a display panel.
  • Two second conductive pads connected by second wires are located on the same side of the first wires to avoid overlapping between the first wires and the second wires.
  • the second wire, the second conductive pad connected to the second wire, the first wire, and the first conductive pad connected to the first wire are located in the same metal layer, which simplifies wiring and reduces the number of metal film layers, which is conducive to improving the Product yield and cost reduction.
  • FIG. 1 is a schematic plan view of a driver chip bound to a backplane and connected to a Mini-LED in a conventional technology
  • FIG. 2 is a schematic cross-sectional view of a backlight module according to a first embodiment of the present application
  • FIG. 3 is a first schematic plan view of the backlight module according to the first embodiment of the present application.
  • FIG. 4 is a first partially enlarged schematic view of the backlight module shown in FIG. 3;
  • FIG. 5 is a first schematic plan view of a backlight module according to a second embodiment of the present application.
  • FIG. 6 is a first partially enlarged schematic view of the backlight module shown in FIG. 5;
  • Fig. 7 is the second kind of partial enlarged schematic diagram of the backlight module shown in Fig. 5;
  • FIG. 8 is a first partially enlarged schematic diagram of a backlight module according to a third embodiment of the present application.
  • Fig. 9 is the second kind of partial enlarged schematic diagram of the backlight module shown in Fig. 3;
  • FIG. 10 is a partially enlarged schematic diagram of a backlight module according to a fourth embodiment of the present application.
  • FIG. 11 is a partially enlarged schematic diagram of a backlight module according to a fifth embodiment of the present application.
  • FIG. 12 is a partial enlarged schematic diagram of a backlight module according to a sixth embodiment of the present application.
  • FIG. 13 is a partial enlarged schematic diagram of a backlight module according to a seventh embodiment of the present application.
  • FIG. 14 is a partial enlarged schematic diagram of a backlight module according to an eighth embodiment of the present application.
  • FIG. 15 is a partial enlarged schematic diagram of a backlight module according to a ninth embodiment of the present application.
  • 16 is a partial enlarged schematic diagram of a backlight module according to a tenth embodiment of the present application.
  • 17 is a partial enlarged schematic diagram of a backlight module according to an eleventh embodiment of the present application.
  • FIG. 18 is a partial enlarged schematic diagram of a backlight module according to a twelfth embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of a backlight module according to a first embodiment of the present application
  • FIG. 3 is a first schematic plan view of the backlight module according to the first embodiment of the present application.
  • the backlight module 100 includes a substrate 10 , at least one first conductive pad 11, at least two second conductive pads 12, at least one third conductive pad 13, first wire 14, second wire 15, third wire 16, fourth wire 17, driver chip 18, The flexible printed circuit board 19 and the light emitting unit 20 .
  • the substrate 10 is a glass substrate. It can be understood that the substrate 10 can also be a flexible substrate.
  • the first conductive pad 11 , the second conductive pad 12 , the third conductive pad 13 , the first wire 14 , the second wire 15 , the third wire 16 and the fourth wire 17 are all disposed on the substrate 10 , and the first conductive pad 11 , the second conductive pad 12 , the third conductive pad 13 , the first wire 14 , the second wire 15 , the third wire 16 and the fourth wire 17 are all disposed on the same metal layer, and the metal layer is located on the substrate 10 to
  • the number of metal layers of the backlight module is reduced, the manufacturing process of the backlight module is simplified, and the manufacturing cost of the backlight module is reduced.
  • first conductive pad 11 , the second conductive pad 12 , the third conductive pad 13 , the first wire 14 , the second wire 15 , the third wire 16 and the fourth wire 17 can also be respectively disposed in two or on more than two metal layers.
  • the preparation material of the metal layer includes at least one of molybdenum, aluminum, titanium and copper.
  • the substrate 10 includes at least two first bonding regions 100a.
  • the substrate 10 includes a plurality of first bonding regions 100a, and the plurality of first bonding regions 100a are arranged in multiple rows and columns on the substrate 10, and a driving chip 18 is fixed to a first bonding region 100a.
  • driving The chips 18 are arranged in multiple rows and multiple columns.
  • the first bonding area 100a of the substrate 10 is provided with a first conductive pad 11, a second conductive pad 12, and a third conductive pad 13, and a driver chip 18 is connected to the first conductive pad 11 and the second conductive pad of the first bonding area 100a. on the pad 12 and the third conductive pad 13 .
  • the driving chip 18 includes first pins 181 corresponding to and connected to the first conductive pads 11 one-to-one, second pins 182 corresponding to and connected to the second conductive pads 12 one-to-one, and corresponding to the third conductive pads 13 one-to-one and connected Connect the third pin 183.
  • the driver chip 18 may further include redundant pins and test pins, the redundant pins are not connected to electrical signals, and the test pins are used to test whether the driver chip works normally and are not used for signal transmission. Between the first conductive pad 11 and the first pin 181, between the second conductive pad 12 and the second pin 182, and between the third conductive pad 13 and the third pin 183, solder paste, conductive glue, etc. connect. As shown in FIG.
  • the shape of the driving chip 18 is a rectangle, for example, the driving chip 18 is a square, and the orthographic projection of each driving chip 18 on the substrate 10 It includes a first parallel edge 18a parallel to the extending direction of the first wire 14, a second parallel edge 18b parallel to the extending direction of the first wire 14, a first vertical edge 18c and a second vertical edge 18d.
  • the two parallel edges 18b are opposite, the first vertical edge 18c is opposite to the second vertical edge 18d, the first vertical edge 18c is vertical to the first parallel edge 18a, and the second vertical edge 18d is vertical to the first parallel edge 18a.
  • the driving chip 18 may also be an irregular pattern.
  • the substrate 10 includes a second bonding area 100b, and the second bonding area 100b is located on one side of the first bonding area 100a.
  • the light-emitting units 20 are fixed on the second bonding area 100b, and each light-emitting unit 20 includes multiple rows of light-emitting devices 201 connected in series.
  • 201 is a sub-millimeter light emitting diode (Mini-LED).
  • Mini-LED sub-millimeter light emitting diode
  • One end of the light emitting unit 20 is electrically connected to the driving chip 18 through the third wire 16 , and the other end of the light emitting unit 20 is connected to the fourth wire 17 , and the fourth wire 17 is a power line.
  • the light emitting device 201 can also be a micro light emitting diode (Micro-LED).
  • the flexible printed circuit board 19 is fixed on the substrate 10 , and the flexible printed circuit board 19 is electrically connected to the first wire 14 , the second wire 15 and the fourth wire 17 to respectively Corresponding electrical signals are input to the first wire 14 , the second wire 15 and the fourth wire 17 .
  • the flexible printed circuit board 19 is disposed at one end of the substrate 10 and is located on the same surface of the substrate 10 as the first wires 14 and the like.
  • the first wire 14 extends to the area where the flexible printed circuit board 19 is fixed; the fifth wire 15I is connected between the first driving chip 18 and the flexible printed circuit board 19 close to the flexible printed circuit board 19, and the flexible printed circuit board
  • the signal output by 19 is output to the driving chip 18 , and then two adjacent driving chips 18 are connected through the second wire 15 to realize signal transmission between the driving chips 18 .
  • One end of the fourth wire 17 extends to the position of the flexible printed circuit board 19 and is electrically connected with the flexible printed circuit board 19 .
  • the flexible printed circuit board 19 can also be fixed on the back surface of the substrate 10 provided with the first conductors 14 , and there can also be multiple flexible printed circuit boards 19 , and each flexible printed circuit board 19 is connected to the first conductor 14 in a partial area. , the second wire 15 and the fourth wire 17 are electrically connected, and the flexible printed circuit board 19 can also be fixed on the opposite ends of the substrate 10 .
  • the first wires 14 are used to transmit the same signal to the first conductive pads 11 that transmit the same signal in the at least two first bonding regions 100 a , and the first wires connected to the first conductive pads 11 pass through the first conductive pads 11 .
  • the pin 181 is input to the inside of the driver chip 18 .
  • the first wires 14 are connected to at least two first conductive pads 11 located in the first bonding area 100a.
  • Each first bonding area 100a is provided with a first conductive pad 11 that transmits the same signal, and at least one first conductive pad 11 located in each first bonding area 100a is connected to at least one first wire 14 in a one-to-one correspondence, that is, each The first conductive pad 11 is only connected to one first wire 14 that transmits its corresponding signal.
  • each first bonding area 100a may also be provided with two or more first conductive pads 11 that transmit the same signal.
  • the first wires 14 are straight wires and extend in the column direction.
  • the second wires 15 are used to transmit signals required for addressing of each driver chip 18 , and are also used to output signals required for the operation of the driver chips 18 .
  • the second wires 15 are connected to the two second conductive pads 12 respectively located in the two first bonding regions 100 a , so that the signal can be cascaded between the two driving chips 18 .
  • Each first bonding region 100a is provided with at least two second conductive pads 12, and one second conductive pad 12 of one first bonding region 100a and one second conductive pad 12 corresponding to another first bonding region 100a pass through the second The wires 15 are connected, one second conductive pad 12 outputs the signal from one driver chip 18 to the other driver chip 18, and the other second conductive pad 12 inputs the signal output from one driver chip 18 to the other driver chip 18, namely
  • the at least two second conductive pads 12 include a first type of second conductive pads and a second type of second conductive pads, the first type of second conductive pads output signals from the driver chip 18, and the second type of second conductive pads to output signals. Received to the driver chip 18 .
  • the second conductive pads 15 connected to the two second conductive pads 12 and the second conductive pads 12 connected to the second conductive pads 15 constitute a set of staging units, and a staging transmission is transmitted between the two driving chips 18 Signals, multiple groups of staging units can be used to transmit a variety of different staging signals.
  • the second wires 15 extend in the column direction, that is, the first wires 14 and the second wires 15 extend in the same direction.
  • the second wire 15 is straight and parallel to the first wire 14 .
  • each first bonding area 100a at least one second conductive pad 12 connected to the second wire 15 and at most one first conductive pad 11 are disposed along the second parallel edge 18b; and/or , in each first bonding area 100a, at least one second conductive pad 12 connected to the second wire 15 and at most two first conductive pads 11 are arranged along the first parallel edge 18a; wherein, along the first parallel edge 18a is arranged At most two first conductive pads 11 are located on the side of at least one second conductive pad 12 disposed along the first parallel edge 18a or the second parallel edge 18b away from the second wire 15 connected to the second conductive pad 12, At most one first conductive pad disposed along the second parallel edge 18b is located on the side away from the second conductive line 15 connected to the second conductive pad at least one second conductive pad disposed along the first parallel edge or the second parallel edge.
  • the two second conductive pads 12 (the second conductive pad 12 a and the second conductive pad 12 b ) connected by the second wire 15 are located on the same side of the first wire 14 , so that the two second conductive pads 12 are conductive
  • the pad 12 is connected by the second wire 15, the second wire 15 does not overlap the first wire 14, so as to avoid the risk of short circuit caused by the overlapping of the second wire 15 and the first wire 14, and optimize the wiring design of the backlight module
  • the first wire 14, the first conductive pad 11, the second wire 15 and the second conductive pad 12 can be arranged in the same layer, which reduces the number of metal layers required by the backlight module, simplifies the process of the backlight module, and reduces the process cost.
  • the third wire 16 transmits the signal in the driving chip 18 to the light emitting unit 20 , one end of the third wire 16 is connected to the third conductive pad 13 , the other end of the third wire 16 is connected to one end of the light emitting unit 20 ,
  • the third wire 16 extends from the position of the third conductive pad 13 to the side of the second parallel edge 18b away from the first parallel edge 18a; wherein, the first wire 14 is located on the side of the second parallel edge close to the first parallel edge 18a ; In each of the first bonding regions 100a, at least one third conductive pad 13 is disposed on one side of the first wire 14 close to the second parallel edge 18b.
  • each first bonding area 100a is provided with a plurality of first conductive pads 11, and the plurality of first conductive pads 11 in each first bonding area 100a can transmit the same signal, or can transmit different Signal.
  • the plurality of first conductive pads 11 include a first type of first conductive pad 11a and a second type of first conductive pad 11b, and the signals transmitted by the first type of first conductive pad 11a and the second type of first conductive pad 11b are different.
  • the first wires 14 are plural, and the plurality of first wires 14 include a first wire 14a and a first wire 14b.
  • the first wires 14a are connected to the first type of first conductive pads 11a in a row of the first bonding area 100a.
  • the first wires 14b is connected to the second type of first conductive pads 11b in a row of first bonding regions 100a.
  • the first wire 14a may be a GND transmission line, and the first wire 14b may be a transmission line for transmitting the operating voltage required for the operation of the driving chip and the light-emitting unit.
  • the first wire 14b may also be a GND transmission line, and the first wire 14a may also be a transmission line for transmitting the operating voltage required for the operation of the driving chip 18 and the light-emitting unit 20 .
  • the first type of first conductive pads 11 a and the second type of first conductive pads 11 b are respectively on the substrate 10 along the driving chip 18 .
  • Different edge settings for the orthographic projection are respectively on the substrate 10 along the driving chip 18 .
  • a first-type first conductive pad 11a is disposed along the first parallel edge 18a
  • a second-type first conductive pad 11b is disposed along the second parallel edge 18b
  • the first-type first conductive pad 11a and the The second-type first conductive pads 11b are arranged side by side in the row direction, one first-type first conductive pad 11a is connected to the first wire 14a, one second-type first conductive pad 11b is connected to the first wire 14b, and one first-type first conductive pad 11b is connected to the first wire 14b.
  • the first wire 14a connected to the first type of conductive pad 11a is located on the side of the first parallel edge 18a away from the second parallel edge 18b, and the first wire 14b connected to a second type of first conductive pad 11b is located at the first parallel edge 18a and the second parallel edge 18b.
  • FIG. 5 is a first schematic plan view of the backlight module according to the second embodiment of the present application
  • FIG. 6 is a partial enlarged schematic view of the backlight module shown in FIG. 5
  • the backlight module shown in FIG. 6 is basically similar to the backlight module shown in FIG. 4 , and the differences include the first wires 14a connected to the first type of first conductive pads 11a and the first wires 14a connected to the second type of first conductive pads 11b
  • the first wires 14b are all located between the first parallel edge 18a and the second parallel edge 18b, and the first wires 14a connected to the first type of first conductive pad 11a are disposed close to the first parallel edge 18a, and are connected to the second type of first conductive pad 11a.
  • the first wire 14b to which the pad 11b is connected is disposed adjacent to the second parallel edge 18b, and the first wire 14a is parallel to the first wire 14b.
  • the difference between the backlight module shown in FIG. 6 and the backlight module shown in FIG. 4 is that the positions of the first wires 14a are different, which will lead to differences in the size of the driving chip 18 of the backlight module.
  • FIG. 7 is a second enlarged schematic view of the backlight module shown in FIG. 5
  • the backlight module shown in FIG. 7 is basically similar to the backlight module shown in FIG. 6 , and the differences include that a first The first-like conductive pads 11a are arranged along the first vertical edge 18c, and a second-like first conductive pad 11b is arranged along the second parallel edge 18b.
  • FIG. 8 is a first partially enlarged schematic diagram of the backlight module according to the third embodiment of the present application.
  • the backlight module shown in FIG. 8 is basically similar to the backlight module shown in FIG. 4, and the differences include: the backlight module shown in FIG.
  • the 8 further includes a third type of first conductive pad 11c and a fourth type of first conductive pad 11d,
  • the third type of first conductive pad 11c is disposed along the first vertical edge 18c and connected to the first wire 14c
  • the fourth type of first conductive pad 11d is disposed along the second vertical edge 18d and connected to the first wire 14d
  • the first wire 14a is disposed On the side of the first parallel edge 18a away from the first conductive pad 11a
  • the first wire 14b, the first wire 14c and the first wire 14d are all disposed between the first parallel edge 18a and the second parallel edge 18b
  • the first The conducting wire 14d is disposed between the first conducting wire 14b and the first conducting wire 14c
  • the first conducting wire 14b is disposed close to the second parallel edge 18b.
  • the first conducting wire 14a, the first conducting wire 14b, the first conducting wire 14c and the first conducting wire 14d are all parallel to each other. It can be understood that the third type of first conductive pads 11c may also be disposed on the first parallel edges 18a. The signals transmitted by the third-type first conductive pads 11c are different from the signals transmitted by the first-type first conductive pads 11a and the second-type first conductive pads 11b.
  • the first conductive pads 11 may be arranged along at least one of the first parallel edge 18a, the second parallel edge 18b, the first vertical edge 18c and the second vertical edge 18d, and may be arranged along different edges.
  • the third conductive pads 13 are arranged along the second parallel edge 18b, at most two first conductive pads 11 are arranged along the first parallel edge 18a, and at most one first conductive pad 11 is arranged along the second parallel edge 18b.
  • the first conductive pad 11 may be disposed along at least one of the first vertical edge 18c and the second vertical edge 18d, however, the first conductive pad 11 may be disposed along at least one of the first vertical edge 18c and the second vertical edge 18d
  • the first conductive pad 11 and the third conductive pad 13 are simultaneously disposed along at least one of the first vertical edge 18c and the second vertical edge 18d, the first conductive pad 11 is disposed on the third conductive pad 13 away from the One side of the extending direction of the third wire 16 connected to the three conductive pads 13 .
  • At least one third conductive pad is disposed along at least one of the first vertical edge and the second vertical edge, and/or, at least one first conductive pad is provided along the first vertical edge At least one of the vertical edge and the second vertical edge is provided.
  • each of the first bonding regions 100 a at least two second conductive pads 12 are arranged along the second parallel edge 18 b and arranged along the second parallel edge 18 b
  • the at least two second conductive pads 12 are respectively located on opposite sides of one second type first conductive pad 11b to avoid connecting the second wires 15 of the two second conductive pads 12 respectively located in the two first bonding regions 100a It overlaps with the first wire 14b connected to the second type of first conductive pad 11b.
  • each first bonding region 100a is provided with a first type of second conductive pad 12b and a second type of second conductive pad 12a, the first type of second conductive pad 12b outputs signals from the driving chip 18, the second type of second conductive pad 12b
  • the second-type conductive pads 12a receive signals to the driving chip 18, and the first-type second-type conductive pads 12b in one first bonding area 100a pass through the second-type second-type conductive pads 12a in the other first bonding area 100a
  • the second wires 15 are connected to realize the transmission of staging signals between the two driving chips 18 .
  • one driving chip 18 is electrically connected to one light-emitting unit 20 or a plurality of light-emitting units 20 through the third wire 16 .
  • the number of light-emitting units 20 driven by one driver chip 18 depends on the number of third conductive pads 13 in one first bonding region 100 a and the number of third pins 183 on one driver chip 18 . The greater the number of third conductive pads 13 in one first bonding region 100a, the greater the number of light emitting units 20 driven by one driving chip 18 correspondingly.
  • the first type first conductive pad 11a and the second type first conductive pad 11b are arranged along the same edge of the orthographic projection of the driving chip 18 on the substrate .
  • each of the first bonding areas 100 a , the first type of first conductive pads 11 a and the second type of first conductive pads 11 b are all along the The first parallel edges 18a are disposed, and the first wires 14a connected to the first type of conductive pads 11a and the first wires 14b connected to the second type of first conductive pads 11b are located on both sides of the first parallel edges 18a, respectively.
  • FIG. 9 is a second enlarged schematic view of the backlight module shown in FIG. 3 .
  • each first bonding area 100a in each first bonding area 100a, at least two second conductive pads 12 are disposed along the second parallel edge 18b, and at least two second conductive pads
  • One of the second conductive pads 12 in 12 is connected to the light-emitting unit 20 through the third wire 16, that is, one second conductive pad 12 is multiplexed into the third conductive pad 13, and the first conductive pad 12 is time-division multiplexed to transmit signals respectively.
  • the light-emitting unit 20 and transmit signals to other driver chips 18 .
  • the at least two second conductive pads 12 include a first-type second conductive pad 12b and a second-type second conductive pad 12a, both of which are along the second parallel edges 18b, the first type of second conductive pads 12b are time-multiplexed to output signals to the third conductive pads 13 of the light-emitting unit 20.
  • the first type second conductive pad 12b in one first bonding area 100a is connected with the second type second conductive pad 12a in the other first bonding area 100a through the second wire 15, and the second type second conductive pad 12a
  • the first-type second conductive pads 12 b When outputting signals to other driving chips 18 , the first-type second conductive pads 12 b output signals from the driving chips 18 , and the second-type second conductive pads 12 a receive signals into the driving chips 18 .
  • the backlight module shown in FIG. 10 is basically similar to the backlight module shown in FIG. 9 , and the differences include that in each first In the bonding area 100a, at least two second conductive pads 12 are disposed along the second parallel edges 18b.
  • the at least two second conductive pads 12 include a first type of second conductive pad 12b, a second type of second conductive pad 12a, a third type of second conductive pad 12c, and a fourth type of second conductive pad 12d.
  • the first type of second conductive pad 12b and the second type of second conductive pad 12a are located on both sides of the third type of second conductive pad 12c and the fourth type of second conductive pad 12d.
  • the second conductive pad 12c is disposed adjacent to the first type of second conductive pad 12b
  • the fourth type of second conductive pad 12d is disposed adjacent to the second type of second conductive pad 12
  • the first type of second conductive pad in the first bonding region 100a 12b is connected to the second type of second conductive pad 12a in another first bonding area 100a through a second wire 15a
  • the fourth type of second conductive pad 12d in one first bonding area 100a is connected to another first bonding area 100a
  • the third type of second conductive pads 12c are connected by second wires 15b.
  • the second conducting wire 15a is parallel to the second conducting wire 15b.
  • the third type of second conductive pads 12c and the first type of second conductive pads 12b output signals from the driver chip 18, and the signals transmitted by the third type of second conductive pads 12c and the first type of second conductive pads 12b are different;
  • the second-type second conductive pads 12a and the fourth-type second conductive pads 12d receive signals from the outside and transmit them to the driving chip 18 , and the signals transmitted by the second-type second conductive pads 12a and the fourth-type second conductive pads 12d are different.
  • the backlight module shown in FIG. 11 is basically similar to the backlight module shown in FIG.
  • the bonding area 100a at least two second conductive pads 12 are disposed along the first parallel edges 18a, and the first type of first conductive pads 11a and the second type of first conductive pads 11b are disposed between two adjacent second conductive pads 12. between.
  • the first type of first conductive pads 11a and the second type of first conductive pads 11b are disposed between the two second conductive pads 12, and the two second conductive pads 12 and the aforementioned two second conductive pads 12 (No.
  • the first type of second conductive pad and the second type of second conductive pad are the same, and will not be described in detail here.
  • a plurality of third conductive pads 13 are disposed on the second parallel edge 18b, and the plurality of third conductive pads 13 include a third conductive pad 13a, a third conductive pad 13b, a third conductive pad 13c and a third conductive pad 13d.
  • FIG. 12 it is a partial enlarged schematic diagram of the backlight module according to the sixth embodiment of the present application.
  • the backlight module shown in FIG. 12 is basically similar to the backlight module shown in FIG. 11 , the difference is that the backlight module shown in FIG. 12 further includes a third type of first conductive pads 11c, and the third type of first conductive pads 11c are provided On the second vertical edge 18d and connected to the first wire, the first wire connected to the third type of first conductive pad 11c is parallel to the first wire 14a and the first wire 14a.
  • FIG. 13 which is a partial enlarged schematic view of the backlight module of the seventh embodiment of the present application.
  • the backlight module shown in FIG. 13 is basically similar to the backlight module shown in FIG. 11 , except that the third conductive pads 13a are arranged along the first vertical edge 18c, and the third conductive pads 13d are arranged along the second vertical edge 18d.
  • FIG. 14 is a partial enlarged schematic diagram of the backlight module according to the eighth embodiment of the present application.
  • the backlight module shown in FIG. 14 is basically similar to the backlight module shown in FIG. 9 , except that the second conductive pads are not multiplexed into the third conductive pads 13 , and in each of the first bonding regions 100 a , the second conductive pads 15
  • the two connected second conductive pads 12 are respectively disposed along the first vertical edge 18c and the second vertical edge 18d, and a third conductive pad 13 is disposed along the second parallel edge 18b.
  • At least one third conductive pad 13 is disposed along the first parallel edge 18a, and each first bonding area 100a is disposed with a first conductive pad 11 and the first conductive pad 11 is disposed along the first parallel edge 18a is provided to avoid overlapping of the first wire 14 connected to the first conductive pad 11 and the third wire 16 connected to the third conductive pad 13 .
  • at least one third conductive pad 13 may also be disposed on the second parallel edge 18b, the first vertical edge 18c and the second vertical edge 18d.
  • the third conductive pad 13 When the third conductive pad 13 is arranged along the first parallel edge 18a, it can be staggered from the third conductive pad 13 along the second parallel edge 18b, so that the third conductive pad 13 connected to the third conductive pad 13 arranged along the first parallel edge 18a
  • the wire 16 may pass through the gap between the adjacent two third conductive pads 13 provided along the second parallel edge 18b.
  • the third wire 16 connected to the third conductive pad 13 extends to one side (upward or downward) and then along the second parallel edge 18b extends away from the side of the first parallel edge 18a.
  • the present application also provides a display panel, the display panel includes: a substrate, the substrate includes at least two first bonding areas; at least one first conductive pad disposed on the first bonding area of the substrate; and a first bonding area disposed on the substrate at least two second conductive pads on the substrate; first wires are arranged on the substrate and are connected to at least two first conductive pads located in the first bonding area;
  • the second wire is disposed on the substrate and is connected to the two second conductive pads located in the two first bonding regions respectively; and the driving chip is connected to the first conductive pad and the second conductive pad of the first bonding region; wherein, The two second conductive pads connected by the second wire are located on the same side of the first wire.
  • the present application further provides an array substrate, the array substrate includes: a substrate, the substrate includes at least two first bonding areas; at least one first conductive pad disposed on the first bonding area of the substrate; and a first bonding area disposed on the substrate at least two second conductive pads on the substrate; first wires are arranged on the substrate and are connected to at least two first conductive pads located in the first bonding area; second wires are arranged on the substrate and are connected at Two second conductive pads of two first bonding areas; wherein, the two second conductive pads connected by the second wires are located on the same side of the first wires.

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Abstract

一种阵列基板、背光模组及显示面板，通过第二导线（15）连接的两个第二导电垫（12）位于第一导线（14）的同一侧，以避免第一导线（14）与连接的两个第二导电垫（12）的第二导线（15）之间交叠。

Description

阵列基板、背光模组及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、背光模组及显示面板。
 背景技术
微型发光二极管（Micro-LED）发展成未来显示技术的热点之一，和目前的液晶显示面板（Liquid Crystal Display，LCD）、有机发光二极管（Organic Light Emitting Diode，OLED）显示器件相比，其具有反应快、高色域、高分辨率、低能耗等优势，但其技术难点多且技术复杂，特别是其关键技术巨量转移技术、发光二极管（Light Emitting Diode，LED）颗粒微型化成为技术瓶颈，而次毫米发光二极管（Mini-LED）作为Micro-LED与背板结合的产物，具有高对比度、高显色性能等可与OLED相媲美的特点，成本稍高LCD，仅为OLED的六成左右，相对OLED更易实施，所以Mini-LED成为各大面板厂商布局热点。
如图1所示，其为传统技术中驱动芯片绑定于背板上且与Mini-LED连接的平面示意图。每个驱动芯片1上包括第一引脚VCC、第二引脚VSS、第三引脚Di、第四引脚Out以及第五引脚GND，背板上设置有第一信号线2、第二信号线3、第三信号线4、第四信号线5以及电源线6，其中，第一信号线2与每个驱动芯片1上的第一引脚VCC均电性连接以将载波信号传输至驱动芯片1，第二信号线3与每个驱动芯片1上的第二引脚VSS均电性连接，第三信号线4电性连接分别位于两个驱动芯片1上的第三引脚Di以及第四引脚Out以实现信号在两个驱动芯片1之间的传输，第四信号线5与每个驱动芯片1中的第五引脚GND均电性连接以输入接地信号，LED的一端连接第四引脚Out，LED的另一端连接电源线6，第三信号线4与第二信号线3之间出现交叠。
因此，有必要提出一种技术方案以解决传统技术中与驱动芯片电性连接的第三信号线与第二信号线之间交叠不利于简化布线的问题。
 技术问题
本申请的目的在于提供一种阵列基板、背光模组及显示面板，以解决传统技术中与驱动芯片电性连接的信号线之间交叠的问题。
 技术解决方案
一种背光模组，所述背光模组包括：
基板，所述基板包括至少两个第一结合区；
设置于所述基板的所述第一结合区上的至少一个第一导电垫；
设置于所述基板的所述第一结合区上的至少两个第二导电垫；
第一导线，设置于所述基板上，且与至少两个位于所述第一结合区的所述第一导电垫均连接；
第二导线，设置于所述基板上，且连接分别位于两个所述第一结合区的两个所述第二导电垫；以及
驱动芯片，与所述第一结合区的所述第一导电垫以及第二导电垫连接；
其中，所述第二导线连接的两个所述第二导电垫位于所述第一导线的同一侧。
一种显示面板，所述显示面板包括：
基板，所述基板包括至少两个第一结合区；
设置于所述基板的所述第一结合区上的至少一个第一导电垫；
设置于所述基板的所述第一结合区上的至少两个第二导电垫；
第一导线，设置于所述基板上，且与至少两个位于所述第一结合区的所述第一导电垫均连接；
第二导线，设置于所述基板上，且连接分别位于两个所述第一结合区的两个所述第二导电垫；以及
驱动芯片，与所述第一结合区的所述第一导电垫以及第二导电垫连接；
其中，所述第二导线连接的两个所述第二导电垫位于所述第一导线的同一侧。
一种阵列基板，所述阵列基板包括：
基板，所述基板包括至少两个第一结合区；
设置于所述基板的所述第一结合区上的至少一个第一导电垫；
设置于所述基板的所述第一结合区上的至少两个第二导电垫；
第一导线，设置于所述基板上，且与至少两个位于所述第一结合区的所述第一导电垫均连接；
第二导线，设置于所述基板上，且连接分别位于两个所述第一结合区的两个所述第二导电垫；
其中，所述第二导线连接的两个所述第二导电垫位于所述第一导线的同一侧。
 有益效果
本申请提供一种阵列基板、背光模组及显示面板，通过第二导线连接的两个第二导电垫位于第一导线的同一侧，以避免第一导线与第二导线之间交叠，有利于第二导线、第二导线连接的第二导电垫、第一导线以及与第一导线连接的第一导电垫位于同一个金属层，简化布线的同时，减少金属膜层的数量，有利于提高产品良率，降低成本。
 附图说明
图1为传统技术中驱动芯片绑定于背板上且与Mini-LED连接的平面示意图；
图2为本申请第一实施例背光模组的截面示意图；
图3为本申请第一实施例背光模组的第一种平面示意图；
图4为图3所示背光模组的第一种局部放大示意图；
图5为本申请第二实施例背光模组的第一种平面示意图；
图6为图5所示背光模组的第一种局部放大示意图；
图7为图5所示背光模组的第二种局部放大示意图；
图8为本申请第三实施例背光模组的第一种局部放大示意图；
图9为图3所示背光模组的第二种局部放大示意图；
图10为本申请第四实施例背光模组的局部放大示意图；
图11为本申请第五实施例背光模组的局部放大示意图；
图12为本申请第六实施例背光模组的局部放大示意图；
图13为本申请第七实施例背光模组的局部放大示意图；
图14为本申请第八实施例背光模组的局部放大示意图；
图15为本申请第九实施例背光模组的局部放大示意图；
图16为本申请第十实施例背光模组的局部放大示意图；
图17为本申请第十一实施例背光模组的局部放大示意图；
图18为本申请第十二实施例背光模组的局部放大示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图2及图3，图2为本申请第一实施例背光模组的截面示意图，图3为本申请第一实施例背光模组的第一种平面示意图，背光模组100包括基板10、至少一个第一导电垫11、至少两个第二导电垫12、至少一个第三导电垫13、第一导线14、第二导线15、第三导线16、第四导线17、驱动芯片18、柔性印刷电路板19以及发光单元20。
在本实施例，基板10为玻璃基板。可以理解的是，基板10也可以为柔性基板。第一导电垫11、第二导电垫12、第三导电垫13、第一导线14、第二导线15、第三导线16以及第四导线17均设置于基板10上，且第一导电垫11、第二导电垫12、第三导电垫13、第一导线14、第二导线15、第三导线16以及第四导线17均设置于同一个金属层上，该金属层位于基板10上，以减少背光模组的金属层数目，简化背光模组的制程工艺，降低背光模组的制造成本。可以理解的是，第一导电垫11、第二导电垫12、第三导电垫13、第一导线14、第二导线15、第三导线16以及第四导线17也可以分别设置于两个或两个以上的金属层上。金属层的制备材料包括钼、铝、钛以及铜中的至少一种。
在本实施例中，基板10包括至少两个第一结合区100a。具体地，基板10包括多个第一结合区100a，多个第一结合区100a在基板10上呈多行多列排布，一个驱动芯片18固定于一个第一结合区100a，对应地，驱动芯片18呈多行多列排布。基板10的第一结合区100a设置有第一导电垫11、第二导电垫12、第三导电垫13，一个驱动芯片18连接于一个第一结合区100a的第一导电垫11、第二导电垫12、第三导电垫13上。驱动芯片18包括与第一导电垫11一一对应且连接的第一引脚181、与第二导电垫12一一对应且连接的第二引脚182以及与第三导电垫13一一对应且连接的第三引脚183。驱动芯片18还可以包括冗余引脚以及测试引脚，冗余引脚不接入电信号，测试引脚用于测试驱动芯片是否正常工作需要的引脚且并不会作为信号的传输。第一导电垫11与第一引脚181之间、第二导电垫12与第二引脚182之间、第三导电垫13与第三引脚183之间均可以通过锡膏、导电胶等连接。如图4所示，其为图3所示背光模组的第一种局部放大示意图，驱动芯片18的形状为矩形，例如驱动芯片18为正方形，每个驱动芯片18在基板10上的正投影包括与第一导线14延伸方向平行的第一平行边缘18a、与第一导线14延伸方向平行的第二平行边缘18b、第一垂直边缘18c以及第二垂直边缘18d，第一平行边缘18a与第二平行边缘18b相对，第一垂直边缘18c与第二垂直边缘18d相对，第一垂直边缘18c与第一平行边缘18a垂直，第二垂直边缘18d与第一平行边缘18a垂直。其中，驱动芯片18也可以为非规则图形。
在本实施例中，基板10包括第二结合区100b，第二结合区100b位于第一结合区100a的一侧。发光单元20固定于第二结合区100b，每个发光单元20包括多排串接的发光器件201，多排发光器件201电性连接，每排串接的发光器件201的数目大于2，发光器件201为次毫米发光二极管(Mini-LED)。发光单元20的一端通过第三导线16与驱动芯片18电性连接，发光单元20的另一端与第四导线17连接，第四导线17为电源线。可以理解的是，发光器件201也可以为微型发光二极管（Micro-LED）。
在本实施例中，如图3所示，柔性印刷电路板19固定于基板10上，柔性印刷电路板19与第一导线14、第二导线15以及第四导线17均电性连接，以分别向第一导线14、第二导线15以及第四导线17输入对应的电信号。柔性印刷电路板19设置于基板10的一端且与第一导线14等位于基板10的同一表面。其中，第一导线14延伸至固定柔性印刷电路板19的区域；第五导线15I连接于靠近柔性印刷电路板19的第一个驱动芯片18和柔性印刷电路板19之间，将柔性印刷电路板19输出的信号输出至驱动芯片18，再通过第二导线15连接相邻两个驱动芯片18，以实现信号在驱动芯片18之间的传输。第四导线17的一端延伸至柔性印刷电路板19所在的位置且与柔性印刷电路板19电性连接。可以理解的是，柔性印刷电路板19也可以固定于基板10设有第一导线14的背面，柔性印刷电路板19也可以多个且每个柔性印刷电路板19与部分区域的第一导线14、第二导线15以及第四导线17电性连接，柔性印刷电路板19也可以固定于基板10相对的两端。
在本实施例中，第一导线14用于将相同的信号传输到至少两个第一结合区100a中传输相同信号的第一导电垫11，且通过与第一导电垫11连接的第一引脚181输入至驱动芯片18内部。第一导线14与至少两个位于第一结合区100a的第一导电垫11均连接。每个第一结合区100a设置一个传输相同信号的第一导电垫11，位于每个第一结合区100a的至少一个第一导电垫11与至少一个第一导线14一一对应连接，即每个第一导电垫11只与传输其对应信号的一个第一导线14连接，对应地，为了避免传输不同信号的第一导电垫11沿第一平行边缘18a和第二平行边缘18b设置时出现交叠问题，至多两个第一导电垫11沿第一平行边缘18a设置，和/或，至多两个第一导电垫11沿第二平行边缘18b设置，即沿着第一平行边缘18a和第二平行边缘18b中的任意一者最多只能设置两个传输不同信号的第一导电垫11。可以理解的是，每个第一结合区100a也可以设置两个或两个以上传输相同信号的第一导电垫11。第一导线14为直线形导线，且沿列方向延伸。
在本实施例中，第二导线15用于传输各个驱动芯片18寻址所需的信号，还用于输出驱动芯片18工作所需的信号。第二导线15连接分别位于两个第一结合区100a的两个第二导电垫12，以使信号在两个驱动芯片18之间实现级传。每个第一结合区100a设置有至少两个第二导电垫12，一个第一结合区100a的一个第二导电垫12与另一第一结合区100a对应的一个第二导电垫12通过第二导线15连接，一个第二导电垫12将一个驱动芯片18中的信号输出至另一个驱动芯片18，另一个第二导电垫12将一个驱动芯片18输出的信号输入至另一个驱动芯片18，即至少两个第二导电垫12包括第一类第二导电垫和第二类第二导电垫，第一类第二导电垫将信号从驱动芯片18中输出，第二类第二导电垫将信号接收至驱动芯片18。另外，连接两个第二导电垫12的第二导线15以及该第二导线15连接的两个第二导电垫12构成一组级传单元，在两个驱动芯片18之间传输一种级传信号，可以采用多组级传单元传输多种不同级传信号。第二导线15沿列方向延伸，即第一导线14与第二导线15的延伸方向相同。第二导线15为直线形且与第一导线14平行。
在本实施例中，在每个第一结合区100a，与第二导线15连接的至少一个第二导电垫12与至多一个第一导电垫11沿所述第二平行边缘18b设置；和/或，在每个第一结合区100a，与第二导线15连接的至少一个第二导电垫12与至多两个第一导电垫11沿第一平行边缘18a设置；其中，沿第一平行边缘18a设置的至多两个第一导电垫11位于沿第一平行边缘18a或第二平行边缘18b设置的至少一个第二导电垫12远离与第二导电垫12连接的所述第二导线15一侧，沿第二平行边缘18b设置的至多一个第一导电垫位于沿第一平行边缘或第二平行边缘设置的至少一个第二导电垫远离与第二导电垫连接的第二导线15一侧。
另外，如图4所示，第二导线15连接的两个第二导电垫12（第二导电垫12a和第二导电垫12b）位于第一导线14的同一侧，以使得两个第二导电垫12通过第二导线15连接时，第二导线15不与第一导线14交叠，避免第二导线15与第一导线14交叠时导致的短路风险等问题，优化背光模组的布线设计，且使得第一导线14、第一导电垫11、第二导线15与第二导电垫12可以同层设置，减少背光模组所需的金属层数目，简化背光模组的制程的同时，降低制程成本。
在本实施例中，第三导线16将驱动芯片18中的信号传输到发光单元20，第三导线16的一端连接第三导电垫13，第三导线16的另一端连接发光单元20的一端，第三导线16从第三导电垫13所在的位置向第二平行边缘18b远离第一平行边缘18a的一侧延伸；其中，第一导线14位于第二平行边缘靠近第一平行边缘18a的一侧；在每个第一结合区100a，至少一个第三导电垫13设置于第一导线14靠近第二平行边缘18b的一侧。
结合图3和图4，每个第一结合区100a设置有多个第一导电垫11，每个第一结合区100a的多个第一导电垫11可以传输相同的信号，也可以传输不同的信号。多个第一导电垫11包括第一类第一导电垫11a和第二类第一导电垫11b，第一类第一导电垫11a和第二类第一导电垫11b传输的信号不同。第一导线14为多个且多个第一导线14包括第一导线14a以及第一导线14b，第一导线14a连接一列第一结合区100a中的第一类第一导电垫11a，第一导线14b连接一列第一结合区100a中的第二类第一导电垫11b。第一导线14a可以为GND传输线，第一导线14b可以为传输驱动芯片和发光单元工作所需的工作电压的传输线。第一导线14b也可以为GND传输线，第一导线14a也可以为传输驱动芯片18和发光单元20工作所需的工作电压的传输线。
如图4、图6、图7及图8所示，在每个第一结合区100a，第一类第一导电垫11a和第二类第一导电垫11b分别沿驱动芯片18在基板10上的正投影的不同边缘设置。
如图4所示，一个第一类第一导电垫11a沿第一平行边缘18a设置，一个第二类第一导电垫11b沿第二平行边缘18b设置，且第一类第一导电垫11a与第二类第一导电垫11b在行方向上并排设置，一个第一类第一导电垫11a与第一导线14a连接，一个第二类第一导电垫11b与第一导线14b连接，与一个第一类第一导电垫11a连接的第一导线14a位于第一平行边缘18a远离第二平行边缘18b的一侧，与一个第二类第一导电垫11b连接的第一导线14b位于第一平行边缘18a和第二平行边缘18b之间。
结合图5和图6，图5为本申请第二实施例背光模组的第一种平面示意图，图6为图5所示背光模组的第一种局部放大示意图。图6所示背光模组与图4所示背光模组基本相似，不同之处包括，与第一类第一导电垫11a连接的第一导线14a以及与第二类第一导电垫11b连接的第一导线14b均位于第一平行边缘18a和第二平行边缘18b之间，与第一类第一导电垫11a连接的第一导线14a靠近第一平行边缘18a设置，与第二类第一导电垫11b连接的第一导线14b靠近第二平行边缘18b设置，第一导线14a与第一导线14b平行。图6所示背光模组与图4所示背光模组的区别在于第一导线14a的位置存在差异，会导致背光模组的驱动芯片18的尺寸存在差异。
如图7所示，图7为图5所示背光模组的第二种局部放大示意图，图7所示背光模组与图6所示背光模组基本相似，不同之处包括，一个第一类第一导电垫11a沿第一垂直边缘18c设置，一个第二类第一导电垫11b沿第二平行边缘18b设置。
如图8所示，其为本申请第三实施例背光模组的第一种局部放大示意图。图8所示背光模组与图4所示背光模组基本相似，不同之处包括：图8所示背光模组还包括第三类第一导电垫11c以及第四类第一导电垫11d，第三类第一导电垫11c沿第一垂直边缘18c设置且第一导线14c连接，第四类第一导电垫11d沿第二垂直边缘18d设置且与第一导线14d连接，第一导线14a设置于第一平行边缘18a远离第一导电垫11a的一侧，第一导线14b、第一导线14c以及第一导线14d均设置于第一平行边缘18a与第二平行边缘18b之间，且第一导线14d设置于第一导线14b与第一导线14c之间，第一导线14b靠近第二平行边缘18b设置。第一导线14a、第一导线14b、第一导线14c以及第一导线14d均相互平行。可以理解的是，第三类第一导电垫11c也可以设置于第一平行边缘18a。第三类第一导电垫11c传输的信号与第一类第一导电垫11a和第二类第一导电垫11b传输的信号均不同。
由上述可知，第一导电垫11可以沿第一平行边缘18a、第二平行边缘18b、第一垂直边缘18c和第二垂直边缘18d中的至少一个设置，且可以沿着不同的边缘设置。在第三导电垫13沿第二平行边缘18b设置时，至多两个第一导电垫11沿第一平行边缘18a设置，且至多一个第一导电垫11沿第二平行边缘18b。另外，第一导电垫11可以沿第一垂直边缘18c和第二垂直边缘18d中的至少一者设置，然而，第一导电垫11沿第一垂直边缘18c和第二垂直边缘18d中的至少一者设置时，需要注意避免与第一导电垫11连接的第一导线14和与第三导电垫13连接的第三导线16之间交叠。例如，在第一导电垫11与第三导电垫13同时沿第一垂直边缘18c和第二垂直边缘18d中的至少一者设置时，第一导电垫11设置于第三导电垫13远离与第三导电垫13连接的第三导线16延伸方向的一侧。
此外，在每个第一结合区，至少一个第三导电垫沿着第一垂直边缘和第二垂直边缘中的至少一者设置，和/或，至少一个第一导电垫沿着所述第一垂直边缘和所述第二垂直边缘中的至少一者设置。
在图4、图6、图7及图8中，在每个所述第一结合区100a，至少两个第二导电垫12沿着第二平行边缘18b设置，且沿第二平行边缘18b设置的至少两个第二导电垫12分别位于一个第二类第一导电垫11b的相对两侧，以避免连接分别位于两个第一结合区100a的两个第二导电垫12的第二导线15和与第二类第一导电垫11b连接的第一导线14b交叠。具体地，在每个第一结合区100a设置有第一类第二导电垫12b和第二类第二导电垫12a，第一类第二导电垫12b将信号从驱动芯片18中输出，第二类第二导电垫12a将信号接收至驱动芯片18中，一个第一结合区100a中的第一类第二导电垫12b与另一个第一结合区100a中的第二类第二导电垫12a通过第二导线15连接，以实现级传信号在两个驱动芯片18之间的传输。
另外，如图4-图8所示，一个驱动芯片18与一个发光单元20或者多个发光单元20通过第三导线16电性连接。一个驱动芯片18驱动的发光单元20的数目取决于一个第一结合区100a中第三导电垫13的数目以及一个驱动芯片18上第三引脚183的数目。一个第一结合区100a中第三导电垫13的数目越多，对应地一个驱动芯片18驱动的发光单元20的数目越多。
如图9-图12所示，在每个第一结合区100a，第一类第一导电垫11a和第二类第一导电垫11b沿驱动芯片18在基板上的正投影的同一个边缘设置。
如图9所示，其为图3所示背光模组的第二种局部放大示意图，每个第一结合区100a，第一类第一导电垫11a与第二类第一导电垫11b均沿第一平行边缘18a设置，且与第一类导电垫11a连接的第一导线14a和与第二类第一导电垫11b连接的第一导线14b分别位于第一平行边缘18a的两侧。另外，如图9所示，在每个第一结合区100a，在每个第一结合区100a中，至少两个第二导电垫12沿第二平行边缘18b设置，至少两个第二导电垫12中的一个第二导电垫12通过第三导线16与发光单元20连接，即一个第二导电垫12复用为第三导电垫13，第一导电垫12通过分时复用以分别传输信号给发光单元20以及传输信号到其他驱动芯片18。至少两个第二导电垫12包括第一类第二导电垫12b和第二类第二导电垫12a，第一类第二导电垫12b和第二类第二导电垫12a均沿第二平行边缘18b设置，第一类第二导电垫12b分时复用为输出信号到发光单元20的第三导电垫13。一个第一结合区100a中的第一类第二导电垫12b与另一个第一结合区100a中的第二类第二导电垫12a通过第二导线15连接，在第二类第二导电垫12a输出信号到其他驱动芯片18时，第一类第二导电垫12b将信号从驱动芯片18中输出，第二类第二导电垫12a将信号接收至驱动芯片18中。
如图10所示，其为本申请第四实施例背光模组的局部放大示意图，图10所示背光模组与图9所示背光模组基本相似，不同之处包括，在每个第一结合区100a中，至少两个第二导电垫12沿第二平行边缘18b设置。具体地，至少两个第二导电垫12包括第一类第二导电垫12b、第二类第二导电垫12a、第三类第二导电垫12c以及第四类第二导电垫12d。在第一结合区100a中，第一类第二导电垫12b和第二类第二导电垫12a位于第三类第二导电垫12c以及第四类第二导电垫12d的两侧，第三类第二导电垫12c靠近第一类第二导电垫12b设置，第四类第二导电垫12d靠近第二类第二导电垫12设置，一个第一结合区100a中的第一类第二导电垫12b与另一个第一结合区100a中的第二类第二导电垫12a通过第二导线15a连接，一个第一结合区100a中的第四类第二导电垫12d与另一个第一结合区100a中的第三类第二导电垫12c通过第二导线15b连接。第二导线15a与第二导线15b平行。第三类第二导电垫12c和第一类第二导电垫12b将信号从驱动芯片18中输出，第三类第二导电垫12c和第一类第二导电垫12b传输的信号不同；第二类第二导电垫12a和第四类第二导电垫12d从外部将信号接收后传输至驱动芯片18，第二类第二导电垫12a和第四类第二导电垫12d传输的信号不同。
如图11所示，其为本申请第五实施例背光模组的局部放大示意图，图11所示背光模组与图9所示背光模组基本相似，不同之处包括，在每个第一结合区100a中，至少两个第二导电垫12沿第一平行边缘18a设置，第一类第一导电垫11a与第二类第一导电垫11b设置于相邻两个第二导电垫12之间。具体地，第一类第一导电垫11a与第二类第一导电垫11b设置于两个第二导电垫12之间，两个第二导电垫12与前述两个第二导电垫12（第一类第二导电垫和第二类第二导电垫）相同，此处不作详述。另外，多个第三导电垫13设置于第二平行边缘18b，多个第三导电垫13包括第三导电垫13a、第三导电垫13b、第三导电垫13c以及第三导电垫13d。
如图12所示，其为本申请第六实施例背光模组的局部放大示意图。图12所示背光模组与图11所示背光模组基本相似，不同之处在于，图12所示背光模组还包括第三类第一导电垫11c，第三类第一导电垫11c设置于第二垂直边缘18d且与第一导线连接，与第三类第一导电垫11c连接的第一导线与第一导线14a和第一导线14a平行。
如图13所示，其为本申请第七实施例背光模组的局部放大示意图。图13所示背光模组与图11所示背光模组基本相似，不同之处在于，第三导电垫13a沿第一垂直边缘18c设置，第三导电垫13d沿第二垂直边缘18d设置。
如图14所示，其为本申请第八实施例背光模组的局部放大示意图。图14所示背光模组与图9所示背光模组基本相似，不同之处包括，第二导电垫没有复用为第三导电垫13，每个第一结合区100a中，第二导线15连接的两个第二导电垫12分别沿所述第一垂直边缘18c和第二垂直边缘18d设置，且一个第三导电垫13沿第二平行边缘18b设置。
如图15-图18所示，至少一个第三导电垫13沿第一平行边缘18a设置，每个第一结合区100a设置有一个第一导电垫11且第一导电垫11沿第一平行边缘18a设置，以避免与第一导电垫11连接的第一导线14和与第三导电垫13连接的第三导线16交叠。另外，至少一个第三导电垫13还可以设置于第二平行边缘18b、第一垂直边缘18c以及第二垂直边缘18d。第三导电垫13沿第一平行边缘18a设置时，可以与沿第二平行边缘18b的第三导电垫13错开设置，使得与沿第一平行边缘18a设置的第三导电垫13连接的第三导线16可以穿过沿第二平行边缘18b设置的相邻两个第三导电垫13之间的间隙。另外，第三导电垫13沿第一垂直边缘18c以及第二垂直边缘18d设置时，与第三导电垫13连接的第三导线16向一侧延伸（向上或向下）后沿第二平行边缘18b远离第一平行边缘18a的一侧延伸。
本申请还提供一种显示面板，显示面板包括：基板，基板包括至少两个第一结合区；设置于基板的第一结合区上的至少一个第一导电垫；设置于基板的第一结合区上的至少两个第二导电垫；第一导线，设置于基板上，且与至少两个位于第一结合区的第一导电垫均连接；
第二导线，设置于基板上，且连接分别位于两个第一结合区的两个第二导电垫；以及驱动芯片，与第一结合区的第一导电垫以及第二导电垫连接；其中，第二导线连接的两个第二导电垫位于第一导线的同一侧。上述背光模组的技术方案也应用于显示面板，此处不作详述。
本申请还提供一种阵列基板，阵列基板包括：基板，基板包括至少两个第一结合区；设置于基板的第一结合区上的至少一个第一导电垫；设置于基板的第一结合区上的至少两个第二导电垫；第一导线，设置于基板上，且与至少两个位于第一结合区的第一导电垫均连接；第二导线，设置于基板上，且连接分别位于两个第一结合区的两个第二导电垫；其中，第二导线连接的两个第二导电垫位于第一导线的同一侧。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种背光模组，其中，所述背光模组包括：
    基板，所述基板包括至少两个第一结合区；
    设置于所述基板的所述第一结合区上的至少一个第一导电垫；
    设置于所述基板的所述第一结合区上的至少两个第二导电垫；
    第一导线，设置于所述基板上，且与至少两个位于所述第一结合区的所述第一导电垫均连接；
    第二导线，设置于所述基板上，且连接分别位于两个所述第一结合区的两个所述第二导电垫；以及
    驱动芯片，与所述第一结合区的所述第一导电垫以及第二导电垫连接；
    其中，所述第二导线连接的两个所述第二导电垫位于所述第一导线的同一侧。
  2. 根据权利要求1所述的背光模组，其中，所述第一结合区设置有一个所述驱动芯片，每个所述驱动芯片在所述基板上的正投影包括与所述第一导线延伸方向平行的第一平行边缘以及第二平行边缘，所述第一平行边缘与所述第二平行边缘相对；
    位于所述第一结合区的至少一个所述第一导电垫与至少一个所述第一导线一一对应连接；
    其中，至多两个所述第一导电垫沿所述第一平行边缘设置，和/或，至多两个所述第一导电垫沿所述第二平行边缘设置。
  3. 根据权利要求2所述的背光模组，其中，所述基板还包括第二结合区，所述背光模组还包括：
    设置于所述基板的所述第一结合区的至少一个第三导电垫，至少一个所述第三导电垫与所述驱动芯片连接；
    发光单元，设置于所述基板的所述第二结合区上；以及
    第三导线，所述第三导线的一端连接所述第三导电垫，所述第三导线的另一端连接所述发光单元的一端，所述第三导线从所述第三导电垫所在的位置向所述第二平行边缘远离所述第一平行边缘的一侧延伸；
    其中，所述第一导线位于所述第二平行边缘靠近所述第一平行边缘的一侧；在所述第一结合区，至少一个所述第三导电垫设置于所述第一导线靠近所述第二平行边缘的一侧。
  4. 根据权利要求3所述的背光模组，其中，在第一结合区，与所述第二导线连接的至少一个所述第二导电垫与至多一个所述第一导电垫沿所述第二平行边缘设置；和/或，
    在所述第一结合区，与所述第二导线连接的至少一个所述第二导电垫与至多两个所述第一导电垫沿所述第一平行边缘设置；
    其中，沿所述第一平行边缘设置的至多两个所述第一导电垫位于沿所述第一平行边缘或所述第二平行边缘设置的至少一个所述第二导电垫远离与所述第二导电垫连接的所述第二导线一侧，沿所述第二平行边缘设置的至多一个所述第一导电垫位于沿所述第一平行边缘或所述第二平行边缘设置的至少一个所述第二导电垫远离与所述第二导电垫连接的所述第二导线一侧。
  5. 根据权利要求3所述的背光模组，其中，多个所述第一导电垫包括第一类第一导电垫和第二类第一导电垫；
    在所述第一结合区，所述第一类第一导电垫和所述第二类第一导电垫沿所述驱动芯片在所述基板上的正投影的同一个边缘设置；或，
    在所述第一结合区，所述第一类第一导电垫和所述第二类第一导电垫分别沿所述驱动芯片在所述基板上的正投影的不同边缘设置。
  6. 根据权利要求5所述的背光模组，其中，在所述第一类第一导电垫和所述第二类第一导电垫沿所述驱动芯片在所述基板上的正投影的同一个边缘设置的情况下，所述第一类第一导电垫与所述第二类第一导电垫均沿所述第一平行边缘设置，且与所述第一类导电垫连接的所述第一导线和与所述第二类第一导电垫连接的所述第一导线分别位于所述第一平行边缘的两侧。
  7. 根据权利要求6所述的背光模组，其中，在所述第一结合区中，至少两个所述第二导电垫沿所述第一平行边缘设置，所述第一类第一导电垫与所述第二类第一导电垫设置于相邻两个所述第二导电垫之间。
  8. 根据权利要求6所述的背光模组，其中，在所述第一结合区中，至少两个所述第二导电垫沿所述第二平行边缘设置。
  9. 根据权利要求8所述的背光模组，其中，至少两个所述第二导电垫中的一个所述第二导电垫通过所述第三导线与所述发光单元连接。
  10. 根据权利要求6所述的背光模组，其中，所述驱动芯片在所述基板上的正投影还包括相对的第一垂直边缘以及第二垂直边缘，所述第一垂直边缘与所述第一平行边缘垂直，所述第二垂直边缘与所述第一平行边缘垂直；
    所述第一结合区中，所述第二导线连接的两个所述第二导电垫分别沿所述第一垂直边缘和所述第二垂直边缘设置。
  11. 根据权利要求6所述的背光模组，其中，在所述第一结合区，至少一个所述第三导电垫沿所述第二平行边缘设置。
  12. 根据权利要求5所述的背光模组，其中，在所述第一类第一导电垫和所述第二类第一导电垫分别沿着所述驱动芯片在所述基板上的正投影的不同边缘设置的情况下，第一类第一导电垫沿所述第一平行边缘设置，所述第二类第一导电垫沿所述第二平行边缘设置。
  13. 根据权利要求12所述的背光模组，其中，与所述第一类第一导电垫连接的所述第一导线位于所述第一平行边缘远离所述第二平行边缘的一侧，与所述第二类第一导电垫连接的所述第一导线位于所述第一平行边缘和所述第二平行边缘之间。
  14. 根据权利要求12所述的背光模组，其中，与所述第一类第一导电垫连接的所述第一导线以及与所述第二类第一导电垫连接的所述第一导线均位于所述第一平行边缘和所述第二平行边缘之间，与所述第一类第一导电垫连接的所述第一导线靠近第一平行边缘，与所述第二类第一导电垫连接的所述第一导线靠近第二平行边缘。
  15. 根据权利要求12所述的背光模组，其中，位于所述第一结合区的多个所述第一导电垫还包括一个第三类第一导电垫，一个所述第三类第一导电垫沿所述第一平行边缘设置；
    在所述第一结合区，至少两个所述第二导电垫沿着所述第二平行边缘设置，且沿所述第二平行边缘设置的至少两个所述第二导电垫分别位于一个所述第二类第一导电垫的相对两侧。
  16. 根据权利要求3所述的背光模组，其中，至少一个所述第三导电垫沿所述第一平行边缘设置，所述第一结合区设置有一个所述第一导电垫且所述第一导电垫沿所述第一平行边缘设置。
  17. 根据权利要求3所述的背光模组，其中，所述驱动芯片在所述基板上的正投影还包括相对的第一垂直边缘以及第二垂直边缘，所述第一垂直边缘与所述第一平行边缘垂直，所述第二垂直边缘与所述第一平行边缘垂直；
    在所述第一结合区，至少一个所述第三导电垫沿着所述第一垂直边缘和所述第二垂直边缘中的至少一者设置，和/或，至少一个所述第一导电垫沿着所述第一垂直边缘和所述第二垂直边缘中的至少一者设置。
  18. 根据权利要求3所述的背光模组，其中，所述驱动芯片包括与所述第一导电垫一一对应且连接的第一引脚、与所述第二导电垫一一对应且连接的第二引脚以及与所述第三导电垫一一对应且连接的第三引脚；
    所述发光单元的另一端与第四导线连接；
    所述第一导电垫、所述第一导线、所述第二导电垫、所述第二导线、所述第三导电垫以及所述第三导线均位于同一个金属层。
  19. 一种显示面板，其中，所述显示面板包括：
    基板，所述基板包括至少两个第一结合区；
    设置于所述基板的所述第一结合区上的至少一个第一导电垫；
    设置于所述基板的所述第一结合区上的至少两个第二导电垫；
    第一导线，设置于所述基板上，且与至少两个位于所述第一结合区的所述第一导电垫均连接；
    第二导线，设置于所述基板上，且连接分别位于两个所述第一结合区的两个所述第二导电垫；以及
    驱动芯片，与所述第一结合区的所述第一导电垫以及第二导电垫连接；
    其中，所述第二导线连接的两个所述第二导电垫位于所述第一导线的同一侧。
  20. 一种阵列基板，其中，所述阵列基板包括：
    基板，所述基板包括至少两个第一结合区；
    设置于所述基板的所述第一结合区上的至少一个第一导电垫；
    设置于所述基板的所述第一结合区上的至少两个第二导电垫；
    第一导线，设置于所述基板上，且与至少两个位于所述第一结合区的所述第一导电垫均连接；
    第二导线，设置于所述基板上，且连接分别位于两个所述第一结合区的两个所述第二导电垫；
    其中，所述第二导线连接的两个所述第二导电垫位于所述第一导线的同一侧。
PCT/CN2021/083842 2021-02-10 2021-03-30 阵列基板、背光模组及显示面板 Ceased WO2022170672A1 (zh)

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