WO2022166426A1 - 裸芯间高速扩展系统及其扩展方法 - Google Patents

裸芯间高速扩展系统及其扩展方法 Download PDF

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WO2022166426A1
WO2022166426A1 PCT/CN2021/138703 CN2021138703W WO2022166426A1 WO 2022166426 A1 WO2022166426 A1 WO 2022166426A1 CN 2021138703 W CN2021138703 W CN 2021138703W WO 2022166426 A1 WO2022166426 A1 WO 2022166426A1
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die
signal
expansion
synchronizer
data
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PCT/CN2021/138703
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English (en)
French (fr)
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魏敬和
黄乐天
于宗光
赵天津
鞠虎
冯敏刚
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中国电子科技集团公司第五十八研究所
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Priority to US17/626,825 priority Critical patent/US20220276677A1/en
Publication of WO2022166426A1 publication Critical patent/WO2022166426A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/1613—Constructional details or arrangements for portable computers
    • G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
    • G06F1/1656—Details related to functional adaptations of the enclosure, e.g. to provide protection against EMI, shock, water, or to host detachable peripherals like a mouse or removable expansions units like PCMCIA cards, or to provide access to internal components for maintenance or to removable storage supports like CDs or DVDs, or to mechanically mount accessories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention relates to an expansion connection of bare cores, in particular to a high-speed expansion system between bare cores and an expansion method thereof.
  • multi-die integration is an inevitable choice.
  • the difficulty of multi-die integration is how to efficiently interconnect each die and ensure high microsystem performance under power consumption constraints.
  • the existing communication protocols for multi-die integration are either dedicated protocols with poor versatility, or the technical system is too complex and difficult to use. Under the condition that the multi-die interconnection bus protocol is immature, how to define a multi-die interconnection bus protocol that meets the current development needs of integrated circuits based on the reality of our country and the current level of technology is a key issue to break through the new generation of integrated microsystems .
  • the present invention provides a high-speed expansion system between bare cores, which is used for multi-protocol chip cascading and expansion, and can realize the cross-die interconnection and source synchronization of the core interface.
  • the high-speed expansion system between bare cores includes a cross-die expansion synchronizer and a direct connection path connected to the cross-die expansion synchronizer.
  • the cross-die expansion synchronizer is set on the bare core, and the die is synchronized through the cross-die expansion.
  • the inter-die extended synchronizer is used to control data transmission, the data includes: clock signal, reset signal, handshake signal and data signal, wherein all signals appear in pairs in differential form.
  • the cross-die expansion synchronizer includes a bidirectional LVDS, and the direct connection path is connected to the bidirectional LVDS.
  • the handshake signal is a VALID/READY handshake signal.
  • the data signal is a DATA data signal with a configurable bit width.
  • the clock signal is a source-synchronous clock signal.
  • a high-speed expansion method between die including the following steps:
  • the two-way LVDS is used for direct communication between bare chips.
  • the data includes clock signal, reset signal, handshake signal and data signal. All signals appear in pairs in differential form.
  • the bidirectional LVDS differentiates the clock signal, the reset signal, the data signal and the handshake signal to obtain two signals respectively, the two signals are received by an LVDS receiver, and the receiver determines the difference between the two signals to obtain Determine the data sent.
  • the clock signal is a source synchronous clock signal, wherein the differential clocks CPICLKb and CPICLKn at the input end of the bidirectional LVDS are both derived from the clocks CPOCLKb and CPOCLKn at the output end of another bidirectional LVDS connected thereto.
  • the present invention has the following beneficial effects:
  • the high-speed expansion system between bare cores provided by the invention has good versatility and low complexity, and realizes flexible expansion of interconnected bare cores, thereby forming a larger package-level network and laying a foundation for subsequent micro-system integration.
  • the high-speed expansion system between die is composed of two independent clock domain channels, each channel has an independent signal, and all signals appear in pairs in the form of differential signals, which satisfies the source synchronization characteristics of the cross-die interface and the cross-die mutual. connected high-speed communication.
  • Fig. 1 is the structural schematic diagram of interconnecting die and its interconnection
  • FIG. 2 is a schematic structural diagram of a high-speed expansion system between bare cores
  • Fig. 3 is the structural schematic diagram of the straight-through path
  • Figure 4 shows the generation and integration of differential signals.
  • the high-speed expansion system between bare cores includes a cross-die expansion synchronizer and a direct-connection path connected to the cross-die expansion synchronizer.
  • the cores are connected by a cross-die extended synchronizer and a direct path.
  • the cross-die extended synchronizer is used to control data transmission.
  • the data includes: clock signal, reset signal, handshake signal and data signal, all of which are in differential form. Comes in pairs.
  • Extending the synchronizer across the die includes bidirectional LVDS, and the direct path is connected to the bidirectional LVDS.
  • the handshake signal is a VALID/READY handshake signal.
  • the data signal is a DATA data signal with a configurable bit width.
  • the clock signal is a source-synchronous clock signal.
  • the interconnected die is a general standard die, which can easily realize data transmission, interface expansion and inter-die cascade.
  • a die-level network (Network on Die, NoD), which consists of routers and transmission buses.
  • the interconnected die mainly includes a protocol conversion circuit and an internal die-level network, and the protocol conversion circuit includes a plurality of protocol conversion modules for providing a variety of standard mainstream protocol interfaces connected to the outside; the internal die-level network
  • the network includes a transmission bus and a router, and the protocol conversion modules are respectively connected with the border nodes of the internal bare-core network for transmitting data packets from the interface.
  • NoD is used for data routing and high-speed transmission.
  • the protocol conversion circuit also converts the NoD protocol to the mainstream protocol for connection with other functional bare chips.
  • the cross-die extended synchronizer is arranged on the interconnected die to realize data transmission in different clock domains inside and outside the interconnected die, and the cross-die extended synchronizer is connected to a boundary node in the NoD to form a data transmission path.
  • the interconnecting die is connected by the high-speed expansion system between die.
  • the high-speed expansion system between die is also called the expansion bus CIBP (Chiplet Interconnect Bus on-Package). It is an expansion bus protocol between die and is used for multi-protocol chips. Cascading and scaling enable cross-die interconnection and cross-die interface source synchronization of the NoD (Network-on-Die) at the die level.
  • the direct path includes input channels and output channels.
  • the input channels include CPICLKb, CPICLKn, CPIRESETn, CPIVALID, CPIDATA and CPIREADY;
  • the output channels include CPOCLKb, CPOCLKn, CPOVALID, CPODATA and CPOREADY.
  • the expansion bus CIBP is used for the cross-die interconnection of NoD, and it needs to meet the source synchronization characteristics of the cross-die interface.
  • a configurable bidirectional LVDS low-voltage differential signal interface
  • the two direct-connection paths of CIBP are independent.
  • the channel composition of the clock domain, each channel has an independent clock, reset signal, VALID/READY handshake signal and DATA data signal with configurable bit width, and all signals appear in pairs in differential form.
  • Table 1 is the signal format for extending the synchronizer's data across the die
  • signal name bit width direction illustrate CPICLKb 1 enter CIBP input channel with differential clock 1
  • CPICLKn 1 enter CIBP input channel with differential clock 2
  • CPIVALID 2 enter CIBP input channel data valid
  • CPIDATA 2N enter CIBP input channel data
  • CPIREADY 2 output CIBP input channel data confirmation CPOCLKb 1 output CIBP output channel with differential clock 1 CPOCLKn 1 output CIBP output channel with differential clock 2
  • CPOVALID 2 output CIBP output channel data valid CPODATA 2N output CIBP output channel data
  • CPOREADY 2 enter CIBP output channel data confirmation
  • the expansion bus CIBP needs to meet the high-speed communication across the bare core interconnection.
  • the source synchronous clock used, and the differential clocks CPICLKb and CPICLKn of the input channel are derived from the output port clocks CPOCLKb and CPOCLKn of the channel connected to it.
  • its The local clock of the output channel generates the differential clocks CPOCLKb and CPOCLKn with the channel through the differentiator as the clock of the input channel of the port connected to it, and the data and handshake signals also adopt the form of differential signals.
  • the direct connection of the expansion bus CIBP is composed of two channels in independent clock domains, each channel has independent clock, reset signal, VALID, READY handshake signal and DATA data signal with configurable bit width, and all signals are differential Forms come in pairs. As shown in Figure 2 to Figure 4, all signals at the transmitting end generate corresponding differential signals through LVDS, and then send to the receiving end for integration of the differential signals.
  • the LVDS interface is divided into a driver (Driver) and a receiver (Receiver).
  • the LVDS driver differentiates the clock, reset, data and handshake signals to obtain two signals respectively.
  • the receiver receives, and the receiver determines the sent data by judging the difference between the two signals.
  • a high-speed expansion method between die including the following steps:
  • the two-way LVDS is used for direct communication between bare chips.
  • the data includes clock signal, reset signal, handshake signal and data signal. All signals appear in pairs in differential form.
  • Bidirectional LVDS differentiates the clock signal, reset signal, data signal and handshake signal to obtain two signals respectively.
  • the two signals are received by the LVDS receiver, and the receiver determines the sent data by judging the difference between the two signals. .
  • the clock signal is a source-synchronous clock signal, wherein the differential clocks CPICLKb and CPICLKn at the input end of the bidirectional LVDS are both derived from the clocks CPOCLKb and CPOCLKn at the output end of another bidirectional LVDS connected to it.

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Abstract

裸芯间高速扩展系统及其扩展方法，用于多协议芯片级联和扩展。裸芯间高速扩展系统包括跨裸芯扩展同步器和与跨裸芯扩展同步器连接的直连通路，跨裸芯扩展同步器设置在裸芯上，裸芯之间通过跨裸芯扩展同步器和直连通路连接，所述跨裸芯扩展同步器用于控制数据传输，所述数据包括：时钟信号、复位信号、握手信号和数据信号，其中，所有信号都以差分形式成对出现。该系统通用性好、复杂度低、实现了互连裸芯的灵活扩展，进而构成更大的封装级网络，为后续的微系统集成奠定了基础。

Description

裸芯间高速扩展系统及其扩展方法 技术领域
本发明涉及一种裸芯的扩张连接，尤其是裸芯间高速扩展系统及其扩展方法。
背景技术
在单片专用集成电路中，所有元件都是在一个硅片上用同一种工艺设计和制造的。随着工艺尺寸的缩小，开发这样的集成电路成本和开发周期变得极高。在此情况下，多裸芯集成是必然的选择。而多裸芯集成的难点在于如何高效互联各个裸芯，并保证在功耗约束下实现较高的微系统性能。目前已有的面向多裸芯集成的通信协议要么是专用协议，通用性较差，要么是技术体系过于庞杂难以使用。在多裸芯互联总线协议不成熟的情况下，如何基于我国的现实情况和现阶段技术水平，定义出符合目前集成电路发展需求的多裸芯互联总线协议是突破新一代集成微系统的关键问题。
发明内容
为解决上述问题，本发明提供一种裸芯间高速扩展系统，用于多协议芯片级联和扩展，可实现裸芯级网络NoD(Network-on-Die)的跨裸芯互连以及跨裸芯接口的源同步。
具体技术方案为：
裸芯间高速扩展系统，包括跨裸芯扩展同步器和与跨裸芯扩展同步器连接的直连通路，跨裸芯扩展同步器设置在裸芯上，裸芯之间通过跨裸芯扩展同步器和直连通路连接，所述跨裸芯扩展同步器用于控制数据传输，所述数据包括：时钟信号、复位信号、握手信号和数据信号，其中，所有信号都以差分形式成对出现。
优选的，所述跨裸芯扩展同步器包括双向LVDS，所述直连通路与所述双向LVDS连接。
优选的，所述握手信号为VALID/READY握手信号。
优选的，所述数据信号为位宽可配置的DATA数据信号。
优选的，所述时钟信号为源同步时钟信号。
裸芯间高速扩展方法，包括以下步骤：
裸芯间采用双向LVDS进行直连通信，数据包括时钟信号、复位信号、握手信号和数据信号，所有信号都以差分形式成对出现。
优选的，所述双向LVDS将时钟信号、复位信号、数据信号和握手信号进行差分，分别得到两路信号，所述两路信号由LVDS接收器接收，接收器通过判断两路信号的差值来确定所发送的数据。
优选的，所述时钟信号为源同步时钟信号，其中双向LVDS的输入端的随路差分时钟CPICLKb和CPICLKn均来自于与之相连的另一个双向LVDS的输出端的时钟CPOCLKb、CPOCLKn。
与现有技术相比本发明具有以下有益效果：
本发明提供的裸芯间高速扩展系统通用性好、复杂度低、实现了互连裸芯的灵活扩展，进而构成更大的封装级网络，为后续的微系统集成奠定了基础。裸芯间高速扩展系统由两个独立时钟域的通道构成，每个通道具有独立的信号，所有信号都以差分信号形式成对出现，满足了跨裸芯接口的源同步特性以及跨裸芯互连的高速通信。
附图说明
图1是互联裸芯及其相互连接的结构示意图；
图2是裸芯间高速扩展系统的结构示意图；
图3是直连通路的结构示意图；
图4是差分信号的生成与整合。
具体实施方式
现结合附图对本发明作进一步说明。
实施例一
如图1至图4所示，裸芯间高速扩展系统，包括跨裸芯扩展同步器和与跨裸芯扩展同步器连接的直连通路，跨裸芯扩展同步器设置在裸芯上，裸芯之间通过跨裸芯扩展同步器和直连通路连接，跨裸芯扩展同步器用于控制数据传输，数据包括：时钟信号、复位信号、握手信号和数据信号，其中，所有信号都以差分形式成对出现。
跨裸芯扩展同步器包括双向LVDS，直连通路与双向LVDS连接。
握手信号为VALID/READY握手信号。
数据信号为位宽可配置的DATA数据信号。
时钟信号为源同步时钟信号。
如图1所示，互联裸芯是一种通用标准裸芯，它能够方便地实现数据传输、接口扩展和裸芯间级联。互联裸芯的内部是一个裸芯级网络(Network on Die，NoD)，它由路由器和传输总线组成。具体的，互联裸芯主要包括协议转换电路和内部裸芯级网络，所述协议转换电路包括多个协议转换模块，用于提供多种与外部连接的标准主流协议接口；所述内部裸芯级网络包括传输总线和路由器，协议转换模块均分别与内部裸芯级网络的边界节点连接，用于传输来自接口的数据包。NoD用于数据路由和高速传输。协议转换电路同时将NoD协议转换到主流协议，用于与其他功能裸芯连接。
跨裸芯扩展同步器设置在互联裸芯上，实现互联裸芯内外不同时钟域的数据传输，跨裸芯扩展同步器与NoD中的一个边界节点连接，从而形成数据传输路径。
互联裸芯之间通过裸芯间高速扩展系统连接，裸芯间高速扩展系统也称为扩展总线CIBP(Chiplet Interconnect Bus on-Package)，是一种裸芯间扩展总线协议，用于多协议芯片级联和扩展，可实现裸芯级网络NoD(Network-on-Die)的跨裸芯互连以及跨裸芯接口的源同步。
直连通路包括输入通道和输出通道，输入通道包括CPICLKb、CPICLKn、CPIRESETn、CPIVALID、CPIDATA和CPIREADY；输出通道包括CPOCLKb、CPOCLKn、CPOVALID、CPODATA和CPOREADY。
扩展总线CIBP用于NoD的跨裸芯互连，需要满足跨裸芯接口的源同步特性，对于直连通路采用可配置双向LVDS(低电压差分信号接口)，CIBP的直连通路由两个处于独立时钟域的通道构成，每个通道具有独立的时钟、复位信号，以及VALID/READY握手信号和位宽可配置的DATA数据信号，并且所有信号都以差分形式成对出现。
表1是跨裸芯扩展同步器的数据的信号格式
信号名 位宽 方向 说明
CPICLKb 1 输入 CIBP输入通道随路差分时钟1
CPICLKn 1 输入 CIBP输入通道随路差分时钟2
CPIVALID 2 输入 CIBP输入通道数据有效
CPIDATA 2N 输入 CIBP输入通道数据
CPIREADY 2 输出 CIBP输入通道数据确认
CPOCLKb 1 输出 CIBP输出通道随路差分时钟1
CPOCLKn 1 输出 CIBP输出通道随路差分时钟2
CPOVALID 2 输出 CIBP输出通道数据有效
CPODATA 2N 输出 CIBP输出通道数据
CPOREADY 2 输入 CIBP输出通道数据确认
扩展总线CIBP需要满足跨裸芯互连的高速通信，采用的源同步时钟，其输入通道的随路差分时钟CPICLKb、CPICLKn均来自于与之相连通道的输出端口时钟CPOCLKb、CPOCLKn；同样的，其输出通道的本地时钟经过差分器生成随路差分时钟CPOCLKb、CPOCLKn作为与之相连端口的输入通道的时钟，并且数据与握手信号也采用了差分信号形式。
扩展总线CIBP的直连通路由两个处于独立时钟域的通道构成，每个通道具有独立的时钟、复位信号，以及VALID、READY握手信号和位宽可配置的DATA数据信号，并且所有信号都以差分形式成对出现。如图2至图4所示，发送端所有信号经过LVDS生成对应的差分信号，然后发送给接收端由其进行差分信号的整合。
如图2至图4所示，LVDS接口分为驱动器(Driver)和接收器(Receiver)，LVDS驱动器将时钟、复位、数据和握手信号等进行差分分别得到两路信号，这两路信号由LVDS接收器接收，接收器通过判断两路信号的差值来确定所发送的数据。
实施例二
裸芯间高速扩展方法，包括以下步骤：
裸芯间采用双向LVDS进行直连通信，数据包括时钟信号、复位信号、握手信号和数据信号，所有信号都以差分形式成对出现。
双向LVDS将时钟信号、复位信号、数据信号和握手信号进行差分，分别得到两路信号，所述两路信号由LVDS接收器接收，接收器通过判断两路信号的差值来确定所发送的数据。
时钟信号为源同步时钟信号，其中双向LVDS的输入端的随路差分时钟CPICLKb和CPICLKn均来自于与之相连的另一个双向LVDS的输出端的时钟 CPOCLKb和CPOCLKn。
以上结合具体实施例描述了本发明的技术原理。这些描述只是为了解释本发明的原理，而不能以任何方式解释为对本发明保护范围的限制。基于此处的解释，本领域的技术人员不需要付出创造性的劳动即可联想到本发明的其它具体实施方式，这些方式都将落入本发明权利要求的保护范围之内。

Claims (8)

  1. 裸芯间高速扩展系统，其特征在于，包括跨裸芯扩展同步器和与跨裸芯扩展同步器连接的直连通路，跨裸芯扩展同步器设置在裸芯上，裸芯之间通过跨裸芯扩展同步器和直连通路连接，所述跨裸芯扩展同步器用于控制数据传输，所述数据包括：时钟信号、复位信号、握手信号和数据信号，其中，所有信号都以差分形式成对出现。
  2. 根据权利要求1所述的裸芯间高速扩展系统，其特征在于，所述跨裸芯扩展同步器包括双向LVDS，所述直连通路与所述双向LVDS连接。
  3. 根据权利要求1所述的裸芯间高速扩展系统，其特征在于，所述握手信号为VALID/READY握手信号。
  4. 根据权利要求1所述的裸芯间高速扩展系统，其特征在于，所述数据信号为位宽可配置的DATA数据信号。
  5. 根据权利要求1所述的裸芯间高速扩展系统，其特征在于，所述时钟信号为源同步时钟信号。
  6. 裸芯间高速扩展方法，其特征在于，包括以下步骤：
    裸芯间采用双向LVDS进行直连通信，数据包括时钟信号、复位信号、握手信号和数据信号，所有信号都以差分形式成对出现。
  7. 根据权利要求6所述的裸芯间高速扩展方法，其特征在于，所述双向LVDS将时钟信号、复位信号、数据信号和握手信号进行差分，分别得到两路信号，所述两路信号由LVDS接收器接收，接收器通过判断两路信号的差值来确定所发送的数据。
  8. 根据权利要求6所述的裸芯间高速扩展方法，其特征在于，所述时钟信号为源同步时钟信号，其中双向LVDS的输入端的随路差分时钟CPICLKb和CPICLKn均来自于与之相连的另一个双向LVDS的输出端的时钟CPOCLKb、CPOCLKn。
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