WO2022163504A1 - 発光装置 - Google Patents
発光装置 Download PDFInfo
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- WO2022163504A1 WO2022163504A1 PCT/JP2022/002088 JP2022002088W WO2022163504A1 WO 2022163504 A1 WO2022163504 A1 WO 2022163504A1 JP 2022002088 W JP2022002088 W JP 2022002088W WO 2022163504 A1 WO2022163504 A1 WO 2022163504A1
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- 239000003990 capacitor Substances 0.000 claims abstract description 147
- 239000007787 solid Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims description 77
- 230000003071 parasitic effect Effects 0.000 description 39
- 238000010586 diagram Methods 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 9
- 239000002344 surface layer Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/32—Pulse-control circuits
- H05B45/325—Pulse-width modulation [PWM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0239—Combinations of electrical or optical elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0428—Electrical excitation ; Circuits therefor for applying pulses to the laser
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/40—Details of LED load circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
- H05B47/16—Controlling the light source by timing means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0233—Mounting configuration of laser chips
- H01S5/02345—Wire-bonding
Definitions
- the present invention relates to a light-emitting device that drives a solid-state light-emitting device such as a laser diode, and more particularly to a light-emitting device that effectively obtains short-pulse, high-peak light emission.
- FIG. 12(A) is a plan view of the light emitting device 100 disclosed in Patent Document 1
- FIG. 12(B) is a cross-sectional view taken along line II in FIG. 12(A).
- FIG. 13 is a circuit diagram of the light emitting device 100. As shown in FIG.
- a light-emitting device 100 disclosed in Patent Document 1 includes a capacitor 10, a solid-state light-emitting element 20 that emits light when power is supplied from the capacitor 10, and a semiconductor switch element 30 that controls power supply from the capacitor 10 to the solid-state light-emitting element 20. and A solid-state light-emitting element 20 is mounted on the outer surface of the capacitor 10, and a semiconductor switch element 30 is provided on the outer surface or inside the capacitor 10. As shown in FIG. A connection electrode 32 is formed between the external electrodes 11 and 12 to connect the solid state light emitting element 20 and the semiconductor switch element 30 in series.
- Capacitor 10 comprises internal electrodes 14 and 15 formed on dielectric ceramic layer 13 .
- a gate extraction electrode 31 and wirings 21 and 33 are formed on the upper surface of the light emitting device 100 .
- the light-emitting part 22 is provided on the side of the solid-state light-emitting device 20 .
- the closed loop connecting the semiconductor switch device 30, the solid-state light-emitting device 20, and the capacitor 10 is configured to be short, thereby allowing the current path to A closed-loop parasitic impedance is reduced, and high peak and short pulse light is emitted.
- the emitted light power can be increased by increasing the input voltage (the voltage charged to the capacitor 10 in FIG. 13).
- the input voltage the voltage charged to the capacitor 10 in FIG. 13.
- a booster circuit is separately provided to increase the input voltage, the circuit becomes complicated and the number of parts increases, which causes an increase in cost.
- application of a high voltage widens the pulse width of emitted light, which poses a problem for applications that require a short pulse width and a high instantaneous peak.
- an object of the present invention is to provide a light-emitting device that effectively obtains short-pulse, high-peak light emission.
- a light-emitting device as an example of the present disclosure includes a solid-state light-emitting element, a driving capacitor, and a switching element, which are formed or mounted on substrates, respectively, and the switching element is turned on to transfer the charge of the driving capacitor to the solid-state light-emitting element.
- a driving current loop for discharging is formed, and the driving capacitor is composed of a plurality of capacitors connected in parallel for accumulating driving charges for the solid-state light emitting device, each capacitor among the plurality of capacitors and the solid-state light emitting device.
- a plurality of drive current loops are configured by the device and the switch device, and the time constants of the plurality of discharge paths respectively configured by the plurality of capacitors and the plurality of drive current loops are uniform. .
- each capacitor out of the plurality of capacitors, the solid-state light-emitting element, and the switching element constitute a plurality of drive current loops, so the combined impedance of the parasitic impedances of the plurality of closed loops, which are the current paths, is reduced. be.
- the time constants of the plurality of discharge paths formed by the plurality of capacitors and the plurality of drive current loops are reduced.
- a light-emitting device that obtains short-pulse, high-peak light emission is constructed.
- FIG. 1 is a plan view of a light emitting device 101 according to the first embodiment.
- 2A is a cross-sectional view taken along the line AA in FIG. 1
- FIG. 2B is a cross-sectional view taken along the line BB in FIG.
- FIG. 3A is a circuit diagram of the light emitting device 101.
- FIG. 3B is an overall circuit diagram of the light emitting device 101 connected to a driving power source.
- FIG. 4 is a waveform diagram of the drive current (drain current of the switch element Q1) flowing through the solid-state light emitting element LD1 when the switch element Q1 is turned on.
- FIG. 5 is a circuit diagram of a light emitting device with n driving capacitors.
- FIG. 6A is an equivalent circuit diagram of the circuit shown in FIG.
- FIG. 6B is a circuit diagram showing the equivalent circuit of FIG. 6A as an LCR circuit.
- FIG. 7 is a plan view of the light emitting device according to the second embodiment.
- FIG. 8 is a plan view of a light emitting device 103A according to the third embodiment.
- FIG. 9 is a plan view of another light emitting device 103B according to the third embodiment.
- FIG. 10 has a parasitic inductance component of 100 pH and a parasitic resistance component of 0.5 ⁇ as the parasitic impedance present in the path from the switching element Q1 to the drive capacitor C1, and the parasitic impedance present in the path from the switch element Q1 to the drive capacitor C2.
- FIG. 12A is a plan view of the light emitting device 100 disclosed in Patent Document 1
- FIG. 12B is a cross-sectional view taken along line II in FIG. 12A
- FIG. 13 is a circuit diagram of the light emitting device 100. As shown in FIG.
- FIG. 1 is a plan view of a light emitting device 101 according to the first embodiment.
- 2A is a cross-sectional view taken along the line AA in FIG. 1
- FIG. 2B is a cross-sectional view taken along the line BB in FIG.
- This light-emitting device 101 includes a solid-state light-emitting element LD1, two drive capacitors C1 and C2, and a switch element Q1 formed on a substrate 1.
- the thick arrows in FIGS. 1 and 2(B) indicate the light emitting direction of the solid state light emitting device LD1.
- the switch element Q1 when turned on, it forms a drive current loop that discharges the charges in the drive capacitors C1 and C2 to the solid state light emitting element LD1.
- the drive capacitors C1 and C2 are connected in parallel with each other and store drive charges for the solid-state light emitting device LD1.
- a first drive current loop is configured by the drive capacitor C1, the solid state light emitting element LD1, and the switch element Q1
- a second drive current loop is configured by the drive capacitor C2, the solid state light emitting element LD1, and the switch element Q1.
- the driving capacitors C1 and C2 are formed at positions that do not overlap the solid state light emitting device LD1 and the switching device Q1.
- the driving capacitors C1 and C2 are substantially equal, and the driving capacitors C1 and C2 are formed at positions substantially equidistant from the solid state light emitting device LD1.
- upper conductor patterns 6A and 6B are formed on the surface layer of the substrate 1, and lower conductor patterns 8A, 8B and 8C are formed inside.
- the substrate 1 is, for example, a silicon substrate, and the upper conductor patterns 6A, 6B and the lower conductor patterns 8A, 8B, 8C are, for example, Al patterns or Cu patterns.
- the upper conductor patterns 6A, 6B and the lower conductor patterns 8A, 8B, 8C are separated by several ⁇ m.
- drive capacitors C1 and C2 are provided between the lower conductor patterns 8A and 8B and the upper conductor patterns 6A and 6B.
- an interlayer connection conductor 7 is formed between the lower conductor pattern 8C and the switch element Q1. This interlayer connection conductor 7 connects one end (source terminal shown later) of the switch element Q1 and the lower conductor pattern 8C.
- an upper conductor pattern 6C is formed on the surface layer of the substrate 1.
- a solid light emitting device LD1 is mounted on the top of the upper conductor pattern 6C.
- Light-emitting element connection conductors 4A and 4B are formed by conductor patterns from the top surfaces of the upper conductor patterns 6A and 6B to the top surface of the solid-state light-emitting element LD1.
- the other end (drain terminal shown later) of the switch element Q1 is connected to the upper conductor pattern 6C.
- the upper conductor patterns 6A, 6B correspond to the "upper conductor pattern” according to the present invention
- the lower conductor patterns 8A, 8B correspond to the "lower conductor pattern” according to the present invention.
- FIG. 3A is a circuit diagram of the light emitting device 101.
- FIG. FIG. 3B is an overall circuit diagram of the light emitting device 101 connected to a driving power source.
- the light-emitting device 101 has a solid-state light-emitting element LD1 and a switching element Q1 connected in series.
- the solid state light emitting device LD1 is a laser diode and the switching device Q1 is a MOS-FET.
- a drive capacitor C1 is connected in parallel to the series circuit of the solid-state light-emitting element LD1 and the switch element Q1.
- a drive capacitor C2 is connected in parallel with the drive capacitor C1.
- the light-emitting device 101 forms a drive current loop that discharges the charges in the drive capacitors C1 and C2 to the solid-state light-emitting element LD1 by turning on the switch element Q1.
- parasitic impedance ZpA is parasitic impedance formed by upper conductor pattern 6A and lower conductor pattern 8A.
- parasitic impedance ZpB is a parasitic impedance formed by the upper conductor pattern 6B and the lower conductor pattern 8B.
- a parasitic impedance ZpC is a parasitic impedance formed by the upper conductor pattern 6C and the lower conductor pattern 8C.
- FIG. 3(B) also shows the constant-voltage power source E1 and the resistance element R1 inserted in the path through which the current from the constant-voltage power source E1 flows. If the switch element Q1 is in the OFF state, the driving capacitors C1 and C2 are charged by the constant voltage power source E1. When the switch element Q1 is turned on, the drive current flows through the path indicated by the arrow in FIG. 3(A).
- the drive capacitors C1 and C2 are substantially equal, and the drive capacitors C1 and C2 are formed at positions substantially equidistant from the solid state light emitting device LD1. Therefore, as shown in FIG. 3A, the upper conductor patterns 6A and 6B connecting one end (anode) of the solid state light emitting device LD1 and one end of the drive capacitors C1 and C2 are substantially equal in length, and the solid state light emitting devices have substantially the same length.
- the lengths of the lower conductor patterns 8A, 8B connecting the other end (cathode) of the element LD1 and the other ends of the drive capacitors C1, C2 are substantially equal.
- the parasitic impedances of the upper conductor patterns 6A, 6B are substantially equal, and the parasitic impedances of the lower conductor patterns 8A, 8B are substantially equal. Therefore, the parasitic impedances ZpA and ZpB shown in FIG. 3B are substantially equal.
- the closed loop discharge time constant of the driving capacitor C1, the parasitic impedances ZpA and ZpC, the solid light emitting element LD1 and the switch element Q1, and the closed loop of the driving capacitor C2, the parasitic impedances ZpB and ZpC, the solid light emitting element LD1 and the switch element Q1 is substantially equal to the discharge time constant of
- the drive capacitors C1 and C2 are substantially equal.
- the capacitances of the drive capacitors C1 and C2 are uniform to the extent that there is no significant collapse in the output light waveform.
- the drive capacitors C1 and C2 should be aligned within ⁇ 50% of their average value.
- the drive capacitors C1 and C2 are formed at positions substantially equidistant from the solid-state light-emitting device LD1" means that "the drive capacitors C1 and C2 are formed to the extent that there is no significant distortion in the output light waveform.” It is arranged at a position equidistant from the solid-state light emitting device LD1.” For example, the driving capacitors C1 and C2 are aligned so that the distance from the solid state light emitting device LD1 is within ⁇ 50% of their average value.
- FIG. 10 has a parasitic inductance component of 100 pH and a parasitic resistance component of 0.5 ⁇ as the parasitic impedance present in the path from the switching element Q1 to the drive capacitor C1, and the parasitic impedance present in the path from the switch element Q1 to the drive capacitor C2.
- It is a circuit diagram having a parasitic inductance component of 100 pH and a parasitic resistance component of 0.5 ⁇ as impedance.
- Table 1 shows examples of variations in the values of the driving capacitors C1 and C2.
- FIG. 11 shows that the waveform of the driving current (waveform similar to the optical waveform of the light emitted from the laser diode LD) collapses by using the driving capacitors C1 and C2 exceeding the range of ⁇ 50% with the parameters shown in Table 1.
- a silicon substrate is used as the substrate 1, and the upper conductor patterns 6A, 6B and the lower conductor patterns 8A, 8B, 8C are provided at intervals of several ⁇ m. , 8B and 8C can reduce the area of the current loop. Therefore, the equivalent series inductance ESL due to the current loop can be reduced.
- FIG. 4 is a waveform diagram of the drive current (drain current of the switch element Q1) flowing through the solid-state light emitting element LD1 when the switch element Q1 is turned on.
- Waveform A in FIG. 4 is the waveform of the light emitting device 101 of this embodiment
- waveform B in FIG. 4 is the waveform of the light emitting device as a comparative example.
- the light emitting device of this comparative example is provided with only the driving capacitor C1 shown in FIGS. 1, 3A, and 3B as the driving capacitor.
- the light emitting device of the comparative example has a peak value of about 60 A and a half width of about 0.65 ns.
- the peak value is 90 A and the half width is about 0.4 ns.
- the light emitting device 101 of the present embodiment can obtain short-pulse, high-peak light emission.
- the capacitance per drive capacitor C1, C2 is reduced by the amount corresponding to the increase in current paths, so the parasitic impedance per capacitance is reduced.
- the light emitting device 101 of this embodiment not only has a small parasitic impedance, but also has substantially the same discharge time constants of the two closed loops including the two drive capacitors C1 and C2. As a result, the transient characteristics of the drive current flowing through the solid state light emitting device LD1 via the drive capacitor C1 and the drive current flowing through the solid state light emitting device LD1 via the drive capacitor C2 are uniform, and the pulse width of the drive current is broadened. Suppressed.
- the capacitances of a plurality of capacitors are substantially equal means that they are aligned within a range of ⁇ 50% from their average value, for example.
- the fact that the plurality of drive current loops are substantially equal means that they are aligned within a range of ⁇ 50% from their average value, for example. Within this range, there is no significant distortion in the output light waveform.
- the capacitances of the drive capacitors C1, C2 are substantially equal, and the two closed loops containing the drive capacitors C1, C2, respectively, are substantially equal in magnitude, thereby containing the drive capacitors C1, C2, respectively.
- An example is shown in which the discharge time constants of the two closed loops are substantially equal.
- the closed loops may be sized accordingly so that the discharge time constants of the closed loops, each including the driving capacitors, are substantially equal. .
- a light-emitting device capable of obtaining short-pulse, high-peak light emission is constructed.
- FIGS. 1 to 4 show the light emitting device including two drive capacitors C1 and C2, the light emitting device may include three or more drive capacitors.
- FIG. 5 is a circuit diagram of a light-emitting device with n driving capacitors.
- One end (anode) of the solid-state light emitting device LD1 and one end of the drive capacitors C1, C2, . . . Cn are connected via upper conductor patterns 6A, 6B, .
- Each capacitance of drive capacitors C1, C2, . . . Cn is substantially equal. Also, the drive capacitors C1, C2, .
- the drive capacitors C1, C2, ..., Cn are substantially equal
- the capacitances of the drive capacitors C1, C2, ..., Cn are aligned to the extent that there is no significant distortion in the output light waveform.” It means “there is”.
- the drive capacitors C1, C2, . . . Cn should be aligned within ⁇ 50% of their average value.
- the driving capacitors C1, C2, . This means that the capacitors C1, C2, .
- the other end of the drive capacitors C1, C2, . . . Cn and the source of the switch element Q1 are connected via the lower conductor pattern 8.
- the switch element Q1 and the solid state light emitting element LD1 can be arranged close to each other, and the drive capacitors C1, C2, . . . . . , Cn are also formed at positions substantially equidistant from the switch element Q1.
- FIG. 6A is an equivalent circuit diagram of the circuit shown in FIG. 3A.
- capacitor C is a capacitor having a combined capacitance of drive capacitors C1 and C2
- equivalent series resistance ESR is the resistance components of parasitic impedances ZpA, ZpB, and ZpC shown in FIG.
- the series inductance ESL is an inductance component of the parasitic impedances ZpA, ZpB and ZpC shown in FIG. 3(B).
- Load corresponds to the resistance component of the solid state light emitting device LD1.
- FIG. 6B is a circuit diagram showing the equivalent circuit of FIG. 6A as an LCR circuit.
- the resistance value of resistance element R is the combined resistance value of Load and ESR
- the inductance of inductor L is the inductance of ESL.
- the state after the switch element Q1 is turned on can be expressed by the following equation (1).
- Equation (2) derive i(t) from the formula. First, both sides of equation (2) are differentiated with respect to t.
- the pulse width is 1/2 of the cycle of this sine wave. From this, the pulse width is given by the following equation.
- the pulse width and the inductance L have a monotonically increasing relationship.
- the pulse width Tpuls and the resistance value R also have a monotonically increasing relationship.
- the reduction of L and the reduction of R make it possible to supply a current with a short pulse width.
- the inductance L in the equation (5) corresponds to the equivalent series inductance ESL, and the resistive element R in the equation (5) includes ESR, which is a parasitic resistance. Therefore, the pulse width can be shortened by reducing the ESR.
- the capacitance of the capacitor C and the initial voltage are constant, the pulse width and the peak value of the drive current are negatively correlated. .
- FIG. 7 is a plan view of the light emitting device according to the second embodiment.
- This light-emitting device 102 includes a solid-state light-emitting element LD1, two drive capacitors C1 and C2, and a switch element Q1 mounted on a substrate 1.
- FIG. LD1 solid-state light-emitting element LD1
- LD2 two drive capacitors C1 and C2
- switch element Q1 mounted on a substrate 1.
- Lower conductor patterns 8A, 8B, and 8C are formed on the lower layer of the substrate 1. Interlayer connection conductors are mounted between the ends of the lower conductor patterns 8A, 8B and the lower surface electrodes of the drive capacitors C1, C2, respectively. As a result, the bottom electrodes of the drive capacitors C1 and C2 are connected to the ends of the bottom conductor patterns 8A and 8B, respectively. An end of the lower conductor pattern 8C is connected to the source electrode of the switch element Q1.
- An upper conductor pattern 6 is formed on the upper surface of the substrate 1 .
- a first end of the upper conductor pattern 6 is connected to the cathode electrode of the solid light emitting device LD1.
- a second end of the upper conductor pattern 6 is connected to the drain of the switch element Q1.
- the upper electrodes of the driving capacitors C1 and C2 and the upper electrode (anode electrode) of the solid light emitting device LD1 are connected via wires 5A and 5B.
- the third embodiment shows several examples of the positional relationship between the driving capacitors and the solid-state light emitting device LD1.
- FIG. 8 is a plan view of a light emitting device 103A according to the third embodiment.
- This light-emitting device 103A includes a solid-state light-emitting element LD1, two drive capacitors C1 and C2, and a switch element Q1 mounted on a substrate 1, respectively.
- Conductor patterns 2A, 2B, and 3 are formed on the surface layer of the substrate 1.
- Drive capacitors C1 and C2 are mounted on the first ends of the conductor patterns 2A and 2B, respectively. Thereby, the lower surface electrodes of the drive capacitors C1 and C2 are connected to the first ends of the conductor patterns 2A and 2B, respectively.
- a solid-state light-emitting device LD1 is mounted on the first end of the conductor pattern 3.
- a first end of the solid-state light emitting device LD1 and one end (drain terminal) of the switching device Q1 are connected via a conductor pattern 3 .
- a switch element Q1 is mounted on the second ends of the conductor patterns 2A and 2B and the second end of the conductor pattern 3. As shown in FIG. A second end of each of the conductor patterns 2A and 2B is connected to one end (source terminal) of the switch element Q1.
- the upper electrodes of the drive capacitors C1 and C2 and the upper electrode of the solid light emitting device LD1 are connected via wires 5A and 5B.
- the capacitances of drive capacitors C1 and C2 are substantially equal.
- the driving capacitors C1 and C2 are formed at substantially equidistant positions from the solid state light emitting device LD1.
- the drive capacitors C1 and C2 are connected in parallel with each other and store drive charges for the solid-state light emitting device LD1.
- a drive current loop is formed by the drive capacitor C1, the solid state light emitting element LD1, and the switch element Q1, and a drive current loop is formed by the drive capacitor C2, the solid state light emitting element LD1, and the switch element Q1.
- the conductor pattern may be formed only on the surface layer of the substrate.
- FIG. 9 is a plan view of another light emitting device 103B according to the third embodiment.
- This light-emitting device 103B includes a solid-state light-emitting element LD1, four drive capacitors C1, C2, C3, C4, and a switch element Q1 mounted on a substrate 1, respectively.
- Conductor patterns 2A, 2B, 2C, 2D, and 3 are formed on the surface layer of the substrate 1.
- Drive capacitors C1, C2, C3 and C4 are mounted on the first ends of the conductor patterns 2A, 2B, 2C and 2D, respectively.
- the lower surface electrodes of the drive capacitors C1, C2, C3 and C4 are connected to the first ends of the conductor patterns 2A, 2B, 2C and 2D, respectively.
- a solid-state light-emitting device LD1 is mounted on the first end of the conductor pattern 3.
- a first end of the solid-state light emitting device LD1 and one end (drain terminal) of the switching device Q1 are connected via a conductor pattern 3 .
- a second end of each of the conductor patterns 2A, 2B, 2C, 2D is connected to one end (source terminal) of the switch element Q1.
- the upper electrodes of the drive capacitors C1, C2, C3, C4 and the upper electrode of the solid-state light emitting device LD1 are connected via wires 5A, 5B, 5C, 5D.
- the drive capacitors C1, C2, C3, and C4 are connected in parallel with each other, and store drive charges for the solid-state light emitting device LD1.
- a drive current loop is formed by the drive capacitor C1, the solid state light emitting element LD1, and the switch element Q1
- a drive current loop is formed by the drive capacitor C2, the solid state light emitting element LD1, and the switch element Q1, and the drive capacitor C3 and the solid state light emitting element LD1 are formed.
- the switch element Q1 form a drive current loop
- the drive capacitor C4, the solid-state light emitting element LD1, and the switch element Q1 form a drive current loop.
- the capacitances of the drive capacitors C1, C2, C3 and C4 are substantially equal. Further, the drive capacitors C1, C2, C3, C4 are formed at substantially equidistant positions from the solid state light emitting device LD1. Therefore, the lengths of the wires 5A, 5B, 5C, 5D connecting the solid state light emitting device LD1 and the drive capacitors C1, C2, C3, C4 are substantially equal, and their parasitic impedances are substantially equal.
- the switching element Q1 and the solid-state light emitting element LD1 are relatively distant, the distance from the switching element Q1 to the driving capacitors C1 and C4 is different from the distance from the switching element Q1 to the driving capacitors C2 and C3. .
- the line width of the lower conductor pattern 8 can be easily increased, their parasitic impedances can be made relatively small. This makes it possible to match the discharge time constants of the closed loops including the drive capacitors.
- solid-state light-emitting devices such as light-emitting diodes and organic EL can be similarly applied.
- the light emitting device provided with a single solid state light emitting element LD1 was shown, but a plurality of solid state light emitting elements may be provided.
- a light emitting device having an individual chip-shaped drive capacitor was shown. may be configured.
- the switch element may be configured on a part of the semiconductor substrate.
- the light-emitting device in which the solid-state light-emitting element LD1 is mounted on the substrate is shown, but the solid-state light-emitting element may be formed on a part of the semiconductor substrate.
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Abstract
Description
図1は第1の実施形態に係る発光装置101の平面図である。図2(A)は図1におけるA-A部分での断面図であり、図2(B)は図1におけるB-B部分での断面図である。
第2の実施形態では、第1の実施形態で示した例とは複数の駆動キャパシタと固体発光素子LD1との位置関係が異なる発光装置について例示する。
第3の実施形態では、複数の駆動キャパシタと固体発光素子LD1との位置関係についての幾つかの例を示す。
C1,C2,C3,C4…駆動キャパシタ
E1…定電圧電源
ESL…等価直列インダクタンス
ESR…等価直列抵抗
L…インダクタ
LD1…固体発光素子
Q1…スイッチ素子
R,R1…抵抗素子
ZpA,ZpB,ZpC…寄生インピーダンス
1…基板
2A,2B,2C,2D…導体パターン
3…導体パターン
4A,4B…発光素子接続導体
5A,5B,5C,5D…ワイヤ
6,6A,6B,6C…上部導体パターン
7…層間接続導体
8,8A,8B,8C…下部導体パターン
10…コンデンサ
11,12…外部電極
20…固体発光素子
30…半導体スイッチ素子
32…接続電極
100,101,102,103A,103B…発光装置
Claims (7)
- それぞれ基板に形成又は搭載された、固体発光素子、駆動キャパシタ及びスイッチ素子を備え、
前記スイッチ素子はターンオンにより、前記駆動キャパシタの充電電荷を前記固体発光素子へ放電させる駆動電流ループを形成し、
前記駆動キャパシタは、前記固体発光素子に対する駆動電荷をそれぞれ蓄積する互いに並列接続された複数のキャパシタで構成され、
前記複数のキャパシタのうちの各キャパシタ、前記固体発光素子、及び前記スイッチ素子によって複数の駆動電流ループが構成され、
前記複数のキャパシタと前記複数の駆動電流ループとでそれぞれ構成される複数の放電経路の時定数が揃っている、
発光装置。 - 前記複数の放電経路の時定数が揃っていることにより、
前記複数のキャパシタを単一であるとした場合の前記固体発光素子の発光パルス幅より発光パルス幅が狭い、
請求項1に記載の発光装置。 - 前記複数の放電経路の時定数は、それらの平均値から±50%の範囲内で揃っている、
請求項1又は2に記載の発光装置。 - 前記複数のキャパシタのキャパシタンスはそれぞれ実質的に等しく、
前記複数の駆動電流ループはそれぞれ実質的に等しい、
請求項1又は2に記載の発光装置。 - 前記複数のキャパシタのキャパシタンスは、それらの平均値から±50%の範囲内で揃っていて、
前記複数のキャパシタから前記固体発光素子までの距離は、それらの平均値から±50%の範囲内で揃っている、
請求項4に記載の発光装置。 - 前記複数のキャパシタは、前記固体発光素子及び前記スイッチ素子とは重ならない位置に形成された、
請求項1から5のいずれかに記載の発光装置。 - 前記基板は上部導体パターン及び下部導体パターンを備え、
前記スイッチ素子の第1端と前記固体発光素子の第1端とは、前記上部導体パターンに接続されていて、前記スイッチ素子の第2端は前記下部導体パターンに接続されていて、前記上部導体パターンと前記下部導体パターンとの間に前記複数のキャパシタが設けられている、
請求項1から6のいずれかに記載の発光装置。
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JP2022578311A JP7485097B2 (ja) | 2021-01-29 | 2022-01-21 | 発光装置 |
DE112022000325.1T DE112022000325T5 (de) | 2021-01-29 | 2022-01-21 | Leuchtvorrichtung |
CN202280012024.1A CN116830407A (zh) | 2021-01-29 | 2022-01-21 | 发光装置 |
US18/361,230 US20230371146A1 (en) | 2021-01-29 | 2023-07-28 | Light-emitting device |
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Citations (3)
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US20020181533A1 (en) * | 2001-03-30 | 2002-12-05 | Vail Edward C. | High speed modulation of arrayed lasers |
JP2018019044A (ja) * | 2016-07-29 | 2018-02-01 | パイオニア株式会社 | 光源駆動装置および距離測定装置 |
JP2020126979A (ja) * | 2019-02-06 | 2020-08-20 | 富士ゼロックス株式会社 | 発光装置、光学装置および情報処理装置 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20020181533A1 (en) * | 2001-03-30 | 2002-12-05 | Vail Edward C. | High speed modulation of arrayed lasers |
JP2018019044A (ja) * | 2016-07-29 | 2018-02-01 | パイオニア株式会社 | 光源駆動装置および距離測定装置 |
JP2020126979A (ja) * | 2019-02-06 | 2020-08-20 | 富士ゼロックス株式会社 | 発光装置、光学装置および情報処理装置 |
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JP7485097B2 (ja) | 2024-05-16 |
JPWO2022163504A1 (ja) | 2022-08-04 |
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