WO2022160775A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2022160775A1
WO2022160775A1 PCT/CN2021/122922 CN2021122922W WO2022160775A1 WO 2022160775 A1 WO2022160775 A1 WO 2022160775A1 CN 2021122922 W CN2021122922 W CN 2021122922W WO 2022160775 A1 WO2022160775 A1 WO 2022160775A1
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WO
WIPO (PCT)
Prior art keywords
display panel
pixel circuit
pixel
units
arrangement
Prior art date
Application number
PCT/CN2021/122922
Other languages
English (en)
French (fr)
Inventor
李洪瑞
刘如胜
冯宏庆
盖翠丽
张兵
Original Assignee
云谷（固安）科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 云谷（固安）科技有限公司 filed Critical 云谷（固安）科技有限公司
Priority to KR1020237018160A priority Critical patent/KR20230087606A/ko
Publication of WO2022160775A1 publication Critical patent/WO2022160775A1/zh
Priority to US18/324,402 priority patent/US20230300976A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting

Definitions

  • the present application relates to the field of display, in particular to a display panel.
  • the display area of the display panel is configured to be at least partially transparent, so that a photosensitive component can be integrated on the back of the display panel to realize full-screen display of the electronic device.
  • the above-mentioned display panel has a serious diffraction effect on the transmitted light, which affects the light collection effect of the photosensitive element.
  • the present application provides a display panel, which improves the diffraction effect of the display panel on light.
  • Embodiments of the present application provide a display panel, which includes: a substrate; a plurality of pixel units, which are arrayed on the substrate along a first direction and a second direction intersecting with each other, each pixel unit includes N sub-pixels, and N is an integer greater than or equal to 3; and a plurality of pixel circuit units, arranged on the substrate, each pixel circuit unit includes N pixel circuits, each pixel circuit is electrically connected with a corresponding sub-pixel, and each pixel circuit unit is set.
  • M pixel circuits are arranged adjacently in sequence, M is an integer greater than or equal to 2 and less than or equal to N, and the arrangement direction of the pixel circuits in the arrangement unit includes the first The inclined direction, the first inclined direction is inclined with respect to both the first direction and the second direction.
  • the arrangement of pixel circuits in each pixel circuit unit is redesigned, and M pixel circuits in each arrangement unit are arranged in close proximity (ie, clustered together).
  • the arrangement direction of the pixel circuits in the arrangement unit includes a first inclined direction, and the first inclined direction is inclined with respect to both the first direction and the second direction, that is, the arrangement direction of the pixel circuits in the arrangement unit is relative to the pixel unit.
  • the arrangement direction is inclined, so that when the display panel can transmit light, the diffraction of light by the display panel is reduced, and the photosensitive effect of the photosensitive component integrated on the side of the non-display surface of the display panel is improved.
  • the orthographic projections of all the arrangement units provided in each pixel circuit unit on the substrate overlap with the orthographic projections of the P sub-pixels in the corresponding pixel unit on the substrate, and P is An integer greater than or equal to 1 and less than N, so that the pixel circuits are compactly arranged on the side of the P sub-pixels facing the substrate, which reduces the occlusion area of the pixel circuits and sub-pixels on the plane parallel to the substrate, and facilitates And the larger area blocked by the sub-pixels is configured as a light-transmitting area, which improves the overall light transmittance of the display panel. While realizing the under-screen integration of photosensitive components, it can realize full-screen display and full-screen uniform display.
  • the extension direction of at least one second line segment is inclined with respect to the extension direction of the first line segment, thereby reducing the diffraction of the transmitted light by the display panel, improving and The photosensitive effect of the photosensitive components integrated in the display panel.
  • each second signal line includes a fourth line segment and a fifth line segment
  • the orthographic projection of the fourth line segment on the substrate is located within the orthographic projection of the pixel circuit on the substrate
  • the fifth line segment is connected Between adjacent pixel circuit units, at least two second signal lines are close to each other at the fifth line segment relative to the fourth line segment, so that the signal lines between adjacent pixel circuit units are concentrated, and the display panel can be optimized for transparency. Diffraction effect of passing light.
  • each third-color sub-pixel is smaller than the light-emitting area of each first-color sub-pixel and each second-color sub-pixel, and the orthographic projection of the arrangement unit on the substrate is the same as the
  • the orthographic overlap of the first color sub-pixel and/or the second color sub-pixel means that multiple pixel units are overlapped with larger-sized sub-pixels as much as possible to increase the overlapping area of multiple pixel circuits and sub-pixels. There are more unblocked areas around the third sub-pixels of smaller size, which increases the area of the light-transmitting area, thereby improving the light-transmitting performance of the display panel.
  • FIG. 1 is a schematic top view of a display panel provided according to a first embodiment of the present application
  • FIG. 2 is a schematic cross-sectional view of a wire of a display panel provided according to an alternative embodiment of the present application
  • FIG. 3 is a schematic top view of a display panel provided according to a second embodiment of the present application.
  • FIG. 4 is a schematic top view of a display panel provided according to a third embodiment of the present application.
  • FIG. 5 is a schematic top view of a display panel provided according to a fourth embodiment of the present application.
  • FIG. 6 is a schematic top view of a display panel with hidden pixel units provided according to a fourth embodiment of the present application.
  • FIG. 7 is a schematic top view of a display panel provided according to a fifth embodiment of the present application.
  • FIG. 8 shows a schematic top view of a display device according to an embodiment of the present application.
  • FIG. 9 shows a cross-sectional view taken along the line A-A in FIG. 8 .
  • FIG. 1 is a schematic top view of a display panel provided according to a first embodiment of the present application.
  • the display panel 100 includes a substrate 110 , a plurality of pixel units 120 and a plurality of pixel circuit units 130 .
  • the substrate 110 includes a display area DA and a non-display area NA surrounding at least part of the periphery of the display area DA.
  • the plurality of pixel units 120 are arrayed on the substrate 110 along the first direction X and the second direction Y intersecting with each other, and specifically, the plurality of pixel units 120 are arrayed in the display area DA.
  • Each pixel unit 120 includes N sub-pixels 121 , where N is an integer greater than or equal to 3. In this embodiment, the pixel unit 120 includes four sub-pixels 121 as an example for description.
  • a plurality of pixel circuit units 130 are arranged on the substrate 110 .
  • Each pixel circuit unit 130 includes N pixel circuits 131 , and each pixel circuit 131 is electrically connected to a corresponding sub-pixel 121 .
  • Each pixel circuit unit 130 is provided with at least one arrangement unit AU.
  • M pixel circuits 131 are arranged adjacently in sequence, and M is an integer greater than or equal to 2 and less than or equal to N.
  • the arrangement direction of the pixel circuits 131 in the arrangement unit AU includes a first inclination direction T1 , and the first inclination direction T1 is inclined with respect to both the first direction X and the second direction Y.
  • the arrangement of the pixel circuits 131 in each pixel circuit unit 130 is redesigned, and the M pixel circuits 131 in each arrangement unit AU are arranged next to each other (ie, clustered together).
  • the arrangement direction of the pixel circuits 131 in the arrangement unit AU includes a first inclination direction T1, and the first inclination direction T1 is inclined with respect to both the first direction X and the second direction Y, that is, the pixel circuits 131 in the arrangement unit AU are arranged obliquely.
  • the arrangement direction of the pixel units 120 is inclined relative to the arrangement direction of the pixel units 120, so that when the display panel 100 can transmit light, the diffraction of light by the display panel 100 is reduced, and the light sensitivity of the photosensitive components integrated on the side where the non-display surface of the display panel 100 is located is improved. Effect.
  • the inclination angle formed by the first inclination direction T1 with respect to at least one of the first direction X and the second direction Y is 4 degrees to 60 degrees.
  • the inclination angle of the first inclination direction T1 relative to the first direction X is 5 degrees.
  • the pixel unit 120 is electrically connected to the pixel circuit unit 130 correspondingly, and the orthographic projection of all the arrangement units AU provided in each pixel circuit unit 130 on the substrate 110 corresponds to the P sub-pixels 121 in the pixel unit 120 .
  • Orthographic overlap on the substrate 110, P is an integer greater than or equal to 1 and less than N.
  • the arrangement unit AU in the arrangement unit AU, four pixel circuits 131 are arranged adjacently in sequence, and the orthographic projection of all the arrangement units AU provided in each pixel circuit unit 130 on the substrate 110 is the same as that of the corresponding pixel unit.
  • the pixel circuits 131 are compactly arranged on the side of the P sub-pixels 121 facing the substrate 110, which reduces the shielding area of the pixel circuits 131 and the sub-pixels 121 on a plane parallel to the substrate 110, so as to facilitate the separation of the pixel circuits 131 that are not covered by the pixel circuits.
  • the larger area blocked by 131 and sub-pixels 121 is configured as a light-transmitting area, which improves the overall light transmittance of the display panel, and can realize full-screen display and full-screen uniform display while realizing under-screen integration of photosensitive components.
  • the orthographic projection of the arrangement unit AU on the substrate 110 and the orthographic projection of the sub-pixels 121 on the substrate 110 partially overlap each other.
  • the size of the arrangement unit AU can be reduced, so that the orthographic projection of the P sub-pixels 121 on the substrate 110 completely covers the orthographic projection of all the arrangement units AU provided in each pixel circuit unit 130 on the substrate 110, thereby The light transmittance of the display panel 100 is further improved.
  • the sub-pixel 121 of each pixel unit 120 includes a first-color sub-pixel 121a, a second-color sub-pixel 121b and a third-color sub-pixel 121c, and the light-emitting area of each third-color sub-pixel 121c is smaller than that of each first-color sub-pixel
  • the light-emitting area of 121a is smaller than the light-emitting area of each second-color sub-pixel 121b, the orthographic projection of the arrangement unit AU on the substrate 110 and the orthographic projection of the first-color sub-pixel 121a and/or the second-color sub-pixel 121b overlap.
  • the arrangement unit AU is overlapped with the larger-sized sub-pixel 121 as much as possible to increase the overlapping area of the plurality of pixel circuits 131 and the sub-pixel 121, and at the same time, more space is left around the smaller-sized third sub-pixel 121.
  • the shaded area increases the area of the light-transmitting area, thereby improving the light-transmitting performance of the display panel 100 .
  • the adjacent arrangement units AU are connected with wires CL.
  • at least part of the wires CL can transmit light, so as to improve the light transmittance of the area between adjacent arrangement units AU.
  • the wire CL is a light-transmitting wire CL
  • the material of the wire CL is, for example, Indium tin oxide (ITO), Indium Zinc Oxide (IZO), etc., which can further improve the adjacent rows.
  • ITO Indium tin oxide
  • IZO Indium Zinc Oxide
  • FIG. 2 is a schematic cross-sectional view of a wire of a display panel provided according to an alternative embodiment of the present application, and the cross-section is perpendicular to the extending direction of the wire CL.
  • the wire CL includes a first conductor layer SC1 and a second conductor layer SC2 stacked in a direction perpendicular to the substrate 110 .
  • the resistivity of the first conductor layer SC1 is lower than that of the second conductor layer SC2, and the light transmittance of the second conductor layer SC2 is greater than the light transmittance of the first conductor layer SC1.
  • the first conductor layer SC1 is a metal layer
  • the second conductor layer SC2 is a light-transmitting conductive layer such as ITO and IZO.
  • the orthographic projection of the first conductor layer SC1 on the substrate 110 is located within the orthographic projection of the second conductor layer SC2 on the substrate 110. While ensuring that the wires CL between the adjacent arrangement units AU have a certain transmittance, The load on the wires CL can be reduced, and the display uniformity of the sub-pixels 121 in each region can be improved.
  • each pixel circuit unit 130 is provided with an arrangement unit AU, and in the arrangement unit AU, N pixel circuits 131 are arranged adjacently in sequence along the first inclined direction T1 .
  • the four pixel circuits 131 are arranged adjacently in sequence along the first inclined direction T1.
  • the number of arrangement units AU provided in each pixel circuit unit 130 and the number and arrangement of pixel circuits 131 in each arrangement unit AU may not be limited to the above examples, and may be other situations.
  • FIG. 3 is a schematic top view of a display panel according to a second embodiment of the present application. Part of the structure of the second embodiment is the same as that of the first embodiment. The differences between the two will be described below, and the similarities will not be described in detail. .
  • the arrangement direction of the pixel circuits 131 in the arrangement unit AU further includes a second inclination direction T2, the second inclination direction T2 intersects with the first inclination direction T1, and the second inclination direction T2 is relative to the first direction Both X and the second direction Y are inclined.
  • each pixel circuit unit 130 is provided with one arrangement unit AU, and in the arrangement unit AU, N pixel circuits 131 are arrayed adjacent to each other along the first tilt direction T1 and the second tilt direction T2 Arrangement, the second inclination direction T2 and the first inclination direction T1 may be perpendicular.
  • each pixel circuit unit 130 includes four pixel circuits 131 , and in the arrangement unit AU, the four pixel circuits 131 are arranged in a 2 ⁇ 2 layout. Therefore, in each arrangement unit AU, the pixel circuits 131 may be arranged in sequence along a preset direction, may also be arranged in an array in two intersecting directions, or may be arranged in other successively adjacent arrangements.
  • FIG. 4 is a schematic top view of a display panel according to a third embodiment of the present application, wherein the pixel unit is hidden and shown in FIG. 4 .
  • Part of the structure of the third embodiment is the same as that of the first embodiment, and the differences between the two will be described below, and the similarities will not be described in detail.
  • the plurality of pixel circuit units 130 are arranged in a plurality of rows and columns. In each row of pixel circuit units UR, a plurality of pixel circuit units 130 are arranged along the first direction X. In each column of pixel circuit units UC, a plurality of pixel circuit units 130 are arranged along the second direction Y.
  • the display panel further includes a plurality of first signal lines 140, and each first signal line 140 is connected to a row of pixel circuit units UR.
  • the first signal line 140 includes a first line segment 141 and a second line segment 142, the orthographic projection of the first line segment 141 on the substrate 110 is located within the orthographic projection of the pixel circuit 131 on the substrate 110, and the second line segment 142 is connected to Between adjacent pixel circuit units 130 , the extension direction of at least one second line segment 142 is inclined relative to the extension direction of the first line segment 141 , thereby improving the diversity of the extension direction of the first signal line 140 and reducing the number of pairs of display panels 100 . Through the diffraction of light, the photosensitive effect of the photosensitive component integrated with the display panel 100 is improved.
  • each first signal line 140 is connected to one row of pixel circuit units UR
  • the number of first signal lines 140 correspondingly connected to each row of pixel circuit units UR is not limited to one, and may be two, three or other numbers.
  • the first signal line 140 includes, for example, at least one of a scanning signal line and a light-emitting signal line, and the number of each signal line is not limited to one.
  • each row of pixel circuit units UR is correspondingly connected with three first signal lines 140 , and the three first signal lines 140 respectively include, for example, two scan signal lines and one light-emitting signal line.
  • FIG. 5 and 6 are schematic top views of a display panel according to a fourth embodiment of the present application, wherein the pixel unit is hidden and shown in FIG. 6 .
  • Part of the structure of the fourth embodiment is the same as that of the first embodiment, and the differences between the two will be described below, and the similarities will not be described in detail.
  • each pixel circuit unit 130 is provided with at least two arrangement units AU.
  • each pixel unit 120 includes one first-color sub-pixel 121a, one second-color sub-pixel 121b, and two third-color sub-pixels 121c.
  • Each pixel circuit unit 130 includes four pixel circuits 131 .
  • each pixel circuit unit 130 is provided with two arrangement units AU, and in each arrangement unit AU, two pixel circuits 131 are arranged adjacently along the first inclined direction T1.
  • the orthographic projection of one arrangement unit AU on the substrate 110 overlaps with the first color sub-pixel 121 a
  • the other arrangement unit AU is on the substrate 110 .
  • each pixel circuit unit 130 includes at least two arrangement units AU, the number of arrangement units AU is not limited to the above example, and may also be three, four, etc. In each arrangement unit AU, the number and arrangement of the pixel circuits 131 may not be limited to the above examples.
  • each pixel circuit unit 130 is provided with at least two arrangement units AU.
  • each pixel circuit unit 130 is provided with two arrangement units AU.
  • the first signal line 140 further includes a third line segment 143, and the third line segment 143 is connected between adjacent arrangement units AU in the pixel circuit unit 130.
  • the extension direction of the at least one third line segment 143 is inclined relative to the extension direction of the second line segment 142 , thereby further reducing the diffraction of the transmitted light by the display panel 100 and improving the photosensitive effect of the photosensitive component integrated with the display panel 100 .
  • the extension directions of the second line segments 142 of the adjacent first signal lines 140 intersect with each other to reduce the extension uniformity of the first signal lines 140 , thereby reducing the transmission rate of the display panel 100 Diffraction of light.
  • the extending directions of the third line segments 143 of the adjacent first signal lines 140 intersect with each other, thereby further improving the diversity of the extending directions of the first signal lines 140 and further reducing the diffraction of the transmitted light by the display panel 100 .
  • the extending directions of the second line segments 142 of the adjacent first signal lines 140 may be parallel to each other.
  • each pixel circuit unit 130 is provided with at least two arrangement units AU, the first signal line 140 further includes a third line segment 143, and the third line segment 143 is connected to the adjacent arrangement units AU in the pixel circuit 131. between.
  • the extending directions of the third line segments 143 of the adjacent first signal lines 140 may be parallel to each other.
  • FIG. 7 is a schematic top view of a display panel according to a fifth embodiment of the present application, wherein the pixel unit is hidden and shown in FIG. 7 .
  • Part of the structure of the fifth embodiment is the same as that of the first embodiment, and the differences between the two will be described below, and the similarities will not be described in detail.
  • the plurality of pixel circuit units 130 are arranged in multiple rows and columns. In each row of pixel circuit units UR, the plurality of pixel circuit units 130 are arranged along the first direction X, and in each column of pixel circuit units UC , the plurality of pixel circuit units 130 are arranged along the second direction Y.
  • the display panel 100 may further include second signal line groups LG2, each of which is connected to a column of pixel circuit units UC.
  • Each second signal line group LG2 includes a plurality of second signal lines 150 .
  • Each of the second signal lines 150 includes a fourth line segment 151 and a fifth line segment 152 .
  • the orthographic projection of the fourth line segment 151 on the substrate 110 is located within the orthographic projection of the pixel circuit 131 on the substrate 110 .
  • the fifth line segment 152 is connected between adjacent pixel circuit units 130 .
  • at least two second signal lines 150 are close to each other at the fifth line segment 152 relative to the fourth line segment 151, so that the signal lines between adjacent pixel circuit units 130 are concentrated, and the display panel 100 can be optimized for transparency. Diffraction effect of passing light.
  • the number of the second signal lines 150 included in the second signal line group LG2 can be adjusted and changed according to the design of the wiring structure of the display panel 100 .
  • the second signal line 150 includes, for example, at least one of a data signal line and a power supply signal line.
  • the embodiment of the present application further provides a display device, and the display device may include the display panel 100 of any one of the foregoing embodiments.
  • the display device may include the display panel 100 of any one of the foregoing embodiments.
  • the following will take a display device of an embodiment as an example for description.
  • the display device includes the display panel 100 of the above-mentioned embodiment.
  • FIG. 8 shows a schematic top view of a display device according to an embodiment of the present application
  • FIG. 9 shows a cross-sectional view taken along the line A-A in FIG. 8
  • the display panel 100 may be the display panel 100 of one of the foregoing embodiments.
  • the display panel 100 includes a first surface S1 and a second surface S2 opposite to each other, wherein the first surface S1 is a display surface.
  • the display device further includes at least one photosensitive component 200 , and the at least one photosensitive component 200 is located on the side where the second surface S2 of the display panel 100 is located.
  • the number of photosensitive components 200 is two, one of which may be an image acquisition device for acquiring external image information, and the other may be an optical fingerprint identification device.
  • the image acquisition device is a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image acquisition device, and in some other embodiments, the image acquisition device may also be a charge-coupled device (Charge-coupled Device, CCD) Image acquisition devices and other forms of image acquisition devices.
  • CMOS complementary Metal Oxide Semiconductor
  • CCD Charge-coupled Device
  • the number and types of the photosensitive components 200 may not be limited to the above examples.
  • the photosensitive components 200 may also be infrared sensors, proximity sensors, infrared lenses, flood light sensing elements, ambient light sensors, and point sensors. Array projectors and other light sensors.
  • the display device may also integrate other components on the side where the second surface S2 of the display panel 100 is located, such as an earpiece, a speaker, and the like.
  • the display panel 100 includes a substrate 110 , a plurality of pixel units 120 and a plurality of pixel circuit units 130 .
  • the substrate 110 includes a display area DA and a non-display area NA surrounding at least part of the periphery of the display area DA.
  • a plurality of pixel units 120 are arrayed on the substrate 110 along a first direction X and a second direction Y intersecting with each other, each pixel unit 120 includes N sub-pixels 121 , where N is an integer greater than or equal to 3.
  • a plurality of pixel circuit units 130 are arranged on the substrate 110 .
  • Each pixel circuit unit 130 includes N pixel circuits 131 , and each pixel circuit 131 is electrically connected to a corresponding sub-pixel 121 .
  • Each pixel circuit unit 130 is provided with at least one arrangement unit AU.
  • M pixel circuits 131 are arranged adjacently in sequence, and M is an integer greater than or equal to 2 and less than or equal to N.
  • the arrangement direction of the pixel circuits 131 in the arrangement unit AU includes a first inclined direction T1, and the first inclined direction T1 is inclined with respect to both the first direction X and the second direction Y.
  • the arrangement of the pixel circuits 131 in each pixel circuit unit 130 in the display panel 100 is redesigned, and the M pixel circuits 131 in each arrangement unit AU are arranged in close proximity (ie, together).
  • the arrangement direction of the pixel circuits 131 in the arrangement unit AU includes a first inclination direction T1, and the first inclination direction T1 is inclined with respect to both the first direction X and the second direction Y, that is, the pixel circuits 131 in the arrangement unit AU are arranged obliquely.
  • the arrangement direction of the pixel units 120 is inclined relative to the arrangement direction of the pixel units 120, so that when the display panel 100 can transmit light, the diffraction of light by the display panel 100 is reduced, and the light sensitivity of the photosensitive components integrated on the side where the non-display surface of the display panel 100 is located is improved. Effect.
  • the pixel unit 120 is electrically connected to the pixel circuit unit 130 correspondingly, and the orthographic projection of all the arrangement units AU provided in each pixel circuit unit 130 on the substrate 110 corresponds to the P sub-pixels 121 in the pixel unit 120 .
  • the orthographic projections on the substrate 110 overlap, and P is an integer greater than or equal to 1 and less than N, which reduces the occlusion area of the pixel circuit 131 and the sub-pixel 121 on the plane parallel to the substrate 110 , and facilitates the unobstructed area of the pixel circuit 131 and the sub-pixel 121 .
  • the larger area shielded by the sub-pixels 121 is configured as a light-transmitting area, which improves the light transmittance of the entire display panel.
  • the entire display area DA of the display panel 100 can apply the above-mentioned arrangement design of the pixel circuits 131 , so that the entire display area DA of the display panel 100 can transmit light, on the one hand, the transmittance of the display panel 100 is improved.
  • the arrangement structure of the sub-pixels 121 and the arrangement structure of the pixel circuits 131 of the entire display panel 100 is relatively uniform, which avoids the uneven display phenomenon caused by arranging at least two sub-display areas with different light transmittances.
  • the display panel 100 of the embodiment of the present application can realize the under-screen integration of the photosensitive component 200, and can realize full-screen display and full-screen uniform display.

Abstract

本申请公开了一种显示面板。显示面板包括：衬底；多个像素单元，沿彼此相交的第一方向和第二方向阵列排布于衬底上，每个像素单元包括N个子像素，N为大于或等于3的整数；以及多个像素电路单元，排布于衬底上，每个像素电路单元包括N个像素电路，每个像素电路与对应子像素电连接，每个像素电路单元设有至少一个排布单元，排布单元中，M个像素电路依次相邻排布，M为大于或等于2且小于或等于N的整数，排布单元中的像素电路的排布方向包括第一倾斜方向，第一倾斜方向相对于第一方向以及第二方向均倾斜设置。根据本申请实施例的显示面板，降低显示面板对光线的衍射，提高集成于显示面板的非显示面所在侧的感光组件的感光效果。

Description

显示面板 技术领域
本申请涉及显示领域，具体涉及一种显示面板。
相关申请的交叉引用
本申请要求享有于2021年01月29日提交的名称为“显示面板”的中国专利申请第202110129024.7号的优先权，该申请的全部内容通过引用并入本文中。
背景技术
随着电子设备的快速发展，用户对屏占比的要求越来越高，使得电子设备的全面屏显示受到业界越来越多的关注。
传统的电子设备如手机、平板电脑等，需要集成诸如前置摄像头、听筒以及红外感应元件等。现有技术中，将显示面板的显示区配置为至少部分可透光，从而能在显示面板的背面集成感光组件，实现电子设备的全面屏显示。然而，上述显示面板对透过光线产生较严重的衍射效果，影响感光组件的光线采集效果。
发明内容
本申请提供一种显示面板，改善显示面板对光线的衍射效果。
本申请实施例提供一种显示面板，其包括：衬底；多个像素单元，沿彼此相交的第一方向和第二方向阵列排布于衬底上，每个像素单元包括N个子像素，N为大于或等于3的整数；以及多个像素电路单元，排布于衬底上，每个像素电路单元包括N个像素电路，每个像素电路与对应子像素电连接，每个像素电路单元设有至少一个排布单元，排布单元中，M个像素电路依次相邻排布，M为大于或等于2且小于或等于N的整数，排布单 元中的像素电路的排布方向包括第一倾斜方向，第一倾斜方向相对于第一方向以及第二方向均倾斜设置。
根据本申请实施例的显示面板，重新设计了每个像素电路单元中的像素电路排布方式，每个排布单元中的M个像素电路紧邻排布(即相聚在一起)。排布单元中的像素电路的排布方向包括第一倾斜方向，第一倾斜方向相对于第一方向以及第二方向均倾斜设置，即排布单元中的像素电路的排布方向相对像素单元的排布方向倾斜，从而在显示面板可透光时，降低显示面板对光线的衍射，提高集成于显示面板的非显示面所在侧的感光组件的感光效果。
在一些可选的实施例中，每个像素电路单元设有的所有排布单元在衬底上的正投影，与对应像素单元中的P个子像素在衬底上的正投影交叠，P为大于或等于1且小于N的整数，使得像素电路紧凑排布于P个子像素的朝向衬底的一侧，降低像素电路和子像素在平行于衬底平面上的遮挡面积，便于将未被像素电路及子像素遮挡的更大区域配置为可透光区域，提高显示面板整体的透光率，在实现感光组件屏下集成的同时，能够实现全面屏显示以及全面屏均一性显示。
在一些可选的实施方式中，多条第一信号线中，至少一个第二线段的延伸方向相对于第一线段的延伸方向倾斜设置，从而降低显示面板对透过光线的衍射，提高与显示面板集成的感光组件的感光效果。
在一些可选的实施例中，每条第二信号线包括第四线段和第五线段，第四线段在衬底上的正投影位于像素电路在衬底上的正投影内，第五线段连接于相邻像素电路单元之间，至少两条第二信号线在第五线段处相对在第四线段处彼此靠拢，使得相邻像素电路单元之间的信号线集中化，能够优化显示面板对透过光线的衍射效果。
在一些可选的实施方式中，每个第三颜色子像素的发光面积小于每个第一颜色子像素以及每个第二颜色子像素的发光面积，排布单元在衬底上的正投影与第一颜色子像素和/或第二颜色子像素的正投影交叠，即将多个像素单元尽量与尺寸较大的子像素相重叠，提高多个像素电路与子像素的交叠面积，同时在较小尺寸的第三子像素周边空余出更多的未被遮挡区域， 提高了可透光区域的面积，从而提高显示面板的透光性能。
附图说明
通过阅读以下参照附图对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显，其中，相同或相似的附图标记表示相同或相似的特征，附图并未按照实际的比例绘制。
图1是根据本申请第一实施例提供的显示面板的俯视示意图；
图2是根据本申请一种替代实施例提供的显示面板的导线的横截面示意图；
图3是根据本申请第二实施例提供的显示面板的俯视示意图；
图4是根据本申请第三实施例提供的显示面板的俯视示意图；
图5是根据本申请第四实施例提供的显示面板的俯视示意图；
图6是根据本申请第四实施例提供的显示面板隐去像素单元的俯视示意图；
图7是根据本申请第五实施例提供的显示面板的俯视示意图；
图8示出根据本申请一种实施例的显示装置的俯视示意图；
图9示出图8中A-A向的剖面图。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本申请，并不被配置为限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。
图1是根据本申请第一实施例提供的显示面板的俯视示意图。显示面板100包括衬底110、多个像素单元120以及多个像素电路单元130。衬底110包括显示区DA以及围绕于至少部分显示区DA外周的非显示区NA。
多个像素单元120沿彼此相交的第一方向X和第二方向Y阵列排布于 衬底110上，具体地，多个像素单元120阵列排布于显示区DA。每个像素单元120包括N个子像素121，N为大于或等于3的整数。本实施例中，以像素单元120包括四个子像素121为例进行说明。
多个像素电路单元130排布于衬底110上。每个像素电路单元130包括N个像素电路131，每个像素电路131与对应子像素121电连接。每个像素电路单元130设有至少一个排布单元AU。每个排布单元AU中，M个像素电路131依次相邻排布，M为大于或等于2且小于或等于N的整数。排布单元AU中的像素电路131的排布方向包括第一倾斜方向T1，第一倾斜方向T1相对于第一方向X以及第二方向Y均倾斜设置。
根据本申请实施例的显示面板，重新设计了每个像素电路单元130中的像素电路131排布方式，每个排布单元AU中的M个像素电路131紧邻排布(即相聚在一起)。排布单元AU中的像素电路131的排布方向包括第一倾斜方向T1，第一倾斜方向T1相对于第一方向X以及第二方向Y均倾斜设置，即排布单元AU中的像素电路131的排布方向相对像素单元120的排布方向倾斜，从而在显示面板100可透光时，降低显示面板100对光线的衍射，提高集成于显示面板100的非显示面所在侧的感光组件的感光效果。
可选地，第一倾斜方向T1相对第一方向X、第二方向Y中的至少一者所成的倾斜角度为4度至60度。例如，第一倾斜方向T1相对第一方向X所成的倾斜角度为5度，通过控制第一倾斜方向T1的倾斜角度在上述范围，能够更大程度优化显示面板对透过光线的衍射效果。
可选地，像素单元120与像素电路单元130对应电连接，每个像素电路单元130设有的所有排布单元AU在衬底110上的正投影，与对应像素单元120中的P个子像素121在衬底110上的正投影交叠，P为大于或等于1且小于N的整数。例如本实施例中，排布单元AU中，四个像素电路131依次相邻排布，每个像素电路单元130设有的所有排布单元AU在衬底110上的正投影，与对应像素单元120中的两个子像素121在衬底110上的正投影交叠，存在另外两个子像素121及其周边区域未被像素电路131遮挡。本实施例中，像素电路131紧凑排布于P个子像素121的朝向衬底110的 一侧，降低像素电路131和子像素121在平行于衬底110平面上的遮挡面积，便于将未被像素电路131及子像素121遮挡的更大区域配置为可透光区域，提高显示面板整体的透光率，在实现感光组件屏下集成的同时，能够实现全面屏显示以及全面屏均一性显示。
在本实施例中，排布单元AU在衬底110上的正投影与子像素121在衬底110上的正投影彼此部分交叠，在一些可选的实施例中，通过缩小像素电路131的尺寸，可以缩小排布单元AU的尺寸，使得P个子像素121在衬底110上的正投影完全覆盖每个像素电路单元130设有的所有排布单元AU在衬底110上的正投影，从而进一步提高显示面板100的透光率。
每个像素单元120的子像素121包括第一颜色子像素121a、第二颜色子像素121b以及第三颜色子像素121c，每个第三颜色子像素121c的发光面积小于每个第一颜色子像素121a的发光面积，且小于每个第二颜色子像素121b的发光面积，排布单元AU在衬底110上的正投影与第一颜色子像素121a和/或第二颜色子像素121b的正投影交叠。将排布单元AU尽量与尺寸较大的子像素121相重叠，提高多个像素电路131与子像素121的交叠面积，同时在较小尺寸的第三子像素121周边空余出更多的未被遮挡区域，提高了可透光区域的面积，从而提高显示面板100的透光性能。
如图1，至少部分相邻排布单元AU之间连接有导线CL。可选地，导线CL的至少部分可透光，以提高相邻排布单元AU之间的区域的可透光能力。例如在一些实施例中，导线CL为透光导线CL，导线CL的材质例如是氧化铟锡(Indium tin oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)等，能够进一步提高相邻排布单元AU之间的区域的透光能力。
图2是根据本申请一种替代实施例提供的显示面板的导线的横截面示意图，该横截面垂直于导线CL的延伸方向。在一种替代实施例中，导线CL包括在垂直于衬底110方向上层叠的第一导体层SC1和第二导体层SC2。第一导体层SC1的电阻率低于第二导体层SC2的电阻率，第二导体层SC2的透光率大于第一导体层SC1的透光率。例如，第一导体层SC1为金属层，第二导体层SC2为诸如ITO、IZO的透光导电层。第一导体层SC1在衬底110上的正投影位于第二导体层SC2在衬底110上的正投影以内，在保证 相邻排布单元AU之间的导线CL具有一定透光率的同时，能够降低导线CL的负载，提高各区域的子像素121的显示均一性。
请继续参考图1，在一些实施例中，每个像素电路单元130设有一个排布单元AU，并且排布单元AU中，N个像素电路131沿第一倾斜方向T1依次相邻排布。例如本实施例中，四个像素电路131沿第一倾斜方向T1依次相邻排布。
每个像素电路单元130设有的排布单元AU的数量、以及每个排布单元AU中的像素电路131的数量以及排布方式可以不限于上述示例，也可以是其它情形。
图3是根据本申请第二实施例提供的显示面板的俯视示意图，第二实施例的部分结构与第一实施例相同，以下将对两者不同之处进行说明，相同之处不再详述。
在一些实施例中，排布单元AU中的像素电路131的排布方向还包括第二倾斜方向T2，第二倾斜方向T2与第一倾斜方向T1相交，第二倾斜方向T2相对于第一方向X以及第二方向Y均倾斜设置。
例如，在第二实施例中，每个像素电路单元130设有一个排布单元AU，并且排布单元AU中，N个像素电路131沿第一倾斜方向T1和第二倾斜方向T2阵列相邻排布，第二倾斜方向T2与第一倾斜方向T1可以垂直。例如，每个像素电路单元130包括四个像素电路131，排布单元AU中，四个像素电路131呈2×2的布局排布。因此，每个排布单元AU中，像素电路131可以沿预设方向依次排列，也可以在交叉的两个方向上阵列排布，还可以是其它依次相邻的排布方式。
图4是根据本申请第三实施例提供的显示面板的俯视示意图，其中图4将像素单元隐去绘示。第三实施例的部分结构与第一实施例相同，以下将对两者不同之处进行说明，相同之处不再详述。
在一些实施例中，多个像素电路单元130排布为多行及多列。每行像素电路单元UR中，多个像素电路单元130沿第一方向X排列。每列像素电路单元UC中，多个像素电路单元130沿第二方向Y排列。
可选地，显示面板还包括多条第一信号线140，每条第一信号线140连 接一行像素电路单元UR。第一信号线140包括第一线段141和第二线段142，第一线段141在衬底110上的正投影位于像素电路131在衬底110上的正投影内，第二线段142连接于相邻像素电路单元130之间，至少一个第二线段142的延伸方向相对于第一线段141的延伸方向倾斜设置，从而提高第一信号线140的延伸方向的多样性，降低显示面板100对透过光线的衍射，提高与显示面板100集成的感光组件的感光效果。
尽管每条第一信号线140连接一行像素电路单元UR，但每行像素电路单元UR对应连接的第一信号线140的数量不限于一条，可以是两条、三条等其它数量。第一信号线140例如包括扫描信号线、发光信号线中的至少一种，并且每种信号线的数量也不限于是一条。在一个示例中，每行像素电路单元UR对应连接有三条第一信号线140，三条第一信号线140例如分别包括两条扫描信号线和一条发光信号线。
图5和图6是根据本申请第四实施例提供的显示面板的俯视示意图，其中图6将像素单元隐去绘示。第四实施例的部分结构与第一实施例相同，以下将对两者不同之处进行说明，相同之处不再详述。
在第四实施例中，每个像素电路单元130设有至少两个排布单元AU。例如，每个像素单元120包括一个第一颜色子像素121a、一个第二颜色子像素121b以及两个第三颜色子像素121c。每个像素电路单元130包括四个像素电路131。其中，每个像素电路单元130设有两个排布单元AU，每个排布单元AU中，两个像素电路131沿第一倾斜方向T1相邻排布。每个像素电路单元130包括的两个排布单元AU中，其中一个排布单元AU在衬底110上的正投影与第一颜色子像素121a交叠，另一个排布单元AU在衬底110上的正投影与第二颜色子像素121b交叠。可以理解的是，每个像素电路单元130包括至少两个排布单元AU时，排布单元AU的数量不限于是上述示例，也可以是三个、四个等。每个排布单元AU中，像素电路131的数量和排布方式也可以不限于上述示例。
请继续参考图6，可选地，每个像素电路单元130设有至少两个排布单元AU，例如本实施例中，每个像素电路单元130设有两个排布单元AU。第一信号线140还包括第三线段143，第三线段143在像素电路单元130中 连接于相邻排布单元AU之间。至少一个第三线段143的延伸方向相对于第二线段142的延伸方向倾斜设置，从而进一步降低显示面板100对透过光线的衍射，提高与显示面板100集成的感光组件的感光效果。
请继续参考图6，在一些实施例中，相邻第一信号线140的第二线段142的延伸方向彼此相交，以降低第一信号线140的延伸一致性，从而降低显示面板100对透过光线的衍射。可选地，相邻第一信号线140的第三线段143的延伸方向彼此相交，从而进一步提高第一信号线140延伸方向的多样性，进一步降低显示面板100对透过光线的衍射。
在其它一些实施例中，相邻第一信号线140的第二线段142的延伸方向可以彼此平行。可选地，每个像素电路单元130设有至少两个排布单元AU，第一信号线140还包括第三线段143，第三线段143在像素电路131中连接于相邻排布单元AU之间。可选地，相邻第一信号线140的第三线段143的延伸方向可以彼此平行。
图7是根据本申请第五实施例提供的显示面板的俯视示意图，其中图7将像素单元隐去绘示。第五实施例的部分结构与第一实施例相同，以下将对两者不同之处进行说明，相同之处不再详述。
在第五实施例中，多个像素电路单元130排布为多行及多列，每行像素电路单元UR中，多个像素电路单元130沿第一方向X排列，每列像素电路单元UC中，多个像素电路单元130沿第二方向Y排列。
显示面板100还可以包括第二信号线组LG2，每组第二信号线组LG2连接一列像素电路单元UC。每组第二信号线组LG2包括多条第二信号线150。每条第二信号线150包括第四线段151和第五线段152。第四线段151在衬底110上的正投影位于像素电路131在衬底110上的正投影内。第五线段152连接于相邻像素电路单元130之间。可选地，至少两条第二信号线150在第五线段152处相对在第四线段151处彼此靠拢，使得相邻像素电路单元130之间的信号线集中化，能够优化显示面板100对透过光线的衍射效果。
第二信号线组LG2包括的第二信号线150的数量可以根据显示面板100的布线结构设计调整变化。第二信号线150例如包括数据信号线、供 电信号线中的至少一种。
本申请实施例还提供一种显示装置，该显示装置可以包括上述任一实施方式的显示面板100。以下将以一种实施例的显示装置为例进行说明，该实施例中，显示装置包括上述实施例的显示面板100。
图8示出根据本申请一种实施例的显示装置的俯视示意图，图9示出图8中A-A向的剖面图。本实施例的显示装置中，显示面板100可以是上述其中一个实施例的显示面板100。
显示面板100包括相对的第一表面S1和第二表面S2，其中第一表面S1为显示面。显示装置还包括至少一个感光组件200，该至少一个感光组件200位于显示面板100的第二表面S2所在侧。
例如，感光组件200的数量为两个，其中一个可以是图像采集装置，用于采集外部图像信息，另一个可以是光学指纹识别装置。本实施例中，图像采集装置为互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)图像采集装置，在其它一些实施例中，图像采集装置也可以是电荷耦合器件(Charge-coupled Device，CCD)图像采集装置等其它形式的图像采集装置。可以理解的是，感光组件200的数量和种类可以不限于上述示例，例如在一些实施例中，感光组件200也可以是红外传感器、接近传感器、红外镜头、泛光感应元件、环境光传感器以及点阵投影器等光传感器。此外，显示装置在显示面板100的第二表面S2所在侧还可以集成其它部件，例如是听筒、扬声器等。
显示面板100包括衬底110、多个像素单元120以及多个像素电路单元130。衬底110包括显示区DA以及围绕于至少部分显示区DA外周的非显示区NA。多个像素单元120沿彼此相交的第一方向X和第二方向Y阵列排布于衬底110上，每个像素单元120包括N个子像素121，N为大于或等于3的整数。多个像素电路单元130排布于衬底110上。每个像素电路单元130包括N个像素电路131，每个像素电路131与对应子像素121电连接。每个像素电路单元130设有至少一个排布单元AU，排布单元AU中，M个像素电路131依次相邻排布，M为大于或等于2且小于或等于N的整数。排布单元AU中的像素电路131的排布方向包括第一倾斜方向T1，第 一倾斜方向T1相对于第一方向X以及第二方向Y均倾斜设置。
根据本申请实施例的显示装置，重新设计了显示面板100中的每个像素电路单元130中的像素电路131排布方式，每个排布单元AU中的M个像素电路131紧邻排布(即相聚在一起)。排布单元AU中的像素电路131的排布方向包括第一倾斜方向T1，第一倾斜方向T1相对于第一方向X以及第二方向Y均倾斜设置，即排布单元AU中的像素电路131的排布方向相对像素单元120的排布方向倾斜，从而在显示面板100可透光时，降低显示面板100对光线的衍射，提高集成于显示面板100的非显示面所在侧的感光组件的感光效果。
可选地，像素单元120与像素电路单元130对应电连接，每个像素电路单元130设有的所有排布单元AU在衬底110上的正投影，与对应像素单元120中的P个子像素121在衬底110上的正投影交叠，P为大于或等于1且小于N的整数，降低像素电路131和子像素121在平行于衬底110平面上的遮挡面积，便于将未被像素电路131及子像素121遮挡的更大区域配置为可透光区域，提高显示面板整体的透光率。在本实施例中，显示面板100的整个显示区DA均可以应用上述像素电路131的排布设计，使得整个显示面板100的显示区DA均能透光，一方面提高显示面板100的可透光面积，另一方面，整个显示面板100的子像素121排布结构和像素电路131排布结构较为均一，避免了设置透光率不同的至少两个子显示区产生的显示不均现象。本申请实施例的显示面板100能实现感光组件200屏下集成的同时，能够实现全面屏显示以及全面屏均一性显示。
依照本申请如上文所述的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该申请仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本申请的原理和实际应用，从而使所属技术领域技术人员能很好地利用本申请以及在本申请基础上的修改使用。本申请仅受权利要求书及其全部范围和等效物的限制。

Claims (19)

  1. 一种显示面板，包括：
    衬底；
    多个像素单元，沿彼此相交的第一方向和第二方向阵列排布于所述衬底上，每个所述像素单元包括N个子像素，N为大于或等于3的整数；以及
    多个像素电路单元，排布于所述衬底上，每个所述像素电路单元包括N个像素电路，每个像素电路与对应所述子像素电连接，每个所述像素电路单元设有至少一个排布单元，所述排布单元中，M个所述像素电路依次相邻排布，M为大于或等于2且小于或等于N的整数，所述排布单元中的所述像素电路的排布方向包括第一倾斜方向，所述第一倾斜方向相对于所述第一方向以及所述第二方向均倾斜设置。
  2. 根据权利要求1所述的显示面板，其中，每个所述像素电路单元设有的所有所述排布单元在所述衬底上的正投影，与对应所述像素单元中的P个所述子像素在所述衬底上的正投影交叠，P为大于或等于1且小于N的整数。
  3. 根据权利要求1所述的显示面板，其中，所述第一倾斜方向相对所述第一方向、所述第二方向中的至少一者所成的倾斜角度为4度至60度。
  4. 根据权利要求1所述的显示面板，其中，每个所述像素电路单元设有至少两个所述排布单元。
  5. 根据权利要求1所述的显示面板，其中，每个所述像素电路单元设有一个所述排布单元，并且所述排布单元中，N个所述像素电路沿所述第一倾斜方向依次相邻排布。
  6. 根据权利要求1所述的显示面板，其中，所述排布单元中的所述像素电路的所述排布方向还包括第二倾斜方向，所述第二倾斜方向与所述第一倾斜方向相交，所述第二倾斜方向相对于所述第一方向以及所述第二方向均倾斜设置。
  7. 根据权利要求1所述的显示面板，其中，所述多个像素电路单元排布为多行及多列，每行所述像素电路单元中，多个所述像素电路单元沿所述第一方向排列，每列所述像素电路单元中，多个所述像素电路单元沿所述第二方向排列，所述显示面板还包括：
    多条第一信号线，每条所述第一信号线连接一行所述像素电路单元，所述第一信号线包括第一线段和第二线段，所述第一线段在所述衬底上的正投影位于所述像素电路在所述衬底上的正投影内，所述第二线段连接于相邻所述像素电路单元之间，至少一个所述第二线段的延伸方向相对于所述第一线段的延伸方向倾斜设置。
  8. 根据权利要求7所述的显示面板，其中，每个所述像素电路单元设有至少两个所述排布单元，所述第一信号线还包括第三线段，所述第三线段在所述像素电路单元中连接于相邻所述排布单元之间，至少一个所述第三线段的延伸方向相对于所述第二线段的延伸方向倾斜设置。
  9. 根据权利要求1所述的显示面板，其中，所述多个像素电路单元排布为多行及多列，每行所述像素电路单元中，多个所述像素电路单元沿所述第一方向排列，每列所述像素电路单元中，多个所述像素电路单元沿所述第二方向排列，所述显示面板还包括：
    第二信号线组，每组所述第二信号线组连接一列所述像素电路单元，每组所述第二信号线组包括多条所述第二信号线，每条所述第二信号线包括第四线段和第五线段，所述第四线段在所述衬底上的正投影位于所述像素电路在所述衬底上的正投影内，所述第五线段连接于相邻所述像素电路单元之间，至少两条所述第二信号线在所述第五线段处相对在所述第四线段处彼此靠拢。
  10. 根据权利要求2所述的显示面板，其中，每个所述像素单元的所述子像素包括第一颜色子像素、第二颜色子像素以及第三颜色子像素，每个所述第三颜色子像素的发光面积小于每个所述第一颜色子像素的发光面积，且小于每个所述第二颜色子像素的发光面积，所述排布单元在所述衬底上的正投影与所述第一颜色子像素和/或所述第二颜色子像素的正投影交叠。
  11. 根据权利要求1所述的显示面板，其中，至少部分相邻所述排布单元之间连接有导线，其中，所述导线为透光导线。
  12. 根据权利要求1所述的显示面板，其中，至少部分相邻所述排布单元之间连接有导线，所述导线包括在垂直于所述衬底方向上层叠的第一导体层和第二导体层，所述第一导体层的电阻率低于所述第二导体层的电阻率，所述第二导体层的透光率大于所述第一导体层的透光率，所述第一导体层在所述衬底上的正投影位于所述第二导体层在所述衬底上的正投影以内。
  13. 根据权利要求2所述的显示面板，其中，P个所述子像素在所述衬底上的正投影完全覆盖每个所述像素电路单元设有的所有所述排布单元在所述衬底上的正投影。
  14. 根据权利要求7所述的显示面板，其中，相邻所述第一信号线的所述第二线段的延伸方向彼此相交。
  15. 根据权利要求8所述的显示面板，其中，相邻所述第一信号线的所述第三线段的延伸方向彼此相交。
  16. 根据权利要求7所述的显示面板，其中，所述第一信号线包括扫描信号线、发光信号线中的至少一种。
  17. 根据权利要求9所述的显示面板，其中，所述第二信号线包括数据信号线、供电信号线中的至少一种。
  18. 根据权利要求7所述的显示面板，其中，相邻所述第一信号线的所述第二线段的延伸方向彼此平行。
  19. 根据权利要求8所述的显示面板，其中，相邻所述第一信号线的所述第三线段的延伸方向彼此平行。
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