WO2022160556A1 - Gaa晶体管及其制备方法、电子设备 - Google Patents

Gaa晶体管及其制备方法、电子设备 Download PDF

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Publication number
WO2022160556A1
WO2022160556A1 PCT/CN2021/099380 CN2021099380W WO2022160556A1 WO 2022160556 A1 WO2022160556 A1 WO 2022160556A1 CN 2021099380 W CN2021099380 W CN 2021099380W WO 2022160556 A1 WO2022160556 A1 WO 2022160556A1
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Prior art keywords
fin
substrate
etching
layer
epitaxial layer
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PCT/CN2021/099380
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English (en)
French (fr)
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张卫
徐敏
陈鲲
杨静雯
徐赛生
王晨
吴春蕾
尹睿
Original Assignee
复旦大学
上海集成电路制造创新中心有限公司
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Publication of WO2022160556A1 publication Critical patent/WO2022160556A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the invention relates to the field of semiconductors, in particular to a GAA transistor, a preparation method thereof, and an electronic device.
  • a transistor can be understood as a current switch structure made of semiconductor materials.
  • a gate metal
  • the source semiconductor
  • the drain semiconductor
  • the on-off of the current between the source and the drain can be controlled by the gate.
  • GAA transistor The full name of GAA is Gate-All-Around, which is a surround gate technology.
  • GAA transistors can also be called GAAFETs.
  • the present invention provides a GAA transistor, a preparation method thereof, and an electronic device to solve the problem that the generated parasitic transistor will affect the gate control capability.
  • a method for preparing a GAA transistor comprising:
  • the epitaxial layer comprising alternately stacked sacrificial layers and silicon layers, wherein a layer of the epitaxial layer in contact with the substrate is a bottom sacrificial layer;
  • the highest point of the middle and bottom sacrificial layer is not lower than the connection between the substrate and the bottom sacrificial layer; the first side and the second side of the fin are opposite sides of a pair of fins;
  • a source is formed in the source region, and a drain is formed in the drain region.
  • etching the remaining epitaxial layer in the fin to etch the source region and the drain region on the first side and the second side of the fin including:
  • the change of the corresponding etching depth is detected, and after the etching reaches the final end point, the etching is stopped.
  • performing the first etching on the remaining epitaxial layer in the fin includes: performing the first etching by means of plasma etching;
  • the second etching is performed on the remaining epitaxial layer in the fin, including: performing the second etching by using at least one of plasma etching means, gas etching means, and wet etching means.
  • detecting the change in the corresponding etching depth includes: detecting the change in the etching depth by using an OES or IEP detection method.
  • the etching end point of the first etching is higher than the highest position of the corresponding underlying sacrificial layer.
  • the final end point of the second etching is matched with the connection between the substrate and the bottom sacrificial layer.
  • etching the remaining epitaxial layer in the fin to etch out the source region and the drain region on both sides of the fin further comprising:
  • An isolation layer is formed on the substrate outside the third side and the fourth side of the fin; wherein, the third side and the fourth side of the fin are opposite sides of another pair of fins;
  • a dielectric layer is formed on the outer wall of the dummy gate stack, and the dielectric layer is distributed on the isolation layer and the fin.
  • forming a dielectric layer on the outer wall of the dummy gate stack includes:
  • a portion of the dielectric layer above the dummy gate stack is ground away.
  • the isolation layer is a SiO 2 layer.
  • the sacrificial layer is a SiGe layer.
  • a GAA transistor comprising: a fin, a source electrode disposed in a source region, and a drain electrode disposed in the drain region, the fin comprising a substrate-in-fin, and a An epitaxial layer on the substrate in the fin, the epitaxial layer includes alternately stacked sacrificial layers and silicon layers, wherein the sacrificial layer in contact with the substrate in the fin is the bottom sacrificial layer; the source and The drain is arranged on the first side and the second side of the fin, and the bottom of the source region and the drain region is not lower than the connection between the substrate and the bottom sacrificial layer in the fin where the bottom of the source region and the drain region is lower than the top of the bottom sacrificial layer, and the first side and the second side of the fin are opposite sides of a pair of fins.
  • the GAA transistor further includes a transistor substrate, the transistor substrate includes a transistor substrate, the substrate in the fin is located on the transistor substrate, and the substrate in the fin and the transistor substrate are integrated of.
  • the transistor substrate further includes an isolation layer, the isolation layer is provided on the transistor substrate and is located outside the third side and the fourth side of the fin, wherein the third side of the fin The fourth side is the opposite side of the other pair of fins.
  • the GAA transistor further includes a dummy gate stack and a dielectric layer, the dummy gate stack spans the top of the fin, the third sidewall, and the fourth sidewall, so The dielectric layer is disposed on the outer wall of the dummy gate stack and is spaced between the outer wall of the dummy gate stack and the source region, and the outer wall of the dummy gate stack and the between the drain regions.
  • the GAA transistor is prepared by using the preparation method involved in the first aspect and its optional solution.
  • an electronic device including the GAA transistor involved in the second aspect and its optional solutions.
  • the preparation method thereof, and the electronic device provided by the present invention since the bottoms of the source region and the drain region are not lower than the connection between the substrate and the bottom sacrificial layer in the fin, further, Avoid over-etching (etching more than the underlying sacrificial layer) when forming the source and drain regions, thereby avoiding the resulting parasitic transistors, that is, physically avoiding the generation of parasitic FinFET sources and drains, making it impossible to derive parasitic currents, effectively improving gate control capability.
  • 1 is a schematic diagram of the principle of forming a parasitic transistor by source-drain overetching in the prior art
  • Fig. 2 is a kind of simulation curve schematic diagram one of the existing GAA transistor
  • Fig. 3 is a kind of simulation curve schematic diagram II of the existing GAA transistor
  • FIG. 4 is a schematic diagram of a partial structure of a GAA transistor in an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a GAA transistor in an embodiment of the present invention.
  • FIG. 6 is a schematic flow chart 1 of a method for manufacturing a GAA transistor in an embodiment of the present invention
  • step S14 is a schematic flowchart of step S14 in an embodiment of the present invention.
  • FIG. 8 is a second schematic flowchart of a method for manufacturing a GAA transistor according to an embodiment of the present invention.
  • FIG. 9 is a schematic flowchart of step S18 in an embodiment of the present invention.
  • step S12 is implemented in an embodiment of the present invention.
  • FIG. 11a and 11b are schematic structural diagrams after step S13 is implemented in an embodiment of the present invention.
  • step S16 is implemented in an embodiment of the present invention.
  • FIG. 13a and 13b are schematic structural diagrams after step S17 is implemented in an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram after step S181 is implemented in an embodiment of the present invention.
  • 15a and 15b are schematic structural diagrams after step S182 is implemented in an embodiment of the present invention.
  • FIG. 16 is a schematic structural diagram after step S141 is implemented in an embodiment of the present invention.
  • FIG. 17 is a schematic structural diagram after step S142 is implemented in an embodiment of the present invention.
  • FIG. 1 illustrates a transistor substrate 203 and a fin.
  • the fin includes the substrate 202 in the fin and the epitaxial layer 201 thereon.
  • the silicon material in the transistor substrate 203 can be combined with the substrate 202 in the fin.
  • the base 202 is unitary.
  • the source region and the drain region for making the source electrode and the drain electrode can be formed on both sides of the fin (eg, the left and right sides in FIG. 1 ).
  • the source-drain overetching situation shown in FIG. 1 can be formed, wherein the distance between the bottom of the epitaxial layer and the etching end point can be characterized as the etching depth Hsd.
  • the structural characteristics of parasitic transistors depend on the shape of the substrate and different gate/source-drain heights.
  • the current mainstream process routes parasitic transistors into FinFET structures to enhance the gate control capability of parasitic transistors and reduce the impact of parasitic transistors on performance. This means that the structure generated from this process route becomes a parallel connection of parasitic FinFET and GAA MOSFET as a whole. Therefore, compared with a simple GAA transistor, the gate control capability of the overall device will inevitably be reduced, flooding the GAA transistor. Outstanding performance.
  • FIG. 2 When using the existing transistor for simulation, as shown in FIG. 2, it shows the relationship between the etching depth Hsd and the source line signal SSLin, as shown in FIG. 3, which shows the etching depth Hsd and the switching current ratio ( That is, the relationship between Ion/off Ratio), it can be seen that based on the etching depth Hsd of the source and drain regions, a parasitic transistor PT (which can be understood as: Parasitic Transistor) can be formed.
  • the larger the Hsd) the more obvious the effect of the parasitic transistor, the larger the source line signal SSLin, and the smaller the switching current ratio (that is, the gate control capability is weakened).
  • the embodiment of the present invention creatively discovers the relationship between the etching depth and the gate control capability during the preparation of the GAA transistor, thereby forming a technical solution capable of limiting the etching depth.
  • an embodiment of the present invention provides a GAA transistor including: a fin, a source electrode disposed in the source region 102 and a drain electrode disposed in the drain region 103 , and the fin includes a substrate-in-fin 101, and an epitaxial layer disposed on the substrate 101 in the fin, the epitaxial layer including alternately stacked sacrificial layers and silicon layers.
  • the sacrificial layer in contact with the substrate in the fin is the bottom sacrificial layer 104, and the rest of the sacrificial layers can be, for example, the sacrificial layers 106 shown in FIG. Silicon layer 107 .
  • the numbers of silicon layers and sacrificial layers are not limited to those shown in FIG. 4 and other drawings, and the thicknesses thereof are also not limited thereto.
  • the source electrode (which can be understood by referring to the source region 102 in FIG. 4 ) and the drain electrode (which can be understood by referring to the drain region 103 in FIG. 4 ) are provided on the first and second sides of the fin ( It can be understood as the two sides along the first direction, the first direction can be, for example, the left and right directions shown in FIG. 4 and FIG. 5 ), and the bottoms of the source region 102 and the drain region 103 are not lower than the At the connection between the substrate 101 and the bottom sacrificial layer 104 in the fin, the bottom of the source region 102 and the drain region 103 is lower than the top of the bottom sacrificial layer 104 .
  • the source region 102 can be understood as a region etched for accommodating and forming a source electrode
  • the drain region 103 can be understood as a region etched for accommodating and forming a drain.
  • the source region only the source can be included, and other structures can also be included. If the number of sources is multiple, the sources can be spaced or not spaced.
  • the drain region the Only the drains are included, and other structures may also be included. If the number of drains is multiple, the drains may be spaced or not spaced.
  • both sides (ie, the first side and the second side) of the layer 104 along the first direction may have a sacrificial layer retention layer 108 and a sacrificial layer retention layer 109 , and the sacrificial layer retention layer 108 is provided on the source region 102 and the substrate 101 in the fin In between, the sacrificial layer retention layer 109 is disposed between the drain region 103 and the substrate-in-fin 101.
  • the bottoms of the source region 102 and the drain region 103 can also be flush with the top of the substrate-in-fin 101 (Or can be understood as being flat on the connection between the substrate 101 and the underlying sacrificial layer 104 in the fin).
  • the material of the sacrificial layer may be, for example, SiGe, but is not limited thereto, and any material that can facilitate the realization of the channel layer does not deviate from the scope of the embodiments of the present invention.
  • the over-etching (etching) when forming the source and drain regions is avoided. etched more than the bottom sacrificial layer), thereby avoiding the parasitic transistor caused by it, that is, physically avoiding the generation of parasitic FinFET source and drain, making it impossible to derive parasitic current, and effectively improving the gate control capability.
  • the creative contribution of the embodiments of the present invention is not only in that the bottom of the source region and the drain region is not lower than the connection between the substrate in the fin and the bottom sacrificial layer, nor is it only in the process of realizing the structure, It is also found in the embodiment of the present invention that as the etching depth of the source and drain regions is deeper, the effect of the parasitic transistor is more obvious, the source line signal is larger, and the switching current ratio is smaller (that is, the gate control capability is weakened). , and solve the problem of this phenomenon by physically avoiding the generation of parasitic FinFET source and drain. Anything in the art that does not specify the technical problem, nor declare a solution to the technical problem, is difficult to give corresponding technical inspiration.
  • the GAA transistor further includes a transistor substrate
  • the transistor substrate includes a transistor substrate 113
  • the substrate-in-fin 101 is located on the transistor substrate 113
  • the substrate-in-fin 101 Being integral with the transistor substrate 113 , the mid-fin substrate 101 and the transistor substrate 113 may specifically be different structures formed by etching the substrate.
  • the material of the transistor base, the base in the fin, and the substrate can be silicon or other materials based on silicon, or other materials.
  • the substrate can be a silicon substrate, a silicon germanium substrate, or formed of other semiconductor materials.
  • the substrate, meanwhile, the transistor substrate, the substrate in the fin, and the substrate may be specifically doped or undoped.
  • the transistor substrate further includes an isolation layer 112, the isolation layer 112 is disposed on the transistor substrate 113, and is located outside the third side and the fourth side of the fin, wherein the third side of the fin.
  • the three sides and the fourth side are opposite sides of another pair of fins, wherein the fins may have four sides, wherein the first side, the third side, the second side and the fourth side are connected and enclosed in sequence.
  • the isolation layer 112 can be understood as any structure that can achieve the isolation effect.
  • the material of the isolation layer 112 can be oxide, and further, the material of the isolation layer 112 can be, for example, silicon dioxide (SiO 2 ), Germanium dioxide (GeO 2 ), etc., but not limited thereto.
  • the GAA transistor further includes a dummy gate stack 110 and a dielectric layer 111 , and the dummy gate stack 110 spans the top of the fin, the third sidewall, the third Four sidewalls, the dielectric layer 111 is disposed on the outer wall of the dummy gate stack 110 and separated between the outer wall of the dummy gate stack 110 and the source region 102 , and the Between the outer wall of the dummy gate stack 110 and the drain region 103 .
  • the dummy gate stacks therein may, for example, comprise polysilicon, although other materials may also be used.
  • the material of the dielectric layer 11 may be a dielectric material such as silicon oxycarbonitride (SiOCN), silicon nitride (Si3N4), etc., which may be a single-layer structure or a multi-layer structure.
  • the above GAA transistors can be prepared based on the preparation methods provided in the embodiments of the present invention, and other preparation methods are not excluded.
  • the preparation method of GAA transistor including:
  • S12 forming an epitaxial layer on the substrate, the epitaxial layer comprising alternately stacked sacrificial layers and silicon layers, wherein a layer of the epitaxial layer in contact with the substrate is a bottom sacrificial layer;
  • an epitaxial layer can be epitaxial on the substrate 114, and in the epitaxial time, a sacrificial layer of SiGe and a silicon layer (Si layer) can be epitaxial in turn as a cycle to complete the process.
  • a sacrificial layer of SiGe and a silicon layer Si layer
  • One or more cycles to form a SiGe/Si multi-layered layer wherein the thickness of the sacrificial layer of SiGe can be in the range of 3nm-30nm, the thickness of the silicon layer can also be in the range of 3nm-30nm, each sacrificial layer,
  • the thickness, material, and number of layers of the silicon layer are not limited to the above examples.
  • doping techniques such as ion implantation or in-situ epitaxy doping can also be used to dope the upper surface of the substrate (the doping concentration range can be, for example, 1e15-1e19). between), changing its top surface properties to help improve the selectivity of post-etching.
  • the substrate and the epitaxial layer can be etched on both sides of the substrate and the epitaxial layer along the second direction (the second direction is perpendicular to the first direction mentioned above, that is, the left-right direction shown in FIG. 11a).
  • the second direction is perpendicular to the first direction mentioned above, that is, the left-right direction shown in FIG. 11a.
  • the epitaxial layer and the substrate ie, the substrate-in-fins 101
  • the two sides of the fin along the second direction ie, the left and right sides shown in FIG. 11 a
  • step S13 and before step S14 it may further include:
  • S16 forming an isolation layer on the substrate outside the third side and the fourth side of the fin; wherein the third side and the fourth side of the fin are opposite sides of another pair of fins;
  • S17 forming a dummy gate stack across the top of the fin, the third sidewall and the fourth sidewall on the isolation layer and the fin;
  • the third and fourth sides of the fin involved are the left and right sides of the fin in FIG. 12 .
  • the formation method of the isolation layer 112 can be understood with reference to any method of forming an isolation layer in the art, and a suitable process can be arbitrarily selected according to the materials used.
  • the third side and the fourth side of the fin are the left and right sides of the fin in FIG. 13a, correspondingly, the left and right direction is the second direction
  • the first side and the second side are the left and right sides of the fin in FIG. 13b, correspondingly, the left and right direction is the first direction
  • the dummy gate stack 110 can be formed into a zigzag-shaped structure, with two ends of the zigzag. It can be connected to the isolation layer 112, and the inner side of the indented dummy gate stack 110 can be respectively connected to the upper surface of the epitaxial layer, the sidewalls on both sides of the epitaxial layer, and the sidewalls on both sides of the substrate 101 in some fins.
  • the side walls on both sides may be understood as two side walls perpendicular to the second direction, and may also be understood as two side walls parallel to the first direction.
  • step S18 may include:
  • S182 Grind off a portion of the dielectric layer higher than the dummy gate stack.
  • the dielectric layer 111 may specifically surround and connect to the top of the dummy gate stack 110, the sidewall of the first side along the second direction, and the first sidewall along the second direction.
  • the sidewalls on both sides and the bottom of the dielectric layer 111 can be connected to the isolation layer 112 .
  • the dielectric layer 111 may further surround the sidewalls of the dummy gate stack 110 along the first side along the first direction and the sidewalls along the second side along the first direction.
  • the top of the dummy gate stack and the top of the dielectric layer 111 may be flat.
  • step S141 may include:
  • the embodiments of the present invention creatively require etching depth (that is, the source The bottom of the electrode region and the drain region is not lower than the connection between the substrate in the fin and the bottom sacrificial layer), therefore, in the above scheme, in order to accurately meet the special requirements of the etching depth, only the introduction
  • the solution of step S141 and step S142 is provided, which can effectively and accurately ensure that the etching depth will not be lower than the connection between the substrate and the bottom sacrificial layer in the fin.
  • performing the first etching on the remaining epitaxial layer in the fin may include: performing the first etching by means of plasma etching.
  • the etching end point of the first etching can be higher than the highest point of the corresponding bottom sacrificial layer 104 (it can also be understood as not etched to the bottom sacrificial layer), for example, only the bottom layer is etched
  • the etching end point of the first etching may also be lower than the highest point of the underlying sacrificial layer 104 .
  • high-directional high-selectivity plasma etching technology can be used for the first etching (the gas used includes one or more of fluorine-containing alkanes, chlorine-based others, hydrogen, oxygen, and inert gases. combination) etch away most of the fin above the isolation layer.
  • performing the second etching on the remaining epitaxial layer in the fin includes: performing the second etching by using at least one of plasma etching means, gas etching means, and wet etching means; Detecting the change of the corresponding etching depth, including: using the OES or IEP detection method to detect the change of the etching depth.
  • OES specifically Optical Emission Spectroscopy
  • IEP is specifically Interferometric EndPoint, which can be understood as: interferometric end point.
  • the final end point of the second etching is matched with the connection between the substrate and the underlying sacrificial layer, for example, exactly at the connection, or close to the connection (for example, with the connection difference is less than a certain threshold).
  • the sacrificial layer retention layer 108 and the sacrificial layer retention layer 109 may be formed after the second etching.
  • technologies such as plasma gas etching process endpoint detection technology (including OES, IEP and other detection technologies), high-selectivity gas etching, high-selectivity wet etching and other technologies can be used.
  • the combination of completes the second etching, so that the final etching depth is not lower than the highest point of the lowermost substrate and not higher than the highest point of the bottom sacrificial layer.
  • the source electrode and the drain electrode may be fabricated by suitable techniques and combinations such as deposition and epitaxy. No matter which technique is used to fabricate the source electrode and the drain electrode, it does not deviate from the scope of the embodiments of the present invention.
  • step S15 process steps such as filling dielectric and planarizing may also be included.
  • Embodiments of the present invention also provide an electronic device, including the GAA transistors involved in the above optional solutions, such as the GAA transistors involved in FIGS.

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Abstract

本发明提供了一种GAA晶体管及其制备方法、电子设备，其中的制备方法，包括：提供一衬底；在所述衬底上形成外延层，所述外延层包括交替层叠的牺牲层与硅层，其中，所述外延层中与所述衬底相接触的一层为底层牺牲层；刻蚀所述衬底与所述外延层，以形成鳍片；刻蚀所述鳍片中剩余的外延层，以在鳍片的第一侧与第二侧刻蚀出源极区域与漏极区域，其中，刻蚀的最终终点低于所述剩余的外延层中底层牺牲层的最高处，且不低于衬底与底层牺牲层的连接处；鳍片的第一侧与第二侧为鳍片一对相对的两侧；在所述源极区域制作源极，在所述漏极区域制作漏极。

Description

GAA晶体管及其制备方法、电子设备 技术领域
本发明涉及半导体领域，尤其涉及一种GAA晶体管及其制备方法、电子设备。
背景技术
晶体管，可理解为用半导体材料制作的电流开关结构。例如：源极(半导体)与漏极(半导体)之间，可设有栅极(金属)，进而，可利用栅极来控制电流在源极与漏极之间的通断。其中一种晶体管为GAA晶体管。GAA全称为Gate-All-Around，是一种环绕式栅极技术，GAA晶体管也可叫做GAAFET。
在目前主流的GAA工艺中，可以先制作带牺牲层的Fin结构，再去除牺牲层形成悬空GAA的方案，然而，该工艺路线会不可避免的在GAA晶体管下方的衬底形成寄生晶体管，所产生的寄生晶体管会影响栅控能力。
发明内容
本发明提供一种GAA晶体管及其制备方法、电子设备，以解决所产生的寄生晶体管会影响栅控能力的问题。
根据本发明的第一方面，提供了一种GAA晶体管的制备方法，包括：
提供一衬底；
在所述衬底上形成外延层，所述外延层包括交替层叠的牺牲层与硅层，其中，所述外延层中与所述衬底相接触的一层为底层牺牲层；
刻蚀所述衬底与所述外延层，以形成鳍片；
刻蚀所述鳍片中剩余的外延层，以在鳍片的第一侧与第二侧刻蚀出源极区域与漏极区域，其中，刻蚀的最终终点低于所述剩余的外延层中底层牺牲层的最高处，且不低于衬底与底层牺牲层的连接处；鳍片的第一侧与第二侧为鳍片一对相对的两侧；
在所述源极区域制作源极，在所述漏极区域制作漏极。
可选的，刻蚀所述鳍片中剩余的外延层，以在鳍片的第一侧与第二侧刻蚀出源极区域与漏极区域，包括：
对所述鳍片中剩余的外延层进行第一次刻蚀；
边对所述鳍片中剩余的外延层进行第二次刻蚀，边检测对应刻蚀深度的变化，并在刻蚀到所述最终终点之后，停止刻蚀。
可选的，对所述鳍片中剩余的外延层进行第一次刻蚀，包括：采用等离子刻蚀手段实施所述第一次刻蚀；
对所述鳍片中剩余的外延层进行第二次刻蚀，包括：采用等离子刻蚀手段、气体刻蚀手段、湿法刻蚀手段中至少之一实施所述第二次刻蚀。
可选的，检测对应刻蚀深度的变化，包括：采用OES或IEP检测手段检测刻蚀深度的变化。
可选的，所述第一次刻蚀的刻蚀终点高于对应底层牺牲层的最高处。
可选的，所述第二次刻蚀的最终终点匹配于所述衬底与所述底层牺牲层的连接处。
可选的，刻蚀所述鳍片中剩余的外延层，以在鳍片两侧刻蚀出源极区域与漏极区域之前，还包括：
在所述鳍片的第三侧外与第四侧外的衬底上形成隔离层；其中，鳍片的第三侧与第四侧为鳍片另一对相对的两侧；
在所述隔离层与所述鳍片上形成横跨所述鳍片顶部、第三侧侧壁与第四侧侧壁的伪栅极堆叠件；
在所述伪栅极堆叠件的外壁形成介电层，所述介电层分布于所述隔离层与所述鳍片上。
可选的，在所述伪栅极堆叠件的外壁形成介电层，包括：
在所述伪栅极堆叠件、所述隔离层与所述鳍片上形成包围所述伪栅极堆叠件外壁的介电层；
磨去所述介电层中高于伪栅极堆叠件的部分。
可选的，所述隔离层为SiO 2层。
可选的，所述牺牲层为SiGe层。
根据本发明的第二方面，提供了一种GAA晶体管，包括：鳍片、设于 源极区域的源极与设于漏极区域的漏极，所述鳍片包括鳍片中基底，以及设于所述鳍片中基底上的外延层，所述外延层包括交替层叠的牺牲层与硅层，其中，与所述鳍片中基底相接触的牺牲层为底层牺牲层；所述源极与所述漏极设于所述鳍片的第一侧与第二侧，且所述源极区域与所述漏极区域的底部不低于所述鳍片中基底与所述底层牺牲层的连接处，所述源极区域与所述漏极区域的底部低于所述底层牺牲层的顶部，，鳍片的第一侧与第二侧为鳍片一对相对的两侧。
可选的，所述的GAA晶体管，还包括晶体管基底，所述晶体管基底包括晶体管基底，所述鳍片中基底位于所述晶体管基底上，且所述鳍片中基底与所述晶体管基底是一体的。
可选的，所述晶体管基底还包括隔离层，所述隔离层设于所述晶体管基底上，且位于所述鳍片的第三侧外与第四侧外，其中，鳍片的第三侧与第四侧为鳍片另一对相对的两侧。
可选的，所述的GAA晶体管，还包括伪栅极堆叠件与介电层，所述伪栅极堆叠件横跨所述鳍片顶部、第三侧侧壁、第四侧侧壁，所述介电层设于所述伪栅极堆叠件的外壁，且隔于所述伪栅极堆叠件的外壁与所述源极区域之间，以及所述伪栅极堆叠件的外壁与所述漏极区域之间。
可选的，所述的GAA晶体管，采用第一方面及其可选方案涉及的制备方法制备而成的。
根据本发明的第三方面，提供了一种电子设备，包括第二方面及其可选方案涉及的GAA晶体管。
本发明提供的GAA晶体管及其制备方法、电子设备中，由于所述源极区域与所述漏极区域的底部不低于所述鳍片中基底与所述底层牺牲层的连接处，进而，避免形成源漏区域时的过刻(刻蚀超过底层牺牲层)，进而避免了因此而产生的寄生晶体管，即：从物理上避免寄生FinFET源漏的产生，使其无法导出寄生电流，有效提高了栅控能力。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面 描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中源漏过刻形成寄生晶体管的原理示意图；
图2是现有的GAA晶体管的一种仿真曲线示意图一；
图3是现有的GAA晶体管的一种仿真曲线示意图二；
图4是本发明一实施例中GAA晶体管的部分结构示意图；
图5是本发明一实施例中GAA晶体管的结构示意图；
图6是本发明一实施例中GAA晶体管的制备方法的流程示意图一；
图7是本发明一实施例中步骤S14的流程示意图；
图8是本发明一实施例中GAA晶体管的制备方法的流程示意图二；
图9是本发明一实施例中步骤S18的流程示意图；
图10是本发明一实施例中实施步骤S12之后的结构示意图；
图11a与图11b是本发明一实施例中实施步骤S13之后的结构示意图；
图12是本发明一实施例中实施步骤S16之后的结构示意图；
图13a与图13b是本发明一实施例中实施步骤S17之后的结构示意图；
图14是本发明一实施例中实施步骤S181之后的结构示意图；
图15a与图15b是本发明一实施例中实施步骤S182之后的结构示意图；
图16是本发明一实施例中实施步骤S141之后的结构示意图；
图17是本发明一实施例中实施步骤S142之后的结构示意图。
附图标记说明：
101-鳍片中基底；
102-源极区域；
103-漏极区域；
104-底层牺牲层；
105-硅层；
106-牺牲层；
107-硅层；
108-牺牲层保留层；
109-牺牲层保留层；
110-伪栅极堆叠件；
111-介电层；
112-隔离层；
113-晶体管基底；
114-衬底；
201-外延层；
202-鳍片中基底；
203-晶体管基底。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
下面以具体地实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
为了能对本发明实施例的方案进行准确的阐述，以下将结合图1至图3，对现有技术中所存在的部分缺陷进行具体的说明。
在现有相关技术中，请参考图1，示意了晶体管基底203与鳍片，鳍片包括了鳍片中基底202与其上的外延层201，晶体管基底203中的硅材,可以与鳍片中基底202是一体的。在制作过程中，通过对外延层、以及衬底的刻蚀，可在鳍片的两侧(例如图1中左右两侧)形成用于制作源极、漏极的源极区域与漏极区域，进而，可形成图1所示的源漏过刻的情形，其中，外延层底 部至刻蚀终点之间的距离可表征为刻蚀深度Hsd。
寄生晶体管的结构特性取决于基底的形状和不同的栅极/源漏高度，目前主流工艺路线将寄生晶体管制作成FinFET的结构，增强寄生晶体管栅极控制能力，减小寄生晶体管对性能的影响。这样一来就意味着从该工艺路线生成的结构从整体上变成寄生FinFET和GAA MOSFET的并联，因此，相比单纯的GAA晶体管会不可避免的降低整体器件的栅控能力，淹没GAA晶体管的突出性能。
在利用现有的晶体管进行仿真时，如图2所示，其示意了刻蚀深度Hsd与源极线信号SSLin的关系，如图3所示，其示意了刻蚀深度Hsd与开关电流比(即Ion/off Ratio)的关系，可见，基于源漏区域的刻蚀深度Hsd，可形成寄生晶体管PT(其可理解为：Parasitic Transistor)，随着源漏区域刻蚀深度越深(即刻蚀深度Hsd越大)，寄生晶体管的效应越明显，源极线信号SSLin越大，开关电流比越小(即栅控能力减弱)。
进而，本发明实施例创造性地发现了GAA晶体管制备过程中刻蚀深度与栅控能力的关系，进而形成了一种能够对该刻蚀深度进行限制的技术方案。
请参考图4，本发明实施例提供了一种GAA晶体管，包括：鳍片、设于源极区域102的源极与设于漏极区域103的漏极，所述鳍片包括鳍片中基底101，以及设于所述鳍片中基底101上的外延层，所述外延层包括交替层叠的牺牲层与硅层。
其中，与所述鳍片中基底相接触的牺牲层为底层牺牲层104，其余的牺牲层可例如图4所示的牺牲层106，其中的硅层可例如图4所示的硅层105与硅层107。在其他举例中，硅层、牺牲层的数量可不限于图4及其他附图所示，其厚度也可不限于此。
所述源极(可参见图4中的源极区域102理解)与所述漏极(可参见图4中的漏极区域103理解)设于所述鳍片的第一侧与第二侧(可理解为沿第一方向的两侧，该第一方向可例如为图4、图5所示的左右方向)，且所述源极区域102与所述漏极区域103的底部不低于所述鳍片中基底101与所述底层牺牲层104的连接处，所述源极区域102与所述漏极区域103的底部低于所述底层牺牲层104的顶部。
其中的源极区域102可理解为刻蚀出的用于容置并形成源极的区域，漏 极区域103可理解为刻蚀出的用于容置并形成漏极的区域。在源极区域中，可以仅包含源极，也可包含其他结构，若源极数量为多个，则源极可以是间隔设置的，也可以是未间隔设置的，在漏极区域中，可以仅包含漏极，也可包含其他结构，若漏极数量为多个，则漏极可以是间隔设置的，也可以是未间隔设置的。
其中，一种举例中，当所述源极区域102与所述漏极区域103的底部高于鳍片中基底101与所述底层牺牲层104的连接处时，如图4所示，底层牺牲层104沿第一方向的两侧(即第一侧与第二侧)可具有牺牲层保留层108与牺牲层保留层109，牺牲层保留层108设于源极区域102与鳍片中基底101之间，牺牲层保留层109设于漏极区域103与鳍片中基底101之间，另一举例中，源极区域102与漏极区域103的底部也可以与鳍片中基底101的顶部持平(或可理解为持平于鳍片中基底101与底层牺牲层104的连接处)。
其中的牺牲层材料可例如为SiGe，但也不限于此，任意可便于实现沟道层的材料，均不脱离本发明实施例的范围。
以上方案中，由于所述源极区域与所述漏极区域的底部不低于所述鳍片中基底与所述底层牺牲层的连接处，进而，避免形成源漏区域时的过刻(刻蚀超过底层牺牲层)，进而避免了因此而产生的寄生晶体管，即：从物理上避免寄生FinFET源漏的产生，使其无法导出寄生电流，有效提高了栅控能力。
此外，本发明实施例的创造性贡献不仅仅在于源极区域与漏极区域的底部不低于所述鳍片中基底与所述底层牺牲层的连接处，也不仅仅在于实现该结构的工艺，还在于：本发明实施例创造性地发现了：随着源漏区域刻蚀深度越深，寄生晶体管的效应越明显，源极线信越大，开关电流比越小(即栅控能力减弱)的现象，并通过物理上避免寄生FinFET源漏产生的思路来解决这一现象的问题。本领域任意未指明该技术问题，也未声明解决该技术问题的方案，均难以给出相应的技术启示。
其中一种实施方式中，所述的GAA晶体管，还包括晶体管基底，所述晶体管基底包括晶体管基底113，所述鳍片中基底101位于所述晶体管基底113上，且所述鳍片中基底101与所述晶体管基底113是一体的，所述鳍片 中基底101与所述晶体管基底113具体可以是对衬底进行刻蚀后所形成的不同结构。
晶体管基底、鳍片中基底、衬底的材料可以是硅或基于硅的其他材质，也可以为其他材料，例如，该衬底可以为硅衬底、硅锗衬底或由其他半导体材料形成的衬底，同时，晶体管基底、鳍片中基底、衬底具体可以是掺杂的，也可以是不掺杂的。
进一步的，所述晶体管基底还包括隔离层112，所述隔离层112设于所述晶体管基底113上，且位于所述鳍片的第三侧外与第四侧外，其中，鳍片的第三侧与第四侧为鳍片另一对相对的两侧，其中，鳍片可具有四侧，其中的第一侧、第三侧、第二侧与第四侧依次连接围合。
其中的隔离层112，可理解为能实现隔离效果的任意结构，具体举例中，隔离层112的材料可以为氧化物，进一步的，隔离层112的材料可例如为二氧化硅(SiO 2)、二氧化锗(GeO 2)等，但也不限于此。
其中一种实施方式中，所述的GAA晶体管，还包括伪栅极堆叠件110与介电层111，所述伪栅极堆叠件110横跨所述鳍片顶部、第三侧侧壁、第四侧侧壁，所述介电层111设于所述伪栅极堆叠件110的外壁，且隔于所述伪栅极堆叠件110的外壁与所述源极区域102之间，以及所述伪栅极堆叠件110的外壁与所述漏极区域103之间。
其中的伪栅极堆叠件可例如包含多晶硅，但也可以使用其他材料。介电层11的材料可例如碳氮氧化硅(SiOCN)、氮化硅(Si3N4)等的介电材料，其可以为单层结构，也可以为多层结构。
以上GAA晶体管可基于本发明实施例提供的制备方法制备而成，也不排除采用其他制备方法进行制备的方案。
请参考图6，GAA晶体管的制备方法，包括：
S11：提供一衬底；
S12：在所述衬底上形成外延层，所述外延层包括交替层叠的牺牲层与硅层，其中，所述外延层中与所述衬底相接触的一层为底层牺牲层；
S13：刻蚀所述衬底与所述外延层，以形成鳍片；
S14：刻蚀所述鳍片中剩余的外延层，以在鳍片的第一侧与第二侧刻蚀出源极区域与漏极区域，其中，刻蚀的最终终点低于所述剩余的外延层中底 层牺牲层的最高处，且不低于衬底与底层牺牲层的连接处；鳍片的第一侧与第二侧为鳍片一对相对的两侧；
S14：在所述源极区域制作源极，在所述漏极区域制作漏极。
针对于其中的步骤S12，请参考图10，一种举例中，可以在衬底114上外延外延层，在外延时，可以依次外延SiGe的牺牲层、硅层(Si层)作为一个循环，完成一次或多次循环，形成SiGe/Si多层叠层，其中，SiGe的牺牲层的厚度可处于3nm-30nm的区间范围内，硅层的厚度也可处于3nm-30nm的区间范围，各牺牲层、硅层的厚度、材料、层叠的数目，也可不限于以上举例。
进一步的举例中，在此多次循环外延的过程中，还可利用离子注入或者原位外延参杂等参杂技术对衬底的上表面进行参杂(参杂浓度范围可例如为1e15-1e19之间)，改变其上表面特性，以帮助提高后期刻蚀的选择性。
针对于其中的步骤S13，可刻蚀掉衬底与外延层沿第二方向的两侧(该第二方向垂直于前文所提及的第一方向，亦即图11a所示的左右方向)的部分材料，从而使得：保留在晶体管基底113上中间位置的外延层与基底(即鳍片中基底101)，形成所需的鳍片。进而，鳍片沿第二方向的两侧(即图11a所示的左右两侧)可视作前文所涉及的鳍片的第三侧与第四侧。
其中一种实施方式中，请参考图8，步骤S13之后，步骤S14之前，还可包括：
S16：在所述鳍片的第三侧外与第四侧外的衬底上形成隔离层；其中，鳍片的第三侧与第四侧为鳍片另一对相对的两侧；
S17：在所述隔离层与所述鳍片上形成横跨所述鳍片顶部、第三侧侧壁与第四侧侧壁的伪栅极堆叠件；
S18：在所述伪栅极堆叠件的外壁形成介电层，所述介电层分布于所述隔离层与所述鳍片上。
针对于其中的步骤S16，请参考图12，所涉及的鳍片的第三侧与第四侧为图12中鳍片的左右两侧。隔离层112的形成方式可以参照本领域任意形成隔离层的方式理解，根据所采用的材料，可任意选择合适的工艺来实现。
针对于其中的步骤S17，请参考图13a与图13b，鳍片的第三侧与第四侧为图13a中鳍片的左右两侧，对应的，其左右方向即为第二方向，鳍片的 第一侧与第二侧为图13b中鳍片的左右两侧，对应的，其左右方向即为第一方向，伪栅极堆叠件110可形成例如匚字形的结构，匚字形的两端可连接于隔离层112，匚字形的伪栅极堆叠件110的内侧可分别连接于外延层上表面、外延层的两侧侧壁，以及部分鳍片中基底101的两侧侧壁，其中的两侧侧壁可理解为是垂直于第二方向的两个侧壁，也可理解为平行于第一方向的两个侧壁。
进一步方案中，请参考图9，步骤S18可以包括：
S181：在所述伪栅极堆叠件、所述隔离层与所述鳍片上形成包围所述伪栅极堆叠件外壁的介电层；
S182：磨去所述介电层中高于伪栅极堆叠件的部分。
针对于其中的步骤S181，请参考图14，介电层111具体可包围并连接于伪栅极堆叠件110的顶部、沿第二方向的第一侧的侧壁，以及沿第二方向的第二侧的侧壁，介电层111的底部可连接于隔离层112。进一步的，介电层还111还可包围于伪栅极堆叠件110沿第一方向的第一侧的侧壁，以及沿第一方向的第二侧的侧壁。
针对于其中的步骤S182，请参考图15a与图15b，在将介电层111中高于伪栅极堆叠件的部分磨去之后，伪栅极堆叠件的顶部与介电层111的顶部可以是持平的。
其中一种实施方式中，针对于步骤S14，请参考图7，步骤S141可以包括：
S141：对所述鳍片中剩余的外延层进行第一次刻蚀；
S142：边对所述鳍片中剩余的外延层进行第二次刻蚀，边检测对应刻蚀深度的变化，并在刻蚀到所述最终终点之后，停止刻蚀。
由于本发明实施例出于“从物理上避免寄生FinFET源漏的产生，使其无法导出寄生电流，有效提高了栅控能力”的目的，创造性地对刻蚀深度提出了要求(即所述源极区域与所述漏极区域的底部不低于所述鳍片中基底与所述底层牺牲层的连接处)，故而，在以上方案中，为了能够准确满足刻蚀深度的特殊要求，才引入了步骤S141、步骤S142的方案，其可以有效、精确地保障刻蚀深度不会低于鳍片中基底与所述底层牺牲层的连接处。
其中，对所述鳍片中剩余的外延层进行第一次刻蚀，可以包括：采用等 离子刻蚀手段实施所述第一次刻蚀。
具体方案中，以图16为例，第一次刻蚀的刻蚀终点可以高于对应底层牺牲层104的最高处(也可理解为不刻蚀到底层牺牲层)，例如仅刻蚀到底层牺牲层104上的硅层105，进而，在第一次刻蚀时，可避免刻蚀到底层牺牲层，在此基础上，可避免第一次刻蚀时过度刻蚀而直接刻蚀到底层牺牲层下，也可以为第二次更精确的刻蚀提供足够的余量。在其他方案中，第一次刻蚀的刻蚀终点也可以低于底层牺牲层104的最高处。
一种举例中，第一次刻蚀时，可以采用高方向性高选择性等离子刻蚀技术(使用气体包括含氟基烷，氯基其他，氢气，氧气，惰性气体中的一种或多种组合)刻蚀掉鳍片高于隔离层的绝大部分。
其中，对所述鳍片中剩余的外延层进行第二次刻蚀，包括：采用等离子刻蚀手段、气体刻蚀手段、湿法刻蚀手段中至少之一实施所述第二次刻蚀；检测对应刻蚀深度的变化，包括：采用OES或IEP检测手段检测刻蚀深度的变化。
其中的OES，具体为Optical Emission Spectroscopy，可理解为：光学发射光谱；其中的IEP具体为Interferometric EndPoint，可理解为：干涉测量终点。
在部分方案中，所述第二次刻蚀的最终终点匹配于所述衬底与所述底层牺牲层的连接处，例如精确处于该连接处，或与接近于该连接处(例如与该连接处的差距小于一定的阈值)。以图17为例，可在第二次刻蚀后形成牺牲层保留层108与牺牲层保留层109。
一种举例中，在第二次刻蚀时，可以通过诸如等离子气体刻蚀过程终点检测技术(包括OES，IEP等检测技术)、高选择性气体刻蚀，高选择性湿法刻蚀等技术的组合完成第二次刻蚀，使最终刻蚀深度不低于最下层基底的最高点，不高于底层牺牲层的最高处。
针对于步骤S15，可以通过诸如沉积、外延等合适的技术和组合制作源极和漏极，不论采用何种技术制作源极与漏极，均不脱离本发明实施例的范围。
在步骤S15之后，还可包括填充介电质并平整化等工艺步骤。
本发明实施例还提供了一种电子设备，包括以上可选方案涉及的GAA 晶体管，例如图4、图5所涉及的GAA晶体管，再例如经以上制备方法制备而成的任意GAA晶体管。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (16)

  1. 一种GAA晶体管的制备方法，其特征在于，包括：
    提供一衬底；
    在所述衬底上形成外延层，所述外延层包括交替层叠的牺牲层与硅层，其中，所述外延层中与所述衬底相接触的一层为底层牺牲层；
    刻蚀所述衬底与所述外延层，以形成鳍片；
    刻蚀所述鳍片中剩余的外延层，以在鳍片的第一侧与第二侧刻蚀出源极区域与漏极区域，其中，刻蚀的最终终点低于所述剩余的外延层中底层牺牲层的最高处，且不低于衬底与底层牺牲层的连接处；鳍片的第一侧与第二侧为鳍片一对相对的两侧；
    在所述源极区域制作源极，在所述漏极区域制作漏极。
  2. 根据权利要求1所述的GAA晶体管的制备方法，其特征在于，
    刻蚀所述鳍片中剩余的外延层，以在鳍片的第一侧与第二侧刻蚀出源极区域与漏极区域，包括：
    对所述鳍片中剩余的外延层进行第一次刻蚀；
    边对所述鳍片中剩余的外延层进行第二次刻蚀，边检测对应刻蚀深度的变化，并在刻蚀到所述最终终点之后，停止刻蚀。
  3. 根据权利要求2所述的GAA晶体管的制备方法，其特征在于，
    对所述鳍片中剩余的外延层进行第一次刻蚀，包括：采用等离子刻蚀手段实施所述第一次刻蚀；
    对所述鳍片中剩余的外延层进行第二次刻蚀，包括：采用等离子刻蚀手段、气体刻蚀手段、湿法刻蚀手段中至少之一实施所述第二次刻蚀。
  4. 根据权利要求2所述的GAA晶体管的制备方法，其特征在于，
    检测对应刻蚀深度的变化，包括：采用OES或IEP检测手段检测刻蚀深度的变化。
  5. 根据权利要求2所述的GAA晶体管的制备方法，其特征在于，所述第一次刻蚀的刻蚀终点高于对应底层牺牲层的最高处。
  6. 根据权利要求2所述的GAA晶体管的制备方法，其特征在于，所述第二次刻蚀的最终终点匹配于所述衬底与所述底层牺牲层的连接处。
  7. 根据权利要求1至6任一项所述的GAA晶体管的制备方法，其特征 在于，
    刻蚀所述鳍片中剩余的外延层，以在鳍片两侧刻蚀出源极区域与漏极区域之前，还包括：
    在所述鳍片的第三侧外与第四侧外的衬底上形成隔离层；其中，鳍片的第三侧与第四侧为鳍片另一对相对的两侧；
    在所述隔离层与所述鳍片上形成横跨所述鳍片顶部、第三侧侧壁与第四侧侧壁的伪栅极堆叠件；
    在所述伪栅极堆叠件的外壁形成介电层，所述介电层分布于所述隔离层与所述鳍片上。
  8. 根据权利要求7所述的GAA晶体管的制备方法，其特征在于，
    在所述伪栅极堆叠件的侧壁形成介电层，包括：
    在所述伪栅极堆叠件、所述隔离层与所述鳍片上形成包围所述伪栅极堆叠件外壁的介电层；
    磨去所述介电层中高于伪栅极堆叠件的部分。
  9. 根据权利要求7所述的GAA晶体管的制备方法，其特征在于，所述隔离层为SiO 2层。
  10. 根据权利要求1至6任一项所述的GAA晶体管的制备方法，其特征在于，所述牺牲层为SiGe层。
  11. 一种GAA晶体管，其特征在于，包括：鳍片、设于源极区域的源极与设于漏极区域的漏极，所述鳍片包括鳍片中基底，以及设于所述鳍片中基底上的外延层，所述外延层包括交替层叠的牺牲层与硅层，其中，与所述鳍片中基底相接触的牺牲层为底层牺牲层；所述源极区域与所述漏极区域分布于所述鳍片的第一侧与第二侧，且位于所述鳍片中基底上侧，所述源极区域与所述漏极区域的底部不低于所述鳍片中基底与所述底层牺牲层的连接处，所述源极区域与所述漏极区域的底部低于所述底层牺牲层的顶部，鳍片的第一侧与第二侧为鳍片一对相对的两侧。
  12. 根据权利要求11所述的GAA晶体管，其特征在于，还包括晶体管基底，所述晶体管基底包括晶体管基底，所述鳍片中基底位于所述晶体管基底上，且所述鳍片中基底与所述晶体管基底是一体的。
  13. 根据权利要求12所述的GAA晶体管，其特征在于，所述晶体管基 底还包括隔离层，所述隔离层设于所述晶体管基底上，且位于所述鳍片的第三侧外与第四侧外，其中，鳍片的第三侧与第四侧为鳍片另一对相对的两侧。
  14. 根据权利要求11所述的GAA晶体管，其特征在于，还包括伪栅极堆叠件与介电层，所述伪栅极堆叠件横跨所述鳍片顶部、第三侧侧壁、第四侧侧壁，所述介电层设于所述伪栅极堆叠件的外壁，且隔于所述伪栅极堆叠件的外壁与所述源极区域之间，以及所述伪栅极堆叠件的外壁与所述漏极区域之间。
  15. 根据权利要求11所述的GAA晶体管，其特征在于，采用权利要求1至10任一项所述的制备方法制备而成的。
  16. 一种电子设备，其特征在于，包括权利要求11至15任一项所述的GAA晶体管。
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