WO2022156488A1 - 故障保护装置及光伏发电系统 - Google Patents

故障保护装置及光伏发电系统 Download PDF

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Publication number
WO2022156488A1
WO2022156488A1 PCT/CN2021/141683 CN2021141683W WO2022156488A1 WO 2022156488 A1 WO2022156488 A1 WO 2022156488A1 CN 2021141683 W CN2021141683 W CN 2021141683W WO 2022156488 A1 WO2022156488 A1 WO 2022156488A1
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WO
WIPO (PCT)
Prior art keywords
input port
protection device
fault protection
output port
bridge arm
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Application number
PCT/CN2021/141683
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English (en)
French (fr)
Inventor
陈东
石磊
王均
Original Assignee
华为数字能源技术有限公司
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Application filed by 华为数字能源技术有限公司 filed Critical 华为数字能源技术有限公司
Priority to JP2022509176A priority Critical patent/JP7405948B2/ja
Priority to BR112022001041A priority patent/BR112022001041A2/pt
Priority to AU2021420937A priority patent/AU2021420937A1/en
Priority to CN202180004272.7A priority patent/CN114424446A/zh
Priority to EP21831209.8A priority patent/EP4060846A4/en
Priority to DE202022100172.3U priority patent/DE202022100172U1/de
Priority to US17/584,102 priority patent/US11811217B2/en
Publication of WO2022156488A1 publication Critical patent/WO2022156488A1/zh
Priority to US18/479,625 priority patent/US20240030703A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Definitions

  • the present application relates to the field of power electronics, in particular to a fault protection device and a photovoltaic power generation system.
  • Multi-level circuits that can output three or more voltage levels have been widely used and paid attention to. Compared with the two-level circuit, the multi-level circuit that can output three or more voltage levels has the advantages of many output levels, small voltage stress, small ripple current, and good harmonic characteristics, which is conducive to the realization of output voltage.
  • the voltage pulse is close to the power frequency AC voltage to reduce the size and weight of the filter.
  • Multilevel circuits usually use semiconductor switching devices to realize the conversion of direct current to alternating current.
  • the semiconductor switch tube of each bridge arm is turned on for half a cycle in a sine cycle, and the respective bridge arms of the three phases are alternately turned on and have a conduction angle difference of 120 degrees, so The resulting output voltage waveform is approximately a sine wave.
  • a three-level circuit including two DC voltage sources is widely used.
  • the intermediate nodes of the two DC voltage sources using this three-level circuit are directly electrically connected to the intermediate nodes of the semiconductor switching device, so when the inverter bridge arm of the semiconductor switching device fails, it is easy to cause damage to the half-busbar capacitance. Overvoltage damage may further spread and damage the circuit and equipment, greatly reducing the reliability of the circuit.
  • the purpose of the present application is to provide a fault protection device and a photovoltaic power generation system, so as to protect the capacitor bridge arm when a short circuit fault occurs in the inverter bridge arm, thereby avoiding circuit failure and damage.
  • inventions of the present application provide a photovoltaic power generation system.
  • the photovoltaic power generation system includes: a capacitor bridge arm, wherein the capacitor bridge arm includes a positive output port, a negative output port, and a reference output port between the positive output port and the negative output port; an inverter bridge arm , wherein the inverter bridge arm includes a positive input port, a negative input port and a reference input port between the positive input port and the negative input port, the positive input port is connected to the positive output port, the negative input port is connected to the negative output port; and a fault protection device, wherein the reference input port is connected to the reference output port through the fault protection device, the fault protection device is based on the positive input port Or the voltage between the negative input port and the reference input port is turned off due to the magnitude or change of the voltage or the magnitude or change of the current.
  • connection relationship between the reference output port and the reference input port can be adjusted by closing and disconnecting the fault protection device, thereby avoiding damage to the half-bus capacitor overvoltage and improving the reliability of the circuit.
  • the fault protection device is turned off according to the positive input port or the magnitude or change of the voltage between the negative input port and the reference input port, including: when the voltage between the negative input port and the reference input port is lower than a first threshold, the fault protection device is disconnected; or when the voltage between the positive input port and the reference input port is below a second threshold, the fault protection device opens; or when the rate of voltage drop between the negative input port and the reference input port is higher than a third threshold, the fault protection device opens; or The fault protection device opens when the rate of voltage drop between the positive input port and the reference input port is higher than a fourth threshold.
  • the fault protection device is controlled to be disconnected by monitoring the voltage change, so as to adjust the connection relationship between the reference output port and the reference input port, thereby avoiding the overvoltage damage of the half-bus capacitor and improving the reliability of the circuit.
  • the fault protection device is further turned off according to the current flowing through the fault protection device.
  • the fault protection device is controlled to be disconnected by monitoring the current flowing through the fault protection device, thereby adjusting the connection relationship between the reference output port and the reference input port, thereby avoiding damage to the half-bus capacitor overvoltage and improving the reliability of the circuit.
  • the inverter bridge arm further includes at least one semiconductor switching device connected between the positive input port or the negative input port and the reference input port,
  • the fault protection device is also turned off according to the current flowing through the at least one semiconductor switching device or the voltage applied between the first transfer electrode and the second transfer electrode of the at least one semiconductor switching device.
  • the fault protection device is controlled to be disconnected by monitoring the voltage and current conditions of the semiconductor switching device to adjust the connection relationship between the reference output port and the reference input port, thereby avoiding overvoltage damage to the half-bus capacitor and improving the reliability of the circuit.
  • the fault protection device includes a main circuit breaker, wherein the main circuit breaker includes a first switching transistor and a second switching transistor, the first switching transistor and all The second switching transistor is connected between the reference output port and the reference input port in a series-paired manner, and the fault protection device controls the conduction of the first switching transistor and the second switching transistor by controlling and off to close and open.
  • the first switching transistor and the second switching transistor are MOSFETs, IGBTs, GTRs, GTOs, HEMTs, MODFETs, 2-DEGFETs or SDHTs.
  • the fault protection device further includes: a high-impedance device, wherein the high-impedance device and the main circuit breaker are connected in parallel between the reference output port and the between reference input ports.
  • the charging and discharging speed of the capacitor bridge arm is slowed down by the high impedance device, which is beneficial to other protection mechanisms to respond and improve the stability of the system.
  • the high-impedance device is a thermistor.
  • the charging and discharging speed of the capacitor bridge arm is slowed down by the thermistor, which is beneficial for other protection mechanisms to respond and improves the stability of the system.
  • the fault protection device further includes: a varistor, wherein the varistor and the main circuit breaker are connected in parallel between the reference output port and the between reference input ports.
  • the residual energy of the fault protection device during the circuit breaking process is absorbed by the varistor, which is beneficial to prevent overvoltage damage and improve the reliability of the circuit.
  • the fault protection device further includes: a high-speed mechanical switch, wherein the high-speed mechanical switch, the varistor and the main circuit breaker are connected in parallel together at all Between the reference output port and the reference input port, the high-speed mechanical switch is closed after the first switching transistor and the second switching transistor of the main circuit breaker are turned on, and the high-speed mechanical switch is in the The first switching transistor and the second switching transistor of the main circuit breaker are turned off before turning off.
  • a high-speed mechanical switch wherein the high-speed mechanical switch, the varistor and the main circuit breaker are connected in parallel together at all Between the reference output port and the reference input port, the high-speed mechanical switch is closed after the first switching transistor and the second switching transistor of the main circuit breaker are turned on, and the high-speed mechanical switch is in the The first switching transistor and the second switching transistor of the main circuit breaker are turned off before turning off.
  • the fault protection device further includes: a high-speed mechanical switch, and an auxiliary circuit breaker, wherein the auxiliary circuit breaker includes a third switching transistor and a fourth switching transistor, so The third switching transistor and the fourth switching transistor are connected in series with the high-speed mechanical switch between the reference output port and the reference input port, and the high-speed mechanical switch and the high-speed mechanical switch are connected in series.
  • the auxiliary circuit breaker After the auxiliary circuit breaker is connected in series, it is connected in parallel with the varistor and the main circuit breaker between the reference output port and the reference input port, the third switching transistor of the auxiliary circuit breaker and The fourth switching transistor and the high-speed mechanical switch are closed after the first switching transistor and the second switching transistor of the main circuit breaker are turned on, and the high-speed mechanical switch is at all positions of the main circuit breaker.
  • the first switching transistor and the second switching transistor are turned off before turning off, and the third switching transistor and the fourth switching transistor of the auxiliary circuit breaker are turned off before the high-speed mechanical switch is turned off.
  • the third switching transistor and the fourth switching transistor are MOSFET, IGBT, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.
  • the inverter bridge arm includes an ANPC three-level bridge arm, and the ANPC three-level bridge arm includes a series connection between the positive input port and the reference input a plurality of semiconductor switching devices connected in series between the ports and between the negative input port and the reference input port, the fault protection device is also applied to the plurality of semiconductor switching devices according to the current flowing through the plurality of semiconductor switching devices or The voltage between the first transfer electrode and the second transfer electrode of the plurality of semiconductor switching devices is turned off.
  • the connection between the reference output port and the reference input port can be adjusted by controlling the fault protection device to disconnect in time. , so as to avoid the overvoltage damage of the half bus capacitor and improve the reliability of the circuit.
  • the inverter bridge arm includes an NPC three-level bridge arm, and the NPC three-level bridge arm includes a series connection between the positive input port and the reference input a plurality of semiconductor switching devices connected in series between the ports and between the negative input port and the reference input port, the fault protection device is also applied to the plurality of semiconductor switching devices according to the current flowing through the plurality of semiconductor switching devices or The voltage between the first transfer electrode and the second transfer electrode of the plurality of semiconductor switching devices is turned off.
  • the inverter bridge arm includes a T-type three-level bridge arm, and the T-type three-level bridge arm includes a series connection between the positive input port and the a plurality of semiconductor switching devices between the negative input ports, the fault protection device is further based on the current flowing through the plurality of semiconductor switching devices or applied to the first transfer electrode and the second transfer electrode of the plurality of semiconductor switching devices the voltage between and turn off.
  • the T-type three-level bridge arm has a short-circuit fault, and the connection between the reference output port and the reference input port can be adjusted by controlling the fault protection device to disconnect in time. relationship, thereby avoiding the overvoltage damage of the half-bus capacitor and improving the reliability of the circuit.
  • the inverter bridge arm includes a five-level bridge arm, and the five-level bridge arm includes a series connection between the positive input port and the reference input port and a plurality of semiconductor switching devices connected in series between the negative input port and the reference input port, the fault protection device is also applied to the plurality of semiconductor switching devices according to the current flowing through the plurality of semiconductor switching devices or applied to the plurality of semiconductor switching devices. The voltage between the first transfer electrode and the second transfer electrode of the semiconductor switching device is turned off.
  • the embodiments of the present application provide a control method for a fault protection device, which is applied to a photovoltaic power generation system.
  • the photovoltaic power generation system includes a capacitor bridge arm, an inverter bridge arm, and the fault protection device, wherein the capacitor bridge arm includes a positive output port, a negative output port, and a connection between the positive output port and the negative output port.
  • the reference output port between the inverter bridge arms includes a positive input port, a negative input port, and a reference input port between the positive input port and the negative input port, and the positive input port is connected to the positive output port.
  • the negative input port is connected to the negative output port
  • the reference input port is connected to the reference output port through the fault protection device
  • the method includes: according to the positive input port or the negative electrode The magnitude or variation of the voltage or the magnitude or variation of the current between the input port and the reference input port controls the fault protection device to turn off.
  • connection relationship between the reference output port and the reference input port can be adjusted by closing and disconnecting the fault protection device, thereby avoiding damage to the half-bus capacitor overvoltage and improving the reliability of the circuit.
  • FIG. 1 shows a principle block diagram of a multi-level circuit with a fault protection device provided by an embodiment of the present application.
  • FIG. 2 shows a structural block diagram of a first implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 according to an embodiment of the present application.
  • FIG. 3 shows a structural block diagram of a second implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 according to an embodiment of the present application.
  • FIG. 4 shows a structural block diagram of a third implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 according to an embodiment of the present application.
  • FIG. 5 shows a structural block diagram of a fourth implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 according to an embodiment of the present application.
  • FIG. 6 shows a structural block diagram of a fifth implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 according to an embodiment of the present application.
  • FIG. 7 shows a schematic block diagram of the ANPC three-level circuit with a fault protection device provided by an embodiment of the present application.
  • FIG. 8 shows a schematic block diagram of the NPC three-level circuit with a fault protection device provided by an embodiment of the present application.
  • FIG. 9 shows a schematic block diagram of a T-type three-level circuit with a fault protection device provided by an embodiment of the present application.
  • FIG. 10 shows a schematic block diagram of a five-level circuit with a fault protection device provided by an embodiment of the present application.
  • Embodiments of the present application provide a photovoltaic power generation system.
  • the photovoltaic power generation system includes: a capacitor bridge arm, wherein the capacitor bridge arm includes a positive output port, a negative output port, and a reference output port between the positive output port and the negative output port; an inverter bridge arm , wherein the inverter bridge arm includes a positive input port, a negative input port and a reference input port between the positive input port and the negative input port, the positive input port is connected to the positive output port, the negative input port is connected to the negative output port; and a fault protection device, wherein the reference input port is connected to the reference output port through the fault protection device, the fault protection device is based on the positive input port Or the voltage between the negative input port and the reference input port is turned off due to the magnitude or change of the voltage or the magnitude or change of the current. In this way, the connection relationship between the reference output port and the reference input port can be adjusted by closing and disconnecting the fault protection device, so as to avoid overvoltage damage of the
  • the embodiments of the present application can be used in the following application scenarios: solar power generation, wind power generation, frequency converters, UPS, motor drives, new energy vehicles, or other application scenarios requiring multi-level inverter circuits.
  • FIG. 1 shows a functional block diagram of a multi-level circuit with a fault protection device provided by an embodiment of the present application.
  • the multilevel circuit 100 includes a fault protection device 110 , a capacitor bridge arm 120 and an inverter multilevel bridge arm 130 .
  • the capacitor bridge arm 120 has three output ports, which are the positive output port P, the negative output port N, and the reference output port M, respectively.
  • the inverter multilevel bridge arm 130 has three input ports, which are the positive input port P', the negative input port N' and the reference input port M' respectively.
  • the positive output port P is connected with the positive input port P'
  • the negative output port N is connected with the negative input port N'
  • one end of the fault protection device 110 is connected with the reference output port M
  • the other end is connected with the reference input port M'.
  • the positive electrode and the negative electrode mentioned in the embodiments of the present application are only relative concepts, and one port is designated as the positive electrode and the other port is the negative electrode for the convenience of description, which should not be construed as limiting.
  • the fault protection device 110 includes a circuit breaker SP and a controller 111 .
  • One end of the disconnect switch SP is connected to the reference output port M, and the other end is connected to the reference input port M'.
  • the controller 111 is communicatively connected to the disconnect switch SP and is configured to control closing and opening of the disconnect switch SP.
  • the controller 111 controls the disconnect switch SP to close the reference output port M is connected to the reference input port M' through the disconnect switch SP; when the controller 111 controls the disconnect switch SP to open, the reference output port M is blocked by the disconnect switch SP and cannot be Connect to reference input port M'.
  • the fault protection device 110 has the following various implementation structures, but it can be understood that the present application is not limited to the implementation of the following specific circuit breaking structures.
  • the key point of this application is to connect a circuit breaker SP protection device between the reference terminal of the capacitor bridge arm and the reference terminal of the inverter bridge arm, and the specific structure of the protection device is not critical. The structure will not be repeated here.
  • FIG. 2 shows a structural block diagram of a first implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 provided by an embodiment of the present application.
  • the circuit breaker SP includes a main circuit breaker 212 .
  • the main circuit breaker 212 includes two semiconductor switching devices, taking an insulated gate bipolar transistor (IGBT) as an example, which are Q1 and Q2 respectively.
  • Q1 and Q2 are connected in series between the reference output port M and the reference input port M'. That is, the emitter of Q1 and the emitter of Q2 are connected to each other, the collector of Q1 is connected to the reference input port M', and the collector of Q2 is connected to the reference output port M.
  • IGBT insulated gate bipolar transistor
  • the collector of Q1 and the collector of Q2 are connected to each other, the emitter of Q1 is connected to the reference input port M', and the emitter of Q2 is connected to the reference output port M.
  • the positions of Q1 and Q2 can also be interchanged.
  • the main circuit breaker 212 also includes two diodes T1 and T2, which are in an anti-parallel relationship with Q1 and Q2, respectively.
  • diode T1 corresponds to Q1
  • the anode of T1 is connected to the emitter of Q1
  • the cathode of T1 is connected to the collector of Q1
  • diode T2 corresponds to Q2
  • the anode of T2 is connected to the emitter of Q2
  • the cathode of T2 is connected to the collector of Q2.
  • the gate voltage of the IGBT in the circuit breaker SP can be controlled to make the IGBT turn on, so as to realize the connection between the reference output port M and the reference input port M'; when The circuit breaker SP receives the control signal indicating disconnection, and can control the gate voltage of the IGBT in the circuit breaker SP to turn off the IGBT, thereby blocking the connection between the reference output port M and the reference input port M'; using the IGBT
  • the control mechanism can also stop sending the closed control signal to the circuit breaker SP, so that the circuit breaker SP can drive the IGBT to turn off after not receiving the closed control signal.
  • the reverse current voltage can be suppressed by a diode connected in an anti-parallel relationship with the IGBT to avoid damage caused by an excessive reverse current voltage.
  • the IGBT shown in FIG. 2 is merely exemplary.
  • the two semiconductor switching devices included in the main circuit breaker 212 are a first switching transistor and a second switching transistor, respectively.
  • the first switch transistor and the second switch transistor are connected between the reference output port of the capacitor bridge arm and the reference input port of the inverter multilevel bridge arm in a pair-wise series connection.
  • the controller controls the closing and opening of the circuit breaker by controlling the on and off of the first switching transistor and the second switching transistor of the main circuit breaker.
  • the two semiconductor switching devices included in the main circuit breaker 212 may be implemented using other semiconductor devices with similar functions, such as metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistors). Transistor, MOSFET), power transistor (Giant Transistor, GTR), turn-off thyristor (Gate Turn-Off Thyristor, GTO) or other suitable devices, and configure pairs of diodes accordingly.
  • MOSFET Metal-oxide-semiconductor field-effect transistors
  • GTR power transistor
  • turn-off thyristor Gate Turn-Off Thyristor, GTO
  • GTO Gate Turn-Off Thyristor
  • These semiconductor devices may also employ High Electron Mobility Transistor (HEMT), also known as Modulation-Doped FET (MODFET), or Two Dimensional Electron Gas Field Effect Transistor, 2-DEGFET), or Selectively-Doped Heterojunction Transistor (SDHT).
  • HEMT High Electron Mobility Transistor
  • MODFET Modulation-Doped FET
  • 2-DEGFET Two Dimensional Electron Gas Field Effect Transistor
  • SDHT Selectively-Doped Heterojunction Transistor
  • FIG. 3 shows a structural block diagram of a second implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 according to an embodiment of the present application.
  • the circuit breaker SP includes a main circuit breaker 312 and a varistor 313 .
  • the structure and function of the main circuit breaker 312 are similar to those of the main circuit breaker 212 shown in FIG. 2 , which will not be repeated here.
  • the varistor 313 may be based on a metal oxide material, and the varistor 313 and the main circuit breaker 312 are connected in parallel between the reference output port M and the reference input port M'.
  • the varistor 313 has non-linear volt-ampere characteristics and is used to absorb the residual energy of the circuit breaker SP during the circuit-breaking process, which is beneficial to preventing the main circuit breaker 312 from being damaged by overvoltage and improving the reliability of the circuit.
  • FIG. 4 shows a structural block diagram of a third implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 according to an embodiment of the present application.
  • the circuit breaker SP includes a main circuit breaker 412 , a varistor 413 and a high-speed mechanical switch 414 .
  • the main circuit breaker 412, the varistor 413 and the high-speed mechanical switch 414 are all connected in parallel between the reference output port M and the reference input port M'.
  • the structure and function of the main circuit breaker 412 are similar to those of the main circuit breaker 212 shown in FIG. 2 , which will not be repeated here.
  • the structure and function of the varistor 413 are similar to those of the varistor 313 shown in FIG. 3 , and details are not repeated here.
  • the high-speed mechanical switch 414 is closed after the IGBT of the main circuit breaker 412 is turned on, that is, after the IGBT of the main circuit breaker 412 is turned on, the main circuit breaker 412 is bypassed by the closed high-speed mechanical switch 414, so that the main circuit breaker 412 can be bypassed through the closed high-speed mechanical switch 414.
  • the closed high speed mechanical switch 414 reduces the losses of the disconnect switch SP.
  • the high speed mechanical switch 414 opens before the IGBT of the main circuit breaker 412 is turned off, thereby ensuring that the IGBT of the main circuit breaker 412 bears the effects of current interruption and avoids the effect of the current interruption being assumed by the high speed mechanical switch 414 .
  • FIG. 5 shows a structural block diagram of a fourth implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 provided by an embodiment of the present application.
  • the circuit breaker SP includes a main circuit breaker 512 , a varistor 513 and a high-speed mechanical switch 514 and an auxiliary circuit breaker 515 .
  • the high-speed mechanical switch 514 and the auxiliary circuit breaker 515 are connected in series, and then connected in parallel with the main circuit breaker 512 and the varistor 513 between the reference output port M and the reference input port M'.
  • the structure and function of the main circuit breaker 512 are similar to those of the main circuit breaker 212 shown in FIG. 2 , which will not be repeated here.
  • the structure and function of the varistor 513 are similar to those of the varistor 313 shown in FIG. 3 , and details are not repeated here.
  • the structure and function of the high-speed mechanical switch 514 are similar to those of the high-speed mechanical switch 414 shown in FIG. 4 , and will not be repeated here.
  • the auxiliary circuit breaker 515 includes two semiconductor switching devices, taking IGBT as an example, which are Q3 and Q4 respectively.
  • Q3 and Q4 are connected between the reference input port M' and the high-speed mechanical switch 514 in series pairwise. That is, the emitter of Q3 and the emitter of Q4 are connected to each other, the collector of Q3 is connected to the reference input port M', and the collector of Q4 is connected to the reference high-speed mechanical switch 514.
  • the collector of Q3 and the collector of Q4 are connected to each other, the emitter of Q3 is connected to the reference input port M', and the emitter of Q4 is connected to the high speed mechanical switch 514.
  • the positions of Q3 and Q4 can also be interchanged in both embodiments. Also, the positions of the high-speed mechanical switch 514 and the auxiliary circuit breaker 515 may be interchanged.
  • the auxiliary circuit breaker 515 also includes two diodes T3 and T4, which are in an anti-parallel relationship with Q3 and Q4, respectively.
  • the auxiliary circuit breaker 515 and the high-speed mechanical switch 514 are closed after the IGBT of the main circuit breaker 512 is turned on, that is, the bypass branch is formed by closing the high-speed mechanical switch 514 and the auxiliary circuit breaker 515 after the IGBT of the main circuit breaker 512 is turned on.
  • the main circuit breaker 512 is bypassed, so that the loss of the circuit breaker SP can be reduced.
  • the high-speed mechanical switch 514 is turned off before the IGBT of the main breaker 512 is turned off, and the auxiliary circuit breaker 515 is turned off before the high-speed mechanical switch 514 is turned off, so that the high-speed mechanical
  • the bypass branches of switch 514 and auxiliary circuit breaker 515 are opened before the IGBT of main circuit breaker 512 is turned off, thereby avoiding the impact of current interruption by high-speed mechanical switch 514 and ensuring that the IGBT of main circuit breaker 512 is responsible for the current The effect of circuit breakers.
  • the IGBT shown in FIG. 5 is merely exemplary.
  • the two semiconductor switching devices included in the auxiliary circuit breaker 515 are a third switching transistor and a fourth switching transistor, respectively.
  • the third switching transistor and the fourth switching transistor are MOSFET, IGBT, GTR, GTO, HEMT, MODFET, 2-DEGFET or SDHT.
  • FIG. 6 shows a structural block diagram of a fifth implementation manner of the circuit breaker SP of the fault protection device shown in FIG. 1 according to an embodiment of the present application.
  • the circuit breaker SP includes a main circuit breaker 612 and a thermistor 615 .
  • Thermistor 615 may also be other types of high impedance devices.
  • the structure and function of the main circuit breaker 612 are similar to those of the main circuit breaker 212 shown in FIG. 2 , which will not be repeated here.
  • the thermistor 615 and the main circuit breaker 612 are connected in parallel between the reference output port M and the reference input port M'.
  • the thermistor 615 receives short-circuit current and charges and discharges the capacitor bridge arm connected to the circuit breaker SP. Because the resistance value of the thermistor 615 is relatively large and the resistance value further increases at high temperature, the charging and discharging speed of the capacitor bridge arm is slowed down, which is beneficial for other protection mechanisms to respond and improves the stability of the system. Similarly, the thermistor 615 can be used in parallel with the second, third, and fourth embodiments of the circuit breaker SP, which will not be repeated here.
  • FIG. 7 shows a schematic block diagram of an ANPC three-level circuit with a fault protection device provided by an embodiment of the present application.
  • the Active Neutral Point Clamped (ANPC) three-level circuit 700 includes a fault protection device 710 , a capacitor bridge arm 720 and an ANPC three-level bridge arm 730 .
  • the fault protection device 710 includes a circuit breaker SP, and the circuit breaker SP shown in FIG. 7 may correspond to the circuit breaker SP shown in any of the embodiments in FIGS. 2 to 5 or any possible combination or variation of these embodiments.
  • the capacitor bridge arm 720 has three output ports, which are the positive output port P, the negative output port N, and the reference output port M, respectively.
  • the ANPC three-level bridge arm 730 has three input ports, which are the positive input port P', the negative input port N' and the reference input port M' respectively.
  • the ANPC three-level bridge arm 730 also has an external output port O, which is used to provide the output level voltage to the next-level load or the external network.
  • the positive output port P is connected to the positive input port P'
  • the negative output port N is connected to the negative input port N'
  • one end of the fault protection device 710 is connected to the reference output port M
  • the other end is connected to the reference input port M'.
  • each output port of the capacitor bridge arm 720 and each input port of the ANPC three-level bridge arm 730 there is a one-to-one correspondence between each output port of the capacitor bridge arm 720 and each input port of the ANPC three-level bridge arm 730 , and the reference output port M is indirectly connected to the reference input port M through the fault protection device 710 '.
  • the positive electrode and the negative electrode mentioned in the embodiments of the present application are only relative concepts, and one port is designated as the positive electrode and the other port is the negative electrode for the convenience of description, which should not be construed as limiting.
  • the capacitor bridge arm 720 includes two capacitors C1 and C2.
  • the capacitors C1 and C2 are connected in series between the positive output port P and the negative output port N, and the intermediate node between the capacitors C1 and C2 is connected to the reference output port M.
  • the ANPC three-level bridge arm 730 includes a total of six semiconductor switching devices, labeled S1, S2, S3, S4, S5, and S6, respectively. It should be understood that each of the semiconductor switching devices S1, S2, S3, S4, S5 and S6 included in the ANPC three-level bridge arm 730 is a pair of IGBTs and is connected in an anti-parallel relationship with the IGBTs diode.
  • these semiconductor switching devices can also be implemented by other semiconductor devices with similar functions, such as metal oxide semiconductor field effect transistor MOSFET, power transistor GTR, turn-off thyristor GTO or other suitable devices, And configure the paired diodes accordingly.
  • these semiconductor devices may also employ High Electron Mobility Transistors HEMTs, also known as Modulation Doped Field Effect Transistors MODFETs, or 2D Electron Gas Field Effect Transistors 2-DEGFETs, or Selectively Doped Heterogeneous Junction transistor SDHT. These can be adjusted and improved according to the specific application environment, which is not specifically limited here.
  • the semiconductor switching devices S1 and S2 are connected in series between the positive input port P' and the reference input port M', and the semiconductor switching devices S3 and S4 are connected in series between the reference input port M' and the negative input port N' between.
  • the semiconductor switching devices S2 and S3 are connected, and the intermediate node between the semiconductor switching devices S2 and S3 is connected to the reference input port M'.
  • the semiconductor switching devices S5 and S6 are connected in series to connect the intermediate node between the semiconductor switching devices S1 and S2 and the intermediate node between the semiconductor switching devices S3 and S4, respectively.
  • the intermediate node between the semiconductor switching devices S5 and S6 is connected to the external output port O of the ANPC three-level bridge arm 730 .
  • the external output port O is connected to the positive input port P' through the branch composed of the semiconductor switching devices S1 and S5, and the positive output port P is connected to the positive input port P', so the external output is The voltage output at port O is the first voltage applied to the positive output port P.
  • the external output port O is connected to the negative input port N' through the branch composed of the semiconductor switching devices S4 and S6, and the negative output port N is connected to the negative input port N', so the external output is The voltage output at port O is the second voltage applied to the negative output port N.
  • the external output port O passes through the branch composed of the semiconductor switching devices S2 and S5 or the branch composed of the semiconductor switching devices S3 and S6
  • the reference input port M' is connected, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 710, so the voltage output by the external output port O is the third voltage applied to the reference output port M.
  • the voltage output from the external output port O can be applied to the first voltage applied to the positive output port P, and the voltage applied to the negative output Switching between the second voltage of the port N and the third voltage applied to the reference output port M realizes a three-level output.
  • the negative input port N' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' remain The connection relationship will cause the capacitor C2 to be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1.
  • the capacitors C1 and C2 are respectively subjected to half the voltage between the positive output port P and the negative output port N, so when the voltage between the positive output port P and the negative output port N is When it is all applied to the capacitor C1, it may cause the capacitor C1 to bear twice the voltage of the normal design, thereby causing overvoltage damage, or even diffusion and damage to the circuit and equipment, which greatly reduces the reliability of the circuit.
  • the positive input port P' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' maintain a connection relationship, It will cause the capacitor C1 to be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C2, resulting in overvoltage damage. To this end, it is necessary to adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the disconnect switch SP.
  • a short-circuit fault of the semiconductor switching device occurs by monitoring one of the following conditions: monitoring the voltage between the negative input port N' and the reference input port M', and determining the semiconductor switching device when the voltage is lower than a certain threshold S3 and S4 have a short-circuit fault at the same time; monitor the voltage between the positive input port P' and the reference input port M', when the voltage is lower than a certain threshold, determine that the semiconductor switching devices S1 and S2 have a short-circuit fault at the same time; monitor the negative input port N The voltage drop rate between ' and the reference input port M', when the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switching devices S3 and S4 have short-circuit faults at the same time; monitor the positive input port P' and the reference input port M' When the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switching devices S1 and S2 have short-circuit faults at the same time; monitor the flow from the positive input
  • the voltage between the poles is determined, and when the voltage is higher than a certain threshold, it is determined that the corresponding semiconductor switching device S1, S2, S3 or S4 has a short-circuit fault.
  • a short-circuit fault has occurred in the ANPC three-level bridge arm 730, and the reference output port M and Reference is made to the connection relationship between the input ports M', so as to avoid the overvoltage damage of the half-bus capacitor and improve the reliability of the circuit.
  • the current flowing through the disconnect switch SP can also be monitored, and when the current is greater than a certain threshold, it is determined that the ANPC three-level bridge arm 730 has a short-circuit fault.
  • the ANPC three-level circuit 700 may include a plurality of ANPC three-level bridge arms 730 , wherein each ANPC three-level bridge arm 730 has the structure shown in FIG. 7 , and each has three input ports.
  • the respective input ports of the multiple ANPC three-level bridge arms 730 are connected in parallel to the corresponding positive input port P', negative input port N' and reference input port M' shown in FIG. 7 , so that the multiple ANPC three-level bridges are connected in parallel.
  • the arms 730 form a parallel relationship.
  • the circuit breaker SP of the fault protection device 710 When the multiple ANPC three-level bridge arms 730 are all working normally, the circuit breaker SP of the fault protection device 710 is closed; when any one of the multiple ANPC three-level bridge arms 730 has a short-circuit fault, the circuit breaker of the fault protection device 710 is opened. The switch SP is turned off, thereby avoiding the overvoltage damage of the half-busbar capacitors and improving the reliability of the circuit. Wherein, judging that any one of the multiple ANPC three-level bridge arms 730 has a short-circuit fault can be realized by monitoring whether one of the above-mentioned conditions occurs in all the ANPC three-level bridge arms 730 .
  • a controller 711 included in the fault protection device 710 is communicatively connected to the circuit breaker SP and configured to control the closing and opening of the circuit breaker SP.
  • the controller 711 may have corresponding circuits and components to monitor the above-mentioned short-circuit fault, and may also receive commands from the outside through an interface circuit.
  • controller 711 may be provided separately from fault protection device 710, that is, as a separate device.
  • other technical means can also be used to determine whether a short-circuit fault has occurred in the semiconductor switching device. These can be adjusted and improved according to the specific application environment, which is not specifically limited here.
  • the semiconductor switching devices included in the ANPC three-level bridge arm 730 shown in FIG. 7 are IGBTs as an example, and the respective collectors and emitters of these semiconductor switching devices are schematically shown in FIG. 7 . .
  • the above-mentioned collector and emitter are correspondingly replaced with drain and source.
  • the collectors and emitters shown in FIG. 7 should therefore be understood as schematic representations of the respective first and second transfer electrodes of these semiconductor switching devices.
  • FIG. 8 shows a schematic block diagram of an NPC three-level circuit with a fault protection device provided by an embodiment of the present application.
  • a neutral point clamped (Neutral Point Clamped, NPC) three-level circuit 800 includes a fault protection device 810 , a capacitor bridge arm 820 and an NPC three-level bridge arm 830 .
  • the fault protection device 810 includes a circuit breaker SP, and the circuit breaker SP shown in FIG. 8 may correspond to the circuit breaker SP shown in any of the embodiments in FIGS. 2 to 5 or any possible combination or variation of these embodiments.
  • the capacitor bridge arm 820 has three output ports, which are the positive output port P, the negative output port N, and the reference output port M, respectively.
  • the NPC three-level bridge arm 830 has three input ports, which are the positive input port P', the negative input port N' and the reference input port M' respectively.
  • the NPC three-level bridge arm 830 also has an external output port O, which is used to provide the output level voltage to the next-level load or the external network.
  • the positive output port P is connected to the positive input port P'
  • the negative output port N is connected to the negative input port N'
  • one end of the fault protection device 810 is connected to the reference output port M
  • the other end is connected to the reference input port M'.
  • each output port of the capacitor bridge arm 820 and each input port of the NPC three-level bridge arm 830 there is a one-to-one correspondence between each output port of the capacitor bridge arm 820 and each input port of the NPC three-level bridge arm 830 , and the reference output port M is indirectly connected to the reference input port M through the fault protection device 810 '.
  • the positive electrode and the negative electrode mentioned in the embodiments of the present application are only relative concepts, and one port is designated as the positive electrode and the other port is the negative electrode for the convenience of description, which should not be construed as limiting.
  • the capacitor bridge arm 820 includes two capacitors C1 and C2.
  • the capacitors C1 and C2 are connected in series between the positive output port P and the negative output port N, and the intermediate node between the capacitors C1 and C2 is connected to the reference output port M.
  • the NPC three-level bridge arm 830 includes a total of six semiconductor devices, labeled S1, D2, D3, S4, S5, and S6, respectively.
  • the semiconductor devices S1, S4, S5 and S6 are semiconductor switching devices and the semiconductor devices D2 and D3 are diodes.
  • each of the semiconductor switching devices S1 , S4 , S5 and S6 included in the NPC three-level bridge arm 830 is a pair of IGBTs and a diode connected in an anti-parallel relationship with the IGBTs.
  • these semiconductor switching devices may also be implemented using other semiconductor devices having similar functions, such as MOSFETs, GTRs, GTOs, or other suitable devices, and configured in pairs of diodes accordingly.
  • these semiconductor devices may also employ HEMTs, also known as MODFETs, or 2-DEGFETs, or SDHTs. These can be adjusted and improved according to the specific application environment, which is not specifically limited here.
  • the semiconductor switching devices S1 and D2 are connected in series between the positive input port P' and the reference input port M', and the semiconductor switching devices D3 and S4 are connected in series between the reference input port M' and the negative input port N' between.
  • the semiconductor switching devices D2 and D3 are connected, and the intermediate node between the semiconductor switching devices D2 and D3 is connected to the reference input port M'.
  • the semiconductor switching devices S5 and S6 are connected in series to connect the intermediate node between the semiconductor switching devices S1 and D2 and the intermediate node between the semiconductor switching devices D3 and S4, respectively.
  • the intermediate node between the semiconductor switching devices S5 and S6 is connected to the external output port O of the NPC three-level bridge arm 830 .
  • the anode of the diode D2 is connected to the reference input port M', and the cathode is connected to the emitter of the semiconductor switching device S1.
  • the cathode of the diode D3 is connected to the reference input port M', and the anode is connected to the collector of the semiconductor switching device S4.
  • the anode of diode D2 is connected to the cathode of diode D3.
  • the external output port O is connected to the negative input port N' through the branch composed of the semiconductor switching devices S4 and S6, and the negative output port N is connected to the negative input port N', so the external output is
  • the voltage output at port O is the second voltage applied to the negative output port N.
  • the external output port O passes through the branch formed by the semiconductor switching devices D2 and S5 or the branch formed by the semiconductor switching devices D3 and S6
  • the reference input port M' is connected, and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 810, so the voltage output by the external output port O is the third voltage applied to the reference output port M.
  • the voltage output from the external output port O can be the first voltage applied to the positive output port P, the first voltage applied to the negative output Switching between the second voltage of the port N and the third voltage applied to the reference output port M realizes a three-level output.
  • the negative input port N' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' remain The connection relationship will cause the capacitor C2 to be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1.
  • the capacitors C1 and C2 are respectively subjected to half the voltage between the positive output port P and the negative output port N, so when the voltage between the positive output port P and the negative output port N is When it is all applied to the capacitor C1, it may cause the capacitor C1 to bear twice the voltage of the normal design, thereby causing overvoltage damage, or even diffusion and damage to the circuit and equipment, which greatly reduces the reliability of the circuit.
  • the positive input port P' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' maintain a connection relationship, It will cause the capacitor C1 to be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C2, resulting in overvoltage damage. To this end, it is necessary to adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the disconnect switch SP.
  • a short-circuit fault of the semiconductor switching device occurs by monitoring one of the following conditions: monitoring the voltage between the negative input port N' and the reference input port M', and determining the semiconductor switching device when the voltage is lower than a certain threshold D3 and S4 have a short-circuit fault at the same time; monitor the voltage between the positive input port P' and the reference input port M', when the voltage is lower than a certain threshold, determine that the semiconductor switching devices S1 and D2 have a short-circuit fault at the same time; monitor the negative input port N The voltage drop rate between ' and the reference input port M', when the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switching devices D3 and S4 have short-circuit faults at the same time; monitor the positive input port P' and the reference input port M' between When the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switching devices S1 and D2 have a short-circuit fault at the same time; monitor the flow from the
  • the voltage is higher than a certain threshold, it is determined that the corresponding semiconductor switching device S1 or S4 has a short-circuit fault.
  • the reference output port M and the reference output port M can be adjusted in time by controlling the closing and opening of the disconnect switch SP Reference is made to the connection relationship between the input ports M', so as to avoid the overvoltage damage of the half-bus capacitor and improve the reliability of the circuit.
  • the current flowing through the disconnect switch SP can also be monitored, and when the current is greater than a certain threshold, it is determined that a short-circuit fault has occurred in the NPC three-level bridge arm 830 .
  • the NPC three-level circuit 800 may include a plurality of NPC three-level bridge arms 830 , wherein each NPC three-level bridge arm 830 has the structure shown in FIG. 8 , and each has three input ports.
  • the respective input ports of the plurality of NPC three-level bridge arms 830 are connected in parallel to the corresponding positive input port P′, negative input port N′ and reference input port M′ shown in FIG. 8 , so that the plurality of NPC three-level bridges are connected in parallel
  • the arms 830 form a parallel relationship.
  • the circuit breaker SP of the fault protection device 810 When the multiple NPC three-level bridge arms 830 work normally, the circuit breaker SP of the fault protection device 810 is closed; when any one of the multiple NPC three-level bridge arms 830 has a short-circuit fault, the circuit breaker of the fault protection device 810 is opened. The switch SP is turned off, thereby avoiding the overvoltage damage of the half-busbar capacitors and improving the reliability of the circuit. Wherein, judging that any one of the multiple NPC three-level bridge arms 830 has a short-circuit fault can be realized by monitoring whether one of the above-mentioned situations occurs in all the NPC three-level bridge arms 830 .
  • a controller 811 included in the fault protection device 810 is communicatively connected to the circuit breaker SP and is configured to control the closing and opening of the circuit breaker SP.
  • the controller 811 may have corresponding circuits and components to monitor the above-mentioned short-circuit fault, and may also receive commands from the outside through an interface circuit.
  • controller 811 may be provided separately from fault protection device 810, that is, as a separate device.
  • other technical means can also be used to determine whether a short-circuit fault has occurred in the semiconductor switching device. These can be adjusted and improved according to the specific application environment, which is not specifically limited here.
  • the semiconductor switching devices included in the NPC three-level bridge arm 830 shown in FIG. 8 are IGBTs as an example, and the respective collectors and emitters of these semiconductor switching devices are schematically shown in FIG. 8 . .
  • the above-mentioned collector and emitter are correspondingly replaced with drain and source.
  • the collectors and emitters shown in FIG. 8 should therefore be understood as schematic representations of the respective first and second transfer electrodes of these semiconductor switching devices.
  • FIG. 9 shows a schematic block diagram of the T-type three-level circuit with a fault protection device provided by an embodiment of the present application.
  • the T-type three-level circuit 900 includes a fault protection device 910 , a capacitor bridge arm 920 and a T-type three-level bridge arm 930 .
  • the fault protection device 910 includes a circuit breaker SP, and the circuit breaker SP shown in FIG. 9 may correspond to the circuit breaker SP shown in any of the embodiments in FIGS. 2 to 5 or any possible combination or variation of these embodiments.
  • the capacitor bridge arm 920 has three output ports, which are the positive output port P, the negative output port N, and the reference output port M, respectively.
  • the T-shaped three-level bridge arm 930 has three input ports, which are the positive input port P', the negative input port N' and the reference input port M' respectively.
  • the T-type three-level bridge arm 930 also has an external output port O, which is used to provide the output level voltage to the next-level load or the external network.
  • the positive output port P is connected to the positive input port P'
  • the negative output port N is connected to the negative input port N'
  • one end of the fault protection device 910 is connected to the reference output port M
  • the other end is connected to the reference input port M'.
  • each output port of the capacitor bridge arm 920 and each input port of the T-type three-level bridge arm 930 there is a one-to-one correspondence between each output port of the capacitor bridge arm 920 and each input port of the T-type three-level bridge arm 930 , and the reference output port M is indirectly connected to the reference input port through the fault protection device 910 M'.
  • the positive electrode and the negative electrode mentioned in the embodiments of the present application are only relative concepts, and one port is designated as the positive electrode and the other port is the negative electrode for the convenience of description, which should not be construed as limiting.
  • the capacitor bridge arm 920 includes two capacitors C1 and C2.
  • the capacitors C1 and C2 are connected in series between the positive output port P and the negative output port N, and the intermediate node between the capacitors C1 and C2 is connected to the reference output port M.
  • the T-type three-level bridge arm 930 includes a total of four semiconductor switching devices, which are marked as S1 , S2 , S3 and S4 respectively. It should be understood that each of the semiconductor switching devices S1 , S2 , S3 and S4 included in the T-type three-level bridge arm 930 is a pair of IGBTs and a diode connected in an anti-parallel relationship with the IGBTs.
  • these semiconductor switching devices may also be implemented using other semiconductor devices having similar functions, such as MOSFETs, GTRs, GTOs, or other suitable devices, and configured in pairs of diodes accordingly.
  • these semiconductor devices may also employ HEMTs, also known as MODFETs, or 2-DEGFETs, or SDHTs. These can be adjusted and improved according to the specific application environment, which is not specifically limited here.
  • the semiconductor switching devices S1 and S2 are connected in series between the positive input port P' and the negative input port N', and the intermediate node between the semiconductor switching devices S1 and S2 is connected to the external output port O.
  • the semiconductor switching devices S3 and S4 are connected in series between the reference input port M' and the external output port O.
  • the semiconductor switching devices S3 and S4 are connected between the reference input port M' and the external output port O in a series-connected manner. That is to say, the emitter of S3 and the emitter of S4 are connected to each other, the collector of S3 is connected to the reference input port M', and the collector of S4 is connected to the external output port O.
  • the positions of S3 and S4 can also be interchanged, as long as the respective emitters are kept connected to each other, the collector of one is connected to the reference input port M', and the collector of the other is connected to the external output port O .
  • the semiconductor switching device S1 is turned on, the external output port O is connected to the positive input port P' through the branch composed of the semiconductor switching device S1, and the positive output port P is connected to the positive input port P', so the external output port O output
  • the voltage is the first voltage applied to the positive output port P.
  • the external output port O When the semiconductor switching device S2 is turned on, the external output port O is connected to the negative input port N' through the branch composed of the semiconductor switching device S2, and the negative output port N is connected to the negative input port N', so the external output port O output The voltage is the second voltage applied to the negative output port N.
  • the semiconductor switching devices S3 and S4 When the semiconductor switching devices S3 and S4 are turned on, the external output port O is connected to the reference input port M′ through the branch formed by the semiconductor switching devices S3 and S4 , and the reference output port M is indirectly connected to the reference through the fault protection device 910 The input port M', so the voltage output from the external output port O is the third voltage applied to the reference output port M.
  • the voltage output from the external output port O can be made between the first voltage applied to the positive output port P, the first voltage applied to the negative electrode Switching between the second voltage of the output port N and the third voltage applied to the reference output port M realizes a three-level output.
  • the negative input port N' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M are short-circuited 'Keeping the connection relationship will cause the capacitor C2 to be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1.
  • the capacitors C1 and C2 are respectively subjected to half the voltage between the positive output port P and the negative output port N, so when the voltage between the positive output port P and the negative output port N is When it is all applied to the capacitor C1, it may cause the capacitor C1 to bear twice the voltage of the normal design, thereby causing overvoltage damage, or even diffusion and damage to the circuit and equipment, which greatly reduces the reliability of the circuit.
  • the positive input port P' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' remain connected relationship, it will cause the capacitor C1 to be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C2, resulting in overvoltage damage.
  • a short-circuit fault of the semiconductor switching device occurs by monitoring one of the following conditions: monitoring the voltage between the negative input port N' and the reference input port M', and determining the semiconductor switching device when the voltage is lower than a certain threshold S2, S3 and S4 have short-circuit faults at the same time; monitor the voltage between the positive input port P' and the reference input port M', when the voltage is lower than a certain threshold, determine that the semiconductor switching devices S1, S3 and S4 have short-circuit faults at the same time; monitor The voltage drop rate between the negative input port N' and the reference input port M', when the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switching devices S2, S3 and S4 have short-circuit faults at the same time; monitor the positive input port P' and the reference The voltage drop rate between the input ports M', when the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switching devices S1, S3 and S4 have short-circuit faults
  • the voltage between the poles is determined, and when the voltage is higher than a certain threshold, it is determined that the corresponding semiconductor switching device S1, S2, S3 or S4 has a short-circuit fault.
  • the reference output port M can be adjusted by controlling the closing and opening of the disconnect switch SP in time.
  • the connection relationship with the reference input port M' thereby avoiding the overvoltage damage of the half-busbar capacitor and improving the reliability of the circuit.
  • the current flowing through the disconnect switch SP can also be monitored, and when the current is greater than a certain threshold, it is determined that the T-type three-level bridge arm 930 has a short-circuit fault.
  • the T-type three-level bridge arm 930 may include a plurality of T-type three-level bridge arms 930, wherein each T-type three-level bridge arm 930 has the structure shown in FIG. 9, and each has three input ports.
  • the respective input ports of the plurality of T-type three-level bridge arms 930 are connected in parallel to the corresponding positive input port P', negative input port N' and reference input port M' shown in FIG.
  • the flat bridge arms 930 form a parallel relationship.
  • the circuit breaker SP of the fault protection device 910 When the multiple T-type three-level bridge arms 930 are all working normally, the circuit breaker SP of the fault protection device 910 is closed; when any one of the multiple T-type three-level bridge arms 930 has a short-circuit fault, the fault protection device 910 The circuit breaker SP is disconnected, thereby avoiding the overvoltage damage of the half-bus capacitor and improving the reliability of the circuit. Wherein, judging that any one of the multiple T-type three-level bridge arms 930 has a short-circuit fault can be realized by monitoring whether all the T-type three-level bridge arms 930 have one of the above conditions.
  • a controller 911 included in the fault protection device 910 is communicatively connected to the circuit breaker SP and is configured to control the closing and opening of the circuit breaker SP.
  • the controller 911 may have corresponding circuits and components to monitor the above-mentioned short-circuit fault, and may also receive commands from the outside through an interface circuit.
  • controller 911 may be provided separately from fault protection device 910, that is, as a separate device.
  • other technical means can also be used to determine whether a short-circuit fault has occurred in the semiconductor switching device. These can be adjusted and improved according to the specific application environment, which is not specifically limited here.
  • the plurality of semiconductor switching devices included in the T-type three-level bridge arm 930 shown in FIG. 9 are IGBTs as an example, and the respective collectors and emitters of these semiconductor switching devices are schematically shown in FIG. 9 . pole.
  • the above-mentioned collector and emitter are correspondingly replaced with drain and source.
  • the collector and emitter shown in FIG. 9 should therefore be understood as a schematic representation of the respective first and second transfer electrodes of these semiconductor switching devices.
  • FIG. 10 shows a schematic block diagram of a five-level circuit with a fault protection device provided by an embodiment of the present application.
  • the five-level circuit 1000 includes a fault protection device 1010 , a capacitor bridge arm 1020 and a five-level bridge arm 1030 .
  • the fault protection device 1010 includes a circuit breaker SP, and the circuit breaker SP shown in FIG. 10 may correspond to the circuit breaker SP shown in any of the embodiments in FIGS. 2 to 5 or any possible combination or variation of these embodiments.
  • the capacitor bridge arm 1020 has three output ports, which are the positive output port P, the negative output port N, and the reference output port M, respectively.
  • the five-level bridge arm 1030 has three input ports, which are the positive input port P', the negative input port N' and the reference input port M' respectively.
  • the five-level bridge arm 1030 also has an external output port O, which is used to provide the output level voltage to the next-level load or the external network.
  • the positive output port P is connected with the positive input port P'
  • the negative output port N is connected with the negative input port N'
  • one end of the fault protection device 1010 is connected with the reference output port M
  • the other end is connected with the reference input port M'.
  • each output port of the capacitor bridge arm 1020 and each input port of the five-level bridge arm 1030 there is a one-to-one correspondence between each output port of the capacitor bridge arm 1020 and each input port of the five-level bridge arm 1030 , and the reference output port M is indirectly connected to the reference input port M′ through the fault protection device 1010 .
  • the positive electrode and the negative electrode mentioned in the embodiments of the present application are only relative concepts, and for the convenience of description, one port is designated as the positive electrode and the other port is the negative electrode, which should not be construed as limiting.
  • the capacitor bridge arm 1020 includes two capacitors C1 and C2.
  • the capacitors C1 and C2 are connected in series between the positive output port P and the negative output port N, and the intermediate node between the capacitors C1 and C2 is connected to the reference output port M.
  • the five-level bridge arm 1030 includes a total of eight semiconductor switching devices, which are marked as S1 , S2 , S3 , S4 , S5 , S6 , S7 and S8 respectively.
  • each of the semiconductor switching devices S1 , S2 , S3 , S4 , S5 , S6 , S7 and S8 included in the five-level bridge arm 1030 is a pair of IGBTs and opposite to the IGBTs. diodes connected in parallel relationship.
  • these semiconductor switching devices may also be implemented using other semiconductor devices having similar functions, such as MOSFETs, GTRs, GTOs, or other suitable devices, and configured in pairs of diodes accordingly.
  • these semiconductor devices may also employ HEMTs, also known as MODFETs, or 2-DEGFETs, or SDHTs. These can be adjusted and improved according to the specific application environment, which is not specifically limited here.
  • the semiconductor switching devices S1 and S2 are connected in series between the positive input port P' and the reference input port M', and the semiconductor switching devices S3 and S4 are connected in series between the reference input port M' and the negative input port N' between.
  • the semiconductor switching devices S2 and S3 are connected, and the intermediate node between the semiconductor switching devices S2 and S3 is connected to the reference input port M'.
  • the semiconductor switching devices S5 and S7 are connected in series, they are respectively connected to the intermediate node between the semiconductor switching devices S1 and S2 and the external output port O of the five-level bridge arm 1030 .
  • the intermediate node between the semiconductor switching devices S3 and S4 and the external output port O of the five-level bridge arm 1030 are respectively connected.
  • the semiconductor switching devices S7 and S9 are connected, and the intermediate node between the semiconductor switching devices S7 and S8 is connected to the external output port O of the five-level bridge arm 1030 .
  • the semiconductor switching devices S1, S2, S3 and S4 are connected in series between the positive input port P' and the negative input port N'.
  • the semiconductor switching devices S5, S7, S8 and S6 are connected in series between the intermediate node between the semiconductor switching devices S1 and S2 and the intermediate node between the semiconductor switching devices S3 and S4.
  • the five-level bridge arm 1030 also includes two capacitors Ca and Cb.
  • One end of the capacitor Ca is connected to the intermediate node between the semiconductor switching devices S2 and S5, and the other end is connected to the intermediate node between the semiconductor switching devices S3 and S6.
  • One end of the capacitor Cb is connected to the intermediate node between the semiconductor switching devices S5 and S7, and the other end is connected to the intermediate node between the semiconductor switching devices S6 and S8.
  • the external output port O is connected to the negative input port N' through the branch composed of the semiconductor switching devices S4, S6 and S8, and the negative output port N is connected to the negative input port N' , so the voltage output from the external output port O is the second voltage applied to the negative output port N.
  • the external output port O passes through the branch composed of the semiconductor switching devices S2, S5 and S7 or the semiconductor switching device S3
  • the branch formed by , S6 and S8 is connected to the reference input port M', and the reference output port M is indirectly connected to the reference input port M' through the fault protection device 1010, so the voltage output by the external output port O is applied to the reference output port The third voltage of M.
  • the voltage output from the external output port O can be made between the first voltage applied to the positive output port P and the first voltage applied to the negative output port.
  • Switching between the second voltage of N and the third voltage applied to the reference output port M realizes a three-level output.
  • a voltage dividing branch can be formed or a control signal design can be used to further provide outputs of the fourth level and the fifth level, which can be obtained based on conventional techniques and will not be repeated here.
  • the negative input port N' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' remain The connection relationship will cause the capacitor C2 to be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C1.
  • the capacitors C1 and C2 are respectively subjected to half the voltage between the positive output port P and the negative output port N, so when the voltage between the positive output port P and the negative output port N is When it is all applied to the capacitor C1, it may cause the capacitor C1 to bear twice the voltage of the normal design, thereby causing overvoltage damage, or even diffusion and damage to the circuit and equipment, which greatly reduces the reliability of the circuit.
  • the positive input port P' and the reference input port M' are equivalent to a short-circuit connection, and if the reference output port M and the reference input port M' maintain a connection relationship, It will cause the capacitor C1 to be bypassed, so that the voltage between the positive output port P and the negative output port N is all applied to the capacitor C2, resulting in overvoltage damage. To this end, it is necessary to adjust the connection relationship between the reference output port M and the reference input port M' by controlling the closing and opening of the disconnect switch SP.
  • a short-circuit fault of the semiconductor switching device occurs by monitoring one of the following conditions: monitoring the voltage between the negative input port N' and the reference input port M', and determining the semiconductor switching device when the voltage is lower than a certain threshold S3 and S4 have a short-circuit fault at the same time; monitor the voltage between the positive input port P' and the reference input port M', when the voltage is lower than a certain threshold, determine that the semiconductor switching devices S1 and S2 have a short-circuit fault at the same time; monitor the negative input port N The voltage drop rate between ' and the reference input port M', when the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switching devices S3 and S4 have short-circuit faults at the same time; monitor the positive input port P' and the reference input port M' When the voltage drop rate is higher than a certain threshold, it is judged that the semiconductor switching devices S1 and S2 have short-circuit faults at the same time; monitor the flow from the positive input
  • the voltage between the poles is determined, and when the voltage is higher than a certain threshold, it is determined that the corresponding semiconductor switching device S1, S2, S3 or S4 has a short-circuit fault.
  • the above conditions such as monitoring the current and voltage of a specific semiconductor switching device, it can be determined whether a short-circuit fault has occurred in the five-level bridge arm 1030, and the reference output port M and the reference output port M can be adjusted in time by controlling the closing and opening of the circuit breaker SP.
  • the connection relationship between the input ports M' thereby avoiding the overvoltage damage of the half-bus capacitor and improving the reliability of the circuit.
  • the current flowing through the disconnect switch SP can also be monitored, and when the current is greater than a certain threshold, it is determined that the five-level bridge arm 1030 has a short-circuit fault.
  • controller 1011 included in the fault protection device 1010 is communicatively connected to the circuit breaker SP and is configured to control the closing and opening of the circuit breaker SP.
  • the controller 1011 may have corresponding circuits and components to monitor the above-mentioned short-circuit fault, and may also receive commands from the outside through an interface circuit.
  • controller 1011 may be provided separately from fault protection device 1010, that is, as a separate device.
  • other technical means can also be used to determine whether a short-circuit fault has occurred in the semiconductor switching device. These can be adjusted and improved according to the specific application environment, which is not specifically limited here.
  • the semiconductor switching devices included in the five-level circuit 1000 shown in FIG. 10 are IGBTs as an example, and the respective collectors and emitters of these semiconductor switching devices are schematically shown in FIG. 10 .
  • the above-mentioned collector and emitter are correspondingly replaced with drain and source.
  • the collector and emitter shown in FIG. 10 should therefore be understood as a schematic representation of the respective first and second transfer electrodes of these semiconductor switching devices.
  • the specific embodiments provided herein may be implemented in any one or combination of hardware, software, firmware or solid state logic circuits, and may be implemented in conjunction with signal processing, control and/or special purpose circuits.
  • the apparatus or apparatus provided by the specific embodiments of the present application may include one or more processors (eg, microprocessor, controller, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) ), etc.), these processors process various computer-executable instructions to control the operation of a device or apparatus.
  • the device or apparatus provided by the specific embodiments of the present application may include a system bus or a data transmission system that couples various components together.
  • a system bus may include any one or a combination of different bus structures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and/or processing utilizing any of a variety of bus architectures device or local bus.
  • the equipment or apparatus provided by the specific embodiments of the present application may be provided independently, may be a part of a system, or may be a part of other equipment or apparatus.
  • Embodiments provided herein may include or be combined with computer-readable storage media, such as one or more storage devices capable of providing non-transitory data storage.
  • the computer-readable storage medium/storage device may be configured to hold data, programmers and/or instructions that, when executed by the processors of the apparatuses or apparatuses provided by the specific embodiments of the present application, cause these apparatuses Or the device realizes the relevant operation.
  • Computer-readable storage media/storage devices may include one or more of the following characteristics: volatile, non-volatile, dynamic, static, read/write, read-only, random access, sequential access, location addressability, File addressability and content addressability.
  • the computer-readable storage medium/storage device may be integrated into the device or apparatus provided by the specific embodiments of the present application or belong to a public system.
  • Computer readable storage media/storage devices may include optical storage devices, semiconductor storage devices and/or magnetic storage devices, etc., and may also include random access memory (RAM), flash memory, read only memory (ROM), erasable and programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Registers, Hard Disk, Removable Disk, Recordable and/or Rewritable Compact Disc (CD), Digital Versatile Disc (DVD), Mass storage media device or any other form of suitable storage media.
  • RAM random access memory
  • ROM read only memory
  • EPROM erasable and programmable Read Only Memory
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • CD Compact Disc
  • DVD Digital Versatile Disc
  • Mass storage media device or any other form of suitable storage media.

Abstract

本申请涉及一种故障保护装置及光伏发电系统。光伏发电系统包括：电容桥臂，所述电容桥臂包括正极输出端口、负极输出端口和在所述正极输出端口和所述负极输出端口之间的参考输出端口；逆变桥臂，所述逆变桥臂包括正极输入端口、负极输入端口和在所述正极输入端口和所述负极输入端口之间的参考输入端口，所述正极输入端口与所述正极输出端口连接，所述负极输入端口与所述负极输出端口连接；以及故障保护装置，其中，所述参考输入端口通过所述故障保护装置与所述参考输出端口连接，所述故障保护装置根据所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的电压的大小或变化情况或电流的大小或变化情况而关断。

Description

故障保护装置及光伏发电系统 技术领域
本申请涉及电力电子领域，具体涉及一种故障保护装置及光伏发电系统。
背景技术
太阳能发电、风力发电、变频器、不间断供电电源(Uninterruptible Power System，UPS)、电动机驱动器以及新能源汽车等领域都需要用于实现直流电到交流电转换的电能变换器，也叫逆变器。其中，能输出三种及以上电压电平的多电平电路得到了广泛应用和关注。与两电平电路相比，能输出三种及以上的电压电平的多电平电路具有输出电平多、电压应力小、纹波电流小、谐波特性好等优势，有利于实现输出的电压脉冲接近工频交流电压从而减小滤波器的体积和重量。多电平电路通常利用半导体开关器件来实现直流电到交流电的转换。以典型的三相桥式逆变电路为例，每个桥臂的半导体开关管在一个正弦周期中开通半个周期，三相各自的桥臂交替导通且有120度的导电角度差，如此得到的输出电压波形近似为正弦波。
现有技术中，包括两个直流电压源的三电平电路有广泛应用。但是，应用这种三电平电路的两个直流电压源的中间节点与半导体开关器件的中间节点是直接电气连接，因此当半导体开关器件的逆变桥臂发生故障时，容易对半母线电容造成过压损坏，还可能进一步扩散进而损坏电路以及设备，极大的降低电路的可靠性。
为此，需要针对多电平电路提供一种技术方案从而在逆变桥臂出现短路故障时对电容桥臂进行保护，从而避免电路失效损坏。
发明内容
本申请的目的在于提供一种故障保护装置及光伏发电系统，从而实现了在逆变桥臂出现短路故障时对电容桥臂进行保护，从而避免电路失效损坏。
第一方面，本申请实施例提供了一种光伏发电系统。所述光伏发电系统包括：电容桥臂，其中，所述电容桥臂包括正极输出端口、负极输出端口和在所述正极输出端口和所述负极输出端口之间的参考输出端口；逆变桥臂，其中，所述逆变桥臂包括正极输入端口、负极输入端口和在所述正极输入端口和所述负极输入端口之间的参考输入端口，所述正极输入端口与所述正极输出端口连接，所述负极输入端口与所述负极输出端口连接；以及故障保护装置，其中，所述参考输入端口通过所述故障保护装置与所述参考输出端口连接，所述故障保护装置根据所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的电压的大小或变化情况或电流的大小或变化情况而关断。
第一方面所描述的技术方案，通过故障保护装置的闭合和断开可以调整参考输出端口与参考输入端口之间的连接关系，从而实现了避免半母线电容过压损坏和提高电路的可靠性。
根据第一方面，在一种可能的实现方式中，所述故障保护装置根据所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的电压的大小或变化情况而关断，包括：当所述负极输入端口和所述参考输入端口之间的电压低于第一阈值时，所述故障保护装置断开； 或当所述正极输入端口和所述参考输入端口之间的电压低于第二阈值时，所述故障保护装置断开；或当所述负极输入端口和所述参考输入端口之间的电压下降速率高于第三阈值时，所述故障保护装置断开；或当所述正极输入端口和所述参考输入端口之间的电压下降速率高于第四阈值时，所述故障保护装置断开。
如此，通过监控电压变化情况而控制故障保护装置断开从而调整参考输出端口与参考输入端口之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。
根据第一方面，在一种可能的实现方式中，所述故障保护装置还根据流经所述故障保护装置的电流而关断。
如此，通过监控流经所述故障保护装置的电流而控制故障保护装置断开从而调整参考输出端口与参考输入端口之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。
根据第一方面，在一种可能的实现方式中，所述逆变桥臂还包括连接在所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的至少一个半导体开关器件，所述故障保护装置还根据流经所述至少一个半导体开关器件的电流或者施加在所述至少一个半导体开关器件的第一传输电极和第二传输电极之间的电压而关断。
如此，通过监控半导体开关器件的电压电流情况而控制故障保护装置断开从而调整参考输出端口与参考输入端口之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。
根据第一方面，在一种可能的实现方式中，所述故障保护装置包括主断路器，其中，所述主断路器包括第一开关晶体管和第二开关晶体管，所述第一开关晶体管和所述第二开关晶体管按照对项串联的方式连接在所述参考输出端口和所述参考输入端口之间，所述故障保护装置通过控制所述第一开关晶体管和所述第二开关晶体管的导通和关断来闭合和断开。
如此，通过控制第一开关晶体管和第二开关晶体管的导通和关断实现了控制断路开关的闭合和断开。
根据第一方面，在一种可能的实现方式中，所述第一开关晶体管和所述第二开关晶体管是MOSFET、IGBT、GTR、GTO、HEMT、MODFET、2-DEGFET或者SDHT。
如此，实现了利用各种类型的开关晶体管。
根据第一方面，在一种可能的实现方式中，所述故障保护装置还包括：高阻抗器件，其中，所述高阻抗器件和所述主断路器并联连接在所述参考输出端口和所述参考输入端口之间。
如此，通过高阻抗器件实现了减慢电容桥臂的充放电速度，有利于其它保护机制做出反应并提高系统的稳定性。
根据第一方面，在一种可能的实现方式中，所述高阻抗器件是热敏电阻。
如此，通过热敏电阻实现了减慢电容桥臂的充放电速度，有利于其它保护机制做出反应并提高系统的稳定性。
根据第一方面，在一种可能的实现方式中，所述故障保护装置还包括：压敏电阻，其中，所述压敏电阻和所述主断路器并联连接在所述参考输出端口和所述参考输入端口之间。
如此，通过压敏电阻吸收故障保护装置在断路过程中残留的能量，有利于防止过压损坏和提高电路的可靠性。
根据第一方面，在一种可能的实现方式中，所述故障保护装置还包括：高速机械开关，其中，所述高速机械开关、所述压敏电阻和所述主断路器一起并联连接在所述参考输出端口和所述参考输入端口之间，所述高速机械开关在所述主断路器的所述第一开关晶体管和所述 第二开关晶体管导通之后闭合，所述高速机械开关在所述主断路器的所述第一开关晶体管和所述第二开关晶体管关断之前断开。
如此，通过在主断路器的开关晶体管导通之后通过闭合的高速机械开关对主断路器做旁路化处理，从而可以通过闭合的高速机械开关来降低损耗。
根据第一方面，在一种可能的实现方式中，所述故障保护装置还包括：高速机械开关，和辅助断路器，其中，所述辅助断路器包括第三开关晶体管和第四开关晶体管，所述第三开关晶体管和所述第四开关晶体管按照对项串联的方式连接之后与所述高速机械开关串联连接在所述参考输出端口和所述参考输入端口之间，所述高速机械开关和所述辅助断路器串联连接之后与所述压敏电阻和所述主断路器一起并联连接在所述参考输出端口和所述参考输入端口之间，所述辅助断路器的所述第三开关晶体管和所述第四开关晶体管以及所述高速机械开关在所述主断路器的所述第一开关晶体管和所述第二开关晶体管导通之后闭合，所述高速机械开关在所述主断路器的所述第一开关晶体管和所述第二开关晶体管关断之前断开，所述辅助断路器的所述第三开关晶体管和所述第四开关晶体管在所述高速机械开关断开之前关断。
如此，通过在主断路器的开关晶体管导通之后通过闭合高速机械开关和辅助断路器从而组成旁路支路对主断路器做旁路化处理，从而可以降低断路开关SP的损耗。
根据第一方面，在一种可能的实现方式中，所述第三开关晶体管和所述第四开关晶体管是MOSFET、IGBT、GTR、GTO、HEMT、MODFET、2-DEGFET或者SDHT。
如此，实现了利用各种类型的开关晶体管。
根据第一方面，在一种可能的实现方式中，所述逆变桥臂包括ANPC三电平桥臂，所述ANPC三电平桥臂包括串联连接在所述正极输入端口和所述参考输入端口之间以及串联连接在所述负极输入端口和所述参考输入端口之间的多个半导体开关器件，所述故障保护装置还根据流经所述多个半导体开关器件的电流或者施加在所述多个半导体开关器件的第一传输电极和第二传输电极之间的电压而关断。
如此，通过监测多个半导体开关器件的电压电流情况可以判断ANPC三电平桥臂是否出现了短路故障，并及时通过控制故障保护装置断开从而调整参考输出端口与参考输入端口之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。
根据第一方面，在一种可能的实现方式中，所述逆变桥臂包括NPC三电平桥臂，所述NPC三电平桥臂包括串联连接在所述正极输入端口和所述参考输入端口之间以及串联连接在所述负极输入端口和所述参考输入端口之间的多个半导体开关器件，所述故障保护装置还根据流经所述多个半导体开关器件的电流或者施加在所述多个半导体开关器件的第一传输电极和第二传输电极之间的电压而关断。
如此，通过监测多个半导体开关器件的电压电流情况可以判断NPC三电平桥臂是否出现了短路故障，并及时通过控制故障保护装置断开从而调整参考输出端口与参考输入端口之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。
根据第一方面，在一种可能的实现方式中，所述逆变桥臂包括T型三电平桥臂，所述T型三电平桥臂包括串联连接在所述正极输入端口和所述负极输入端口之间的多个半导体开关器件，所述故障保护装置还根据流经所述多个半导体开关器件的电流或者施加在所述多个半导体开关器件的第一传输电极和第二传输电极之间的电压而关断。
如此，通过监测多个半导体开关器件的电压电流情况可以判断T型三电平桥臂是否出现了短路故障，并及时通过控制故障保护装置断开从而调整参考输出端口与参考输入端口之间 的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。
根据第一方面，在一种可能的实现方式中，所述逆变桥臂包括五电平桥臂，所述五电平桥臂包括串联连接在所述正极输入端口和所述参考输入端口之间以及串联连接在所述负极输入端口和所述参考输入端口之间的多个半导体开关器件，所述故障保护装置还根据流经所述多个半导体开关器件的电流或者施加在所述多个半导体开关器件的第一传输电极和第二传输电极之间的电压而关断。
如此，通过监测多个半导体开关器件的电压电流情况可以判断五电平桥臂是否出现了短路故障，并及时通过控制故障保护装置断开从而调整参考输出端口与参考输入端口之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。
第二方面，本申请实施例提供了一种故障保护装置的控制方法，应用于光伏发电系统。所述光伏发电系统包括电容桥臂、逆变桥臂和所述故障保护装置，其中，所述电容桥臂包括正极输出端口、负极输出端口和在所述正极输出端口和所述负极输出端口之间的参考输出端口，所述逆变桥臂包括正极输入端口、负极输入端口和在所述正极输入端口和所述负极输入端口之间的参考输入端口，所述正极输入端口与所述正极输出端口连接，所述负极输入端口与所述负极输出端口连接，所述参考输入端口通过所述故障保护装置与所述参考输出端口连接，所述方法包括：根据所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的电压的大小或变化情况或电流的大小或变化情况而控制所述故障保护装置关断。
第二方面所描述的技术方案，通过故障保护装置的闭合和断开可以调整参考输出端口与参考输入端口之间的连接关系，从而实现了避免半母线电容过压损坏和提高电路的可靠性。
附图说明
为了说明本申请实施例或背景技术中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。
图1示出了本申请实施例提供的带有故障保护装置的多电平电路的原理框图。
图2示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第一种实施方式的结构框图。
图3示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第二种实施方式的结构框图。
图4示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第三种实施方式的结构框图。
图5示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第四种实施方式的结构框图。
图6示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第五种实施方式的结构框图。
图7示出了本申请实施例提供的带有故障保护装置的ANPC三电平电路的原理框图。
图8示出了本申请实施例提供的带有故障保护装置的NPC三电平电路的原理框图。
图9示出了本申请实施例提供的带有故障保护装置的T型三电平电路的原理框图。
图10示出了本申请实施例提供的带有故障保护装置的五电平电路的原理框图。
具体实施方式
本申请实施例提供了一种光伏发电系统。所述光伏发电系统包括：电容桥臂，其中，所述电容桥臂包括正极输出端口、负极输出端口和在所述正极输出端口和所述负极输出端口之间的参考输出端口；逆变桥臂，其中，所述逆变桥臂包括正极输入端口、负极输入端口和在所述正极输入端口和所述负极输入端口之间的参考输入端口，所述正极输入端口与所述正极输出端口连接，所述负极输入端口与所述负极输出端口连接；以及故障保护装置，其中，所述参考输入端口通过所述故障保护装置与所述参考输出端口连接，所述故障保护装置根据所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的电压的大小或变化情况或电流的大小或变化情况而关断。如此，通过故障保护装置的闭合和断开可以调整参考输出端口与参考输入端口之间的连接关系，从而实现了避免半母线电容过压损坏和提高电路的可靠性。
本申请实施例可用于以下应用场景：太阳能发电、风力发电、变频器、UPS、电动机驱动器、新能源汽车或者其它需要多电平逆变电路的应用场景。
本申请实施例可以依据具体应用环境进行调整和改进，此处不做具体限定。
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请的实施例进行描述。
请参阅图1，图1示出了本申请实施例提供的带有故障保护装置的多电平电路的原理框图。如图1所示，多电平电路100包括故障保护装置110、电容桥臂120和逆变多电平桥臂130。电容桥臂120有三个输出端口，分别是正极输出端口P、负极输出端口N和参考输出端口M。相对的，逆变多电平桥臂130有三个输入端口，分别是正极输入端口P’、负极输入端口N’和参考输入端口M’。其中，正极输出端口P与正极输入端口P’连接，负极输出端口N与负极输入端口N’连接，故障保护装置110的一端与参考输出端口M连接，另一端与参考输入端口M’连接。如此，电容桥臂120的各个输出端口和逆变多电平桥臂130的各个输入端口之间存在一一对应的连接关系，并且参考输出端口M通过故障保护装置110而间接地连接参考输入端口M’。应当理解的是，本申请实施例中提到的正极和负极只是相对的概念，是为了便于描述而指定一个端口为正极另一个端口为负极，不应理解成限制性。
请继续参阅图1，故障保护装置110包括断路开关SP和控制器111。断路开关SP的一端与参考输出端口M连接，另一端与参考输入端口M’连接。控制器111与断路开关SP通信地连接并配置成用于控制断路开关SP的闭合和断开。当控制器111控制断路开关SP闭合时，参考输出端口M通过断路开关SP与参考输入端口M’连接；当控制器111控制断路开关SP断开时，参考输出端口M被断路开关SP阻碍而无法与参考输入端口M’连接。如此，通过控制器111来控制断路开关SP的闭合和断开可以调整参考输出端口M与参考输入端口M’之间的连接关系。所述故障保护装置110有下面多种实现结构，但是可以理解本申请并不仅仅限于下面的这些具体断路结构的实现方式。本申请的关键在于在电容桥臂参考端以及逆变桥臂的参考端之间连接断路开关SP保护装置，而保护装置的具体结构并不是关键，可以参照市面常用的各种断路保护实现方式和结构，在此不一一赘述。
请参阅图2，图2示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第一种实施方式的结构框图。如图2所示，断路开关SP包括主断路器212。主断路器212包括两个半导体开关器件，以绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)为例，分别是Q1和Q2。Q1和Q2采用对项串联的方式连接在参考输出端口M与参考输入 端口M’之间。也就是说，Q1的发射极和Q2的发射极互相连接，Q1的集电极连接参考输入端口M’，Q2的集电极连接参考输出端口M。在另一种实施方式中，Q1的集电极和Q2的集电极互相连接，Q1的发射极连接参考输入端口M’，Q2的发射极连接参考输出端口M。在这两种实施方式中，Q1和Q2的位置也可以互换。主断路器212还包括两个二极管T1和T2，T1和T2分别与Q1和Q2成反并联关系。具体地，二极管T1对应Q1，T1的阳极连接Q1的发射极，T1的阴极连接Q1的集电极；二极管T2对应Q2，T2的阳极连接Q2的发射极，T2的阴极连接Q2的集电极。如此，通过对项串联方式连接的两个绝缘栅双极型晶体管Q1和Q2，以及按照反并联关系连接的一对二极管T1和T2，实现了断路开关SP的控制机制。具体地，当断路开关SP接收到指示闭合的控制信号，可以控制断路开关SP中的IGBT的栅极电压从而让IGBT导通，实现参考输出端口M与参考输入端口M’之间的连接；当断路开关SP接收到指示断开的控制信号，可以控制断路开关SP中的IGBT的栅极电压从而让IGBT关断，从而阻断参考输出端口M与参考输入端口M’之间的连接；利用IGBT的控制机制，还可以通过停止向断路开关SP发送闭合的控制信号，从而使得断路开关SP在未接收到闭合的控制信号后，可以驱动IGBT关断。另外，通过与IGBT按照反并联关系连接的二极管可以抑制反向电流电压，避免过大的反向电流电压引起损坏。
请继续参阅图2，应当理解的是，图2所示的IGBT仅为示例性。在一些示例性实施例中，主断路器212所包括的两个半导体开关器件分别是第一开关晶体管和第二开关晶体管。所述第一开关晶体管和所述第二开关晶体管按照对项串联的方式连接在所述电容桥臂的参考输出端口和所述逆变多电平桥臂的参考输入端口之间。所述控制器通过控制所述主断路器的所述第一开关晶体管和所述第二开关晶体管的导通和关断来控制所述断路开关的闭合和断开。在一些示例性实施例中，主断路器212所包括的两个半导体开关器件可以采用其它具有类似功能的半导体器件来实现，例如金属氧化物半导体场效应管((Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)、电力晶体管(Giant Transistor，GTR)、可关断晶闸管(Gate Turn-Off Thyristor，GTO)或者其它合适的器件，并且相应地配置成对的二极管。在一些示例性实施例中，这些半导体器件还可以采用高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)，也称作调制掺杂场效应晶体管(Modulation-Doped FET，MODFET)，或者二维电子气场效应晶体管(Two Dimensional Electron Gas Field Effect Transistor，2-DEGFET)，或者选择掺杂异质结晶体管(Selectively-Doped Heterojunction Transistor，SDHT)。这些可以依据具体应用环境进行调整和改进，此处不做具体限定。换句话说，所述第一开关晶体管和所述第二开关晶体管是MOSFET、IGBT、GTR、GTO、HEMT、MODFET、2-DEGFET或者SDHT。
请参阅图3，图3示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第二种实施方式的结构框图。如图3所示，断路开关SP包括主断路器312和压敏电阻313。其中，主断路器312的构造和功能与图2所示的主断路器212相似，在此不再赘述。压敏电阻313可以基于金属氧化物材料，压敏电阻313和主断路器312并联连接于参考输出端口M与参考输入端口M’之间。压敏电阻313具有非线性伏安特性，用于吸收断路开关SP在断路过程中残留的能量，有利于防止主断路器312过压损坏和提高电路的可靠性。
请参阅图4，图4示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第三种实施方式的结构框图。如图4所示，断路开关SP包括主断路器412、压敏电阻413和高速机械开关414。主断路器412、压敏电阻413和高速机械开关414均并联连接于参考输出 端口M与参考输入端口M’之间。其中，主断路器412的构造和功能与图2所示的主断路器212相似，在此不再赘述。压敏电阻413的构造和功能与图3所示的压敏电阻313相似，在此不再赘述。高速机械开关414在主断路器412的IGBT导通之后才闭合，也就是在主断路器412的IGBT导通之后通过闭合的高速机械开关414对主断路器412做旁路化处理，从而可以通过闭合的高速机械开关414来降低断路开关SP的损耗。高速机械开关414在主断路器412的IGBT关断之前就断开，从而确保由主断路器412的IGBT来承担电流断路的影响，并避免由高速机械开关414来承担电流断路的影响。
请参阅图5，图5示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第四种实施方式的结构框图。如图5所示，断路开关SP包括主断路器512、压敏电阻513和高速机械开关514以及辅助断路器515。其中，高速机械开关514和辅助断路器515串联连接之后再跟主断路器512和压敏电阻513一起并联连接于参考输出端口M与参考输入端口M’之间。其中，主断路器512的构造和功能与图2所示的主断路器212相似，在此不再赘述。压敏电阻513的构造和功能与图3所示的压敏电阻313相似，在此不再赘述。高速机械开关514的结构和功能与图4所示的高速机械开关414相似，在此不再赘述。其中，辅助断路器515包括两个半导体开关器件，以IGBT为例，分别是Q3和Q4。Q3和Q4采用对项串联的方式连接在参考输入端口M’和高速机械开关514之间。也就是说，Q3的发射极和Q4的发射极互相连接，Q3的集电极连接参考输入端口M’，Q4的集电极连接参考高速机械开关514。在另一种实施方式中，Q3的集电极和Q4的集电极互相连接，Q3的发射极连接参考输入端口M’，Q4的发射极连接高速机械开关514。在这两种实施方式中，Q3和Q4的位置也可以互换。并且，高速机械开关514和辅助断路器515的位置也可以互换。辅助断路器515还包括两个二极管T3和T4，T3和T4分别与Q3和Q4成反并联关系。具体地，二极管T3对应Q3，T3的阳极连接Q3的发射极，T3的阴极连接Q3的集电极；二极管T4对应Q4，T4的阳极连接Q4的发射极，T4的阴极连接Q4的集电极。辅助断路器515和高速机械开关514在主断路器512的IGBT导通之后才闭合，也就是在主断路器512的IGBT导通之后通过闭合高速机械开关514和辅助断路器515从而组成旁路支路对主断路器512做旁路化处理，从而可以降低断路开关SP的损耗。高速机械开关514在主断路器512的IGBT关断之前就断开，而辅助断路器515在高速机械开关514断开之前就断开，从而通过辅助断路器515的断开操作来使得包括高速机械开关514和辅助断路器515的旁路支路在主断路器512的IGBT关断之前就断路，进而避免由高速机械开关514来承担电流断路的影响并且确保由主断路器512的IGBT来承担电流断路的影响。
请继续参阅图5，应当理解的是，图5所示的IGBT仅为示例性。在一些示例性实施例中，辅助断路器515所包括的两个半导体开关器件分别是第三开关晶体管和第四开关晶体管。所述第三开关晶体管和所述第四开关晶体管是MOSFET、IGBT、GTR、GTO、HEMT、MODFET、2-DEGFET或者SDHT。
请参阅图6，图6示出了本申请实施例提供的图1所示的故障保护装置的断路开关SP的第五种实施方式的结构框图。如图3所示，断路开关SP包括主断路器612和热敏电阻615。热敏电阻615也可以是其它类型的高阻抗器件。其中，主断路器612的构造和功能与图2所示的主断路器212相似，在此不再赘述。热敏电阻615和主断路器612并联连接于参考输出端口M与参考输入端口M’之间。热敏电阻615在主断路器612断开后承受短路电流并对与断路开关SP连接的电容桥臂进行充放电。因为热敏电阻615的阻值较大且在高温时该阻值进 一步增大，从而减慢了电容桥臂的充放电速度，有利于其它保护机制做出反应并提高系统的稳定性。该热敏电阻615同理可以与断路开关SP的第二种、第三种、第四种实施方式并联使用，这里不再赘述。
请参阅图7，图7示出了本申请实施例提供的带有故障保护装置的ANPC三电平电路的原理框图。如图7所示，有源中点嵌位(Active Neutral Point Clamped，ANPC)三电平电路700包括故障保护装置710、电容桥臂720和ANPC三电平桥臂730。其中，故障保护装置710包括断路开关SP，图7所示的断路开关SP可以对应图2至图5中任一实施例所示的断路开关SP或者这些实施例的任意可能组合或者变体。电容桥臂720有三个输出端口，分别是正极输出端口P、负极输出端口N和参考输出端口M。相对的，ANPC三电平桥臂730有三个输入端口，分别是正极输入端口P’、负极输入端口N’和参考输入端口M’。其中，ANPC三电平桥臂730还有对外输出端口O，用于向下一级负载或者外网提供输出的电平电压。其中，正极输出端口P与正极输入端口P’连接，负极输出端口N与负极输入端口N’连接，故障保护装置710的一端与参考输出端口M连接，另一端与参考输入端口M’连接。如此，电容桥臂720的各个输出端口和ANPC三电平桥臂730的各个输入端口之间存在一一对应的连接关系，并且参考输出端口M通过故障保护装置710而间接地连接参考输入端口M’。应当理解的是，本申请实施例中提到的正极和负极只是相对的概念，是为了便于描述而指定一个端口为正极另一个端口为负极，不应理解成限制性。
请继续参阅图7，电容桥臂720包括两个电容C1和C2。电容C1和C2串联连接在正极输出端口P和负极输出端口N之间，电容C1和C2之间的中间节点连接参考输出端口M。ANPC三电平桥臂730包括共计六个半导体开关器件，分别标记为S1、S2、S3、S4、S5和S6。应当理解的是，ANPC三电平桥臂730所包括的半导体开关器件S1、S2、S3、S4、S5和S6中的每一个半导体开关器件是成对的IGBT和与该IGBT成反并联关系连接的二极管。在一些示例性实施例中，这些半导体开关器件也可以采用其它具有类似功能的半导体器件来实现，例如金属氧化物半导体场效应管MOSFET、电力晶体管GTR、可关断晶闸管GTO或者其它合适的器件，并且相应地配置成对的二极管。在一些示例性实施例中，这些半导体器件还可以采用高电子迁移率晶体管HEMT，也称作调制掺杂场效应晶体管MODFET，或者二维电子气场效应晶体管2-DEGFET，或者选择掺杂异质结晶体管SDHT。这些可以依据具体应用环境进行调整和改进，此处不做具体限定。
请继续参阅图7，半导体开关器件S1和S2串联连接在正极输入端口P’和参考输入端口M’之间，半导体开关器件S3和S4串联连接在参考输入端口M’和负极输入端口N’之间。半导体开关器件S2和S3连接，并且半导体开关器件S2和S3之间的中间节点连接参考输入端口M’。半导体开关器件S5和S6串联连接之后分别连接半导体开关器件S1和S2之间的中间节点以及半导体开关器件S3和S4之间的中间节点。半导体开关器件S5和S6之间的中间节点连接ANPC三电平桥臂730的对外输出端口O。当半导体开关器件S1和S5导通时，对外输出端口O通过由半导体开关器件S1和S5组成的支路连接正极输入端口P’，而正极输出端口P与正极输入端口P’连接，因此对外输出端口O输出的电压是施加在正极输出端口P的第一电压。当半导体开关器件S4和S6导通时，对外输出端口O通过由半导体开关器件S4和S6组成的支路连接负极输入端口N’，而负极输出端口N与负极输入端口N’连接，因此对外输出端口O输出的电压是施加在负极输出端口N的第二电压。当半导体开关器件S2和S5导通时或者当半导体开关器件S3和S6导通时，对外输出端口O通过由半导体开关器件S2 和S5组成的支路或者由半导体开关器件S3和S6组成的支路而连接参考输入端口M’，并且参考输出端口M通过故障保护装置710而间接地连接参考输入端口M’，因此对外输出端口O输出的电压是施加在参考输出端口M的第三电压。如此，通过控制ANPC三电平桥臂730所包括的各个半导体开关器件的导通和关断，可以使得对外输出端口O输出的电压在施加在正极输出端口P的第一电压、施加在负极输出端口N的第二电压和施加在参考输出端口M的第三电压之间切换，实现三电平输出。
请继续参阅图7，当半导体开关器件S3和S4同时出现短路故障时，负极输入端口N’和参考输入端口M’之间相当于短路连接，而如果参考输出端口M与参考输入端口M’保持连接关系，则会导致电容C2被旁路化，这样正极输出端口P和负极输出端口N之间的电压就全部施加在电容C1上。当电容桥臂720采用对称性设计时，电容C1和C2分别承受的是正极输出端口P和负极输出端口N之间的电压的一半，所以当正极输出端口P和负极输出端口N之间的电压就全部施加在电容C1时，可能导致电容C1承受正常设计的两倍电压，从而引起过压损坏，甚至扩散进而损坏电路以及设备，极大的降低电路的可靠性。类似地，当半导体开关器件S1和S2同时出现短路故障时，正极输入端口P’和参考输入端口M’之间相当于短路连接，而如果参考输出端口M与参考输入端口M’保持连接关系，则会导致电容C1被旁路化，这样正极输出端口P和负极输出端口N之间的电压就全部施加在电容C2上，从而引起过压损坏。为此，需要通过控制断路开关SP的闭合和断开从而调整参考输出端口M与参考输入端口M’之间的连接关系。具体地，可以通过监测以下情况之一从而判断是否出现半导体开关器件的短路故障：监测负极输入端口N’和参考输入端口M’之间的电压，当该电压低于一定阈值时判断半导体开关器件S3和S4同时出现短路故障；监测正极输入端口P’和参考输入端口M’之间的电压，当该电压低于一定阈值时判断半导体开关器件S1和S2同时出现短路故障；监测负极输入端口N’和参考输入端口M’之间的电压下降速率，当该电压下降速率高于一定阈值时判断半导体开关器件S3和S4同时出现短路故障；监测正极输入端口P’和参考输入端口M’之间的电压下降速率，当该电压下降速率高于一定阈值时判断半导体开关器件S1和S2同时出现短路故障；监测从正极输入端口P’流向负极输入端口N’并且经过半导体开关器件S1、S2、S3或者S4的电流，当该电流高于一定阈值时判断对应的半导体开关器件S1、S2、S3或者S4出现短路故障；监测当半导体开关器件S1、S2、S3或者S4闭合时各自的集电极和发射极之间的电压，当该电压高于一定阈值时判断对应的半导体开关器件S1、S2、S3或者S4出现短路故障。如此，通过监测上述情况例如监测特定半导体开关器件的电流电压，可以判断ANPC三电平桥臂730是否出现了短路故障，并及时通过控制断路开关SP的闭合和断开从而调整参考输出端口M与参考输入端口M’之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。另外，还可以监测流经断路开关SP的电流，当该电流大于一定阈值时，判断ANPC三电平桥臂730出现了短路故障。
请继续参阅图7，ANPC三电平电路700可以包括多个ANPC三电平桥臂730，其中每一个ANPC三电平桥臂730具有图7所示的结构，并且各自具有有三个输入端口。多个ANPC三电平桥臂730各自的输入端口并联连接于对应的图7所示的正极输入端口P’、负极输入端口N’和参考输入端口M’，从而使得多个ANPC三电平桥臂730构成并联关系。当多个ANPC三电平桥臂730均正常工作时，故障保护装置710的断路开关SP闭合；当多个ANPC三电平桥臂730中任意一个出现短路故障时，则故障保护装置710的断路开关SP断开，从而避免半母线电容过压损坏和提高电路的可靠性。其中，判断多个ANPC三电平桥臂730中任意一 个发生短路故障可以通过监测所有ANPC三电平桥臂730是否出现上述情况之一来实现。
应当理解的是，故障保护装置710所包括的控制器711与断路开关SP通信地连接并配置成用于控制断路开关SP的闭合和断开。控制器711可以带有对应的电路和部件从而监测上述短路故障的情况，也可以通过接口电路从外部接收指令。在一些示例性实施例中，控制器711可以与故障保护装置710分开提供，也就是作为一个单独的器件。除了上述提及的多种情况之外，还可以通过其它技术手段来判断半导体开关器件是否发生了短路故障。这些可以依据具体应用环境进行调整和改进，此处不做具体限定。
应当理解的是，图7所示的ANPC三电平桥臂730所包括的多个半导体开关器件以IGBT为例子，图7中示意性示出了这些半导体开关器件的各自的集电极和发射极。当这些半导体开关器件采用其它类型例如MOSFET时，则对应的将上述的集电极和发射极替换成漏极和源极。因此图7所示的集电极和发射极应理解成示意性表述这些半导体开关器件各自的第一传输电极和第二传输电极。
请参阅图8，图8示出了本申请实施例提供的带有故障保护装置的NPC三电平电路的原理框图。如图8所示，中点箝位(Neutral Point Clamped，NPC)三电平电路800包括故障保护装置810、电容桥臂820和NPC三电平桥臂830。其中，故障保护装置810包括断路开关SP，图8所示的断路开关SP可以对应图2至图5中任一实施例所示的断路开关SP或者这些实施例的任意可能组合或者变体。电容桥臂820有三个输出端口，分别是正极输出端口P、负极输出端口N和参考输出端口M。相对的，NPC三电平桥臂830有三个输入端口，分别是正极输入端口P’、负极输入端口N’和参考输入端口M’。其中，NPC三电平桥臂830还有对外输出端口O，用于向下一级负载或者外网提供输出的电平电压。其中，正极输出端口P与正极输入端口P’连接，负极输出端口N与负极输入端口N’连接，故障保护装置810的一端与参考输出端口M连接，另一端与参考输入端口M’连接。如此，电容桥臂820的各个输出端口和NPC三电平桥臂830的各个输入端口之间存在一一对应的连接关系，并且参考输出端口M通过故障保护装置810而间接地连接参考输入端口M’。应当理解的是，本申请实施例中提到的正极和负极只是相对的概念，是为了便于描述而指定一个端口为正极另一个端口为负极，不应理解成限制性。
请继续参阅图8，电容桥臂820包括两个电容C1和C2。电容C1和C2串联连接在正极输出端口P和负极输出端口N之间，电容C1和C2之间的中间节点连接参考输出端口M。NPC三电平桥臂830包括共计六个半导体器件，分别标记为S1、D2、D3、S4、S5和S6。其中，半导体器件S1、S4、S5和S6是半导体开关器件而半导体器件D2和D3是二极管。应当理解的是，NPC三电平桥臂830所包括的半导体开关器件S1、S4、S5和S6中的每一个半导体开关器件是成对的IGBT和与该IGBT成反并联关系连接的二极管。在一些示例性实施例中，这些半导体开关器件也可以采用其它具有类似功能的半导体器件来实现，例如MOSFET、GTR、GTO或者其它合适的器件，并且相应地配置成对的二极管。在一些示例性实施例中，这些半导体器件还可以采用HEMT，也称作MODFET，或者2-DEGFET，或者SDHT。这些可以依据具体应用环境进行调整和改进，此处不做具体限定。
请继续参阅图8，半导体开关器件S1和D2串联连接在正极输入端口P’和参考输入端口M’之间，半导体开关器件D3和S4串联连接在参考输入端口M’和负极输入端口N’之间。半导体开关器件D2和D3连接，并且半导体开关器件D2和D3之间的中间节点连接参考输入端口M’。半导体开关器件S5和S6串联连接之后分别连接半导体开关器件S1和D2之间的 中间节点以及半导体开关器件D3和S4之间的中间节点。半导体开关器件S5和S6之间的中间节点连接NPC三电平桥臂830的对外输出端口O。其中，二极管D2的阳极连接参考输入端口M’，阴极连接半导体开关器件S1的发射极。二极管D3的阴极连接参考输入端口M’，阳极连接半导体开关器件S4的集电极。二极管D2的阳极和二极管D3的阴极连接。当半导体开关器件S1和S5导通时，对外输出端口O通过由半导体开关器件S1和S5组成的支路连接正极输入端口P’，而正极输出端口P与正极输入端口P’连接，因此对外输出端口O输出的电压是施加在正极输出端口P的第一电压。当半导体开关器件S4和S6导通时，对外输出端口O通过由半导体开关器件S4和S6组成的支路连接负极输入端口N’，而负极输出端口N与负极输入端口N’连接，因此对外输出端口O输出的电压是施加在负极输出端口N的第二电压。当半导体开关器件D2和S5导通时或者当半导体开关器件D3和S6导通时，对外输出端口O通过由半导体开关器件D2和S5组成的支路或者由半导体开关器件D3和S6组成的支路而连接参考输入端口M’，并且参考输出端口M通过故障保护装置810而间接地连接参考输入端口M’，因此对外输出端口O输出的电压是施加在参考输出端口M的第三电压。如此，通过控制NPC三电平桥臂830所包括的各个半导体开关器件的导通和关断，可以使得对外输出端口O输出的电压在施加在正极输出端口P的第一电压、施加在负极输出端口N的第二电压和施加在参考输出端口M的第三电压之间切换，实现三电平输出。
请继续参阅图8，当半导体开关器件D3和S4同时出现短路故障时，负极输入端口N’和参考输入端口M’之间相当于短路连接，而如果参考输出端口M与参考输入端口M’保持连接关系，则会导致电容C2被旁路化，这样正极输出端口P和负极输出端口N之间的电压就全部施加在电容C1上。当电容桥臂820采用对称性设计时，电容C1和C2分别承受的是正极输出端口P和负极输出端口N之间的电压的一半，所以当正极输出端口P和负极输出端口N之间的电压就全部施加在电容C1时，可能导致电容C1承受正常设计的两倍电压，从而引起过压损坏，甚至扩散进而损坏电路以及设备，极大的降低电路的可靠性。类似地，当半导体开关器件S1和D2同时出现短路故障时，正极输入端口P’和参考输入端口M’之间相当于短路连接，而如果参考输出端口M与参考输入端口M’保持连接关系，则会导致电容C1被旁路化，这样正极输出端口P和负极输出端口N之间的电压就全部施加在电容C2上，从而引起过压损坏。为此，需要通过控制断路开关SP的闭合和断开从而调整参考输出端口M与参考输入端口M’之间的连接关系。具体地，可以通过监测以下情况之一从而判断是否出现半导体开关器件的短路故障：监测负极输入端口N’和参考输入端口M’之间的电压，当该电压低于一定阈值时判断半导体开关器件D3和S4同时出现短路故障；监测正极输入端口P’和参考输入端口M’之间的电压，当该电压低于一定阈值时判断半导体开关器件S1和D2同时出现短路故障；监测负极输入端口N’和参考输入端口M’之间的电压下降速率，当该电压下降速率高于一定阈值时判断半导体开关器件D3和S4同时出现短路故障；监测正极输入端口P’和参考输入端口M’之间的电压下降速率，当该电压下降速率高于一定阈值时判断半导体开关器件S1和D2同时出现短路故障；监测从正极输入端口P’流向负极输入端口N’并且经过半导体开关器件S1、D2、D3或者S4的电流，当该电流高于一定阈值时判断对应的半导体开关器件S1、D2、D3或者S4出现短路故障；监测当半导体开关器件S1或者S4闭合时各自的集电极和发射极之间的电压，当该电压高于一定阈值时判断对应的半导体开关器件S1或者S4出现短路故障。如此，通过监测上述情况例如监测特定半导体开关器件的电流电压，可以判断NPC三电平桥臂830是否出现了短路故障，并及时通过控制断路开关 SP的闭合和断开从而调整参考输出端口M与参考输入端口M’之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。另外，还可以监测流经断路开关SP的电流，当该电流大于一定阈值时，判断NPC三电平桥臂830出现了短路故障。
请继续参阅图8，NPC三电平电路800可以包括多个NPC三电平桥臂830，其中每一个NPC三电平桥臂830具有图8所示的结构，并且各自具有有三个输入端口。多个NPC三电平桥臂830各自的输入端口并联连接于对应的图8所示的正极输入端口P’、负极输入端口N’和参考输入端口M’，从而使得多个NPC三电平桥臂830构成并联关系。当多个NPC三电平桥臂830均正常工作时，故障保护装置810的断路开关SP闭合；当多个NPC三电平桥臂830中任意一个出现短路故障时，则故障保护装置810的断路开关SP断开，从而避免半母线电容过压损坏和提高电路的可靠性。其中，判断多个NPC三电平桥臂830中任意一个发生短路故障可以通过监测所有NPC三电平桥臂830是否出现上述情况之一来实现。
应当理解的是，故障保护装置810所包括的控制器811与断路开关SP通信地连接并配置成用于控制断路开关SP的闭合和断开。控制器811可以带有对应的电路和部件从而监测上述短路故障的情况，也可以通过接口电路从外部接收指令。在一些示例性实施例中，控制器811可以与故障保护装置810分开提供，也就是作为一个单独的器件。除了上述提及的多种情况之外，还可以通过其它技术手段来判断半导体开关器件是否发生了短路故障。这些可以依据具体应用环境进行调整和改进，此处不做具体限定。
应当理解的是，图8所示的NPC三电平桥臂830所包括的多个半导体开关器件以IGBT为例子，图8中示意性示出了这些半导体开关器件的各自的集电极和发射极。当这些半导体开关器件采用其它类型例如MOSFET时，则对应的将上述的集电极和发射极替换成漏极和源极。因此图8所示的集电极和发射极应理解成示意性表述这些半导体开关器件各自的第一传输电极和第二传输电极。
请参阅图9，图9示出了本申请实施例提供的带有故障保护装置的T型三电平电路的原理框图。如图9所示，T型三电平电路900包括故障保护装置910、电容桥臂920和T型三电平桥臂930。其中，故障保护装置910包括断路开关SP，图9所示的断路开关SP可以对应图2至图5中任一实施例所示的断路开关SP或者这些实施例的任意可能组合或者变体。电容桥臂920有三个输出端口，分别是正极输出端口P、负极输出端口N和参考输出端口M。相对的，T型三电平桥臂930有三个输入端口，分别是正极输入端口P’、负极输入端口N’和参考输入端口M’。其中，T型三电平桥臂930还有对外输出端口O，用于向下一级负载或者外网提供输出的电平电压。其中，正极输出端口P与正极输入端口P’连接，负极输出端口N与负极输入端口N’连接，故障保护装置910的一端与参考输出端口M连接，另一端与参考输入端口M’连接。如此，电容桥臂920的各个输出端口和T型三电平桥臂930的各个输入端口之间存在一一对应的连接关系，并且参考输出端口M通过故障保护装置910而间接地连接参考输入端口M’。应当理解的是，本申请实施例中提到的正极和负极只是相对的概念，是为了便于描述而指定一个端口为正极另一个端口为负极，不应理解成限制性。
请继续参阅图9，电容桥臂920包括两个电容C1和C2。电容C1和C2串联连接在正极输出端口P和负极输出端口N之间，电容C1和C2之间的中间节点连接参考输出端口M。T型三电平桥臂930包括共计四个半导体开关器件，分别标记为S1、S2、S3和S4。应当理解的是，T型三电平桥臂930所包括的半导体开关器件S1、S2、S3和S4中的每一个半导体开关器件是成对的IGBT和与该IGBT成反并联关系连接的二极管。在一些示例性实施例中， 这些半导体开关器件也可以采用其它具有类似功能的半导体器件来实现，例如MOSFET、GTR、GTO或者其它合适的器件，并且相应地配置成对的二极管。在一些示例性实施例中，这些半导体器件还可以采用HEMT，也称作MODFET，或者2-DEGFET，或者SDHT。这些可以依据具体应用环境进行调整和改进，此处不做具体限定。
请继续参阅图9，半导体开关器件S1和S2串联连接在正极输入端口P’和负极输入端口N’之间，半导体开关器件S1和S2之间的中间节点连接对外输出端口O。半导体开关器件S3和S4串联连接在参考输入端口M’和对外输出端口O之间。其中，半导体开关器件S3和S4采用对项串联的方式连接在参考输入端口M’和对外输出端口O之间。也就是说，S3的发射极和S4的发射极互相连接，S3的集电极连接参考输入端口M’，S4的集电极连接对外输出端口O。在另一种实施方式中，S3和S4的位置也可以互换，只要保持各自的发射极互相连接，其中一个的集电极连接参考输入端口M’，而另一个的集电极连接对外输出端口O。当半导体开关器件S1导通时，对外输出端口O通过由半导体开关器件S1组成的支路连接正极输入端口P’，而正极输出端口P与正极输入端口P’连接，因此对外输出端口O输出的电压是施加在正极输出端口P的第一电压。当半导体开关器件S2导通时，对外输出端口O通过由半导体开关器件S2组成的支路连接负极输入端口N’，而负极输出端口N与负极输入端口N’连接，因此对外输出端口O输出的电压是施加在负极输出端口N的第二电压。当半导体开关器件S3和S4导通时，对外输出端口O通过由半导体开关器件S3和S4组成的支路而连接参考输入端口M’，并且参考输出端口M通过故障保护装置910而间接地连接参考输入端口M’，因此对外输出端口O输出的电压是施加在参考输出端口M的第三电压。如此，通过控制T型三电平桥臂930所包括的各个半导体开关器件的导通和关断，可以使得对外输出端口O输出的电压在施加在正极输出端口P的第一电压、施加在负极输出端口N的第二电压和施加在参考输出端口M的第三电压之间切换，实现三电平输出。
请继续参阅图9，当半导体开关器件S2、S3和S4同时出现短路故障时，负极输入端口N’和参考输入端口M’之间相当于短路连接，而如果参考输出端口M与参考输入端口M’保持连接关系，则会导致电容C2被旁路化，这样正极输出端口P和负极输出端口N之间的电压就全部施加在电容C1上。当电容桥臂920采用对称性设计时，电容C1和C2分别承受的是正极输出端口P和负极输出端口N之间的电压的一半，所以当正极输出端口P和负极输出端口N之间的电压就全部施加在电容C1时，可能导致电容C1承受正常设计的两倍电压，从而引起过压损坏，甚至扩散进而损坏电路以及设备，极大的降低电路的可靠性。类似地，当半导体开关器件S1、S3和S4同时出现短路故障时，正极输入端口P’和参考输入端口M’之间相当于短路连接，而如果参考输出端口M与参考输入端口M’保持连接关系，则会导致电容C1被旁路化，这样正极输出端口P和负极输出端口N之间的电压就全部施加在电容C2上，从而引起过压损坏。为此，需要通过控制断路开关SP的闭合和断开从而调整参考输出端口M与参考输入端口M’之间的连接关系。具体地，可以通过监测以下情况之一从而判断是否出现半导体开关器件的短路故障：监测负极输入端口N’和参考输入端口M’之间的电压，当该电压低于一定阈值时判断半导体开关器件S2、S3和S4同时出现短路故障；监测正极输入端口P’和参考输入端口M’之间的电压，当该电压低于一定阈值时判断半导体开关器件S1、S3和S4同时出现短路故障；监测负极输入端口N’和参考输入端口M’之间的电压下降速率，当该电压下降速率高于一定阈值时判断半导体开关器件S2、S3和S4同时出现短路故障；监测正极输入端口P’和参考输入端口M’之间的电压下降速率，当该电压下降速率 高于一定阈值时判断半导体开关器件S1、S3和S4同时出现短路故障；监测从正极输入端口P’流向负极输入端口N’并且经过半导体开关器件S1或者S2的电流，当该电流高于一定阈值时判断对应的半导体开关器件S1或者S2出现短路故障；监测当半导体开关器件S1、S2、S3或者S4闭合时各自的集电极和发射极之间的电压，当该电压高于一定阈值时判断对应的半导体开关器件S1、S2、S3或者S4出现短路故障。如此，通过监测上述情况例如监测特定半导体开关器件的电流电压，可以判断T型三电平桥臂930是否出现了短路故障，并及时通过控制断路开关SP的闭合和断开从而调整参考输出端口M与参考输入端口M’之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。另外，还可以监测流经断路开关SP的电流，当该电流大于一定阈值时，判断T型三电平桥臂930出现了短路故障。
请继续参阅图9，T型三电平桥臂930可以包括多个T型三电平桥臂930，其中每一个T型三电平桥臂930具有图9所示的结构，并且各自具有有三个输入端口。多个T型三电平桥臂930各自的输入端口并联连接于对应的图9所示的正极输入端口P’、负极输入端口N’和参考输入端口M’，从而使得多个T型三电平桥臂930构成并联关系。当多个T型三电平桥臂930均正常工作时，故障保护装置910的断路开关SP闭合；当多个T型三电平桥臂930中任意一个出现短路故障时，则故障保护装置910的断路开关SP断开，从而避免半母线电容过压损坏和提高电路的可靠性。其中，判断多个T型三电平桥臂930中任意一个发生短路故障可以通过监测所有T型三电平桥臂930是否出现上述情况之一来实现。
应当理解的是，故障保护装置910所包括的控制器911与断路开关SP通信地连接并配置成用于控制断路开关SP的闭合和断开。控制器911可以带有对应的电路和部件从而监测上述短路故障的情况，也可以通过接口电路从外部接收指令。在一些示例性实施例中，控制器911可以与故障保护装置910分开提供，也就是作为一个单独的器件。除了上述提及的多种情况之外，还可以通过其它技术手段来判断半导体开关器件是否发生了短路故障。这些可以依据具体应用环境进行调整和改进，此处不做具体限定。
应当理解的是，图9所示的T型三电平桥臂930所包括的多个半导体开关器件以IGBT为例子，图9中示意性示出了这些半导体开关器件的各自的集电极和发射极。当这些半导体开关器件采用其它类型例如MOSFET时，则对应的将上述的集电极和发射极替换成漏极和源极。因此图9所示的集电极和发射极应理解成示意性表述这些半导体开关器件各自的第一传输电极和第二传输电极。
请参阅图10，图10示出了本申请实施例提供的带有故障保护装置的五电平电路的原理框图。如图10所示，五电平电路1000包括故障保护装置1010、电容桥臂1020和五电平桥臂1030。其中，故障保护装置1010包括断路开关SP，图10所示的断路开关SP可以对应图2至图5中任一实施例所示的断路开关SP或者这些实施例的任意可能组合或者变体。电容桥臂1020有三个输出端口，分别是正极输出端口P、负极输出端口N和参考输出端口M。相对的，五电平桥臂1030有三个输入端口，分别是正极输入端口P’、负极输入端口N’和参考输入端口M’。其中，五电平桥臂1030还有对外输出端口O，用于向下一级负载或者外网提供输出的电平电压。其中，正极输出端口P与正极输入端口P’连接，负极输出端口N与负极输入端口N’连接，故障保护装置1010的一端与参考输出端口M连接，另一端与参考输入端口M’连接。如此，电容桥臂1020的各个输出端口和五电平桥臂1030的各个输入端口之间存在一一对应的连接关系，并且参考输出端口M通过故障保护装置1010而间接地连接参考输入端口M’。应当理解的是，本申请实施例中提到的正极和负极只是相对的概念，是为了便于 描述而指定一个端口为正极另一个端口为负极，不应理解成限制性。
请继续参阅图10，电容桥臂1020包括两个电容C1和C2。电容C1和C2串联连接在正极输出端口P和负极输出端口N之间，电容C1和C2之间的中间节点连接参考输出端口M。五电平桥臂1030包括共计八个半导体开关器件，分别标记为S1、S2、S3、S4、S5、S6、S7和S8。应当理解的是，五电平桥臂1030所包括的半导体开关器件S1、S2、S3、S4、S5、S6、S7和S8中的每一个半导体开关器件是成对的IGBT和与该IGBT成反并联关系连接的二极管。在一些示例性实施例中，这些半导体开关器件也可以采用其它具有类似功能的半导体器件来实现，例如MOSFET、GTR、GTO或者其它合适的器件，并且相应地配置成对的二极管。在一些示例性实施例中，这些半导体器件还可以采用HEMT，也称作MODFET，或者2-DEGFET，或者SDHT。这些可以依据具体应用环境进行调整和改进，此处不做具体限定。
请继续参阅图10，半导体开关器件S1和S2串联连接在正极输入端口P’和参考输入端口M’之间，半导体开关器件S3和S4串联连接在参考输入端口M’和负极输入端口N’之间。半导体开关器件S2和S3连接，并且半导体开关器件S2和S3之间的中间节点连接参考输入端口M’。半导体开关器件S5和S7串联连接之后分别连接半导体开关器件S1和S2之间的中间节点以及五电平桥臂1030的外输出端口O。半导体开关器件S6和S8串联连接之后分别连接半导体开关器件S3和S4之间的中间节点以及五电平桥臂1030的外输出端口O。半导体开关器件S7和S9连接，并且半导体开关器件S7和S8之间的中间节点连接五电平桥臂1030的外输出端口O。半导体开关器件S1、S2、S3和S4串联连接在正极输入端口P’和负极输入端口N’之间。半导体开关器件S5、S7、S8和S6串联连接在半导体开关器件S1和S2之间的中间节点以及半导体开关器件S3和S4之间的中间节点之间。五电平桥臂1030还包括两个电容Ca和Cb。其中，电容Ca一端连接半导体开关器件S2和S5之间的中间节点，另一端连接半导体开关器件S3和S6之间的中间节点。电容Cb一端连接半导体开关器件S5和S7之间的中间节点，另一端连接半导体开关器件S6和S8之间的中间节点。当半导体开关器件S1、S5和S7导通时，对外输出端口O通过由半导体开关器件S1、S5和S7组成的支路连接正极输入端口P’，而正极输出端口P与正极输入端口P’连接，因此对外输出端口O输出的电压是施加在正极输出端口P的第一电压。当半导体开关器件S4、S6和S8导通时，对外输出端口O通过由半导体开关器件S4、S6和S8组成的支路连接负极输入端口N’，而负极输出端口N与负极输入端口N’连接，因此对外输出端口O输出的电压是施加在负极输出端口N的第二电压。当半导体开关器件S2、S5和S7导通时或者当半导体开关器件S3、S6和S8导通时，对外输出端口O通过由半导体开关器件S2、S5和S7组成的支路或者由半导体开关器件S3、S6和S8组成的支路而连接参考输入端口M’，并且参考输出端口M通过故障保护装置1010而间接地连接参考输入端口M’，因此对外输出端口O输出的电压是施加在参考输出端口M的第三电压。如此，通过控制五电平桥臂1030所包括的各个半导体开关器件的导通和关断，可以使得对外输出端口O输出的电压在施加在正极输出端口P的第一电压、施加在负极输出端口N的第二电压和施加在参考输出端口M的第三电压之间切换，实现三电平输出。另外，通过结合电容Ca和Cb可以组成分压支路或者结合控制信号设计，从而进一步提供第四电平和第五电平的输出，这些可以基于常规技术得到，在此不再赘述。
请继续参阅图10，当半导体开关器件S3和S4同时出现短路故障时，负极输入端口N’和参考输入端口M’之间相当于短路连接，而如果参考输出端口M与参考输入端口M’保持连接关系，则会导致电容C2被旁路化，这样正极输出端口P和负极输出端口N之间的电 压就全部施加在电容C1上。当电容桥臂1020采用对称性设计时，电容C1和C2分别承受的是正极输出端口P和负极输出端口N之间的电压的一半，所以当正极输出端口P和负极输出端口N之间的电压就全部施加在电容C1时，可能导致电容C1承受正常设计的两倍电压，从而引起过压损坏，甚至扩散进而损坏电路以及设备，极大的降低电路的可靠性。类似地，当半导体开关器件S1和S2同时出现短路故障时，正极输入端口P’和参考输入端口M’之间相当于短路连接，而如果参考输出端口M与参考输入端口M’保持连接关系，则会导致电容C1被旁路化，这样正极输出端口P和负极输出端口N之间的电压就全部施加在电容C2上，从而引起过压损坏。为此，需要通过控制断路开关SP的闭合和断开从而调整参考输出端口M与参考输入端口M’之间的连接关系。具体地，可以通过监测以下情况之一从而判断是否出现半导体开关器件的短路故障：监测负极输入端口N’和参考输入端口M’之间的电压，当该电压低于一定阈值时判断半导体开关器件S3和S4同时出现短路故障；监测正极输入端口P’和参考输入端口M’之间的电压，当该电压低于一定阈值时判断半导体开关器件S1和S2同时出现短路故障；监测负极输入端口N’和参考输入端口M’之间的电压下降速率，当该电压下降速率高于一定阈值时判断半导体开关器件S3和S4同时出现短路故障；监测正极输入端口P’和参考输入端口M’之间的电压下降速率，当该电压下降速率高于一定阈值时判断半导体开关器件S1和S2同时出现短路故障；监测从正极输入端口P’流向负极输入端口N’并且经过半导体开关器件S1、S2、S3或者S4的电流，当该电流高于一定阈值时判断对应的半导体开关器件S1、S2、S3或者S4出现短路故障；监测当半导体开关器件S1、S2、S3或者S4闭合时各自的集电极和发射极之间的电压，当该电压高于一定阈值时判断对应的半导体开关器件S1、S2、S3或者S4出现短路故障。如此，通过监测上述情况例如监测特定半导体开关器件的电流电压，可以判断五电平桥臂1030是否出现了短路故障，并及时通过控制断路开关SP的闭合和断开从而调整参考输出端口M与参考输入端口M’之间的连接关系，进而避免半母线电容过压损坏和提高电路的可靠性。另外，还可以监测流经断路开关SP的电流，当该电流大于一定阈值时，判断五电平桥臂1030出现了短路故障。
应当理解的是，故障保护装置1010所包括的控制器1011与断路开关SP通信地连接并配置成用于控制断路开关SP的闭合和断开。控制器1011可以带有对应的电路和部件从而监测上述短路故障的情况，也可以通过接口电路从外部接收指令。在一些示例性实施例中，控制器1011可以与故障保护装置1010分开提供，也就是作为一个单独的器件。除了上述提及的多种情况之外，还可以通过其它技术手段来判断半导体开关器件是否发生了短路故障。这些可以依据具体应用环境进行调整和改进，此处不做具体限定。
应当理解的是，图10所示的五电平电路1000所包括的多个半导体开关器件以IGBT为例子，图10中示意性示出了这些半导体开关器件的各自的集电极和发射极。当这些半导体开关器件采用其它类型例如MOSFET时，则对应的将上述的集电极和发射极替换成漏极和源极。因此图10所示的集电极和发射极应理解成示意性表述这些半导体开关器件各自的第一传输电极和第二传输电极。
本申请提供的具体实施例可以用硬件，软件，固件或固态逻辑电路中的任何一种或组合来实现，并且可以结合信号处理，控制和/或专用电路来实现。本申请具体实施例提供的设备或装置可以包括一个或多个处理器(例如，微处理器，控制器，数字信号处理器(DSP)，专用集成电路(ASIC)，现场可编程门阵列(FPGA)等)，这些处理器处理各种计算机可执行指令从而控制设备或装置的操作。本申请具体实施例提供的设备或装置可以包括将各个 组件耦合在一起的系统总线或数据传输系统。系统总线可以包括不同总线结构中的任何一种或不同总线结构的组合，例如存储器总线或存储器控制器，外围总线，通用串行总线和/或利用多种总线体系结构中的任何一种的处理器或本地总线。本申请具体实施例提供的设备或装置可以是单独提供，也可以是系统的一部分，也可以是其它设备或装置的一部分。
本申请提供的具体实施例可以包括计算机可读存储介质或与计算机可读存储介质相结合，例如能够提供非暂时性数据存储的一个或多个存储设备。计算机可读存储介质/存储设备可以被配置为保存数据，程序器和/或指令，这些数据，程序器和/或指令在由本申请具体实施例提供的设备或装置的处理器执行时使这些设备或装置实现有关操作。计算机可读存储介质/存储设备可以包括以下一个或多个特征：易失性，非易失性，动态，静态，可读/写，只读，随机访问，顺序访问，位置可寻址性，文件可寻址性和内容可寻址性。在一个或多个示例性实施例中，计算机可读存储介质/存储设备可以被集成到本申请具体实施例提供的设备或装置中或属于公共系统。计算机可读存储介质/存储设备可以包括光存储设备，半导体存储设备和/或磁存储设备等等，也可以包括随机存取存储器(RAM)，闪存，只读存储器(ROM)，可擦可编程只读存储器(EPROM)，电可擦可编程只读存储器(EEPROM)，寄存器，硬盘，可移动磁盘，可记录和/或可重写光盘(CD)，数字多功能光盘(DVD)，大容量存储介质设备或任何其他形式的合适存储介质。
以上是本申请实施例的实施方式，应当指出，本申请具体实施例描述的方法中的步骤可以根据实际需要进行顺序调整、合并和删减。在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详细描述的部分，可以参见其他实施例的相关描述。可以理解的是，本申请实施例以及附图所示的结构并不构成对有关装置或系统的具体限定。在本申请另一些实施例中，有关装置或系统可以包括比具体实施例和附图更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者具有不同的部件布置。本领域技术人员将理解，在不脱离本申请具体实施例的精神和范围的情况下，可以对具体实施例记载的方法和设备的布置，操作和细节进行各种修改或变化；在不脱离本申请实施例原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (25)

  1. 一种光伏发电系统，其特征在于，所述光伏发电系统包括：
    电容桥臂，其中，所述电容桥臂包括正极输出端口、负极输出端口和在所述正极输出端口和所述负极输出端口之间的参考输出端口；
    逆变桥臂，其中，所述逆变桥臂包括正极输入端口、负极输入端口和在所述正极输入端口和所述负极输入端口之间的参考输入端口，所述正极输入端口与所述正极输出端口连接，所述负极输入端口与所述负极输出端口连接；以及
    故障保护装置，其中，所述参考输入端口通过所述故障保护装置与所述参考输出端口连接，所述故障保护装置根据所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的电压的大小或变化情况或电流的大小或变化情况而关断。
  2. 根据权利要求1所述的光伏发电系统，其特征在于，所述故障保护装置根据所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的电压的大小或变化情况而关断，包括：
    当所述负极输入端口和所述参考输入端口之间的电压低于第一阈值时，所述故障保护装置断开；或
    当所述正极输入端口和所述参考输入端口之间的电压低于第二阈值时，所述故障保护装置断开；或
    当所述负极输入端口和所述参考输入端口之间的电压下降速率高于第三阈值时，所述故障保护装置断开；或
    当所述正极输入端口和所述参考输入端口之间的电压下降速率高于第四阈值时，所述故障保护装置断开。
  3. 根据权利要求1所述的光伏发电系统，其特征在于，所述故障保护装置还根据流经所述故障保护装置的电流而关断。
  4. 根据权利要求1所述的光伏发电系统，其特征在于，所述逆变桥臂还包括连接在所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的至少一个开关器件，所述故障保护装置还根据流经所述至少一个开关器件的电流或者施加在所述至少一个开关器件的第一传输电极和第二传输电极之间的电压而关断。
  5. 根据权利要求1至4中任一项所述的光伏发电系统，其特征在于，所述故障保护装置包括主断路器，其中，所述主断路器包括第一开关晶体管和第二开关晶体管，所述第一开关晶体管和所述第二开关晶体管按照对项串联的方式连接在所述参考输出端口和所述参考输入端口之间，所述故障保护装置通过控制所述第一开关晶体管和所述第二开关晶体管的导通和关断来闭合和断开。
  6. 根据权利要求5所述的光伏发电系统，其特征在于，所述第一开关晶体管和所述第二开关晶体管是MOSFET、IGBT、GTR、GTO、HEMT、MODFET、2-DEGFET或者SDHT。
  7. 根据权利要求5所述的光伏发电系统，其特征在于，所述故障保护装置还包括：
    高阻抗器件，其中，所述高阻抗器件和所述主断路器并联连接在所述参考输出端口和所述参考输入端口之间。
  8. 根据权利要求7所述的光伏发电系统，其特征在于，所述高阻抗器件是热敏电阻。
  9. 根据权利要求5所述的光伏发电系统，其特征在于，所述故障保护装置还包括：
    压敏电阻，其中，所述压敏电阻和所述主断路器并联连接在所述参考输出端口和所述参考输入端口之间。
  10. 根据权利要求9所述的光伏发电系统，其特征在于，所述故障保护装置还包括：
    高速机械开关，其中，所述高速机械开关、所述压敏电阻和所述主断路器一起并联连接在所述参考输出端口和所述参考输入端口之间，所述高速机械开关在所述主断路器的所述第一开关晶体管和所述第二开关晶体管导通之后闭合，所述高速机械开关在所述主断路器的所述第一开关晶体管和所述第二开关晶体管关断之前断开。
  11. 根据权利要求9所述的光伏发电系统，其特征在于，所述故障保护装置还包括：
    高速机械开关，和
    辅助断路器，其中，所述辅助断路器包括第三开关晶体管和第四开关晶体管，所述第三开关晶体管和所述第四开关晶体管按照对项串联的方式连接之后与所述高速机械开关串联连接在所述参考输出端口和所述参考输入端口之间，
    所述高速机械开关和所述辅助断路器串联连接之后与所述压敏电阻和所述主断路器一起并联连接在所述参考输出端口和所述参考输入端口之间，
    所述辅助断路器的所述第三开关晶体管和所述第四开关晶体管以及所述高速机械开关在所述主断路器的所述第一开关晶体管和所述第二开关晶体管导通之后闭合，所述高速机械开关在所述主断路器的所述第一开关晶体管和所述第二开关晶体管关断之前断开，所述辅助断路器的所述第三开关晶体管和所述第四开关晶体管在所述高速机械开关断开之前关断。
  12. 根据权利要求11所述的光伏发电系统，其特征在于，所述第三开关晶体管和所述第四开关晶体管是MOSFET、IGBT、GTR、GTO、HEMT、MODFET、2-DEGFET或者SDHT。
  13. 根据权利要求1至3中任一项所述的光伏发电系统，其特征在于，所述逆变桥臂包括ANPC三电平桥臂，所述ANPC三电平桥臂包括串联连接在所述正极输入端口和所述参考输入端口之间以及串联连接在所述负极输入端口和所述参考输入端口之间的多个半导体开关器件，所述故障保护装置还根据流经所述多个半导体开关器件的电流或者施加在所述多个半导体开关器件的第一传输电极和第二传输电极之间的电压而关断。
  14. 根据权利要求13所述的光伏发电系统，其特征在于，所述多个半导体开关器件是IGBT、MOSFET、GTR、GTO、HEMT、MODFET、2-DEGFET或者SDHT。
  15. 根据权利要求1至3中任一项所述的光伏发电系统，其特征在于，所述逆变桥臂包括NPC三电平桥臂，所述NPC三电平桥臂包括串联连接在所述正极输入端口和所述参考输入端口之间以及串联连接在所述负极输入端口和所述参考输入端口之间的多个半导体开关器件，所述故障保护装置还根据流经所述多个半导体开关器件的电流或者施加在所述多个半导体开关器件的第一传输电极和第二传输电极之间的电压而关断。
  16. 根据权利要求15所述的光伏发电系统，其特征在于，所述多个半导体开关器件是IGBT、MOSFET、GTR、GTO、HEMT、MODFET、2-DEGFET或者SDHT。
  17. 根据权利要求1至3中任一项所述的光伏发电系统，其特征在于，所述逆变桥臂包括T型三电平桥臂，所述T型三电平桥臂包括串联连接在所述正极输入端口和所述负极输入端口之间的多个半导体开关器件，所述故障保护装置还根据流经所述多个半导体开关器件的电流或者施加在所述多个半导体开关器件的第一传输电极和第二传输电极之间的电压而关断。
  18. 根据权利要求17所述的光伏发电系统，其特征在于，所述多个半导体开关器件是IGBT、MOSFET、GTR、GTO、HEMT、MODFET、2-DEGFET或者SDHT。
  19. 根据权利要求1至3中任一项所述的光伏发电系统，其特征在于，所述逆变桥臂包括五电平桥臂，所述五电平桥臂包括串联连接在所述正极输入端口和所述参考输入端口之间以及串联连接在所述负极输入端口和所述参考输入端口之间的多个半导体开关器件，所述故障保护装置还根据流经所述多个半导体开关器件的电流或者施加在所述多个半导体开关器件的第一传输电极和第二传输电极之间的电压而关断。
  20. 根据权利要求1至3中任一项所述的光伏发电系统，其特征在于，所述故障保护装置是机械开关。
  21. 一种故障保护装置的控制方法，应用于光伏发电系统，其特征在于，所述光伏发电系统包括电容桥臂、逆变桥臂和所述故障保护装置，其中，所述电容桥臂包括正极输出端口、负极输出端口和在所述正极输出端口和所述负极输出端口之间的参考输出端口，所述逆变桥臂包括正极输入端口、负极输入端口和在所述正极输入端口和所述负极输入端口之间的参考输入端口，所述正极输入端口与所述正极输出端口连接，所述负极输入端口与所述负极输出端口连接，所述参考输入端口通过所述故障保护装置与所述参考输出端口连接，所述方法包括：
    根据所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的电压的大小或变化情况或电流的大小或变化情况而控制所述故障保护装置关断。
  22. 根据权利要求21所述的方法，其特征在于，根据所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的电压的大小或变化情况而控制所述故障保护装置关断，包括：
    当所述负极输入端口和所述参考输入端口之间的电压低于第一阈值时，所述故障保护装置断开；或
    当所述正极输入端口和所述参考输入端口之间的电压低于第二阈值时，所述故障保护装置断开；或
    当所述负极输入端口和所述参考输入端口之间的电压下降速率高于第三阈值时，所述故障保护装置断开；或
    当所述正极输入端口和所述参考输入端口之间的电压下降速率高于第四阈值时，所述故障保护装置断开。
  23. 根据权利要求21所述的方法，其特征在于，所述方法还包括：
    根据流经所述故障保护装置的电流而控制所述故障保护装置关断。
  24. 根据权利要求21所述的方法，其特征在于，所述逆变桥臂还包括连接在所述正极输入端口或者所述负极输入端口和所述参考输入端口之间的至少一个半导体开关器件，所述方法还包括：
    根据流经所述至少一个半导体开关器件的电流或者施加在所述至少一个半导体开关器件的第一传输电极和第二传输电极之间的电压而控制所述故障保护装置关断。
  25. 根据权利要求21至24中任一项所述的方法，其特征在于，所述故障保护装置包括主断路器，其中，所述主断路器包括第一开关晶体管和第二开关晶体管，所述第一开关晶体管和所述第二开关晶体管按照对项串联的方式连接在所述参考输出端口和所述参考输入端口之间，所述方法还包括：
    通过控制所述第一开关晶体管和所述第二开关晶体管的导通和关断来控制所述故障保护装置闭合和断开。
PCT/CN2021/141683 2021-01-19 2021-12-27 故障保护装置及光伏发电系统 WO2022156488A1 (zh)

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