WO2022156127A1 - 裸片裂纹损伤检测电路、裂纹检测方法以及存储器 - Google Patents

裸片裂纹损伤检测电路、裂纹检测方法以及存储器 Download PDF

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Publication number
WO2022156127A1
WO2022156127A1 PCT/CN2021/100011 CN2021100011W WO2022156127A1 WO 2022156127 A1 WO2022156127 A1 WO 2022156127A1 CN 2021100011 W CN2021100011 W CN 2021100011W WO 2022156127 A1 WO2022156127 A1 WO 2022156127A1
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Prior art keywords
crack
bare chip
output
loop
detection
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PCT/CN2021/100011
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English (en)
French (fr)
Inventor
曹玲玲
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长鑫存储技术有限公司
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Priority to US17/458,970 priority Critical patent/US11804412B2/en
Publication of WO2022156127A1 publication Critical patent/WO2022156127A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a bare chip crack damage detection circuit, a crack detection method, and a memory.
  • Semiconductor integrated chips are first produced on a circular silicon wafer with dozens or even hundreds of integrated circuit units at the same time, and then the silicon wafer is cut, and the integrated circuit units are cut to form bare chips, which are then tested, selected, and packaged. , become the chips we see.
  • the present application provides a chip crack damage detection circuit, a crack detection method, and a memory, so as to solve the technical problem of quickly identifying the bare chip damaged by the crack during the detection and selection of the bare chip.
  • the present application provides a circuit for detecting chip crack damage, including:
  • test circuit located in the protection ring of the bare chip, for outputting a pulse detection signal
  • a crack detection loop arranged around the protection ring of the bare chip, the input end of which is connected to the output end of the test circuit, and the output end of which is connected to the output pin of the bare chip;
  • a relay driving unit arranged between the input end and the output end of the crack detection loop, for enhancing the transmission capability of the pulse detection signal
  • the protection ring surrounds the entire die for protecting the die
  • test circuit When the test circuit enters the test mode, it outputs the pulse detection signal to the crack detection loop, and the test machine judges whether the bare chip is cracked by reading the signal on the output pin of the bare chip damaged.
  • the crack detection loop is located on the top metal layer of the substrate where the die to be tested is located.
  • the relay drive unit includes:
  • the buffer circuit is used for enhancing the pulse detection signal and driving the pulse detection signal to transmit to the output end of the crack detection loop.
  • the relay drive unit further includes:
  • a controllable pull-down resistor the first end of the controllable pull-down resistor is connected to the input end of the buffer circuit, and the second end of the controllable pull-down resistor is grounded.
  • the buffer circuit includes an inverter, and the controllable pull-down resistor is used to prevent the input terminal of the inverter from floating.
  • the number of the inverters is at least two.
  • controllable pull-down resistor includes:
  • the MOS resistor is a MOS tube in an on state
  • a switching element the switching element is connected between the source S and the drain D of the MOS transistor, and the switching element is used to control whether the MOS resistor is short-circuited, so as to change the resistance of the controllable pull-down resistor .
  • the shape of the projection of the crack detection loop and the guard ring on the base substrate of the die is the same.
  • the corner of the crack detection loop is a right angle, and the corner of the protection ring is chamfered.
  • the present application provides a circuit for detecting chip crack damage, including:
  • test circuit located in the boundary loop of the internal processing circuit of the bare chip, for outputting a pulse detection signal
  • a crack detection loop is arranged around the guard ring of the bare chip and the inner boundary loop, its input end is connected to the output end of the test circuit, and its output end is connected to the output pin of the bare chip ;
  • a relay driving unit arranged between the input end and the output end of the crack detection loop, for enhancing the transmission capability of the pulse detection signal
  • the protection ring surrounds the entire die for protecting the die
  • test circuit When the test circuit enters the test mode, it outputs the pulse detection signal to the crack detection loop, and the test machine judges whether the bare chip is cracked by reading the signal on the output pin of the bare chip damaged.
  • the crack detection loop is located on the top metal layer of the substrate where the die to be tested is located.
  • the relay drive unit includes:
  • the buffer circuit is used for enhancing the pulse detection signal and driving the pulse detection signal to transmit to the output end of the crack detection loop.
  • the relay drive unit further includes:
  • a controllable pull-down resistor the first end of the controllable pull-down resistor is connected to the input end of the buffer circuit, and the second end of the controllable pull-down resistor is grounded.
  • the buffer circuit includes an inverter, and the controllable pull-down resistor is used to prevent the input terminal of the inverter from floating.
  • the number of the inverters is at least two.
  • controllable pull-down resistor includes:
  • the MOS resistor is a MOS tube in an on state
  • a switching element the switching element is connected between the source S and the drain D of the MOS transistor, and the switching element is used to control whether the MOS resistor is short-circuited, so as to change the resistance of the controllable pull-down resistor .
  • the shape of the projection of the crack detection loop and the guard ring on the base substrate of the die is the same.
  • the corner of the crack detection loop is a right angle
  • the corner of the protection ring is chamfered.
  • the present application provides a circuit for detecting chip crack damage, including:
  • test circuit located in the boundary loop of the internal processing circuit of the bare chip, for outputting the pulse detection signal through the first output terminal and/or the second output terminal;
  • the first crack detection loop is arranged around the guard ring of the bare chip, its input end is connected to the first output end of the test circuit, and its output end is connected to the first output pin of the bare chip;
  • the second crack detection loop is arranged around the guard ring of the die and the inner boundary loop, its input end is connected to the second output end of the test circuit, and its output end is connected to the die The second output pin is connected;
  • a first relay driving unit arranged between the input end and the output end of the first crack detection loop, for enhancing the transmission capability of the pulse detection signal
  • the second relay driving unit is arranged between the input end and the output end of the second crack detection loop, and is used for enhancing the transmission capability of the pulse detection signal;
  • the protection ring surrounds the entire die for protecting the die
  • test circuit When the test circuit enters the test mode, it outputs the pulse detection signal to the crack detection loop, and the test machine reads the first output pin of the bare chip or the second output tube of the bare chip The signal on the pin is used to judge whether the die is damaged by a crack.
  • the crack detection loop is located on the top metal layer of the substrate where the die to be tested is located.
  • the relay drive unit includes:
  • the buffer circuit is used for enhancing the pulse detection signal and driving the pulse detection signal to transmit to the output end of the crack detection loop.
  • the relay drive unit further includes:
  • a controllable pull-down resistor the first end of the controllable pull-down resistor is connected to the input end of the buffer circuit, and the second end of the controllable pull-down resistor is grounded.
  • the buffer circuit includes an inverter, and the controllable pull-down resistor is used to prevent the input terminal of the inverter from floating.
  • the number of the inverters is at least two.
  • controllable pull-down resistor includes:
  • the MOS resistor is a MOS tube in an on state
  • a switching element the switching element is connected between the source S and the drain D of the MOS transistor, and the switching element is used to control whether the MOS resistor is short-circuited, so as to change the resistance of the controllable pull-down resistor .
  • the shape of the projection of the crack detection loop and the guard ring on the base substrate of the die is the same.
  • the corner of the crack detection loop is a right angle, and the corner of the protection ring is chamfered.
  • the first output terminal and the second output terminal of the test circuit are the same output terminal.
  • the present application provides a method for detecting cracks in a semiconductor die, including:
  • Whether the bare chip to be tested has crack damage is determined according to the signal output characteristics of the output pins of the bare chip to be tested and the pulse detection signal, and the bare chip to be tested includes the chip crack damage detection circuit.
  • determining whether the bare chip to be tested has crack damage according to the signal output characteristics of the output pins of the bare chip to be tested and the pulse detection signal includes:
  • the bare chip to be tested has no crack damage; otherwise, the bare chip to be tested has crack damage.
  • the preset corresponding condition includes: the output pin has an output signal.
  • the preset corresponding condition includes: the pulse detection signal is the same as the output signal of the output pin.
  • the present application provides a memory, comprising:
  • the memory chip includes any one of the possible bare chip crack damage detection circuits of the first to third aspects.
  • the memory chip further includes: data input/output pins, the data input/output pins are used to connect external devices;
  • the memory When the memory is connected to the testing machine through the data input/output pins, the memory enters a test mode, and the testing machine determines the Whether the memory chip is damaged by cracks.
  • the present application provides a bare chip crack damage detection circuit, a crack detection method and a memory.
  • the bare chip crack damage detection circuit includes a test circuit, a crack detection loop, and a relay drive unit.
  • the test circuit is located in the guard ring of the bare chip, and is used to output the pulse detection signal;
  • the crack detection loop is located in the guard ring, and/or outside the guard ring, and its input end is connected with the output end of the test circuit, and its output end It is connected with the output pin of the bare chip;
  • the relay drive unit is arranged between the input end and the output end of the crack detection loop to enhance the transmission capability of the pulse detection signal;
  • the guard ring surrounds the entire bare chip to protect the bare chip
  • the test circuit enters the test mode, it outputs a pulse detection signal to the crack detection loop, and the test machine judges whether the bare chip is damaged by the crack by reading the signal on the output pin of the bare chip.
  • the pulse detection signal in the crack detection loop located on the top metal layer is amplified and driven by the relay drive unit, which greatly improves the speed and sensitivity of crack detection.
  • the test machine can directly read the output pins of the bare chip to quickly obtain The testing result improves the testing convenience of the testing machine.
  • 1 is a schematic structural diagram of a first bare chip crack damage detection circuit provided by the application
  • FIG. 2 is a schematic structural diagram of a second type of bare chip crack damage detection circuit provided by the present application.
  • FIG. 3 is a schematic structural diagram of a third bare chip crack damage detection circuit provided by the present application.
  • FIG. 4 is a cross-sectional structural diagram of a crack detection loop provided by the application at different positions
  • FIG. 5 is a schematic structural diagram of a relay drive unit provided by the present application.
  • FIG. 6 is a schematic structural diagram of another relay driving unit provided by the present application.
  • FIG. 7 is a schematic flowchart of a crack detection method provided by the application.
  • the manufacture of semiconductor integrated chips is generally divided into five stages: silicon wafer preparation, integrated circuit manufacturing on silicon wafers, silicon wafer cutting, testing and selection, and final packaging.
  • Blade sawing is cutting silicon wafers at high speeds of 30,000 to 40,000 RPM using an abrasive wheel saw blade made of tiny diamond particles.
  • the table carrying the silicon wafer moves in a straight line at a certain speed along the tangential direction between the blade and the contact point of the silicon wafer.
  • the silicon chips, the bare die, produced by dicing the wafers are washed away with deionized water (purified water).
  • Blade sawing is characterized by slow cutting speeds, the thinner the chip, the more difficult it is to cut, and backside cracking tends to worsen, leaving the top metal layer of the die vulnerable to damage.
  • Laser cutting is to concentrate the laser energy in a small area, and sublime the solid silicon wafer at high temperature in a very short time, and volatilize it during the entire cutting process.
  • the characteristics of laser cutting are fast cutting speed, and it can effectively reduce the cracking phenomenon on the back of the wafer, that is, the silicon wafer; secondly, the width of the groove is small, and the loss of the groove is less than that of the blade sawing method, which can reduce the distance between each die.
  • the damage to each metal functional layer in the die by laser cutting is unpredictable.
  • a crack detection loop is constructed around the bare chip, and the crack detection loop is set on the top metal layer of the silicon wafer, because both blade sawing and laser cutting are carried out from top to bottom, and cracks are most likely to occur. the top layer.
  • the detection signal is input from the input end of the crack detection loop, and then try to receive it from the output end, when the crack intrusion damages the crack detection loop due to the stress action during cutting, the output end will not receive the signal, or the output end will not receive the signal.
  • the signal has changed and does not correspond to the preset standard output signal.
  • the inventor of the present application considers that the power of the general detection signal is relatively small, and the detection is performed in the form of voltage or current, which will cause errors in the detection results, and is easily affected by the electromagnetic field in the environment.
  • the sensitivity and speed of the detection are not high.
  • the use of pulse signals to replace voltage or current detection, and adding a relay drive unit to the crack detection loop can not only amplify the detection signal, but also improve the drive transmission capability of the detection signal in the crack detection loop.
  • the detection speed and efficiency are improved, and the anti-interference ability is improved, reducing false positives.
  • FIG. 1 is a schematic structural diagram of a first bare chip crack damage detection circuit provided by the present application. As shown in FIG. 1 , an enlarged display of any die 100 on the silicon wafer, the die 100 includes:
  • the cutting seam 101 is the track of the blade or laser cutting
  • the protection ring 102 is located outside the internal processing circuit 103 and surrounds the entire die 100 for protecting the die 100, such as absorbing minority carriers, preventing electromagnetic interference, preventing water vapor, moisture, etc.;
  • the internal processing circuit 103 is an integrated circuit that realizes the main functions of the entire chip, and its effective range is within the boundary loop 1031;
  • the bare chip crack damage detection circuit includes:
  • the test circuit 104 located in the boundary loop line 1031, is used for outputting the pulse detection signal
  • the crack detection loop 105 is arranged around the guard ring 102 of the die 100 and the boundary loop line 1031 . ;
  • the relay driving unit 106 is arranged between the input end 1051 and the output end 1052 of the crack detection loop 105, and is used for enhancing the transmission capability of the pulse detection signal;
  • test circuit 104 When the test circuit 104 enters the test mode, it outputs a pulse detection signal to the crack detection loop 105 , and the test machine judges whether the die 100 is damaged by the crack by reading the signal on the output pin 107 of the die 100 .
  • the number of relay driving units 106 is at least one, and when there are multiple relay driving units 106 , they may be evenly distributed on the crack detection loop 105 .
  • the relay driving unit 106 when there is only one relay driving unit 106 in the crack detection loop 105 , the relay driving unit 106 is located at the midpoint of the input end 1051 and the output end 1052 , that is, the connection between the relay driving unit 106 and the input end 1051 and the output end 1052 The distances are equal; when the crack detection loop 105 is a rectangle and there are four relay driving units 106 in the crack detection loop 105, each relay driving unit 106 is located at the midpoint of each side of the rectangle.
  • the crack detection loop 105 may also be provided outside the guard ring 102, as shown in FIG. 2 .
  • FIG. 2 is a schematic structural diagram of a second type of bare chip crack damage detection circuit provided by the present application. As shown in Figure 2, the bare chip crack damage detection circuit includes:
  • the test circuit 104 located in the guard ring 102, is used for outputting the pulse detection signal
  • the crack detection loop 105 is disposed around the guard ring 102, its input end 1051 is connected to the output end of the test circuit 104, and its output end 1052 is connected to the output pin 107 of the bare chip 100;
  • the relay driving unit 106 is arranged between the input end 1051 and the output end 1052 of the crack detection loop 105, and is used for enhancing the transmission capability of the pulse detection signal;
  • the protection ring 102 surrounds the entire die 100 and is used to protect the die 100, such as absorbing sand, preventing electromagnetic interference, preventing water vapor, moisture, and the like;
  • test circuit 104 When the test circuit 104 enters the test mode, it outputs a pulse detection signal to the crack detection loop 105 , and the test machine judges whether the die 100 is damaged by the crack by reading the signal on the output pin 107 of the die 100 .
  • the crack detection loop 105 can also be two loops, which are arranged inside and outside the guard ring 102 at the same time, as shown in FIG. 3 .
  • FIG. 3 is a schematic structural diagram of a third bare chip crack damage detection circuit provided by the present application. As shown in Figure 3, the bare chip crack damage detection circuit includes:
  • the test circuit 104 located in the boundary loop 1031 of the internal processing circuit 103 of the die 100, is used for outputting the pulse detection signal through the first output terminal and/or the second output terminal;
  • the first crack detection loop 115 is disposed around the guard ring 102, its input end 1151 is connected to the first output end of the test circuit 104, and its output end 1152 is connected to the first output pin 1071 of the die 100;
  • the second crack detection loop 125 is disposed around the guard ring 102 and the inner boundary loop line 1031 , the input terminal 1251 of which is connected to the second output terminal of the test circuit, and the output terminal 1252 is connected to the second output pin of the die 100 1072 connect;
  • the first relay driving unit 116 is arranged between the input end 1151 and the output end 1152 of the first crack detection loop 115, and is used for enhancing the transmission capability of the pulse detection signal;
  • the second relay driving unit 126 is disposed between the input end 1251 and the output end 1252 of the second crack detection loop 116, and is used for enhancing the transmission capability of the pulse detection signal;
  • the protection ring 102 surrounds the entire die 100 and is used to protect the die 100, such as absorbing sand, preventing electromagnetic interference, preventing water vapor, moisture, and the like;
  • test circuit 104 When the test circuit 104 enters the test mode, it outputs a pulse detection signal to the crack detection loop 115 and/or the crack detection loop 125 . Two outputs the signal on the pin 1072 to determine whether the die is damaged by cracks.
  • This embodiment provides a bare chip crack damage detection circuit, including: a test circuit, a crack detection loop, and a relay driving unit.
  • the test circuit is located in the guard ring of the bare chip, and is used to output the pulse detection signal
  • the crack detection loop is located in the guard ring, and/or outside the guard ring, and its input end is connected with the output end of the test circuit, and its output end It is connected with the output pin of the bare chip
  • the relay drive unit is arranged between the input end and the output end of the crack detection loop to enhance the transmission capability of the pulse detection signal
  • the guard ring surrounds the entire bare chip to protect the bare chip
  • the pulse detection signal in the crack detection loop located on the top metal layer is amplified and driven by the relay drive unit, which greatly improves the speed and sensitivity of crack detection.
  • the test machine can directly read the output pins of the bare chip to quickly obtain The testing result improves the testing convenience of the testing machine.
  • the signal output from the output end of the crack detection loop is first returned to the internal circuit of the bare chip, and after being converted by the internal circuit, it is output to the output pin of the bare chip, and then the tester Then, check the signal of the output pin.
  • the crack detection loop is disposed on the top metal layer of the silicon wafer substrate where the bare chip 100 is located.
  • FIG. 4 is a cross-sectional structural diagram of the crack detection loop provided by the present application at different positions.
  • the cross-section 401 is a cross-sectional view where the crack detection loop 105 is not connected to other circuits.
  • the base of the bare chip 100 can be regarded as composed of a plurality of metal layers including: the first metal layer 1001 (including The top metal layer 105, the insulating layer between the top metal layer and the sub-top metal layer), the second metal layer 1002 (referred to as the top metal layer as the first metal layer, and then as the second metal layer and the third layer metal layer, the fourth metal layer, the second metal layer 1002 here includes the second metal layer, the insulating layer between the second metal layer and the third metal layer), the third metal layer 1003 (here the first metal layer
  • the three metal layers 1003 include the third metal layer, the third metal layer and the insulating layer below it).
  • the inventor of the present application has found in long-term practice that the top metal layer is the most vulnerable to crack damage. When other metal layers have crack damage, generally the top metal layer will also have crack damage. Therefore, the detection circuit of the crack detection loop 105 Arranged in the top metal layer, crack damage can be effectively detected.
  • an arrangement space can be reserved for other circuits, for example, the second metal layer 1002 and the third metal layer 1003 in FIG. 4 can be arranged with other circuit elements or traces.
  • Section 402 is a schematic diagram of the connection between the relay driving unit 106 connected in series with the crack detection loop 105 and the detection circuit of the crack detection loop 105 .
  • the input end and the output end of the relay driving unit 106 are respectively connected to the crack detection loop 105, and the connection mode may be via holes passing through a plurality of metal layers.
  • relay driving unit 106 will be described in detail below.
  • the essence of the relay driving unit 106 is to amplify the pulse detection signal to increase the driving capability of the pulse detection signal, because generally the voltage of the pulse detection signal is only 0-1.2V, and the current is very small, which causes the pulse detection signal to be detected in cracks.
  • the driving capability in the loop 105 is relatively weak, which increases the detection time of the die 100 , and therefore needs to amplify the pulse detection signal to a certain extent, which is the role of the relay driving unit 106 .
  • the relay driving unit 106 includes: a buffer circuit, ie, a buffer, the buffer circuit is used to enhance the pulse detection signal and drive the pulse detection signal to transmit to the output end of the crack detection loop.
  • the load capacitance of the circuit is reduced by the buffer buffer. After the load capacitance is reduced, under the same voltage, the charging speed of the capacitor is fast (the rising edge is steep), the same capacitance is small, the stored capacitance is small, and the time required for discharging is short (the falling edge). steep).
  • the buffer buffer reduces the load capacitance of the circuit, thereby increasing the driving capability of the circuit.
  • the buffer circuit There are also many implementations of the buffer circuit, and those skilled in the art can choose one of the buffer amplifiers to implement the buffer circuit according to actual needs.
  • the buffer circuit includes an inverter, and the implementation of the inverter includes an integrated Schmitt trigger unit, or is directly formed by cascading NMOS and PMOS. Since the inverters will cause the phase of the signal to be opposite, the inverters are generally used in pairs to form a buffer buffer, that is, the buffer circuit has a circuit with 2n (n is an integer greater than or equal to 1) inverters. Of course, it can be understood that when the number of inverters is odd, it is only necessary to perform the corresponding phase supplement or correction calculation when processing the signal at the output end of the crack detection loop 105, which can also play a detection role.
  • the buffer circuit includes inverters, and the number of inverters is at least two.
  • the input end of the buffer circuit is also connected with a pull-down resistor.
  • the pull-down resistor can be set as a controllable pull-down resistor.
  • the controllable pull-down resistor The first end of the resistor is connected to the input end of the buffer, and the second end of the controllable pull-down resistor is grounded.
  • the realization form of the controllable pull-down resistor includes: using a switch tube to control whether the pure resistor is connected in series to the circuit to realize the change of the resistance value of the controllable resistor.
  • FIG. 5 is a schematic structural diagram of a relay driving unit provided by the present application.
  • the first end of the pull-down resistor 51 is connected to the buffer circuit, that is, the input end of the buffer 52 , and the second end of the pull-down resistor 51 is grounded.
  • the pull-down resistor 51 includes a plurality of resistors: resistor 511, resistor 512, resistor 513, resistor 514, and switch tubes connected in parallel with the resistors: switch tube S1, switch tube S2, switch tube S3, and switch tube S4.
  • the switch tube can be a triode, a MOS tube or other switching elements.
  • the resistor 511, the resistor 512, the resistor 513, and the resistor 514 can be pure resistors, or can be equivalent resistors obtained in other ways.
  • controllable pull-down resistor includes: a MOS resistor, where the MOS resistor is a MOS transistor in an on state; and
  • a switching element the switching element is connected between the source S and the drain D of the MOS transistor, and the switching element is used to control whether the MOS resistor is short-circuited, so as to change the resistance of the controllable pull-down resistor .
  • FIG. 6 is a schematic structural diagram of another relay driving unit provided by the present application.
  • the buffer circuit includes a first inverter and a second inverter, and the on-resistance when the MOS transistors Q1 to Q5 are turned on are used as the resistor 511 , the resistor 512 , the resistor 513 , the resistor 513 , the resistor 513 shown in FIG.
  • Another implementation of the resistor 514 is to replace the resistor 511, the resistor 512, the resistor 513, and the resistor 514 with a MOS tube.
  • the resistor 514 is formed by two series-connected MOS tubes, namely Q4 and Q5. That is to say, each resistance can be obtained by connecting multiple MOS transistors in series or in parallel.
  • the gate G of the MOS tube needs to be connected to the turn-on potential.
  • the NMOS tube needs to be connected to a high level, and the gate G of the PMOS tube is connected to a low level, so that the MOS tube forms a normal conduction. On state to get MOS resistance.
  • the crack detection loop shown in FIGS. 1 to 3 it surrounds the inner integrated circuit of the die, and the specific shape may be the same as that of the guard ring, forming a polygonal shape. That is, the projection shape of the crack detection loop and the guard ring on the base substrate of the die is the same.
  • the corner of the crack detection loop is a right angle
  • the corner of the protection ring is chamfered. degrees into two 135-degree angles).
  • the corner of the crack detection loop is set to a right angle, which can make damage more likely to occur at the right angle due to stress concentration when receiving stress, thereby improving the sensitivity of crack damage detection.
  • the protection ring is to reduce the stress, so a chamfered structure is provided.
  • the bare chip crack damage detection circuit shown in FIG. 3 it includes a first crack detection loop and a second crack detection loop, and the detection signals of the two crack detection loops can be the same signal.
  • the test circuit The first output terminal and the second output terminal can be the same output terminal, so the circuit structure can be simplified, and the control of the pulse detection signal and the detection calculation amount during reception can be simplified.
  • FIG. 7 is a schematic flowchart of a crack detection method provided by the application. As shown in Figure 7, the specific steps of the crack detection method include:
  • the user places the bare chip on the inspection platform through other machines, and the inspection platform sends a crack detection instruction to the bare chip, and then the test circuit of the bare chip crack damage detection circuit sends a pulse detection signal, and the pulse detection signal enters the into the crack detection loop, and then amplified by the relay drive unit and driven to the output end of the crack detection loop.
  • the bare chip to be tested includes any one of the possible bare chip crack damage detection circuits shown in FIGS. 1 to 3 .
  • the output pins of the bare chip to be tested are connected to the testing machine, and the testing machine can judge the crack damage by reading the signals of the output pins.
  • the bare chip to be tested has no crack damage; otherwise, the bare chip to be tested has crack damage.
  • the preset corresponding conditions there are several ways to implement the preset corresponding conditions. One is that as long as there is an output signal on the output pin, the signal is considered to be turned on, and the bare chip to be tested has no crack damage, or the bare chip to be tested is not damaged. The damage of the chip is not serious enough to affect the internal circuit, and it can still be used as a normal chip.
  • the pulse detection signal is the same as the output signal of the output pin. Specifically, since the pulse signal is a periodic signal, as long as the period of the pulse signal detected at the output pin is the same as the period of the input signal, it can be considered that the bare chip to be tested has no crack damage.
  • the pulse detection signal has a corresponding relationship with the pulse frequency of the output signal of the output pin. Since the pulse signal may be subjected to other interference factors when receiving, so that individual pulses cannot be detected. At this time, it is necessary to improve the fault tolerance rate and change the detection frequency of the received output signal, that is, the pulse frequency. For example, a pulse detection signal originally sent at a frequency of 100HZ is sampled at a frequency of 50HZ when it is received, which can reduce the misjudgment caused by interference of a single or several pulses.
  • the present application also provides a memory, the memory comprising: a memory chip for storing data;
  • the memory chip includes the bare chip crack damage detection circuit described in any one of the above embodiments.
  • the memory chip further includes data input/output pins, and the data input/output pins are used to connect external devices;
  • the memory When the memory is connected to the testing machine through the data input/output pins, the memory enters a test mode, and the testing machine determines the Whether the memory chip is damaged by cracks.

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Abstract

一种裸片裂纹损伤检测电路、裂纹检测方法以及存储器。该裸片裂纹损伤检测电路，包括：测试电路（104）、裂纹检测环路（105）、中继驱动单元（106）。其中，测试电路（104）位于裸片（100）的保护环（102）内，用于输出脉冲检测信号；裂纹检测环路（105）位于保护环（102）内，和/或保护环（102）外，其输入端（1051）与测试电路（104）的输出端连接，其输出端（1052）与裸片（100）的输出管脚连接；中继驱动单元（106），设置于裂纹检测环路（105）的输入端（1051）和输出端（1052）之间，用于增强脉冲检测信号的传输能力；保护环（102）环绕整个裸片（100），用于保护裸片（100）；测试电路（104）在进入测试模式时，向裂纹检测环路（105）输出脉冲检测信号，测试机台通过读取裸片（100）的输出管脚上的信号来判断裸片（100）是否被裂纹所损伤。通过中继驱动单元（106）使得裂缝检测的速度和灵敏度得到大幅提升。

Description

裸片裂纹损伤检测电路、裂纹检测方法以及存储器
本申请要求于2021年1月22日提交中国专利局、申请号为202110087721.0、申请名称为“裸片裂纹损伤检测电路、裂纹检测方法以及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种裸片裂纹损伤检测电路、裂纹检测方法以及存储器。
背景技术
半导体集成芯片是先在一张圆形硅片上同时制作几十甚至上百个集成电路单元，然后对硅片进行切割，将集成电路单元切割下来，形成裸片，然后经过测试、挑选、封装，成为我们看到的芯片。
目前硅片切割有刀片锯切和激光切割两种方式。但是无论哪一种方式在切割的时候，都无法避免地会使得硅片产生裂缝，当裂缝蔓延到裸片上，就有可能破坏内部的集成电路，导致裸片报废。
因此需要在裸片上增加裂缝检测电路来快速识别出受到裂缝损伤的裸片。
发明内容
本申请提供一种裸片裂纹损伤检测电路、裂纹检测方法以及存储器，以解决在裸片检测和挑选时，快速识别出受到裂缝损伤的裸片的技术问题。
第一个方面，本申请提供一种裸片裂纹损伤检测电路，包括：
测试电路，位于所述裸片的保护环内，用于输出脉冲检测信号；
裂纹检测环路，环绕设置于所述裸片的保护环外，其输入端与所述测试电路的输出端连接，其输出端与所述裸片的输出管脚连接；
中继驱动单元，设置于所述裂纹检测环路的输入端和输出端之间，用于增强所述脉冲检测信号的传输能力；
其中，所述保护环环绕整个所述裸片，用于保护所述裸片；
所述测试电路在进入测试模式时，向所述裂纹检测环路输出所述脉冲检测信号，测试机台通过读取所述裸片的输出管脚上的信号来判断所述裸片是否被裂纹所损伤。
在一种可能的设计中，所述裂纹检测环路位于所述待测裸片所在基体的顶层金属层上。
在一种可能的设计中，所述中继驱动单元包括：
缓冲电路，所述缓冲电路用于增强所述脉冲检测信号，并驱动所述脉冲检测信号向所述裂纹检测环路的输出端传输。
在一种可能的设计中，所述中继驱动单元还包括：
可控下拉电阻，所述可控下拉电阻的第一端与所述缓冲电路的输入端连接，所述可控下拉电阻的第二端接地。
在一种可能的设计中，所述缓冲电路包括反相器，所述可控下拉电阻用于防止所述反 相器的输入端悬空。
在一种可能的设计中，所述反相器的数量为至少两个。
可选的，所述可控下拉电阻包括：
MOS电阻，所述MOS电阻为导通状态下的MOS管；
开关元件，所述开关元件连接在所述MOS管的源极S和漏极D之间，所述开关元件用于控制所述MOS电阻是否短接，以改变所述可控下拉电阻的阻值。
可选的，所述裂纹检测环路与所述保护环在所述裸片的基体衬底上的投影形状相同。
在一种可能的设计中，所述裂纹检测环路的拐角为直角，所述保护环的拐角进行了倒角处理。
第二个方面，本申请提供一种裸片裂纹损伤检测电路，包括：
测试电路，位于所述裸片的内部处理电路的边界环线内，用于输出脉冲检测信号；
裂纹检测环路，环绕设置于所述裸片的保护环与所述内部边界环线之间，其输入端与所述测试电路的输出端连接，其输出端与所述裸片的输出管脚连接；
中继驱动单元，设置于所述裂纹检测环路的输入端和输出端之间，用于增强所述脉冲检测信号的传输能力；
其中，所述保护环环绕整个所述裸片，用于保护所述裸片；
所述测试电路在进入测试模式时，向所述裂纹检测环路输出所述脉冲检测信号，测试机台通过读取所述裸片的输出管脚上的信号来判断所述裸片是否被裂纹所损伤。
在一种可能的设计中，所述裂纹检测环路位于所述待测裸片所在基体的顶层金属层上。
在一种可能的设计中，所述中继驱动单元包括：
缓冲电路，所述缓冲电路用于增强所述脉冲检测信号，并驱动所述脉冲检测信号向所述裂纹检测环路的输出端传输。
在一种可能的设计中，所述中继驱动单元还包括：
可控下拉电阻，所述可控下拉电阻的第一端与所述缓冲电路的输入端连接，所述可控下拉电阻的第二端接地。
在一种可能的设计中，所述缓冲电路包括反相器，所述可控下拉电阻用于防止所述反相器的输入端悬空。
可选的，所述反相器的数量为至少两个。
在一种可能的设计中，所述可控下拉电阻包括：
MOS电阻，所述MOS电阻为导通状态下的MOS管；
开关元件，所述开关元件连接在所述MOS管的源极S和漏极D之间，所述开关元件用于控制所述MOS电阻是否短接，以改变所述可控下拉电阻的阻值。
可选的，所述裂纹检测环路与所述保护环在所述裸片的基体衬底上的投影形状相同。
可选的，所述裂纹检测环路的拐角为直角，所述保护环的拐角进行了倒角处理。
第三个方面，本申请提供一种裸片裂纹损伤检测电路，包括：
测试电路，位于所述裸片的内部处理电路的边界环线内，用于通过第一输出端，和/或，第二输出端输出脉冲检测信号；
第一裂纹检测环路，环绕设置于所述裸片的保护环外，其输入端与所述测试电路的第 一输出端连接，其输出端与所述裸片的第一输出管脚连接；
第二裂纹检测环路，环绕设置于所述裸片的保护环与所述内部边界环线之间，其输入端与所述测试电路的第二输出端连接，其输出端与所述裸片的第二输出管脚连接；
第一中继驱动单元，设置于所述第一裂纹检测环路的输入端和输出端之间，用于增强所述脉冲检测信号的传输能力；
第二中继驱动单元，设置于所述第二裂纹检测环路的输入端和输出端之间，用于增强所述脉冲检测信号的传输能力；
其中，所述保护环环绕整个所述裸片，用于保护所述裸片；
所述测试电路在进入测试模式时，向所述裂纹检测环路输出所述脉冲检测信号，测试机台通过读取所述裸片的第一输出管脚或所述裸片的第二输出管脚上的信号来判断所述裸片是否被裂纹所损伤。
在一种可能的设计中，所述裂纹检测环路位于所述待测裸片所在基体的顶层金属层上。
在一种可能的设计中，所述中继驱动单元包括：
缓冲电路，所述缓冲电路用于增强所述脉冲检测信号，并驱动所述脉冲检测信号向所述裂纹检测环路的输出端传输。
在一种可能的设计中，所述中继驱动单元还包括：
可控下拉电阻，所述可控下拉电阻的第一端与所述缓冲电路的输入端连接，所述可控下拉电阻的第二端接地。
在一种可能的设计中，所述缓冲电路包括反相器，所述可控下拉电阻用于防止所述反相器的输入端悬空。
可选的，所述反相器的数量为至少两个。
在一种可能的设计中，所述可控下拉电阻包括：
MOS电阻，所述MOS电阻为导通状态下的MOS管；
开关元件，所述开关元件连接在所述MOS管的源极S和漏极D之间，所述开关元件用于控制所述MOS电阻是否短接，以改变所述可控下拉电阻的阻值。
可选的，所述裂纹检测环路与所述保护环在所述裸片的基体衬底上的投影形状相同。
在一种可能的设计中，所述裂纹检测环路的拐角为直角，所述保护环的拐角进行了倒角处理。
可选的，所述测试电路的第一输出端和第二输出端为同一个输出端。
第四个方面，本申请提供一种半导体裸片的裂纹检测方法，包括：
响应于裂纹检测指令，根据所述裂纹检测指令，通过所述裸片裂纹损伤检测电路的测试电路向所述裸片裂纹损伤检测电路的裂纹检测环路输入脉冲检测信号；
根据待测裸片的输出管脚的信号输出特征以及所述脉冲检测信号确定所述待测裸片是否存在裂缝损伤，所述待测裸片中包括所述裸片裂纹损伤检测电路。
在一种可能的设计中，所述根据待测裸片的输出管脚的信号输出特征以及所述脉冲检测信号确定所述待测裸片是否存在裂缝损伤，包括：
若所述信号输出特征与所述脉冲检测信号满足预设对应条件，则所述待测裸片没有裂缝损伤，否则，所述待测裸片存在裂缝损伤。
在一种可能的设计中，所述预设对应条件包括：所述输出管脚存在输出信号。
可选的，所述预设对应条件包括：所述脉冲检测信号与所述输出管脚的输出信号相同。
第五个方面，本申请提供一种存储器，包括：
存储芯片，用于存储数据；
其中，所述存储芯片中包括第一至第三方面任意一种可能的裸片裂纹损伤检测电路。
可选的，该存储芯片还包括：数据输入/输出管脚，所述数据输入/输出管脚用于连接外部设备；
当所述存储器通过所述数据输入/输出管脚连接到检测机台上时，所述存储器进入测试模式，所述检测机台通过检测所述数据输入/输出管脚上的输出信号确定所述存储芯片是否被裂纹所损伤。
本申请提供了一种裸片裂纹损伤检测电路、裂纹检测方法以及存储器。该裸片裂纹损伤检测电路，包括：测试电路、裂纹检测环路、中继驱动单元。其中，测试电路位于裸片的保护环内，用于输出脉冲检测信号；裂纹检测环路位于保护环内，和/或，保护环外，其输入端与测试电路的输出端连接，其输出端与裸片的输出管脚连接；中继驱动单元，设置于裂纹检测环路的输入端和输出端之间，用于增强脉冲检测信号的传输能力；保护环环绕整个裸片，用于保护裸片；测试电路在进入测试模式时，向裂纹检测环路输出脉冲检测信号，测试机台通过读取裸片的输出管脚上的信号来判断裸片是否被裂纹所损伤。通过中继驱动单元对位于顶层金属层的裂纹检测环路中脉冲检测信号进行放大驱动，使得裂缝检测的速度和灵敏度得到大幅提升，测试机台直接读取裸片的输出管脚即可快速得到检测结果，提高了测试机台的检测便利性。
附图说明
为了更清楚地说明本申请或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供的第一种裸片裂纹损伤检测电路的结构示意图；
图2是本申请提供的第二种裸片裂纹损伤检测电路的结构示意图；
图3是本申请提供的第三种裸片裂纹损伤检测电路的结构示意图；
图4为本申请提供的裂纹检测环路在不同位置处的截面结构图；
图5为本申请提供的一种中继驱动单元的结构示意图；
图6为本申请提供的另一种中继驱动单元的结构示意图；
图7为本申请提供的一种裂纹检测方法的流程示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，包括但不限于对多个实施例的组合，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四” 等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
半导体集成芯片的制造一般分为：硅片制备、硅片上集成电路制造、硅片切割、测试和挑选、最终封装，这五个阶段。
目前硅片切割有刀片锯切和激光切割两种方式。
刀片锯切是使用由微小金刚石颗粒制成的砂轮锯片以30,000至40,000RPM的高速切割硅片。同时，承载硅片的工作台沿刀片和硅片接触点之间的切线方向以一定速度沿直线移动。切割晶片产生的硅芯片即裸片被去离子水(纯净水)冲走。刀片锯切的特点是切割速度慢，切屑越薄，切割就越困难，并且背面开裂趋于恶化，裸片的顶部金属层很容易遭受损坏。
激光切割是使激光能量集中在很小的区域内，并且在很短的时间内高温升华硅片固体，并在整个切割过程挥发掉。激光切割的特点是切割速度快，还可以有效减少薄片即硅片的背面开裂现象；其次，切槽宽度小，切槽损失比刀片锯切的方式少，可以减少各个裸片之间的间距，但激光切割对裸片中各个金属功能层的破坏是不可预见的。
可见，无论哪一种方式在切割的时候，都无法避免地会使得硅片产生裂缝，当裂缝蔓延到裸片上，就有可能破坏内部的集成电路，导致裸片报废。
为了在测试挑选阶段能够快速识别出村子裂缝损伤的裸片，本申请的发明构思是：
在裸片的四周构造一圈裂纹检测环路，并且将裂纹检测环路设置在硅片的顶层金属层，因为无论刀片锯切还是激光切割都是从上往下进行的，裂纹也最容易发生的顶层。只要从裂纹检测环路的输入端传入检测信号，再尝试从输出端接收，当切割时因应力作用裂缝侵入破坏了裂纹检测环路时，输出端就接收不到信号，或者是接收到的信号发生了改变，与预设的标准输出信号不对应。
同时，本申请发明人在考虑到一般检测信号功率都比较小，单纯以电压或者电流的形式进行检测，会使得检测结果存在误差，并且容易受到环境中电磁场的影响，检测的灵敏度和速度都不尽如人意。因此，采用脉冲信号的形式来代替电压或电流检测，同时在裂纹检测环路中增加中继驱动单元，不但能够对检测信号进行放大，还能够提高检测信号在裂纹检测环路的驱动传输能力，提高了检测速度和效率，并且抗干扰的能力得到提升，减少了误报的情况。
下面对结合附图对本申请提出的裸片裂纹损伤检测电路进行详细介绍。
图1为本申请提供的第一种裸片裂纹损伤检测电路的结构示意图。如图1所示，对硅片上的任意一个裸片100放大展示，裸片100包括：
切割缝101，是刀片或激光切割的轨迹；
保护环102，位于内部处理电路103外，环绕整个裸片100，用于保护裸片100，如吸收少子，防止电磁干扰，防止水汽、湿气等；
内部处理电路103，是实现整个芯片主要功能的集成电路，其有效范围在边界环线1031 内；
在本实施例中，裸片裂纹损伤检测电路包括：
测试电路104，位于边界环线1031内，用于输出脉冲检测信号；
裂纹检测环路105，环绕设置于裸片100的保护环102与边界环线1031之间，其输入端1051与测试电路104的输出端连接，其输出端1052与裸片100的输出管脚107连接；
中继驱动单元106，设置于裂纹检测环路105的输入端1051和输出端1052之间，用于增强脉冲检测信号的传输能力；
测试电路104在进入测试模式时，向裂纹检测环路105输出脉冲检测信号，测试机台通过读取裸片100的输出管脚107上的信号来判断裸片100是否被裂纹所损伤。
需要说明的是，中继驱动单元106的数量为至少1个，当中继驱动单元106为多个时，其可以均布在裂纹检测环路105上。
例如，当裂纹检测环路105中只有一个中继驱动单元106时，中继驱动单元106位于输入端1051和输出端1052中点上，即中继驱动单元106与输入端1051和输出端1052的距离相等；当裂纹检测环路105为矩形时，且裂纹检测环路105中有四个中继驱动单元106时，每个中继驱动单元106位于矩形各条边的中点上。
在一种可能的设计中，裂纹检测环路105也可以设置在保护环102外，如图2所示。
图2是本申请提供的第二种裸片裂纹损伤检测电路的结构示意图。如图2所示，裸片裂纹损伤检测电路包括：
测试电路104，位于保护环102内，用于输出脉冲检测信号；
裂纹检测环路105，环绕设置于保护环102外，其输入端1051与测试电路104的输出端连接，其输出端1052与裸片100的输出管脚连接107；
中继驱动单元106，设置于裂纹检测环路105的输入端1051和输出端1052之间，用于增强脉冲检测信号的传输能力；
其中，保护环102环绕整个裸片100，用于保护裸片100，如吸收沙子，防止电磁干扰，防止水汽、湿气等；
测试电路104在进入测试模式时，向裂纹检测环路105输出脉冲检测信号，测试机台通过读取裸片100的输出管脚107上的信号来判断裸片100是否被裂纹所损伤。
在另一种可能的设计中，裂纹检测环路105也可以是两个环路，同时设置在保护环102内和外，如图3所示。
图3是本申请提供的第三种裸片裂纹损伤检测电路的结构示意图。如图3所示，裸片裂纹损伤检测电路包括：
测试电路104，位于裸片100的内部处理电路103的边界环线1031内，用于通过第一输出端，和/或，第二输出端输出脉冲检测信号；
第一裂纹检测环路115，环绕设置于保护环102外，其输入端1151与测试电路104的第一输出端连接，其输出端1152与裸片100的第一输出管脚1071连接；
第二裂纹检测环路125，环绕设置于保护环102与内部边界环线1031之间，其输入端1251与测试电路的第二输出端连接，其输出端1252与裸片100的第二输出管脚1072连接；
第一中继驱动单元116，设置于第一裂纹检测环路115的输入端1151和输出端1152之间，用于增强脉冲检测信号的传输能力；
第二中继驱动单元126，设置于第二裂纹检测环路116的输入端1251和输出端1252之间，用于增强脉冲检测信号的传输能力；
其中，保护环102环绕整个裸片100，用于保护裸片100，如吸收沙子，防止电磁干扰，防止水汽、湿气等；
测试电路104在进入测试模式时，向裂纹检测环路115和/或裂纹检测环路125输出脉冲检测信号，测试机台通过读取裸片100的第一输出管脚1071或裸片100的第二输出管脚1072上的信号来判断裸片是否被裂纹所损伤。
本实施例提供了一种裸片裂纹损伤检测电路，包括：测试电路、裂纹检测环路、中继驱动单元。其中，测试电路位于裸片的保护环内，用于输出脉冲检测信号；裂纹检测环路位于保护环内，和/或，保护环外，其输入端与测试电路的输出端连接，其输出端与裸片的输出管脚连接；中继驱动单元，设置于裂纹检测环路的输入端和输出端之间，用于增强脉冲检测信号的传输能力；保护环环绕整个裸片，用于保护裸片；测试电路在进入测试模式时，向裂纹检测环路输出脉冲检测信号，测试机台通过读取裸片的输出管脚上的信号来判断裸片是否被裂纹所损伤。通过中继驱动单元对位于顶层金属层的裂纹检测环路中脉冲检测信号进行放大驱动，使得裂缝检测的速度和灵敏度得到大幅提升，测试机台直接读取裸片的输出管脚即可快速得到检测结果，提高了测试机台的检测便利性。
需要说明的是，在一种可能的设计中，裂纹检测环路输出端所输出的信号先回到裸片的内部电路，经过内部电路转换后，输出到裸片的输出管脚，然后测试机台再对，输出管脚的信号进行检测。
需要说明的是，在一种可能的实施方式中，裂纹检测环路被设置在裸片100所在硅片基体的顶层金属层上。
图4为本申请提供的裂纹检测环路在不同位置处的截面结构图。如图4所示，截面401为在裂纹检测环路105不与其它电路连接处的截面图，裸片100的基体可以看成是由多个金属层组成的包括：第一金属层1001(包括顶层金属层105、顶层金属层与次顶层金属层之间的绝缘层)、第二金属层1002(记顶层金属为第一层金属层、依次往下记为第二层金属层、第三层金属层、第四层金属层，这里的第二金属层1002包括第二层金属层、第二层金属层与第三层金属层之间的绝缘层)、第三金属层1003(这里的第三金属层1003包括第三层金属层、第三层金属层与其下面的绝缘层)。本申请发明人在长期实践中发现，顶层金属层是最容易遭受裂缝损伤的，当其它金属层存在裂缝损伤时，一般顶层金属层也会存在裂缝损伤，因此将裂纹检测环路105的检测线路布置在顶层金属层，就能够有效检测出裂缝损伤。此外还能够为其它电路留出布置空间，如图4中的第二金属层1002、第三金属层1003都能够布置其它电路元件或走线。
截面402为串联在裂缝检测环路105的中继驱动单元106与裂缝检测环路105的检测线路的连接示意图。中继驱动单元106的输入端与输出端分别连接着裂缝检测环路105，连接方式可以是穿越多个金属层的过孔。
为了更好理解，下面对中继驱动单元106进行详细介绍。
中继驱动单元106的本质是对脉冲检测信号进行放大，以增加脉冲检测信号的驱动能力，因为一般脉冲检测信号的电压只有0～1.2V，电流很小，这就导致脉冲检测信号在裂缝检测环路105中的驱动能力较弱，这样就增加了裸片100的检测时间，因此需要对脉冲检 测信号进行一定程度的放大，这就是中继驱动单元106的作用。
在一种可能的实施方式中，中继驱动单元106包括：缓冲电路即buffer缓冲器，所述缓冲电路用于增强脉冲检测信号，并驱动脉冲检测信号向裂纹检测环路的输出端传输。通过buffer缓冲器减少了电路的负载电容，负载电容减少后，同样电压的情况下，对电容充电速度快(上升沿陡峭)，同样电容小时存储的电容小，放电所需的时间短(下降沿陡峭)。一句话来说就是:buffer缓冲器减少了电路的负载电容，从而增大了电路驱动能力。缓冲电路的实现方式也有很多种，本领域技术人员可以根据实际需要选择其中一种缓冲放大器来实现缓冲电路。
在一种可能的实施方式中，所述缓冲电路包括反相器，反相器的实施方式包括集成式的施密特触发器单元，或者是直接由NMOS和PMOS级联而成。而由于反相器会导致信号的相位相反，一般会把反相器成对使用来构成buffer缓冲器，即缓冲电路具备2n(n为大于等于1的整数)个反相器的电路。当然，可以理解的是，当反相器为奇数个时，只需要在处理裂缝检测环路105输出端的信号时，进行对应的相位补充或修正计算，也能够起到检测作用。
因此，一种可能的实施方式中，缓冲电路包括反相器，反相器的数量为至少两个。
进一步的，在一种可能的实施方式中，为了避免反相器输入端悬空而受到周围环境中电磁场的干扰，增大反相器的输入阻抗，所述缓冲电路的输入端还连接有下拉电阻。
再进一步的，为了使得下拉电阻能够适应于多款不同类型的裸片，或者说是不同的反相器，提供不同的输入阻抗，可以把下拉电阻设置为可控下拉电阻，所述可控下拉电阻的第一端与所述缓冲器的输入端连接，所述可控下拉电阻的第二端接地。
可控下拉电阻的实现形式包括：利用开关管来控制纯电阻是否串联到电路中，来实现可控电阻阻值的变化。
图5为本申请提供的一种中继驱动单元的结构示意图。如图5所示，下拉电阻51的第一端与缓冲电路即buffer缓冲器52的输入端连接，下拉电阻51的第二端接地。下拉电阻51中包括多个电阻：电阻511、电阻512、电阻513、电阻514，以及与电阻并联的开关管：开关管S1、开关管S2、开关管S3、开关管S4。
需要说明的是开关管可以是三极管、MOS管或其他开关元件。
对于电阻511、电阻512、电阻513、电阻514可以是纯电阻，也可以是其它途径所得到的等价电阻。
在一种可能的实施方式中，可控下拉电阻包括：MOS电阻，所述MOS电阻为导通状态下的MOS管；以及
开关元件，所述开关元件连接在所述MOS管的源极S和漏极D之间，所述开关元件用于控制所述MOS电阻是否短接，以改变所述可控下拉电阻的阻值。
图6为本申请提供的另一种中继驱动单元的结构示意图。如图6所示，缓冲电路包括第一反相器和第二反相器，并以MOS管Q1至Q5导通时的导通电阻作为图5所示的电阻511、电阻512、电阻513、电阻514的另一种实现方式，即用MOS管来代替电阻511、电阻512、电阻513、电阻514，可以看到电阻514是以两个串联的MOS管即Q4和Q5串联的形成的，也就是说，每个电阻可以通过串联或并联多个MOS管的方式来得到。
需要说明的是，此时需要将MOS管的栅极G连接到导通电位，如NMOS管需要连接 到高电平，而PMOS管的栅极G连接到低电平，使得MOS管形成常导通状态以得到MOS电阻。
对于图1至图3中的裂纹检测环路，其包围在裸片的内部集成电路四周，具体形状可以于保护环的形状相同，形成多边形的形状。即所述裂纹检测环路与所述保护环在所述裸片的基体衬底上的投影形状相同。
在一种可能的设计中，所述裂纹检测环路的拐角为直角，所述保护环的拐角进行了倒角处理，所谓倒角处理可以包括：倒圆角和45度倒角(即把90度变为两个135度角)。裂纹检测环路的拐角设置为直角，能够使得在收到应力时，在直角处由于应力集中而更容易发生破坏，从而提高裂缝损伤检测的灵敏度。而保护环是为了要降低应力，因此设置了倒角结构。
对于图3所示的裸片裂纹损伤检测电路，其包括了第一裂纹检测环路和第二裂纹检测环路，这两个裂纹检测环路的检测信号可以是相同的信号，此时测试电路的第一输出端和第二输出端可以为同一个输出端，如此可以简化电路结构，同时简化对脉冲检测信号的控制和接收时的检测运算量。
下面对于如何利用本申请提供的裸片裂纹损伤检测电路进行裂纹检测的方法，进行介绍。
图7为本申请提供的一种裂纹检测方法的流程示意图。如图7所示，该裂纹检测方法的具体步骤包括：
S701、响应于裂纹检测指令，根据裂纹检测指令，通过裸片裂纹损伤检测电路的测试电路向裸片裂纹损伤检测电路的裂纹检测环路输入脉冲检测信号。
在本步骤中，用户通过其它机器将裸片放置到检测平台上，由检测平台向裸片发出裂纹检测指令，然后裸片裂纹损伤检测电路的测试电路就会发出脉冲检测信号，脉冲检测信号进入到裂缝检测环路中，然后由中继驱动单元进行放大，并向裂缝检测环路的输出端驱动。
S702、根据待测裸片的输出管脚的信号输出特征以及脉冲检测信号确定待测裸片是否存在裂缝损伤。
在本步骤中，所述待测裸片中包括图1至3所示的任意一种可能的裸片裂纹损伤检测电路。
待测裸片的输出管脚与测试机台连接，测试机台通过读取输出管脚的信号来进行裂缝损伤判别。
在一种可能的设计中，若所述信号输出特征与所述脉冲检测信号满足预设对应条件，则所述待测裸片没有裂缝损伤，否则，所述待测裸片存在裂缝损伤。
具体的，预设对应条件有几种实现方式，一种是只要输出管脚存在输出信号，那么就认为信号能够导通，所述待测裸片没有裂缝损伤，或者说是所述待测裸片的损伤并没有严重到能够影响内部电路的程度，还是能够作为正常的芯片使用。
预设对应条件的另一种实现方式是：所述脉冲检测信号与所述输出管脚的输出信号相同。具体的，由于脉冲信号是一个周期性的信号，那么只要在输出管脚检测到的脉冲信号的周期与输入信号的周期相同，那么即可认为所述待测裸片没有裂缝损伤。
预设对应条件的又一种实现方式是：所述脉冲检测信号与所述输出管脚的输出信号的 脉冲频率存在对应关系。由于脉冲信号在接收的时候可能会受到其它干扰因素，使得个别脉冲检测不到，此时，就需要提高容错率，改变接收输出信号的检测频率，即脉冲频率。如，原本以100HZ的频率发送的脉冲检测信号，在接收时，以50HZ的频率来采样，这样就能够降低单个或某几个脉冲受干扰造成的误判。
本申请还提供了一种存储器，该存储器包括：存储芯片，用于存储数据；
其中，所述存储芯片中包括上述实施例中任意一项所述的裸片裂纹损伤检测电路。
在一种可能的设计中，所述存储芯片还包括数据输入/输出管脚，所述数据输入/输出管脚用于连接外部设备；
当所述存储器通过所述数据输入/输出管脚连接到检测机台上时，所述存储器进入测试模式，所述检测机台通过检测所述数据输入/输出管脚上的输出信号确定所述存储芯片是否被裂纹所损伤。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (20)

  1. 一种裸片裂纹损伤检测电路，其特征在于，包括：
    测试电路，位于裸片的保护环内，用于输出脉冲检测信号；
    裂纹检测环路，环绕设置于所述裸片的内部处理电路的边界环线外，其输入端与所述测试电路的输出端连接，其输出端与所述裸片的输出管脚连接；
    中继驱动单元，设置于所述裂纹检测环路的输入端和输出端之间，用于增强所述脉冲检测信号的传输能力；
    其中，所述保护环环绕整个所述裸片，用于保护所述裸片；
    所述测试电路在进入测试模式时，向所述裂纹检测环路输出所述脉冲检测信号，测试机台通过读取所述裸片的输出管脚上的信号来判断所述裸片是否被裂纹所损伤。
  2. 根据权利要求1所述的裸片裂纹损伤检测电路，其特征在于，所述测试电路，位于所述边界环线内。
  3. 根据权利要求1或2所述的裸片裂纹损伤检测电路，其特征在于，所述裂纹检测环路包括：第一裂纹检测环路；
    所述第一裂纹检测环路，环绕设置于所述裸片的保护环外，其输入端与所述测试电路的第一输出端连接，其输出端与所述裸片的第一输出管脚连接；
    其中，所述测试电路的输出端包括所述第一输出端，所述裸片的输出管脚，包括所述第一输出管脚。
  4. 根据权利要求3所述的裸片裂纹损伤检测电路，其特征在于，所述中继驱动单元包括：第一中继驱动单元；
    所述第一中继驱动单元，设置于所述第一裂纹检测环路的输入端和输出端之间，用于增强所述第一裂纹检测环路中第一脉冲检测信号的传输能力；
    所述脉冲检测信号包括所述第一脉冲检测信号。
  5. 根据权利要求1-4中任意一项所述的裸片裂纹损伤检测电路，其特征在于，所述裂纹检测环路包括：第二裂纹检测环路；
    所述第二裂纹检测环路，环绕设置于所述裸片的保护环与所述内部边界环线之间，其输入端与所述测试电路的第二输出端连接，其输出端与所述裸片的第二输出管脚连接；
    其中，所述测试电路的输出端包括所述第二输出端，所述裸片的输出管脚，包括所述第二输出管脚。
  6. 根据权利要求5所述的裸片裂纹损伤检测电路，其特征在于，所述中继驱动单元包括：第二中继驱动单元；
    所述第二中继驱动单元，设置于所述第二裂纹检测环路的输入端和输出端之间，用于增强所述第二裂纹检测环路中第二脉冲检测信号的传输能力；
    所述脉冲检测信号包括所述第二脉冲检测信号。
  7. 根据权利要求1所述的裸片裂纹损伤检测电路，其特征在于，所述裂纹检测环路包括：第一裂纹检测环路以及第二裂纹检测环路；
    所述第一裂纹检测环路，环绕设置于所述裸片的保护环外，其输入端与所述测试电路的第一输出端连接，其输出端与所述裸片的第一输出管脚连接；
    所述第二裂纹检测环路，环绕设置于所述裸片的保护环与所述内部边界环线之间，其输入端与所述测试电路的第二输出端连接，其输出端与所述裸片的第二输出管脚连接；
    所述第一输出端和第二输出端为所述测试电路的同一个输出端。
  8. 根据权利要求1-7中任意一项所述的裸片裂纹损伤检测电路，其特征在于，所述裂纹检测环路位于所述待测裸片所在基体的顶层金属层上。
  9. 根据权利要求1-8中任意一项所述的裸片裂纹损伤检测电路，其特征在于，所述中继驱动单元包括：
    缓冲电路，所述缓冲电路用于增强所述脉冲检测信号，并驱动所述脉冲检测信号向所述裂纹检测环路的输出端传输。
  10. 根据权利要求9所述的裸片裂纹损伤检测电路，其特征在于，所述中继驱动单元还包括：
    可控下拉电阻，所述可控下拉电阻的第一端与所述缓冲电路的输入端连接，所述可控下拉电阻的第二端接地。
  11. 根据权利要求10所述的裸片裂纹损伤检测电路，其特征在于，所述缓冲电路包括反相器，所述可控下拉电阻用于防止所述反相器的输入端悬空。
  12. 根据权利要求11所述的裸片裂纹损伤检测电路，其特征在于，所述反相器的数量为至少两个。
  13. 根据权利要求9-12中任意一项所述的裸片裂纹损伤检测电路，其特征在于，所述可控下拉电阻包括：
    MOS电阻，所述MOS电阻为导通状态下的MOS管；
    开关元件，所述开关元件连接在所述MOS管的源极S和漏极D之间，所述开关元件用于控制所述MOS电阻是否短接，以改变所述可控下拉电阻的阻值。
  14. 根据权利要求1-13中任意一项所述的裸片裂纹损伤检测电路，其特征在于，所述裂纹检测环路与所述保护环在所述裸片的基体衬底上的投影形状相同。
  15. 根据权利要求1-14中任意一项所述的裸片裂纹损伤检测电路，其特征在于，所述裂纹检测环路的拐角为直角，所述保护环的拐角进行了倒角处理。
  16. 一种半导体裸片的裂纹检测方法，其特征在于，应用于权利要求1-28中任意一项所述的裸片裂纹损伤检测电路，所述方法包括：
    响应于裂纹检测指令，根据所述裂纹检测指令，通过所述裸片裂纹损伤检测电路的测试电路向所述裸片裂纹损伤检测电路的裂纹检测环路输入脉冲检测信号；
    根据待测裸片的输出管脚的信号输出特征以及所述脉冲检测信号确定所述待测裸片是否存在裂缝损伤，所述待测裸片中包括所述裸片裂纹损伤检测电路。
  17. 根据权利要求16所述的裂纹检测方法，其特征在于，所述根据待测裸片的输出管脚的信号输出特征以及所述脉冲检测信号确定所述待测裸片是否存在裂缝损伤，包括：
    若所述信号输出特征与所述脉冲检测信号满足预设对应条件，则所述待测裸片没有裂缝损伤，否则，所述待测裸片存在裂缝损伤。
  18. 根据权利要求17所述的裂纹检测方法，其特征在于，所述预设对应条件包括：所述输出管脚存在输出信号。
  19. 根据权利要求18所述的裂纹检测方法，其特征在于，所述预设对应条件包括：所述脉冲检测信号与所述输出管脚的输出信号相同。
  20. 一种存储器，其特征在于，包括：
    存储芯片，用于存储数据；
    其中，所述存储芯片中包括权利要求1-15中任意一项所述的裸片裂纹损伤检测电路；
    所述存储芯片还包括数据输入/输出管脚，所述数据输入/输出管脚用于连接外部设备；
    当所述存储器通过所述数据输入/输出管脚连接到检测机台上时，所述存储器进入测试模式，所述检测机台通过检测所述数据输入/输出管脚上的输出信号确定所述存储芯片是否被裂纹所损伤。
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