WO2022147982A1 - 电极层、电容器及其制备方法 - Google Patents

电极层、电容器及其制备方法 Download PDF

Info

Publication number
WO2022147982A1
WO2022147982A1 PCT/CN2021/103494 CN2021103494W WO2022147982A1 WO 2022147982 A1 WO2022147982 A1 WO 2022147982A1 CN 2021103494 W CN2021103494 W CN 2021103494W WO 2022147982 A1 WO2022147982 A1 WO 2022147982A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode layer
titanium nitride
layers
capacitor
Prior art date
Application number
PCT/CN2021/103494
Other languages
English (en)
French (fr)
Inventor
白卫平
郁梦康
苏星松
周震
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/401,489 priority Critical patent/US20220216297A1/en
Publication of WO2022147982A1 publication Critical patent/WO2022147982A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to an electrode layer, a capacitor and a preparation method thereof.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line
  • the data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • TiN titanium nitride
  • TiN titanium nitride
  • the aspect ratio of the capacitor structure will be greatly improved, especially the evolution of the capacitor structure from a cylindrical structure to a columnar structure. Due to the insufficient mechanical strength of titanium nitride, the capacitor structure is easy to Collapse due to stress.
  • the present application provides a method for preparing an electrode layer, comprising the steps of: forming a first electrode layer, the first electrode layer comprising a doped titanium nitride layer; forming a first electrode layer on the surface of the first electrode layer Two electrode layers, the second electrode layer includes a titanium nitride layer or a work function layer.
  • the present application further provides an electrode layer, comprising: a first electrode layer, the first electrode layer comprising a doped titanium nitride layer; a second electrode layer located on the surface of the first electrode layer, The second electrode layer includes a titanium nitride layer or a work function layer.
  • the present application also provides a method for preparing a capacitor, comprising the steps of: forming a lower electrode layer on the sidewall and bottom of the capacitor hole, wherein the lower electrode layer is prepared by using the method for preparing an electrode layer as described above. Obtained: forming a capacitor medium layer on the inner surface and the outer surface of the lower electrode layer; forming an upper electrode layer on the surface of the capacitor medium layer.
  • the present application further provides a capacitor, comprising: a lower electrode layer, the lower electrode layer includes the electrode layer as described above; a capacitor dielectric layer located on the inner surface and the outer surface of the lower electrode layer; an upper electrode layer; The electrode layer is located on the surface of the capacitor dielectric layer.
  • the present application further provides a method for preparing a capacitor, which includes the following steps: forming a lower electrode layer in a capacitor hole, the lower electrode layer filling the capacitor hole, and the lower electrode layer using the method described above.
  • a capacitor medium layer is formed on the outer surface of the lower electrode layer; and an upper electrode layer is formed on the outer surface of the capacitor medium layer.
  • the present application further provides a capacitor, comprising: a lower electrode layer, the lower electrode layer includes a solid columnar structure; the lower electrode layer includes the above-mentioned electrode layer; a capacitor dielectric layer, located in the lower the outer surface of the electrode layer; the upper electrode layer is located on the outer surface of the capacitor medium layer.
  • the electrode layer, capacitor and preparation method thereof of the present application have at least the following beneficial effects:
  • the preparation method of the electrode layer provided by the present application uses the stacked structure including the doped titanium nitride layer as the electrode layer to replace the electrode layer of a single material, because the doped titanium nitride layer has a larger capacity than the titanium nitride layer.
  • Mechanical strength, and the electrode layer is a laminated structure including at least two material layers, which can significantly enhance the mechanical strength of the electrode layer, and can avoid collapse due to stress when the electrode layer is used for the lower electrode layer of the capacitor.
  • the electrode layer prepared in the present application may include a work function layer in addition to the doped titanium nitride layer, and materials with different functional properties and advantages are combined to form an electrode layer. At the same time, it can reduce the resistivity of the electrode layer and improve the electrical conductivity of the electrode layer; it can meet the requirements of the electrode layer in terms of effective work function and interface compatibility with the dielectric layer, reduce leakage and improve the capacitance value.
  • FIG. 1 is a flowchart of a method for preparing an electrode layer provided in an embodiment of the application
  • FIG. 2 is a schematic cross-sectional structure diagram of an electrode layer provided in an embodiment of the application.
  • FIG. 3 is a flow chart of a doped titanium nitride growth cycle in a method for preparing an electrode layer provided in an embodiment of the present application;
  • FIGS. 4 to 6 are schematic structural diagrams of a first electrode layer formed by an atomic layer deposition process in a method for preparing an electrode layer provided in different embodiments of the present application;
  • FIG. 7 is a flowchart of a titanium nitride growth cycle in the method for preparing an electrode layer provided in an embodiment of the application;
  • FIG. 8 is a flowchart of a method for manufacturing a capacitor provided in an embodiment of the application.
  • FIG. 9 is a schematic top-view structure diagram of a capacitor prepared by the preparation method of the capacitor in FIG. 8;
  • FIG. 10 is a flowchart of a method for manufacturing a capacitor provided in another embodiment of the present application.
  • FIG. 11 is a schematic top view of the structure of the capacitor prepared by the method for manufacturing the capacitor in FIG. 10 .
  • 1-electrode layer 11-first electrode layer, 12-second electrode layer, 2-lower electrode layer, 3-capacitive medium layer, 4-upper electrode layer.
  • first electrode layer is referred to as the second electrode layer
  • second electrode layer may be referred to as the first electrode layer
  • first electrode layer and the second electrode layer are different electrode layers.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques. Thus, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the present application.
  • the present application provides a preparation method of an electrode layer, and the preparation method of the electrode layer 1 includes the following steps:
  • the first electrode layer 11 includes a doped titanium nitride layer
  • the prepared second electrode layer 12 may be a titanium nitride layer.
  • the electrode layer 1 is a stacked structure including a stacked doped titanium nitride layer and a titanium nitride layer. Since the doped titanium nitride layer has more than twice the mechanical strength compared to the titanium nitride layer, and the electrode layer 1 is a laminated structure including the first electrode layer 11 and the second electrode layer 12 , the electrode layer 1 can be significantly increased. When the electrode layer 1 is used as the lower electrode layer of the capacitor, the collapse due to stress can be avoided. However, the introduction of the doped titanium nitride layer causes the resistivity of the electrode layer 1 to be greatly increased compared to that of the single-layer titanium nitride layer, thereby affecting the electrical conductivity of the electrode layer.
  • the prepared second electrode layer 12 may be a work function layer.
  • the electrode layer 1 is a stacked structure including a stacked doped titanium nitride layer and a work function layer. Since the doped titanium nitride layer has more than twice the mechanical strength compared to the titanium nitride layer, and the electrode layer 1 is a laminated structure including the first electrode layer 11 and the second electrode layer 12 , the electrode layer 1 can be significantly increased.
  • the electrode layer 1 When the electrode layer 1 is used for the lower electrode layer of the capacitor, collapse due to stress can be avoided; at the same time, since the electrode layer 1 includes a work function layer, the existence of the work function layer can reduce the resistivity of the electrode layer and improve the The conductivity of the electrode layer can meet the requirements of the electrode layer 1 in terms of effective work function and interface compatibility with the dielectric layer, reducing leakage and increasing capacitance.
  • the first electrode layer 11 is formed by an atomic layer deposition process in step S11.
  • the process of forming the first electrode layer 11 by the atomic layer deposition process includes at least one doped titanium nitride growth cycle, please refer to FIG. 3 , and the doped titanium nitride growth cycle includes:
  • S111 providing a titanium precursor to form a titanium precursor layer; specifically, the first electrode layer 11 may be formed on the inner wall of the capacitor hole, and at this time, a titanium precursor may be provided in the capacitor hole to form a titanium precursor layer on the inner wall of the capacitor hole forming a titanium precursor;
  • S112 providing a dopant precursor to the surface of the titanium precursor layer, so as to adsorb the dopant on the surface of the titanium precursor layer;
  • S113 Provide a first reaction gas to the surface of the titanium precursor layer on which the dopant is adsorbed, so as to form a sub-doped titanium nitride layer.
  • the dopant precursor is introduced to adsorb the dopant on the surface of the titanium precursor layer;
  • a reactive gas since the dopant precursor can only adhere to the surface in a small amount by filling the gaps between the atoms of the titanium precursor atomic capping layer, so that each titanium precursor layer can produce a dopant micro-doping sub-doping Titanium nitride layer.
  • the dopant can be more uniformly distributed in the entire sub-doped titanium nitride layer, so as to achieve the purpose of uniform doping.
  • a cleaning step is included between steps S111 and S112, between steps S112 and S113, and after step S113; specifically, cleaning gas may be introduced into the capacitor hole to remove excess titanium precursors body, excess dopant precursor and excess first reactive gas to achieve cleaning.
  • Purge gases may include, but are not limited to, nitrogen or inert gases.
  • the titanium precursor may include, but is not limited to, titanium tetrachloride (TiCl 4 ), and the type of the titanium precursor is not limited in this embodiment.
  • the dopant precursor may include, but is not limited to, dichlorosilane (DCS), silane (SiH 4 ), tetra-dimethylaminosilane (SiH(NMe 2 ) 3 , TDMAS), or a combination thereof, This embodiment does not limit the types of dopant precursors.
  • DCS dichlorosilane
  • SiH 4 silane
  • SiH(NMe 2 ) 3 tetra-dimethylaminosilane
  • TDMAS tetra-dimethylaminosilane
  • the first reactive gas may include, but is not limited to, at least one of ammonia (NH 3 ), nitric oxide (NO), nitrous oxide (N 2 O), and nitrogen (N 2 ), This embodiment does not limit the specific type of the first reaction gas.
  • the process of forming the first electrode layer 11 by the atomic layer deposition process includes a plurality of doped titanium nitride growth cycles, that is, the formed first electrode layer 11 may include a plurality of layers stacked in sequence. Placed sub-doped titanium nitride layer.
  • the specific number of doped titanium nitride growth cycles can be set according to needs, which is not limited this time.
  • the formation process of the first electrode layer 11 may include 2 to 100 doped titanium nitride growth cycles. Yes, it can include 2, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 or even more doped titanium nitride growth cycles.
  • the doped titanium nitride growth cycle also includes the step of forming at least one layer of titanium nitride by atomic layer deposition; that is, the first electrode layer 11 includes a plurality of sub-doped titanium nitride layers and at least one layer of titanium nitride Layer stack structure; wherein, in FIG.
  • the first electrode layer 11 includes multiple layers of titanium nitride layers arranged at intervals, and multiple layers of sub-doped titanium nitride layers are arranged between adjacent titanium nitride layers;
  • the first electrode layer 11 includes a plurality of sub-doped titanium nitride stacked layer structures in which multiple layers of sub-doped titanium nitride layers are stacked in sequence, and a plurality of sub-doped titanium nitride layers stacked in sequence by multiple layers of titanium nitride layers.
  • Titanium nitride layered layer structure, the titanium nitride layered layer structure and the sub-doped titanium nitride layered layer structure are alternately stacked in sequence; using an atomic deposition process to form the titanium nitride layer includes:
  • a first reactive gas is provided to the surface of the titanium precursor layer to form the titanium nitride layer.
  • the first electrode layer 11 with the required thickness is generated by repeatedly depositing the sub-doped titanium nitride layer, so that the dopant can be more uniformly distributed throughout the entire deposition process.
  • the purpose of uniform doping is achieved.
  • a cleaning step is included; specifically, a cleaning gas may be introduced into the surface of the sub-doped titanium nitride layer To remove excess titanium precursor and excess first reaction gas to achieve cleaning.
  • Purge gases may include, but are not limited to, nitrogen or inert gases.
  • the content of the dopant can be properly regulated within the required low doping range of the dopant.
  • This embodiment does not limit the ratio and sequence of the growth period of the doped titanium nitride and the titanium nitride layer.
  • the low doping range of the dopant is 1%-10%, and may be 3%, 5%, 7%, etc., and the dopant content of the dopant is not limited in this embodiment.
  • the dopant in the doped titanium nitride layer may include silicon, boron, aluminum, zirconium, hafnium, phosphorus, carbon, gallium, germanium, antimony, tellurium, arsenic and tungsten At least one of the dopants in this embodiment is silicon.
  • the second electrode layer 12 is formed by an atomic layer deposition process in step S12.
  • an atomic layer deposition process is used to form the second electrode layer 12.
  • the process includes at least one titanium nitride growth cycle, please refer to FIG. 7 , and the titanium nitride growth cycle includes:
  • a first reaction gas is provided to the surface of the titanium precursor layer to form a sub-titanium nitride layer.
  • a cleaning step is included; specifically, a cleaning gas may be introduced into the surface of the sub-doped titanium nitride layer To remove excess titanium precursor and excess first reaction gas to achieve cleaning.
  • Purge gases may include, but are not limited to, nitrogen or inert gases.
  • step S12 adopts an atomic layer deposition process to form the second electrode layer 12.
  • the work function layer includes a ruthenium layer or a ruthenium oxide layer;
  • the process of forming the second electrode layer 12 by the atomic layer deposition process includes at least one work function layer growth cycle, and the work function layer growth cycle includes:
  • a second reaction gas is provided to the surface of the ruthenium precursor layer to form a sub work function layer.
  • a cleaning step is included;
  • the excess ruthenium precursor and the excess second reaction gas are used for cleaning.
  • Purge gases may include, but are not limited to, nitrogen or inert gases.
  • the ruthenium precursor may include, but is not limited to, ruthenium trichloride (RuCl 3 ), and the type of the ruthenium precursor is not limited in this embodiment.
  • RuCl 3 ruthenium trichloride
  • the number of layers of the first electrode layer 11 and the number of layers of the second electrode layer 12 included in the electrode layer 1 can be set according to actual needs, which are not limited here.
  • the number of layers of the first electrode layer 11 and the second electrode layer 12 in the electrode layer 1 may be one layer, as shown in FIG. 2 ; of course, in other embodiments, after step S12 , the method further includes: repeating step S11 , S12 at least once, with at least one of the number of layers of the first electrode layer 11 and the number of layers of the second electrode layer 12 in the formed electrode layer 1 being a multilayer, at this time the first electrode layer 11 and the first electrode layer 11
  • the two electrode layers 12 are alternately stacked in sequence.
  • step S11 and step S12 can be interchanged, that is, in other embodiments, the second electrode layer can also be formed before the inner wall of the capacitor hole, and then the second electrode layer can be formed on the inner wall of the capacitor hole. A first electrode layer is formed on the surface.
  • the present application further provides an electrode layer 1 , and the electrode layer 1 includes:
  • the first electrode layer 11 includes a doped titanium nitride layer
  • the second electrode layer 12 is located on the surface of the first electrode layer 11 , and the second electrode layer 12 includes a titanium nitride layer or a work function layer.
  • the second electrode layer 12 may be a titanium nitride layer.
  • the electrode layer 1 is a stacked structure including a stacked doped titanium nitride layer and a titanium nitride layer. Since the doped titanium nitride layer has more than twice the mechanical strength compared to the titanium nitride layer, and the electrode layer 1 is a laminated structure including the first electrode layer 11 and the second electrode layer 12 , the electrode layer 1 can be significantly increased. When the electrode layer 1 is used as the lower electrode layer of the capacitor, the collapse due to stress can be avoided. However, the introduction of the doped titanium nitride layer causes the resistivity of the electrode layer 1 to be greatly increased compared to that of the single-layer titanium nitride layer, thereby affecting the electrical conductivity of the electrode layer.
  • the second electrode layer 12 may be a work function layer.
  • the electrode layer 1 is a stacked structure including a stacked doped titanium nitride layer and a work function layer. Since the doped titanium nitride layer has more than twice the mechanical strength compared to the titanium nitride layer, and the electrode layer 1 is a laminated structure including the first electrode layer 11 and the second electrode layer 12 , the electrode layer 1 can be significantly increased.
  • the electrode layer 1 When the electrode layer 1 is used for the lower electrode layer of the capacitor, collapse due to stress can be avoided; at the same time, since the electrode layer 1 includes a work function layer, the existence of the work function layer can reduce the resistivity of the electrode layer and improve the The electrical conductivity of the electrode layer can meet the requirements of the interface compatibility between the effective work function of the electrode layer 1 and the dielectric layer, and the leakage current can be reduced and the capacitance value can be improved.
  • the first electrode layer 11 includes multiple layers of sub-doped titanium nitride layers stacked in sequence.
  • the first electrode layer 11 includes multiple layers of titanium nitride layers arranged at intervals, and multiple layers of sub-doped titanium nitride layers are arranged between adjacent titanium nitride layers. .
  • the first electrode layer 11 includes a plurality of sub-doped titanium nitride stacked layer structures in which a plurality of sub-doped titanium nitride layers are stacked in sequence, and a plurality of The layered titanium nitride layer structure is stacked one by one, and the titanium nitride layered layer structure and the sub-doped titanium nitride layered layer structure are stacked alternately in sequence.
  • the content of the dopant can be properly regulated within the required low dopant doping range.
  • the ratio and sequence of the titanium growth period and the titanium nitride layer are not limited.
  • the dopant in the doped titanium nitride layer includes at least one of silicon, boron, aluminum, zirconium, hafnium, phosphorus, carbon, gallium, germanium, antimony, tellurium, arsenic and tungsten one.
  • the second electrode layer 12 includes multiple layers of titanium nitride layers stacked in sequence or multiple layers of work function layers stacked sequentially.
  • the work function layer includes a ruthenium layer or a ruthenium oxide layer.
  • the electrode layer is a laminated structure.
  • the number of layers of the first electrode layer 11 and the number of layers of the second electrode layer 12 included in the electrode layer 1 can be set according to actual needs, which is not limited here.
  • the number of layers of the first electrode layer 11 and the second electrode layer 12 in the electrode layer 1 may be one layer, as shown in FIG. 2 ; of course, in other embodiments, the first electrode layer in the electrode layer 1 At least one of the number of layers of 11 and the number of layers of the second electrode layer 12 may be multiple layers. In this case, the first electrode layers 11 and the second electrode layers 12 are alternately stacked in sequence.
  • the present application also provides a method for preparing a capacitor, comprising the following steps:
  • the present application also provides a capacitor, including:
  • the lower electrode layer 2 includes the electrode layer described in any of the above embodiments; that is, the lower electrode layer 2 in this embodiment includes the first electrode layer 11 and the second electrode layer 12 in the above embodiments;
  • the capacitor dielectric layer 3 is located on the inner surface and the outer surface of the lower electrode layer 2;
  • the upper electrode layer 4 is located on the surface of the capacitor dielectric layer 3 .
  • the present application also provides a method for preparing a capacitor, comprising the following steps:
  • the lower electrode layer 2 is formed in the capacitor hole, the lower electrode layer 2 fills the capacitor hole, and the lower electrode layer 2 is prepared by using the electrode layer preparation method described in any of the above embodiments; that is, in this embodiment
  • the lower electrode layer 2 includes the first electrode layer 11 and the second electrode layer 12 in the above embodiments;
  • the present application also provides a capacitor, including:
  • the lower electrode layer 2 includes a solid columnar structure; the lower electrode layer 2 includes the electrode layer described in any of the above embodiments; that is, the lower electrode layer 2 in this embodiment includes the first electrode layer in the above embodiments 11 and the second electrode layer 12;
  • the capacitor dielectric layer 3 is located on the outer surface of the lower electrode layer 2;
  • the upper electrode layer 4 is located on the outer surface of the capacitor dielectric layer 3 .
  • FIGS. 1 , 3 , 7 , 8 and 10 are shown in sequence according to the arrows, these steps are not necessarily executed in the sequence indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least some of the steps in FIGS. 1 , 3 , 7 , 8 and 10 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but may be performed at different times. The execution sequence of these steps or stages is not necessarily carried out sequentially, but may be executed in turn or alternately with other steps or at least a part of the steps or stages in the other steps.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

本申请涉及一种电极层、电容器及其制备方法，电极层的制备方法包括如下步骤：形成第一电极层，所述第一电极层包括掺杂氮化钛层；于所述第一电极层的表面形成第二电极层，所述第二电极层包括氮化钛层或功函数层。

Description

电极层、电容器及其制备方法
本申请要求于2021年01月05日提交的申请号为202110009808.6、名称为“电极层、电容器及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种电极层、电容器及其制备方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。目前的DRAM电容器的制造工艺中，氮化钛(TiN)材料由于具有很好的热稳定性、与高介电常数(high-K)介质层的良好兼容性以及较好的机械强度，被作为存储节点(SN)的材料。
随着DRAM技术向先进节点的进一步微缩，电容结构上的深宽比将大大提高，尤其是电容器的结构由筒状向柱状结构的演变，由于氮化钛的机械强度不够大，电容结构很容易因为应力而发生坍塌。
发明内容
一方面，本申请提供了一种电极层的制备方法，包括如下步骤：形成第一电极层，所述第一电极层包括掺杂氮化钛层；于所述第一电极层的表面形成第二电极层，所述第二电极层包括氮化钛层或功函数层。
第二方面，本申请还提供了一种电极层，包括：第一电极层，所述第一电极层包括掺杂氮化钛层；第二电极层，位于所述第一电极层的表面，所述第二电极层包括氮化钛层或功函数层。
第三方面，本申请还提供一种电容器的制备方法，包括如下步骤：于电容孔的侧壁及底部形成下电极层，所述下电极层采用如上述所述的电极层的制备方法制备而得到；于所述下电极层的内表面及外表面形成电容介质层；于所述电容介质层的表面形成上电极层。
第四方面，本申请还提供一种电容器，包括：下电极层，所述下电极层包括如上述所述的电极层；电容介质层，位于所述下电极层的内表面及外表面；上电极层，位于所述电容介质层的表面。
第五方面，本申请还提供一种电容器的制备方法，包括如下步骤：于电容孔内形成下电极层，所述下电极层填满所述电容孔，所述下电极层采用如上述所述的电极层的制备方法制备而得到；于所述下电极层外表面形成电容介质层；于所述电容介质层的外表面形成上电极层。
第六方面，本申请还提供一种电容器，包括：下电极层，所述下电极层包括实心柱状结构；所述下电极层包括如上述所述的电极层；电容介质层，位于所述下电极层的外表面；上电极层，位于所述电容介质层的外表面。
本申请的电极层、电容器及其制备方法至少具有如下有益效果：
本申请提供的电极层的制备方法使用包括掺杂氮化钛层的叠层结构作为 电极层替代单一材料的电极层，由于掺杂氮化钛层相较于氮化钛层具有更大的的机械强度，又电极层为包括至少两层材料层的叠层结构，可以显著增强电极层的机械强度，在电极层用于电容器的下电极层时可以避免因应力而发生坍塌。在一个实施例中，本申请制备的电极层中除了包括掺杂氮化钛层之外还可以包括功函数层，将具有不同功能属性和优势的材料结合在一起形成电极层，在增强电极层的机械强度的同时，可以减少电极层的电阻率，提高电极层的导电性能；并可满足电极层在有效功函数及与介质层的界面兼容性方面的要求，降低漏电和提高电容值。
本申请的各个实施例的细节将在下面的附图和描述中进行说明。根据说明书、附图以及权利要求书的记载，本领域技术人员将容易理解本申请的其它特征、解决的问题以及有益效果。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图
图1为本申请一实施例中提供的电极层的制备方法的流程图；
图2为本申请一实施例中提供的电极层的截面结构示意图；
图3为本申请一实施例中提供的电极层的制备方法中一个掺杂氮化钛生长周期的流程图；
图4至图6为本申请不同实施例中提供的电极层的制备方法中采用原子层沉积工艺所形成的第一电极层的结构示意图；
图7为本申请一实施例中提供的电极层的制备方法中一个氮化钛生长周期的流程图；
图8为本申请一实施例中提供的电容器的制备方法的流程图；
图9为图8中的电容器的制备方法制备的电容器的俯视结构示意图；
图10为本申请另一实施例中提供的电容器的制备方法的流程图；
图11为图10中的电容器的制备方法制备的电容器的俯视结构示意图。
附图标记说明：
1-电极层，11-第一电极层，12-第二电极层，2-下电极层，3-电容介质层，4-上电极层。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二等描 述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一电极层称为第二电极层，且类似地，可以将第二电极层成为第一电极层；第一电极层与第二电极层为不同的电极层。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，实施例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状 的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本申请的范围。
请参阅图1和图2，本申请提供一种电极层的制备方法，电极层1的制备方法包括如下步骤：
S11：形成第一电极层11，第一电极层11包括掺杂氮化钛层；
S12：于第一电极层11的表面形成第二电极层12，第二电极层12包括氮化钛层或功函数层。
在一个实施例中，制备得到的第二电极层12可以为氮化钛层，此时，电极层1为包括叠置的掺杂氮化钛层及氮化钛层的叠层结构。由于掺杂氮化钛层相较于氮化钛层具有两倍以上的机械强度，又电极层1是包括第一电极层11和第二电极层12的叠层结构，可以显著增加电极层1的机械强度，在电极层1用于电容器的下电极层时可以避免因应力而发生崩塌。然而，掺杂氮化钛层的引入会导致电极层1的电阻率相较于单层氮化钛层的电阻率大大增加，从而影响电极层的导电性。
在另一个实施例中，制备得到的第二电极层12可以为功函数层，此时，电极层1为包括叠置的掺杂氮化钛层及功函数层的叠层结构。由于掺杂氮化钛层相较于氮化钛层具有两倍以上的机械强度，又电极层1是包括第一电极层11和第二电极层12的叠层结构，可以显著增加电极层1的机械强度，在电极层1用于电容器的下电极层时可以避免因应力而发生崩塌；同时，由于电极层1中包括功函数层，功函数层的存在可以减少电极层的电阻率，提高电极层的导电性能，并可满足电极层1在有效功函数及与介质层的界面兼容性方面的要求，降低漏电和提高电容值。
对于步骤S11，在其中一个实施例中步骤S11采用原子层沉积工艺形成所述第一电极层11。采用原子层沉积工艺形成第一电极层11的过程中包括至少一个掺杂氮化钛生长周期，请参阅图3，所述掺杂氮化钛生长周期包括：
S111：提供钛前驱体，以形成钛前驱体层；具体的，第一电极层11可以形成于电容孔的内壁上，此时，可以向电容孔内提供钛前驱体，以在电容孔的内壁形成钛前驱体；
S112：向所述钛前驱体层的表面提供掺杂物前驱体，以于所述钛前驱体层的表面吸附掺杂物；
S113：向吸附有所述掺杂物的所述钛前驱体层表面提供第一反应气体，以形成子掺杂氮化钛层。
上述实施例中提供的电极层的制备方法中，在形成钛前驱体层之后，即通入掺杂物前驱体，以于所述钛前驱体层的表面吸附掺杂物；之后再通入第一反应气体，由于掺杂物前驱体只能通过填补钛前驱体原子覆盖层原子间的间隙少量附着在表面，这样每一个钛前驱体层就可以产生一个掺杂物微量掺杂的子掺杂氮化钛层。在此过程中，掺杂物得以更均匀地分布在整个子掺杂氮化钛层中，实现均匀掺杂的目的。
在一个实施例中，步骤S111与步骤S112之间、步骤S112与步骤S113之间及步骤S113之后还均包括清洗的步骤；具体的，可以向电容孔内通入清洗气体以去除多余的钛前驱体、多余的掺杂物前驱体及多余的第一反应气体，以实现清洗。清洗气体可以包括但不仅限于氮气或惰性气体。
在一个实施例中，钛前驱体可以包括但不限于四氯化钛(TiCl 4)，本实施例对钛前驱体的种类并不做限定。
在一个实施例中，掺杂物前驱体可以包括但不限于二氯硅烷(DCS)、硅烷 (SiH 4)、四-二甲基氨基硅烷(SiH(NMe 2) 3，TDMAS)或其组合，本实施例对掺杂物前驱体的种类并不做限定。
在一个实施例中，第一反应气体可以包括但不限于氨气(NH 3)、一氧化氮(NO)、一氧化二氮(N 2O)及氮气(N 2)中的至少一种，本实施例对第一反应气体的具体种类不做限定。
在一个实施例中，请参阅图4，采用原子层沉积工艺形成第一电极层11的过程中包括多个掺杂氮化钛生长周期，即形成的第一电极层11可以包括多个依次叠置的子掺杂氮化钛层。掺杂氮化钛生长周期的具体数量可以根据需要进行设定，此次不做限定，譬如，第一电极层11的形成过程中，可以包括2～100个掺杂氮化钛生长周期，具体的，可以包括2个、10个、20个、30个、40个、50个、60个、70个、80个、90个、100个甚至更多个掺杂氮化钛生长周期。
在另一个实施例中，请参阅图5及图6，第一个所述掺杂氮化钛生长周期之前、最后一个所述掺杂氮化钛生长周期之前及/或至少相邻两所述掺杂氮化钛生长周期之间还包括采用原子层沉积工艺形成至少一层氮化钛层的步骤；即第一电极层11为包括多个子掺杂氮化钛层与至少一层氮化钛层的叠层结构；其中，图5中，第一电极层11中包括多层间隔排布的氮化钛层，相邻氮化钛层之间设有多层子掺杂氮化钛层；图6中，第一电极层11中包括多个由多层子掺杂氮化钛层依次叠置的子掺杂氮化钛层叠层结构及多个由多层氮化钛层依次叠置的氮化钛层叠层结构，氮化钛层叠层结构与子掺杂氮化钛层叠层结构依次交替叠置；采用原子沉积工艺形成所述氮化钛层包括：
向所述子掺杂氮化钛层的表面提供钛前驱体，以于所述子掺杂氮化钛层的表面形成钛前驱体层；
向所述钛前驱体层的表面提供第一反应气体，以形成所述氮化钛层。
上述实施例中提供的电极层的制备方法中，通过反复沉积子掺杂氮化钛层，生成所需厚度的第一电极层11，使得在沉积过程中，掺杂物得以更均匀发布在整个第一电极层11中，实现均匀掺杂的目的。
在一个实施例中，形成钛前驱体层之后提供第一反应气体之前及形成氮化钛层之后均还包括清洗的步骤；具体的，可以向子掺杂氮化钛层的表面通入清洗气体以去除多余的钛前驱体及多余的第一反应气体，以实现清洗。清洗气体可以包括但不仅限于氮气或惰性气体。
在一个实施例中，可以通过调节掺杂氮化钛生长周期与氮化钛层的比例和顺序，在所需的掺杂物低掺杂的范围内，适当调控掺杂物的含量，本实施例对掺杂氮化钛生长周期与氮化钛层的比例和顺序并不做限定。其中，掺杂物低掺杂的范围为1％-10％，具体可以为3％、5％、7％等，本实施例对掺杂物的掺杂含量并不做限定。
具体的，在其中一个实施例中，所述掺杂氮化钛层中的掺杂物可以包括硅、硼、铝、锆、铪、磷、碳、镓、锗、锑、碲、砷及钨中的至少一者，本实施例中，掺杂物为硅。
对于步骤S12，在其中一个实施例中，步骤S12采用原子层沉积工艺形成第二电极层12，当第二电极层12为氮化钛层时，采用原子层沉积工艺形成第二电极层12的过程中包括至少一个氮化钛生长周期，请参阅图7，所述氮化钛生长周期包括：
向第一电极层11的表面提供钛前驱体，以形成钛前驱体层；
向所述钛前驱体层表面提供第一反应气体，以形成子氮化钛层。
在一个实施例中，形成钛前驱体层之后提供第一反应气体之前及形成氮化钛层之后均还包括清洗的步骤；具体的，可以向子掺杂氮化钛层的表面通入清 洗气体以去除多余的钛前驱体及多余的第一反应气体，以实现清洗。清洗气体可以包括但不仅限于氮气或惰性气体。
对于步骤S12，在其中一个实施例中，步骤S12采用原子层沉积工艺形成第二电极层12，当第二电极层12为功函数层时，所述功函数层包括钌层或氧化钌层；采用原子层沉积工艺形成第二电极层12的过程中包括至少一个功函数层生长周期，所述功函数层生长周期包括：
向第一电极层11的表面提供钌前驱体，以形成钌前驱体层；
向所述钌前驱体层表面提供第二反应气体，以形成子功函数层。
在一个实施例中，形成钌前驱体层之后提供第二反应气体之前及形成子功率函数层之后均还包括清洗的步骤；具体的，可以向第一电极层11的表面通入清洗气体以去除多余的钌前驱体及多余的第二反应气体，以实现清洗。清洗气体可以包括但不仅限于氮气或惰性气体。
在一个实施例中，钌前驱体可以包括但不限于三氯化钌(RuCl 3)，本实施例对钌前驱体的种类并不做限定。
具体的，电极层1包括的第一电极层11的层数及第二电极层12层数可以根据实际需要设定，此处不做限定。譬如，电极层1中的第一电极层11及第二电极层12的层数可以均为一层，如图2所示；当然，在其他实施例中，步骤S12之后还包括：重复步骤S11、S12至少一次，以形成的电极层1中的第一电极层11的层数及第二电极层12的层数二者中至少一者可以为多层，此时第一电极层11与第二电极层12依次交替叠置。
需要进一步说明的是，在其他实施例中，步骤S11与步骤S12的顺序可以互换，即在其他实施例中也可以先于电容孔的内壁形成第二电极层，然后再于第二电极层的表面形成第一电极层。
请继续参阅图2至图6，本申请还提供一种电极层1，电极层1包括：
第一电极层11，第一电极层11包括掺杂氮化钛层；
第二电极层12，位于第一电极层11的表面，第二电极层12包括氮化钛层或功函数层。
在一个实施例中，第二电极层12可以为氮化钛层，此时，电极层1为包括叠置的掺杂氮化钛层及氮化钛层的叠层结构。由于掺杂氮化钛层相较于氮化钛层具有两倍以上的机械强度，又电极层1是包括第一电极层11和第二电极层12的叠层结构，可以显著增加电极层1的机械强度，在电极层1用于电容器的下电极层时可以避免因应力而发生崩塌。然而，掺杂氮化钛层的引入会导致电极层1的电阻率相较于单层氮化钛层的电阻率大大增加，从而影响电极层的导电性。
在另一个实施例中，第二电极层12可以为功函数层，此时，电极层1为包括叠置的掺杂氮化钛层及功函数层的叠层结构。由于掺杂氮化钛层相较于氮化钛层具有两倍以上的机械强度，又电极层1是包括第一电极层11和第二电极层12的叠层结构，可以显著增加电极层1的机械强度，在电极层1用于电容器的下电极层时可以避免因应力而发生崩塌；同时，由于电极层1中包括功函数层，功函数层的存在可以减少电极层的电阻率，提高电极层的导电性能，并满足电极层1在有效功函数与介质层的界面兼容性方面的要求，降低漏电和提高电容值。
具体的，在其中一个实施例中，请参阅图4，第一电极层11包括多层依次叠置的子掺杂氮化钛层。
在另一个实施例中，如图5所示，第一电极层11中包括多层间隔排布的氮化钛层，相邻氮化钛层之间设有多层子掺杂氮化钛层。
在又一个实施例中，如图6所示，第一电极层11中包括多个由多层子掺杂氮化钛层依次叠置的子掺杂氮化钛层叠层结构及多个由多层氮化钛层依次叠置的氮化钛层叠层结构，氮化钛层叠层结构与子掺杂氮化钛层叠层结构依次交替叠置。
可以通过调节掺杂氮化钛生长周期与氮化钛层的比例和顺序，在所需的掺杂物低掺杂的范围内，适当调控掺杂物的含量，本实施例对掺杂氮化钛生长周期与氮化钛层的比例和顺序并不做限定。
具体的，在其中一个实施例中，掺杂氮化钛层中的掺杂物包括硅、硼、铝、锆、铪、磷、碳、镓、锗、锑、碲、砷及钨中的至少一者。
在其中一个实施例中，第二电极层12包括多层依次叠置的氮化钛层或多层依次叠置的功函数层。
具体的，在一个实施例中，功函数层包括钌层或氧化钌层。
在其中一个实施例中，电极层为叠层结构，具体的，电极层1包括的第一电极层11的层数及第二电极层12层数可以根据实际需要设定，此处不做限定。譬如，电极层1中的第一电极层11及第二电极层12的层数可以均为一层，如图2所示；当然，在其他实施例中，电极层1中的第一电极层11的层数及第二电极层12的层数二者中至少一者可以为多层，此时第一电极层11与第二电极层12依次交替叠置。
请参阅图8及图9，本申请还提供一种电容器的制备方法，包括如下步骤：
S21：于电容孔的侧壁及底部形成下电极层2，下电极层2采用上述任一实施例所述的电极层的制备方法制备而得到；即本实施例中的下电极层2包括上述实施例中的第一电极层11及第二电极层12；
S22：于下电极层2的内表面及外表面形成电容介质层3；
S23：于电容介质层3的表面形成上电极层4。
具体的，形成电容孔、形成于下电极层2的内表面及外表面形成电容介质层3；及于电容介质层3的表面形成上电极层4的具体方法均为本领域技术人员所知晓，此次不再累述。
请继续参阅图9，本申请还提供一种电容器，包括：
下电极层2，下电极层2包括上述任一实施例所述的电极层；即本实施例中的下电极层2包括上述实施例中的第一电极层11及第二电极层12；
电容介质层3，位于下电极层2的内表面及外表面；
上电极层4，位于电容介质层3的表面。
请参阅图10，本申请还提供一种电容器的制备方法，包括如下步骤：
S31：于电容孔内形成下电极层2，下电极层2填满所述电容孔，下电极层2采用上述任一实施例所述的电极层的制备方法制备而得到；即本实施例中的下电极层2包括上述实施例中的第一电极层11及第二电极层12；
S32：于下电极层2外表面形成电容介质层3；
S33：于电容介质层3的外表面形成上电极层4。
具体的，形成电容孔、形成于下电极层2的内表面及外表面形成电容介质层3；及于电容介质层3的表面形成上电极层4的具体方法均为本领域技术人员所知晓，此次不再累述。
请参阅图11，本申请还提供一种电容器，包括：
下电极层2，下电极层2包括实心柱状结构；下电极层2包括上述任一实施例所述的电极层；即本实施例中的下电极层2包括上述实施例中的第一电极层11及第二电极层12；
电容介质层3，位于下电极层2的外表面；
上电极层4，位于电容介质层3的外表面。
应该理解的是，虽然图1、图3、图7、图8及图10的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1、图3、图7、图8及图10中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种电极层的制备方法，包括如下步骤：
    形成第一电极层，所述第一电极层包括掺杂氮化钛层；
    于所述第一电极层的表面形成第二电极层，所述第二电极层包括氮化钛层或功函数层。
  2. 根据权利要求1所述的电极层的制备方法，其中，采用原子层沉积工艺形成所述第一电极层，采用原子层沉积工艺形成所述第一电极层的过程中包括至少一个掺杂氮化钛生长周期，所述掺杂氮化钛生长周期包括：
    提供钛前驱体，以形成钛前驱体层；
    向所述钛前驱体层的表面提供掺杂物前驱体，以于所述钛前驱体层的表面吸附掺杂物；
    向吸附有所述掺杂物的所述钛前驱体层表面提供第一反应气体，以形成子掺杂氮化钛层。
  3. 根据权利要求2所述的电极层的制备方法，其中，采用原子层沉积工艺形成所述第一电极层的过程中包括多个所述掺杂氮化钛生长周期，第一个所述掺杂氮化钛生长周期之前、最后一个所述掺杂氮化钛生长周期之前及/或至少相邻两所述掺杂氮化钛生长周期之间还包括采用原子层沉积工艺形成至少一层氮化钛层的步骤；采用原子沉积工艺形成所述氮化钛层包括：
    向所述子掺杂氮化钛层的表面提供钛前驱体，以于所述子掺杂氮化钛层的表面形成钛前驱体层；
    向所述钛前驱体层的表面提供第一反应气体，以形成所述氮化钛层。
  4. 根据权利要求1所述的电极层的制备方法，其中，所述掺杂氮化钛层 中的掺杂物包括硅、硼、铝、锆、铪、磷、碳、镓、锗、锑、碲、砷及钨中的至少一者。
  5. 根据权利要求1所述的电极层的制备方法，其中，所述第二电极层为氮化钛层时，采用原子层沉积工艺形成所述第二电极层，采用原子层沉积工艺形成所述第二电极层的过程中包括至少一个氮化钛生长周期，所述氮化钛生长周期包括：
    向所述第一电极层的表面提供钛前驱体，以形成钛前驱体层；
    向所述钛前驱体层表面提供第一反应气体，以形成子氮化钛层。
  6. 根据权利要求1所述的电极层的制备方法，其中，所述第二电极层为功函数层时，所述功函数层包括钌层或氧化钌层；采用原子层沉积工艺形成所述第二电极层，采用原子层沉积工艺形成所述第二电极层的过程中包括至少一个功函数层生长周期，所述功函数层生长周期包括：
    向所述第一电极层的表面提供钌前驱体，以形成钌前驱体层；
    向所述钌前驱体层表面提供第二反应气体，以形成子功函数层。
  7. 根据权利要求1至6中任一项所述的电极层的制备方法，其中，形成所述第二电极层后还包括：重复上述步骤至少一次，以形成包括多层所述第一电极层及多层所述第二电极层的叠层结构，所述叠层结构中所述第一电极层与所述第二电极层交替叠层。
  8. 一种电极层，包括：
    第一电极层，所述第一电极层包括掺杂氮化钛层；
    第二电极层，位于所述第一电极层的表面，所述第二电极层包括氮化钛层或功函数层。
  9. 根据权利要求8所述的电极层，其中，所述第一电极层包括多层依次 叠置的子掺杂氮化钛层。
  10. 根据权利要求9所述的电极层，其中，底层所述子掺杂氮化钛层下方、顶层所述子掺杂氮化钛层上方及/或至少相邻两所述子掺杂氮化钛层之间还设有氮化钛层。
  11. 根据权利要求8所述的电极层，其中，所述第二电极层包括多层依次叠置的氮化钛层或多层依次叠置的功函数层。
  12. 根据权利要求8所述的电极层，其中，所述功函数层包括钌层或氧化钌层。
  13. 根据权利要求8所述的电极层，其中，所述掺杂氮化钛层中的掺杂物包括硅、硼、铝、锆、铪、磷、碳、镓、锗、锑、碲、砷及钨中的至少一者。
  14. 根据权利要求8至13中任一项所述的电极层，其中，所述电极层为叠层结构，所述电极层包括多层所述第一电极层及多层所述第二电极层，所述电极层中所述第一电极层与所述第二电极层交替叠置。
  15. 一种电容器的制备方法，包括：
    于电容孔的侧壁及底部形成下电极层，所述下电极层采用如权利要求1至7中任一项所述的电极层的制备方法制备而得到；
    于所述下电极层的内表面及外表面形成电容介质层；
    于所述电容介质层的表面形成上电极层。
  16. 一种电容器，包括：
    下电极层，所述下电极层包括如权利要求8至14中任一项所述的电极层；
    电容介质层，位于所述下电极层的内表面及外表面；
    上电极层，位于所述电容介质层的表面。
  17. 一种电容器的制备方法，包括：
    于电容孔内形成下电极层，所述下电极层填满所述电容孔，所述下电极层采用如权利要求1至7中任一项所述的电极层的制备方法制备而得到；
    于所述下电极层外表面形成电容介质层；
    于所述电容介质层的外表面形成上电极层。
  18. 一种电容器，包括：
    下电极层，所述下电极层包括实心柱状结构；所述下电极层包括如权利要求8至14中任一项所述的电极层；
    电容介质层，位于所述下电极层的外表面；
    上电极层，位于所述电容介质层的外表面。
PCT/CN2021/103494 2021-01-05 2021-06-30 电极层、电容器及其制备方法 WO2022147982A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/401,489 US20220216297A1 (en) 2021-01-05 2021-08-13 Electrode layer, capacitor and methods for electrode layer and capacitor manufacture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110009808.6 2021-01-05
CN202110009808.6A CN114725105A (zh) 2021-01-05 2021-01-05 电极层、电容器及其制备方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/401,489 Continuation US20220216297A1 (en) 2021-01-05 2021-08-13 Electrode layer, capacitor and methods for electrode layer and capacitor manufacture

Publications (1)

Publication Number Publication Date
WO2022147982A1 true WO2022147982A1 (zh) 2022-07-14

Family

ID=82234412

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/103494 WO2022147982A1 (zh) 2021-01-05 2021-06-30 电极层、电容器及其制备方法

Country Status (2)

Country Link
CN (1) CN114725105A (zh)
WO (1) WO2022147982A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030213987A1 (en) * 2002-05-16 2003-11-20 Cem Basceri MIS capacitor and method of formation
US20120171839A1 (en) * 2009-09-18 2012-07-05 Intermolecular Inc. Fabrication of semiconductor stacks with ruthenium-based materials
US20140187015A1 (en) * 2012-12-27 2014-07-03 Elpida Memory, Inc Methods to Improve Leakage for ZrO2 Based High K MIM Capacitor
US20140183697A1 (en) * 2012-12-27 2014-07-03 Intermolecular, Inc. High Work Function, Manufacturable Top Electrode
CN107868944A (zh) * 2017-10-31 2018-04-03 北京北方华创微电子装备有限公司 一种氮化钛原子层沉积装置及其沉积方法
CN110718538A (zh) * 2018-07-13 2020-01-21 爱思开海力士有限公司 半导体器件以及用于制造其的方法
CN112071981A (zh) * 2019-06-11 2020-12-11 三星电子株式会社 集成电路器件及其制造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030213987A1 (en) * 2002-05-16 2003-11-20 Cem Basceri MIS capacitor and method of formation
US20120171839A1 (en) * 2009-09-18 2012-07-05 Intermolecular Inc. Fabrication of semiconductor stacks with ruthenium-based materials
US20140187015A1 (en) * 2012-12-27 2014-07-03 Elpida Memory, Inc Methods to Improve Leakage for ZrO2 Based High K MIM Capacitor
US20140183697A1 (en) * 2012-12-27 2014-07-03 Intermolecular, Inc. High Work Function, Manufacturable Top Electrode
CN107868944A (zh) * 2017-10-31 2018-04-03 北京北方华创微电子装备有限公司 一种氮化钛原子层沉积装置及其沉积方法
CN110718538A (zh) * 2018-07-13 2020-01-21 爱思开海力士有限公司 半导体器件以及用于制造其的方法
CN112071981A (zh) * 2019-06-11 2020-12-11 三星电子株式会社 集成电路器件及其制造方法

Also Published As

Publication number Publication date
CN114725105A (zh) 2022-07-08

Similar Documents

Publication Publication Date Title
US8415227B2 (en) High performance dielectric stack for DRAM capacitor
JP5587716B2 (ja) 半導体装置及びその製造方法、並びに吸着サイト・ブロッキング原子層堆積法
US8765570B2 (en) Manufacturable high-k DRAM MIM capacitor structure
US9105646B2 (en) Methods for reproducible flash layer deposition
US20140187016A1 (en) High Work Function, Manufacturable Top Electrode
JP5418951B2 (ja) キャパシタおよびキャパシタを形成する方法
JP5932221B2 (ja) 半導体装置
US8828821B2 (en) Fabrication of semiconductor stacks with ruthenium-based materials
US8975633B2 (en) Molybdenum oxide top electrode for DRAM capacitors
TW201937699A (zh) 用於dram電容器的摻雜氮化鈦材料，以及相關的半導體器件、系統和方法
US8581319B2 (en) Semiconductor stacks including catalytic layers
US8486780B2 (en) Doped electrode for dram applications
US8835273B2 (en) High temperature ALD process of metal oxide for DRAM applications
US8563392B2 (en) Method of forming an ALD material
WO2022147982A1 (zh) 电极层、电容器及其制备方法
CN114284216A (zh) 电容器阵列结构及其制造方法与半导体存储器件
CN113594096B (zh) 一种半导体结构的制备方法、半导体结构和电容结构
JP2000196035A (ja) メモリ素子のキャパシタ製造方法
US8853049B2 (en) Single-sided non-noble metal electrode hybrid MIM stack for DRAM devices
US6723613B2 (en) Method of forming an isolated-grain rugged polysilicon surface via a temperature ramping step
US20220216297A1 (en) Electrode layer, capacitor and methods for electrode layer and capacitor manufacture
KR101060771B1 (ko) 반도체 소자의 전극 제조 방법
KR100631949B1 (ko) 반도체 소자의 캐패시터 형성방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21917027

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21917027

Country of ref document: EP

Kind code of ref document: A1