WO2022143037A1 - 芯片测试组件、芯片测试系统和芯片测试方法 - Google Patents

芯片测试组件、芯片测试系统和芯片测试方法 Download PDF

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Publication number
WO2022143037A1
WO2022143037A1 PCT/CN2021/136082 CN2021136082W WO2022143037A1 WO 2022143037 A1 WO2022143037 A1 WO 2022143037A1 CN 2021136082 W CN2021136082 W CN 2021136082W WO 2022143037 A1 WO2022143037 A1 WO 2022143037A1
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Prior art keywords
test
board
chip
sub
tested
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PCT/CN2021/136082
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English (en)
French (fr)
Inventor
林楷辉
倪建兴
Original Assignee
锐石创芯(深圳)科技股份有限公司
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Publication of WO2022143037A1 publication Critical patent/WO2022143037A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2868—Complete testing stations; systems; procedures; software aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating

Definitions

  • the present application relates to the technical field of chip testing, and in particular, to a chip testing component, a chip testing system and a chip testing method.
  • High Temperature Operating Life can be used to evaluate the durability of a device under superheat and overvoltage for a period of time. It is a commonly used detection method for chip testing. Cracks, interdiffusion, instability and ionic contamination, etc.
  • HTOL High Temperature Operating Life
  • most of the existing HTOL test solutions are tested by using sockets to load chips, that is, firstly, the chips to be tested are fixedly loaded on the sockets, then multiple sockets are soldered to the motherboard, and finally the motherboard is placed in a high-temperature oven for HTOL testing. .
  • sockets to load chips, that is, firstly, the chips to be tested are fixedly loaded on the sockets, then multiple sockets are soldered to the motherboard, and finally the motherboard is placed in a high-temperature oven for HTOL testing.
  • sockets due to the high cost of sockets, it is necessary to replace sockets after batch HTOL testing reaches the service life of sockets (usually 3 to 5 times), resulting in high costs for batch testing of socket
  • the present application provides a chip testing component, a chip testing system and a chip testing method, so as to solve the problem that the existing chip testing cost is relatively high and its testing accuracy cannot be guaranteed.
  • the application provides a chip test assembly, including a test daughter board and a performance test main board;
  • the test sub-board includes a chip loading area and a test connection area, the chip load area is used for loading the chips to be tested, and the test connection area is provided with a main board connector;
  • the performance test mainboard includes a mainboard substrate, a sub-board connector and a signal transmission port arranged on the main board substrate, and the signal transmission port is electrically connected with the sub-board connector through a signal connection line;
  • the signal transmission port is connected to the chip to be tested on the test sub-board. Make electrical connections.
  • the main board connecting piece is a main board connecting probe
  • the sub-board connecting piece is a sub-board connecting terminal
  • the main board connecting piece is a main board connecting terminal
  • the sub-board connecting piece is a sub-board connecting probe
  • the chip loading area is provided with chip connecting pins for connecting the chips to be tested;
  • test connection area is arranged on the periphery of the chip loading area, and the main board connector on the test connection area and the chip connection pins are electrically connected through the daughter board signal wiring.
  • the present application provides a chip testing system, including a test sub-board and a performance test main board; the test sub-board is used to load a chip to be tested; when the performance test main board is attached to the test sub-board, the performance test sub-board The test mainboard is electrically connected to the chip to be tested on the test subboard.
  • the chip test system further includes an HTOL test main board, the HTOL test main board is detachably connected to the test sub-board, and is electrically connected to the chip to be tested on the test sub-board, and is used for testing the test sub-board.
  • the chip to be tested is subjected to HTOL test.
  • the test sub-board is provided with a chip loading area and a test connection area, the chip load area is used for loading the chip to be tested, and the test connection area is provided with a main board connector;
  • the performance test mainboard includes a mainboard substrate, a sub-board connector and a signal transmission port arranged on the main board substrate, and the signal transmission port is electrically connected to the sub-board connector through a signal connection line;
  • the signal transmission port is electrically connected to the chip to be tested on the test sub-board .
  • the chip loading area is provided with chip connecting pins for connecting the chips to be tested;
  • the test connection area is arranged on the periphery of the chip loading area, and the test connection area is provided with a mainboard connector, and the mainboard connector and the chip connection pins are electrically connected through the daughter board signal wiring , the motherboard connector includes a functional motherboard probe;
  • the signal transmission port is electrically connected to the chip to be tested on the test sub-board.
  • the mainboard connector further includes an HTOL mainboard probe
  • the test sub-board further includes a pin connector electrically connected to the probe of the HTOL main board;
  • the HTOL test mainboard is provided with a sub-board interface matched with the pin connector.
  • the pin connector is arranged on the side of the test sub-board.
  • the test sub-board further comprises a main board connection hole, and the functional main board probe is arranged on the periphery of the main board connection hole;
  • the chip test system further includes a signal probe, which is assembled in the main board connection hole, and is used to probe the daughter board connector on the performance test main board with the function main board on the test daughter board. When the pins are attached, the performance test main board is electrically connected to the chip to be tested on the test sub-board.
  • the chip testing system further includes a test pressing fixture
  • the test pressing fixture includes a test base plate, a fixing plate, a sliding guide rail, a sliding connecting plate and a pressing component
  • the fixing plate is vertically disposed on the on the test base plate
  • the sliding guide rail is assembled on the fixed plate and is perpendicular to the test base plate
  • the sliding connecting plate is connected with the sliding guide rail and can move along the sliding guide rail
  • the pressing assembly It is assembled on the sliding connection board, and forms an accommodating gap for accommodating the test sub-board and the performance test main board with the test bottom plate.
  • the application provides a chip testing method, including:
  • test sub-board placing the test sub-board in the HTOL test environment, so that the test duration of the test sub-board in the HTOL test environment reaches the target duration, and the chip loading area of the test sub-board is loaded with the chip to be tested;
  • the test sub-board is attached to the performance test main board, so that the performance test main board is electrically connected to the chip to be tested on the test sub-board, and the performance test of the to-be-tested chip is performed.
  • the test sub-board is attached to the performance test main board, so that the performance test main board is electrically connected to the chip to be tested on the test sub-board, including:
  • test sub-board Place the test sub-board on the performance test main board, align the sub-board connector on the performance test main board with the main board connector on the test connection area in the test sub-board, and align the performance test sub-board
  • the test main board and the test sub-board are placed in the accommodating gap between the test bottom plate of the test pressing jig and the pressing component, and the pressing component is controlled to be pressed in the direction of the test bottom plate, so that the The test sub-board is attached to the performance test main board, so that the performance test main board is electrically connected with the to-be-tested chip on the test sub-board, and the performance test of the to-be-tested chip is performed.
  • the chip to be tested is loaded on the test sub-board, and the sub-board connector on the performance test main board passes through the main board on the test connection area on the test sub-board.
  • the connector is attached so as to be electrically connected with the chip to be tested on the test sub-board, so as to ensure the feasibility of the functional test.
  • FIG. 1 is a schematic diagram of a test daughter board in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a performance testing motherboard in an embodiment of the present application
  • FIG. 3 is a schematic diagram of a test pressing jig in an embodiment of the present application.
  • FIG. 4 is a flowchart of a chip testing method in an embodiment of the present application.
  • test daughter board 11, daughter board substrate; 12, chip loading area; 13, test connection area; 20, performance test main board; 21, main board substrate; 22, daughter board connector; 23, signal input port ;24. Signal output port; 25. Signal connecting line; 30. HTOL test motherboard; 40. Test pressing fixture; 41. Test base plate; 42. Fixing plate; 43. Sliding rail; 44. Sliding connecting plate; Press fit components.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used herein for convenience of description This describes the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the embodiment of the present application provides a chip test assembly, including a test sub-board 10 and a performance test main board 20;
  • the test sub-board 10 includes a chip loading area 12 and a test connection area 13, and the chip loading area 12 is used for loading a chip to be tested, and testing
  • the connection area 13 is provided with a mainboard connector;
  • the performance test mainboard 20 includes a mainboard substrate 21, a subboard connector 22 arranged on the mainboard substrate 21, and a signal transmission port, and the signal transmission port is connected to the subboard connector through a signal connection line 25. 22 is electrically connected; when the sub-board connector 22 on the performance test main board 20 is attached to the main board connector on the test connection area 13 in the test sub-board 10, the signal transmission port and the test chip on the test sub-board 10 are realized. electrical connection.
  • the test sub-board 10 is a sub-board for loading the chips to be tested.
  • the test sub-board 10 includes a sub-board substrate 11 , and the sub-board substrate 11 is provided with a chip loading area 12 and a test connection area 13 .
  • the daughter board substrate 11 refers to a board for testing the daughter board 10 .
  • the chip loading area 12 is an area for loading and placing chips to be tested.
  • the test connection area 13 is an area for realizing electrical connection between the chip to be tested and the test motherboard.
  • the test connection area 13 is provided with a mainboard connector, and the mainboard connector is a component used to realize the connection performance test of the mainboard 20 .
  • the performance test mainboard 20 is a mainboard used to implement functional testing, and specifically can be understood as a mainboard for testing whether the chip to be tested can implement specific functions.
  • the performance test mainboard 20 includes a mainboard substrate 21 and a sub-board connector 22 disposed on the mainboard substrate 21 .
  • the sub-board connector 22 is a component provided on the performance test main board 20 for realizing electrical connection with the test sub-board 10 .
  • the signal transmission port is a pin set on the performance test motherboard for communicating with external circuits.
  • the performance testing motherboard 20 is also provided with a signal transmission port, and the signal transmission port is electrically connected to the sub-board connector 22 through a signal connection line 25 for controlling the chip to be tested to perform functional testing.
  • the signal transmission port includes a signal input port 23 and a signal output port 24 for receiving input signals and sending output signals.
  • the mainboard connector is a mainboard connection probe
  • the subboard connector is a subboard connection terminal, that is, when the mainboard connector is a mainboard connection probe, the subboard connector is a subboard connection. Terminal, when the sub-board connection terminal on the performance test main board is attached to the main board connection probe on the test connection area in the test sub-board, the signal transmission port is connected to the test sub-board.
  • the chip to be tested is electrically connected
  • the main board connecting member is a main board connecting terminal
  • the sub-board connecting member is a sub-board connecting probe. That is, when the mainboard connector is a mainboard connection terminal, the subboard connector is a subboard connection probe.
  • the signal transmission port is electrically connected to the chip to be tested on the test sub-board.
  • the signal transmission port on the performance test main board 20 is connected to the test sub-board 10 .
  • the chip to be tested is electrically connected.
  • the test sub-board 10 loaded with the chip to be tested is attached to the performance test motherboard 20, and the chip to be tested on the test sub-board 10 is tested with the performance test.
  • the main board connectors on the sub-board connectors 22 on the main board 20 are electrically connected, thereby ensuring the feasibility of using the performance testing main board 20 for functional testing, making the functional testing process simple and convenient, and helping to reduce functional testing costs.
  • the preset target duration eg 128h, 256h, 512h or 1000h
  • the preset target duration can be 128h, 256h, 512h or 1000h
  • the chip to be tested is functionally tested, multiple sets of test data are obtained, and each set of test data is separated to determine which function of the chip to be tested has a problem, which is helpful for Guarantee the accuracy of chip testing.
  • the signal transmission port on the performance test motherboard 20 can be connected to the signal acquisition controller, so that the performance test motherboard 20 can perform functional tests on the chip to be tested under the control of the signal acquisition controller, collect functional test data, and The test data is sent to the signal acquisition controller.
  • the signal acquisition controller is a controller used to control the performance test main board 20 to perform functional tests on the chips to be tested loaded on the test daughter board 10.
  • the signal acquisition controller can Analyze functional test data and obtain functional test results. Functional testing in this example refers to the process of testing all the functions in the chip to be tested one by one.
  • the functional testing process of the chip to be tested using the above chip testing component specifically includes the following steps:
  • the chip to be tested is loaded on the sub-board 10 to be tested, and specifically, the chip to be tested can be welded or fixed on the sub-board 10 to be tested by other means.
  • the test sub-board 10 is attached to the performance test main board 20, and the chip to be tested on the test sub-board 10 is electrically connected to the performance test main board 20, that is, the performance test main board 20 is electrically connected.
  • the sub-board connector 22 is electrically connected to the chip to be tested on the test sub-board 10 when the sub-board connector 22 is attached to the main board connector on the test connection area 13 on the test sub-board 10 .
  • the signal transmission port of the performance test mainboard 20 is electrically connected with the signal acquisition controller.
  • the signal acquisition controller is used to send function test instructions to the performance test motherboard 20, and the performance test motherboard 20 is controlled to perform a function test on the chip to be tested, and the function test data formed during the function test is collected and sent to the signal acquisition controller, so that the signal acquisition can be performed.
  • the controller analyzes the functional test data and obtains the functional test results. For example, if the chip to be tested is pre-configured with four functions of A, B, C and D, the signal acquisition controller needs to send the function test instructions corresponding to the four functions to the performance test motherboard 20, and collect these four functions respectively for testing. Test data formed during the process to obtain functional test data
  • the chip to be tested is loaded on the test sub-board 10 , and the sub-board connectors 22 on the performance test main board 20 pass through the main board on the test connection area 13 in the test sub-board 10 When the connector is attached, it is electrically connected to the chip to be tested on the test sub-board 10 to ensure the feasibility of the functional test.
  • the performance test main board 20 to perform a functional test on the chip to be tested loaded on the test daughter board 10 can determine which function of the chip to be tested has a problem, which helps to improve the accuracy of the functional test result.
  • the test sub-board 10 is used to load the chip to be tested, and then the test sub-board 10 is attached to the performance test main board 20. Compared with the socket connection, the test sub-board 10 is more helpful to reduce the test cost.
  • the chip loading area 12 is provided with chip connection pins for connecting the chips to be tested; the test connection area 13 is arranged on the periphery of the chip loading area 12, and the motherboard connectors on the test connection area 13 are connected to the chips.
  • the pins are electrically connected through the daughter board signal traces.
  • the sub-board substrate 11 of the test sub-board 10 is provided with a chip loading area 12 for loading the chips to be tested, and the chip loading area 12 is provided with chip connecting pins for connecting the chips to be tested. When on the chip loading area 12, it is electrically connected to the chip to be tested through the chip connection pins.
  • a test connection area 13 is provided on the periphery of the chip loading area 12, so that the chip to be tested can be loaded on the chip loading area 12, and the test connection area 13 is provided with a main board connector, the main board connector and the chip connection lead
  • the pins are electrically connected through the sub-board signal lines, and can be electrically connected to the performance test motherboard 20 through the motherboard connector.
  • the sub-board connector 22 on the performance test main board 20 is attached to the main board connector to be electrically connected to the chip to be tested on the test sub-board 10, and the performance test main board 20 is used to perform a functional test on the chip to be tested. Guarantee the accuracy of functional test results and reduce test costs.
  • chip connection pins are provided on the chip loading area 12, and when the chip to be tested is loaded and fixed to the chip loading area 12 of the test sub-board 10, the chip connection pins are electrically connected to the chip to be tested, so that the The main board connector whose chip connection pins are connected through the sub-board signal lines is also electrically connected to the chip to be tested.
  • the sub-board connector 22 on the performance test main board 20 is pasted with the main board connector on the test connection area 13 on the test sub-board 10
  • the performance test main board 20 is electrically connected to the chip to be tested on the test sub-board 10, It can complete the functional test and collect functional test data to ensure the smooth progress of the test process.
  • the chip to be tested includes a chip substrate and a chip circuit disposed on the chip substrate, the chip substrate is provided with chip connection holes corresponding to the chip connection pins, and the periphery of the chip connection holes is provided with a chip circuit connected to the chip circuit.
  • the chip connecting ring is welded to the chip connecting pin through the chip connecting hole by using a welding piece, so that the chip connecting ring on the chip to be tested is electrically connected with the chip connecting pin on the test sub-board 10 .
  • the chip substrate is the substrate of the chip to be tested.
  • a chip circuit is a circuit formed by a chip and peripheral components arranged on a chip substrate.
  • the chip connection hole is a connection hole provided on the chip substrate, and is used to realize the connection with the test sub-board 10 .
  • the chip connection ring is an annular structure formed by using conductive material to surround the chip connection hole. Welded parts are structural parts formed by welding conductive metal materials.
  • soldering parts can be used to solder to the chip connection pins through the chip connection holes, and the chip connection rings are electrically connected to the chip connection pins through the soldering parts, so as to realize The purpose of loading and fixing the chip to be tested on the test sub-board 10 and electrically connecting it with the test sub-board 10 . It is understandable that, compared with the way of connecting the conventional socket to the sub-board 10 to be tested, soldering the chip to be tested on the sub-board to be tested 10 can effectively reduce the testing cost.
  • the chip connection pins include chip input pins and chip output pins
  • the chip connection holes include a first connection hole and a second connection hole, and a first connection hole connected to the input end of the chip circuit is provided on the periphery of the first connection hole connection ring, the periphery of the second connection hole is provided with a second connection ring which is connected with the output end of the chip circuit;
  • the welding piece is welded on the chip input pin through the first connection hole, so that the first connection ring is connected to the chip input pin
  • the welding piece is welded on the output pin of the chip through the second connection hole, so that the second connection ring is electrically connected with the output pin of the chip.
  • the chip connection pins on the test daughter board 10 include chip input pins and chip output pins.
  • the chip connection holes on the HTOL test mainboard 30 include a first connection hole and a second connection hole.
  • the periphery of the first connection hole is provided with a first connection ring connected to the input end of the chip circuit, and the periphery of the second connection hole is provided with a chip circuit.
  • the output terminal of the second connecting ring is connected.
  • the first connection ring When the soldering piece is welded to the chip input pin of the test sub-board 10 through the first connection hole, the first connection ring can be electrically connected with the chip input pin, so that the input end of the chip circuit can be electrically connected with the chip input pin.
  • the second connection ring when the welding piece is welded to the chip output pin of the test sub-board 10 through the second connection hole, the second connection ring can be electrically connected to the chip output pin, so that the output end of the chip circuit is connected to the chip output pin.
  • the pins are electrically connected.
  • the embodiment of the present application provides a chip testing system, including a test sub-board 10 and a performance test main board 20; the test sub-board 10 is used to load a chip to be tested; when the performance test main board 20 is attached to the test sub-board 10, the performance test The main board 20 is electrically connected to the chip to be tested on the test sub-board 10 .
  • the functional testing process using the chip testing system is as follows: First, load the chip to be tested on the sub-board 10 to be tested. Specifically, the chip to be tested may be soldered or fixed on the sub-board 10 to be tested in other ways. Next, after the functional test conditions are met, such as the test duration of the chip to be tested in the HTOL test environment reaches a preset target duration (eg 128h, 256h, 512h or 1000h), the test sub-board 10 is attached to the performance test motherboard 20 , the chip to be tested on the test sub-board 10 is electrically connected to the performance test main board 20 . Finally, the function test is performed on the chip to be tested through the performance test motherboard 20 .
  • a preset target duration eg 128h, 256h, 512h or 1000h
  • a signal acquisition controller connected to the performance testing motherboard 20 may be used to control the performance testing motherboard 20 to complete the functional test of the chip to be tested. That is, the signal acquisition controller is used to send functional test instructions to the performance test mainboard 20, and the performance test mainboard 20 is controlled to perform functional tests on the chips to be tested, and the functional test data formed in the process of functional testing are collected and sent to the signal acquisition controller to make the signal.
  • the acquisition controller analyzes the functional test data and obtains the functional test results.
  • the chip to be tested is loaded on the test daughter board 10 , and then the performance test main board 20 is attached to the test daughter board, so that the performance test main board 20 is compatible with the chips loaded on the test daughter board 10 .
  • the function test of the chip to be tested can determine which function of the chip to be tested has a problem, which helps to improve the accuracy of the functional test result.
  • the test sub-board 10 is used to load the chip to be tested, and then the test sub-board 10 is attached to the performance test main board 20. Compared with the socket connection, the test sub-board 10 is more helpful to reduce the test cost.
  • the chip testing system further includes an HTOL test mainboard 30, which is detachably connected to the test sub-board 10, and is electrically connected to the chip to be tested on the test sub-board 10, and is used for testing the chip to be tested.
  • HTOL test is detachably connected to the test sub-board 10, and is electrically connected to the chip to be tested on the test sub-board 10, and is used for testing the chip to be tested.
  • the HTOL test mainboard 30 is a mainboard used to implement the HTOL test. Specifically, it can be understood as a mainboard for whether the chip to be tested can meet the HTOL test requirements.
  • the HTOL test main board 30 can be detachably connected to the test sub-board 10, which can realize that after the test duration of the chip to be tested in the HTOL test environment reaches a preset target duration (such as 128h, 256h, 512h or 1000h) and the HTOL test is completed, Take out the test sub-board 10 from the HTOL test main board 30, and use the performance test main board 20 to perform a functional test on the chip to be tested; after each functional test is completed, the test sub-board 10 can also be detachably connected to the HTOL test main board, repeating Perform the above process to ensure the accuracy of the HTOL test.
  • a preset target duration such as 128h, 256h, 512h or 1000h
  • the HTOL test mainboard 30 needs to be connected to the signal acquisition controller, and the signal acquisition controller is used to control the HTOL test mainboard 30 to perform HTOL tests on the chips to be tested loaded on the test sub-board 10, and collect the HTOL tests formed during the HTOL test. Data, analyze the HTOL test data, and obtain the HTOL test results.
  • the HTOL test process using the chip test system includes the following steps:
  • the chip to be tested may be welded or fixed on the sub-board 10 to be tested by other means.
  • test sub-board 10 Removably connect the test sub-board 10 to the HTOL test main board 30, electrically connect the chip to be tested on the test sub-board 10 to the HTOL test main board 30, and place the HTOL test main board 30 and the test sub-board 10 on the HTOL test board as a whole.
  • the HTOL test motherboard 30 is taken out from the HTOL test environment, and the HTOL test motherboard is removed.
  • the 30 is electrically connected with the signal acquisition controller, and the signal acquisition controller is used to control the HTOL test motherboard 30 to perform HTOL test on the chip to be tested.
  • test sub-board 10 removes the test sub-board 10 from the HTOL test main board 30, attach the test sub-board 10 to the performance test main board 20, and electrically connect the chip to be tested on the test sub-board 10 with the performance test main board 20, that is, the performance test
  • the performance test main board 20 is electrically connected to the chip to be tested on the test sub-board 10
  • the test sub-board 10 is electrically connected.
  • the signal acquisition controller of the board 10 is electrically connected, and the signal acquisition controller is used to control the performance test main board 20 to perform function test on the chip to be tested.
  • the signal acquisition controller is used to send a function test instruction to the performance test motherboard 20, and the performance test motherboard 20 is controlled to perform a function test on the chip to be tested, collect the function test data formed during the function test, and send the function test data to the signal acquisition controller. .
  • the HTOL test data refers to the test data that the chip to be tested is subjected to HTOL test after a period of time in an ultra-heat or ultra-high pressure environment to detect its durability.
  • the HTOL test data can be analyzed for durability. If the durability fed back in the data does not meet the preset durability requirements, it is determined that the chip to be tested does not meet the HTOL test requirements, and the HTOL test results that fail the test are obtained; on the contrary, if the durability feedback in the HTOL test data meets the preset durability requirements requirements, it is determined that the chip to be tested meets the HTOL test requirements, and the HTOL test results that pass the test are obtained.
  • Using the performance test main board 20 to perform a functional test on the chip to be tested loaded on the test daughter board 10 can determine which function of the chip to be tested has a problem, which helps to improve the accuracy of the functional test result.
  • the chip to be tested is loaded on the test sub-board 10, the test sub-board 10 is detachably connected to the HTOL test main board 30, the HTOL test is performed on the to-be-tested chip, the HTOL test data formed during the HTOL test is collected, and the For the HTOL test result, it is understandable that the HTOL test main board 30 is used to perform the HTOL test on the chip to be tested loaded on the test daughter board 10, and it can be determined that the chip to be tested does not meet the HTOL test requirements, which helps to improve the accuracy of the functional test results. . Moreover, the test sub-board 10 is used to load the chip to be tested, and the test sub-board 10 can be detachably connected to the HTOL test main board 30. This way, it is more helpful to reduce the cost of testing.
  • the test sub-board 10 includes a chip loading area 12 and a test connection area 13, the chip load area 12 is used to load the chips to be tested, and the test connection area 13 is provided with a mainboard connector;
  • the performance test mainboard 20 includes The main board substrate 21 and the sub-board connector 22 and the signal transmission port arranged on the main board substrate 21, the signal transmission port is electrically connected with the sub-board connector 22 through the signal connection line 25;
  • the signal transmission port is electrically connected to the chip to be tested on the test sub-board 10 .
  • the signal transmission port on the performance test main board 20 is connected to the test sub-board 10 .
  • the chip to be tested is electrically connected.
  • the test sub-board 10 loaded with the chip to be tested is attached to the performance test motherboard 20, and the chip to be tested on the test sub-board 10 is tested with the performance test.
  • the main board connectors on the sub-board connectors 22 on the main board 20 are electrically connected, thereby ensuring the feasibility of using the performance testing main board 20 for functional testing, making the functional testing process simple and convenient, and helping to reduce functional testing costs.
  • the preset target duration eg 128h, 256h, 512h or 1000h
  • the preset target duration can be 128h, 256h, 512h or 1000h
  • the chip to be tested is functionally tested, multiple sets of test data are obtained, and each set of test data is separated to determine which function of the chip to be tested has a problem, which is helpful for Guarantee the accuracy of chip testing.
  • the signal transmission port on the performance test motherboard 20 can be connected to the signal acquisition controller, so that the performance test motherboard 20 can perform functional tests on the chip to be tested under the control of the signal acquisition controller, collect functional test data, and The test data is sent to the signal acquisition controller.
  • the signal acquisition controller is a controller used to control the performance test main board 20 to perform functional tests on the chips to be tested loaded on the test daughter board 10.
  • the signal acquisition controller can Analyze functional test data and obtain functional test results. Functional testing in this example refers to the process of testing all the functions in the chip to be tested one by one.
  • the chip loading area 12 is provided with chip connection pins for connecting the chips to be tested;
  • the test connection area 13 is arranged on the periphery of the chip loading area 12, and the test connection area 13 is provided with a mainboard connector, which is connected to the mainboard.
  • the connection pins of the chip and the chip are electrically connected through the signal traces of the sub-board, and the main-board connectors include functional main-board probes; when the sub-board connectors 22 on the performance test main board 20 are attached to the functional main-board probes, the signal transmission port is The chips to be tested on the board 10 are electrically connected.
  • the sub-board substrate 11 of the test sub-board 10 is provided with a chip loading area 12 for loading the chips to be tested, and the chip loading area 12 is provided with chip connecting pins for connecting the chips to be tested. When on the chip loading area 12, it is electrically connected to the chip to be tested through the chip connection pins.
  • a test connection area 13 is provided on the periphery of the chip loading area 12, so that the chip to be tested can be loaded on the chip loading area 12, and the test connection area 13 is provided with a main board connector, the main board connector and the chip connection lead
  • the pins are electrically connected through the sub-board signal lines, and can be electrically connected to the performance test motherboard 20 through the motherboard connector.
  • the sub-board connector 22 on the performance test main board 20 is attached to the main board connector, so that the performance test main board 20 is electrically connected to the to-be-tested chip on the test sub-board 10 . Functional testing, ensuring the accuracy of functional testing results and reducing testing costs.
  • chip connection pins are provided on the chip loading area 12, and when the chip to be tested is loaded and fixed to the chip loading area 12 of the test sub-board 10, the chip connection pins are electrically connected to the chip to be tested, so that the The main board connector whose chip connection pins are connected through the sub-board signal lines is also electrically connected to the chip to be tested.
  • the sub-board connector 22 on the performance test main board 20 is attached to the main board connector on the test connection area 13 on the test sub-board 10, so that the performance test main board 20 is electrically connected to the chip to be tested on the test sub-board 10. Complete functional testing and collect functional testing data to ensure the smooth progress of the testing process.
  • the mainboard connector further includes HTOL mainboard probes; the test sub-board 10 further includes pin connectors electrically connected with the HTOL mainboard probes; daughter board interface.
  • the HTOL mainboard probe is a pin provided on the test sub-board 10 for connecting to the HTOL test mainboard 30 .
  • the pin connector is a connector set on the test sub-board 10 that matches the sub-board interface.
  • the sub-board interface refers to an interface provided on the HTOL test main board 30 for connecting to the test sub-board 10 .
  • at least one sub-board interface is provided on the HTOL test mainboard 30 , and each sub-board interface can be connected to one test sub-board 10 , so as to simultaneously perform HTOL testing on the chips to be tested loaded on the at least one test sub-board 10 .
  • the test sub-board 10 is provided with an HTOL main board probe for connecting the HTOL test main board 30 and a pin connector electrically connected to the HTOL main board probe.
  • the board 10 is detachably connected to the HTOL test mainboard 30 .
  • the pin connectors of the test sub-board 10 can be inserted into the sub-board interface of the HTOL test main board 30; after the HTOL test is completed , the pin connector of the test sub-board 10 needs to be pulled out from the sub-board interface of the HTOL test main board 30 , so that the test sub-board 10 can be detachably connected to the functional test board subsequently.
  • the detachable connection between the test daughter board 10 and the HTOL test main board 30 is realized by using the sub-board interface and the pin connector, which helps to ensure the feasibility of the HTOL test and the functional test.
  • the pin connector is disposed on the side of the test sub-board 10 .
  • the pin connectors can be arranged in the The side surface of the daughter board 10 is tested, that is, the side surface of the daughter board substrate 11 , so that the side surface of the daughter board substrate 11 can be detachably plugged into the HTOL test main board 30 .
  • the test sub-board 10 further includes a mainboard connection hole, and the functional mainboard probe is arranged on the periphery of the mainboard connection hole;
  • the chip test system further includes a signal probe, and the signal probe is assembled in the mainboard connection hole to make the performance
  • the performance test main board 20 is electrically connected to the chips to be tested on the test sub-board 10 .
  • the functional motherboard probe is a pin provided on the daughter board substrate 11 for connecting to the performance testing motherboard 20 .
  • the main board connection hole is a connection hole provided on the daughter board substrate 11 for connecting to the performance test main board 20 .
  • the functional motherboard probes are arranged at the periphery of the motherboard connection holes, that is, the function motherboard probes are arranged around the periphery of the motherboard connection holes, which helps to ensure the convenience of detachable connection between the test daughter board 10 and the performance test motherboard 20 .
  • the signal probe when the function test needs to be performed, the signal probe can be passed through the main board connection hole on the daughter board substrate 11, and under the clamping action of the external force, one end of the signal probe can be connected to the main board connection hole arranged on the periphery of the main board connection hole.
  • the function main board probe is connected, and the other end is connected to the sub-board connector 22 on the performance test main board 20, and the functional main board probe and the sub-board connector 22 are electrically connected through the signal probe, so as to realize the waiting on the test sub-board 10.
  • the test chip is electrically connected to the performance test motherboard 20, which helps to ensure the feasibility of the function test.
  • the chip testing system further includes a test pressing fixture, and the test pressing fixture includes a test base plate, a fixing plate, a sliding guide rail, a sliding connecting plate and a pressing assembly; the fixing plate is arranged on the test base plate in a vertical direction. ;
  • the sliding guide rail is assembled on the fixed plate and is perpendicular to the test bottom plate; the sliding connecting plate is connected with the sliding guide rail and can move along the sliding guide rail; and the accommodating gap of the performance test motherboard 20 .
  • the chip testing system further includes a test pressing fixture 40, and the test pressing fixture 40 includes a test base plate 41, a fixing plate 42, a sliding guide 43, a sliding connecting plate 44 and a pressing component 45; on the base plate 41; the sliding guide rail 43 is assembled on the fixed plate 42 and is perpendicular to the test base plate 41; the sliding connecting plate 44 is connected with the sliding guide rail 43 and can move along the sliding guide rail 43; the pressing assembly 45 is assembled on the sliding connecting plate 44, and An accommodating gap for accommodating the test sub-board 10 and the performance testing main board 20 is formed between the test base plates 41 .
  • the signal probes can be assembled in the connection holes of the main board, and then the test sub-board 10 and the performance test main board 20 are integrally placed between the press-fit assembly 45 and the test base plate 41 In the accommodating gap formed, the sliding connection plate 44 moves downward, and then the pressing assembly 45 is controlled to press the test sub-board 10 and the performance test main board 20, so that the signal probe is connected with the functional main board probe and the sub-board connector 22,
  • the electrical connection between the performance test main board 20 and the chip to be tested loaded on the test sub-board 10 is guaranteed, so as to ensure the reliability and stability of the functional test.
  • the present application provides a chip testing method, as shown in FIG. 4 , the chip testing method includes:
  • S1 Place the test sub-board in the HTOL test environment, so that the test duration of the test sub-board in the HTOL test environment reaches the target duration, wherein the chip loading area of the test sub-board is loaded with the chips to be tested.
  • test daughter board is attached to the performance test main board, so that the performance test board is electrically connected to the chip to be tested on the test daughter board, and the performance test of the chip to be tested is performed.
  • the target duration is a preset duration that the chip to be tested needs to be in the HTOL test environment.
  • the target duration can be set to 128h, 256h, 512h or 1000h, etc., which can be set independently according to actual needs.
  • step S1 the chip to be tested needs to be loaded on the sub-board 10 to be tested, and specifically, the chip to be tested may be welded or fixed on the sub-board 10 to be tested by other means.
  • place the test sub-board loaded with the chip to be tested in the HTOL test environment detect the test duration of the test sub-board in the HTOL test environment in real time, and determine whether the test duration of the test sub-board in the HTOL test environment reaches the target duration (eg 128h) ; When the test duration reaches the target duration, remove the test daughter board from the HOTL test environment.
  • the target duration eg 128h
  • step S2 the test sub-board 10 is attached to the performance test main board 20, and the chip to be tested on the test sub-board 10 is electrically connected to the performance test main board 20, that is, the sub-board on the performance test main board 20 is connected
  • the component 22 is attached to the test connection area 13 on the test sub-board 10 so as to be electrically connected to the chip to be tested on the test sub-board 10 .
  • the function test is performed on the chip to be tested through the performance test motherboard 20 .
  • a signal acquisition controller connected to the performance testing motherboard 20 may be used to control the performance testing motherboard 20 to complete the functional test of the chip to be tested.
  • the signal acquisition controller is used to send functional test instructions to the performance test mainboard 20, and the performance test mainboard 20 is controlled to perform functional tests on the chips to be tested, and the functional test data formed in the process of functional testing are collected and sent to the signal acquisition controller to make the signal
  • the acquisition controller analyzes the functional test data and obtains the functional test results.
  • step S2 the test sub-board is attached to the performance test main board, so that the performance test main board is electrically connected to the chip to be tested on the test sub-board, and the performance test of the to-be-tested chip is performed, which specifically includes: attaching the test sub-board to the test sub-board.
  • the board 10 is placed on the performance test main board 20, so that the sub-board connector 22 on the performance test main board 20 is aligned with the main board connector on the test connection area 13 in the test sub-board 10, and the performance test main board 20 and the test sub-board are aligned. 10.
  • the performance test motherboard 20 is electrically connected to the chip to be tested on the test sub-board 10 , and the performance test of the chip to be tested is performed.
  • the chip to be tested is loaded on the test sub-board 10 , and then the performance test main board 20 is attached to the test sub-board, so that the performance test main board 20 is compatible with the chips loaded on the test sub-board 10 .
  • the function test of the chip to be tested can determine which function of the chip to be tested has a problem, which helps to improve the accuracy of the functional test result.
  • the test sub-board 10 is used to load the chip to be tested, and then the test sub-board 10 is attached to the performance test main board 20. Compared with the socket connection, the test sub-board 10 is more helpful to reduce the test cost.

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Abstract

一种芯片测试组件、芯片测试系统和芯片测试方法。芯片测试组件包括测试子板(10)和性能测试主板(20)；测试子板(10)上包括芯片装载区(12)和测试连接区(13)，芯片装载区(12)用于装载待测试芯片，测试连接区(13)上设有主板连接件；性能测试主板(20)上包括主板基板(21)和设置在主板基板(21)上的子板连接件(22)和信号传输端口，信号传输端口通过信号连接线(25)与子板连接件(22)电连接；当性能测试主板(20)上的子板连接件(22)与测试子板(10)中的测试连接区(13)上的主板连接件贴合时，信号传输端口与测试子板(10)上的待测试芯片实现电连接。芯片测试组件有助于保障测试准确性并降低测试成本。

Description

芯片测试组件、芯片测试系统和芯片测试方法
本申请要求以2020年12月31日提交的申请号为202011642087.4，名称为“芯片测试组件、芯片测试系统和芯片测试方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片测试技术领域，尤其涉及一种芯片测试组件、芯片测试系统和芯片测试方法。
背景技术
高温操作生命期试验(HighTemperatureOperatingLife，简称HTOL)可用于评估器件在超热和超电压情况下一段时间的耐久力，是当前芯片测试常用的一项检测手段，其失效机制主要包括电子迁移、氧化层破裂、相互扩散、不稳定性和离子玷污等。目前，现有HTOL测试方案大多是通过使用socket装载芯片进行测试，即先将待测试芯片固定装载于socket上，然后将多个socket焊接于主板上，最后将主板放入高温烤箱中进行HTOL测试。然而，由于socket的成本较高，而在进行批量HTOL测试，达到Socket使用寿命(一般是3～5次)之后，就需要更换Socket，从而导致采用socket批量测试时成本很高。另外，由于在将焊接有待测试芯片的主板放入高温烤箱中进行HTOL测试之后，只能得出主板中的哪一个待测试芯片出现问题，但无法准确得到待测试芯片出现问题的具体原因，即当前对待测试芯片进行测试时，无法保障其测试结果的准确性，且其测试过程成本较高。
发明内容
本申请提供一种芯片测试组件、芯片测试系统和芯片测试方法，以解决现有芯片测试成本较高且无法保障其测试准确性的问题。
本申请提供一种芯片测试组件，包括测试子板和性能测试主板；
所述测试子板上包括芯片装载区和测试连接区，所述芯片装载区用于装载待测试芯片，所述测试连接区上设有主板连接件；
所述性能测试主板上包括主板基板和设置在所述主板基板上的子板连接件和信号传 输端口，所述信号传输端口通过信号连接线与所述子板连接件电连接；
当所述性能测试主板上的子板连接件与所述测试子板中的所述测试连接区上的主板连接件贴合时，所述信号传输端口与所述测试子板上的待测试芯片实现电连接。
优选地，所述主板连接件为主板连接探针，所述子板连接件为子板连接端子，或者，所述主板连接件为主板连接端子，所述子板连接件为子板连接探针。
优选地，所述芯片装载区设有用于连接所述待测试芯片的芯片连接引脚；
所述测试连接区，设置在所述芯片装载区的外围，所述测试连接区上的所述主板连接件与所述芯片连接引脚通过所述子板信号走线电连接。
本申请提供一种芯片测试系统，包括测试子板和性能测试主板；所述测试子板，用于装载待测试芯片；当所述性能测试主板与所述测试子板贴合时，所述性能测试主板与所述测试子板上的待测试芯片实现电连接。
优选地，所述芯片测试系统还包括HTOL测试主板，所述HTOL测试主板，与所述测试子板可拆卸连接，并与所述测试子板上的待测试芯片电连接，用于对所述待测试芯片进行HTOL测试。
优选地，所述测试子板上设有芯片装载区和测试连接区，所述芯片装载区用于装载所述待测试芯片，所述测试连接区上设有主板连接件；
所述性能测试主板上包括主板基板和设置在所述主板基板上的子板连接件和信号传输端口，所述信号传输端口通过信号连接线与所述子板连接件电连接；
当所述性能测试主板上的子板连接件与所述测试子板中的测试连接区上的主板连接件贴合时，所述信号传输端口与所述测试子板上的待测试芯片电连接。
优选地，所述芯片装载区设有用于连接所述待测试芯片的芯片连接引脚；
所述测试连接区，设置在所述芯片装载区的外围，且所述测试连接区设有主板连接件，所述主板连接件与所述芯片连接引脚通过所述子板信号走线电连接，所述主板连接件包括功能主板探针；
当所述性能测试主板上的子板连接件与所述功能主板探针贴合时，所述信号传输端口与所述测试子板上的待测试芯片电连接。
优选地，所述主板连接件还包括HTOL主板探针；
所述测试子板还包括与所述HTOL主板探针电连接的引脚插接件；
所述HTOL测试主板上设有与所述引脚插接件相匹配的子板接口。
优选地，所述引脚插接件设置在所述测试子板的侧面。
优选地，所述测试子板还包括主板连接孔，所述功能主板探针设置在所述主板连接孔外围；
所述芯片测试系统还包括信号探针，所述信号探针装配在所述主板连接孔内，用于使所述性能测试主板上的子板连接件与所述测试子板上的功能主板探针贴合时，使所述性能测试主板与所述测试子板上的待测试芯片实现电连接。
优选地，所述芯片测试系统还包括测试压合治具，所述测试压合治具包括测试底板、固定板、滑动导轨、滑动连接板和压合组件；所述固定板沿垂直方向设置在所述测试底板上；所述滑动导轨装配在所述固定板上，与所述测试底板垂直；所述滑动连接板与所述滑动导轨相连，可沿所述滑动导轨运动；所述压合组件装配在所述滑动连接板上，与所述测试底板之间形成容置所述测试子板和所述性能测试主板的容置间隙。
本申请提供一种芯片测试方法，包括：
将测试子板放置在HTOL测试环境中，使所述测试子板在所述HTOL测试环境的测试时长达到目标时长，所述测试子板的芯片装载区装载有待测试芯片；
将所述测试子板贴合到性能测试主板上，使所述性能测试主板与所述测试子板上的待测试芯片电连接，对所述待测试芯片进行性能测试。
优选地，将所述测试子板贴合到性能测试主板上，使所述性能测试主板与所述测试子板上的待测试芯片电连接，包括：
将所述测试子板放置在所述性能测试主板上，使所述性能测试主板上的子板连接件与所述测试子板中的测试连接区上的主板连接件对准，将所述性能测试主板和所述测试子板，放置到测试压合治具的测试底板与压合组件之间的容置间隙内，控制所述压合组件向所述测试底板方向压合，以将所述测试子板贴合到性能测试主板上，使所述性能测试主板与所述测试子板上的待测试芯片电连接，对所述待测试芯片进行性能测试。
上述芯片测试组件、芯片测试系统和芯片测试方法，将待测试芯片装载在测试子板上，所述性能测试主板上的子板连接件通过与所述测试子板上的测试连接区上的主板连接件贴合，以跟所述测试子板上的待测试芯片电连接，保障功能测试的可行性。采用所述性能测试主板对装载在所述测试子板上的待测试芯片进行功能测试，可确定所述待测试芯片中哪个功能出现问题，有助于提高功能测试结果的准确性。而且，利用测试子板装载待测试芯片，再将测试子板贴合到性能测试主板上，相比采用socket连接方式，采用测试子板的方式，更有助于降低测试成本。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例中测试子板的一示意图；
图2是本申请一实施例中性能测试主板的一示意图；
图3是本申请一实施例中测试压合治具的一示意图；
图4是本申请一实施例中芯片测试方法的一流程图。
图中：10、测试子板；11、子板基板；12、芯片装载区；13、测试连接区；20、性能测试主板；21、主板基板；22、子板连接件；23、信号输入端口；24、信号输出端口；25、信号连接线；30、HTOL测试主板；40、测试压合治具；41、测试底板；42、固定板；43、滑动导轨；44、滑动连接板；45、压合组件。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请 教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的结构及步骤，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
本申请实施例提供一种芯片测试组件，包括测试子板10和性能测试主板20；测试子板10上包括芯片装载区12和测试连接区13，芯片装载区12用于装载待测试芯片，测试连接区13上设有主板连接件；性能测试主板20上包括主板基板21和设置在主板基板21上的子板连接件22和信号传输端口，信号传输端口通过信号连接线25与子板连接件22电连接；当性能测试主板20上的子板连接件22与测试子板10中的测试连接区13上的主板连接件贴合时，信号传输端口与测试子板10上的待测试芯片实现电连接。
其中，测试子板10是用于装载待测试芯片的子板。本示例中，测试子板10包括子板基板11，子板基板11上设有芯片装载区12和测试连接区13。子板基板11是指测试子板10的基板。芯片装载区12是用于装载放置待测试芯片的区域。测试连接区13是用于实现待测试芯片与测试主板电连接的区域。测试连接区13上设有主板连接件，该主板连接件是用于实现连接性能测试主板20的部件。
其中，性能测试主板20是用于实现功能测试的主板，具体可以理解为对待测试芯片 能否实现具体功能进行测试的主板。性能测试主板20上包括主板基板21和设置在主板基板21上的子板连接件22。子板连接件22是设置在性能测试主板20上的用于实现与测试子板10电连接的部件。信号传输端口是性能测试主板上设置的用于与外部电路通信的管脚。性能测试主板20上还设有信号传输端口，信号传输端口通过信号连接线25与子板连接件22电连接，用于控制待测试芯片进行功能测试。本示例中，信号传输端口包括信号输入端口23和信号输出端口24，用于接收输入信号和发送输出信号。
在一具体实施例中，所述主板连接件为主板连接探针，所述子板连接件为子板连接端子，即当主板连接件为主板连接探针时，子板连接件为子板连接端子，当所述性能测试主板上的子板连接端子与所述测试子板中的所述测试连接区上的主板连接探针贴合时，所述信号传输端口与所述测试子板上的待测试芯片实现电连接
在一具体实施例中，所述主板连接件为主板连接端子，所述子板连接件为子板连接探针。即当主板连接件为主板连接端子时，子板连接件为子板连接探针，当所述性能测试主板上的子板连接探针与所述测试子板中的所述测试连接区上的主板连接端子贴合时，所述信号传输端口与所述测试子板上的待测试芯片实现电连接。
本示例中，当性能测试主板20上的子板连接件22与测试子板10上的测试连接区13上的主板连接件贴合时，性能测试主板20上的信号传输端口与测试子板10上的待测试芯片实现电连接，在需要对待测试芯片进行功能测试时，将装载有待测试芯片的测试子板10贴合到性能测试主板20上，测试子板10上的待测试芯片与性能测试主板20上的子板连接件22上的主板连接件电连接，从而保障利用性能测试主板20进行功能测试的可行性，使得功能测试过程简单方便，有助于降低功能测试成本。例如，在HTOL测试过程中，可在待测试芯片处于HTOL测试环境中的测试时长达到预先设置的目标时长(如128h、256h、512h或者1000h)之后，再分别对经预先设置的目标时长(如128h、256h、512h或者1000h)HTOL测试后的待测试芯片进行功能测试，获取多组测试数据，再通对每一组测试数据进行分别，从而确定待测试芯片中哪个功能出现问题，有助于保障芯片测试的准确性。
作为一示例，性能测试主板20上的信号传输端口可与信号采集控制器相连，以使性能测试主板20在信号采集控制器的控制下，对待测试芯片进行功能测试，采集功能测试数据，将功能测试数据发送给信号采集控制器。其中，信号采集控制器是用于控制性能测试主板20对测试子板10上装载的待测试芯片进行功能测试的控制器，该信号采集控制器可采集功能测试过程中形成的功能测试数据，对功能测试数据进行分析，获取功能测试结果。本示例中的功能测试是指对待测试芯片中的所有功能逐一进行测试的过程。
本示例中，利用上述芯片测试组件对待测试芯片进行功能测试过程具体包括如下步骤：
将待测试芯片装载在测试子板10上，具体可以将待测试芯片焊接或者采用其他方式固定在待测试子板10上。
在需要对待测试芯片进行功能测试时，如在待测试芯片处于HTOL测试环境中的测试时长达到预先设置的目标时长(如128h、256h、512h或者1000h)后，可经预先设置的目标时长(如128h、256h、512h或者1000h)HTOL测试后的将测试子板10贴合到性能测试主板20上，将测试子板10上的待测试芯片与性能测试主板20电连接，即性能测试主板20上的子板连接件22通过与测试子板10上的测试连接区13上的主板连接件贴合时，与测试子板10上的待测试芯片电连接。
再将性能测试主板20的信号传输端口与信号采集控制器电连接。
采用信号采集控制器给性能测试主板20发送功能测试指令，控制性能测试主板20对待测试芯片进行功能测试，采集功能测试过程中形成的功能测试数据，将发送给信号采集控制器，以使信号采集控制器对功能测试数据进行分析，获取功能测试结果。例如，若待测试芯片预先配置有A、B、C和D四个功能，则信号采集控制器需向性能测试主板20发送这四个功能对应的功能测试指令，分别采集这四个功能在测试过程中形成的测试数据，以获取功能测试数据
本实施例中所提供的芯片测试组件中，将待测试芯片装载在测试子板10上，性能测试主板20上的子板连接件22通过与测试子板10中的测试连接区13上的主板连接件贴合时，跟测试子板10上的待测试芯片电连接，保障功能测试的可行性。采用性能测试主板20对装载在测试子板10上的待测试芯片进行功能测试，可确定待测试芯片中哪个功能出现问题，有助于提高功能测试结果的准确性。而且，利用测试子板10装载待测试芯片，再将测试子板10贴合到性能测试主板20上，相比采用socket连接方式，采用测试子板10的方式，更有助于降低测试成本。
在一实施例中，芯片装载区12设有用于连接待测试芯片的芯片连接引脚；测试连接区13，设置在芯片装载区12的外围，测试连接区13上的主板连接件与芯片连接引脚通过子板信号走线电连接。
作为一示例，在测试子板10的子板基板11上设置用于装载待测试芯片的芯片装载区12，芯片装载区12设有用于连接待测试芯片的芯片连接引脚，在待测试芯片装载在片装载区12上时，通过芯片连接引脚与待测试芯片电连接。
作为一示例，在芯片装载区12的外围设置有测试连接区13，可实现将待测试芯片装载在芯片装载区12上，且测试连接区13设有主板连接件，主板连接件与芯片连接引脚通过子板信号走线电连接，可通过主板连接件与性能测试主板20电连接。本示例中，性能测试主板20上的子板连接件22通过与主板连接件贴合，以跟测试子板10上的待测试芯片电连接，利用性能测试主板20，对待测试芯片进行功能测试，保障功能测试结果的准确性并降低测试成本。
本示例中，在芯片装载区12上设有芯片连接引脚，将待测试芯片装载固定到测试子板10的芯片装载区12时，使得芯片连接引脚与待测试芯片电连接，从而使与芯片连接引脚通过子板信号走线相连的主板连接件也与待测试芯片电连接。当性能测试主板20上的子板连接件22通过与测试子板10上的测试连接区13上的主板连接件贴合时，性能测试主板20与测试子板10上的待测试芯片电连接，可完成功能测试并采集功能测试数据，从而保障测试过程的顺利进行。
在一实施例中，待测试芯片包括芯片基板和设置在芯片基板上的芯片电路，芯片基板上设有与芯片连接引脚相对应的芯片连接孔，芯片连接孔外围设有与芯片电路相连的芯片连接环；采用焊接件穿过芯片连接孔焊接到芯片连接引脚上，以使待测试芯片上的芯片连接环与测试子板10上的芯片连接引脚电连接。
其中，芯片基板是待测试芯片的基板。芯片电路是设置在芯片基板上的芯片和外围元器件所形成的电路。芯片连接孔是设置在芯片基板上的连接孔，用于实现与测试子板10连接。芯片连接环是采用导电材料围绕芯片连接孔设置形成的环形结构。焊接件是采用导电金属材料进行焊接形成的结构件。
本示例中，在需要将待测试芯片装载在芯片基板时，可采用焊接件穿过芯片连接孔焊接到芯片连接引脚上，通过焊接件使芯片连接环与芯片连接引脚电连接，以实现将待测试芯片装载并固定在测试子板10上并与测试子板10电连接的目的。可理解地，与传统socket连接待测试子板10的方式相比，将待测试芯片焊接在测试子板10上，可有效降低其测试成本。
作为一示例，芯片连接引脚包括芯片输入引脚和芯片输出引脚，芯片连接孔包括第一连接孔和第二连接孔，第一连接孔外围设有与芯片电路的输入端相连的第一连接环，第二连接孔外围设有与芯片电路的输出端相连的第二连接环；采用焊接件穿过第一连接孔焊接在芯片输入引脚上，使第一连接环与芯片输入引脚电连接，采用焊接件穿过第二连接孔焊接在芯片输出引脚上，使第二连接环与芯片输出引脚电连接。
本示例中，测试子板10上的芯片连接引脚包括芯片输入引脚和芯片输出引脚。HTOL测试主板30上的芯片连接孔包括第一连接孔和第二连接孔，第一连接孔外围设有与芯片电路的输入端相连的第一连接环，第二连接孔外围设有与芯片电路的输出端相连的第二连接环。在焊接件穿过第一连接孔焊接到测试子板10的芯片输入引脚时，可使第一连接环与芯片输入引脚电连接，进而使得芯片电路的输入端与芯片输入引脚电连接；相应地，在焊接件穿过第二连接孔焊接到测试子板10的芯片输出引脚时，可使第二连接环与芯片输出引脚电连接，进而使得芯片电路的输出端与芯片输出引脚电连接。
本申请实施例提供一种芯片测试系统，包括测试子板10和性能测试主板20；测试子板10，用于装载待测试芯片；当性能测试主板20与测试子板10贴合时，性能测试主板20与测试子板10上的待测试芯片实现电连接。
作为一示例，利用芯片测试系统进行功能测试过程如下：首先，将待测试芯片装载在测试子板10上，具体可以将待测试芯片焊接或者采用其他方式固定在待测试子板10上。接着，在满足功能测试条件，如待测试芯片处于HTOL测试环境中的测试时长达到预先设置的目标时长(如128h、256h、512h或者1000h)之后，将测试子板10贴合到性能测试主板20上，将测试子板10上的待测试芯片与性能测试主板20电连接。最后，通过性能测试主板20对待测试芯片进行功能测试。例如，可采用与性能测试主板20相连的信号采集控制器，控制性能测试主板20完成对待测试芯片的功能测试。即采用信号采集控制器给性能测试主板20发送功能测试指令，控制性能测试主板20对待测试芯片进行功能测试，采集功能测试过程中形成的功能测试数据，将发送给信号采集控制器，以使信号采集控制器对功能测试数据进行分析，获取功能测试结果。
本实施例所提供的芯片测试系统，将待测试芯片装载在测试子板10上，再将性能测试主板20贴合到测试子板上，使性能测试主板20对装载在测试子板10上的待测试芯片进行功能测试，可确定待测试芯片中哪个功能出现问题，有助于提高功能测试结果的准确性。而且，利用测试子板10装载待测试芯片，再将测试子板10贴合到性能测试主板20上，相比采用socket连接方式，采用测试子板10的方式，更有助于降低测试成本。
在一实施例中，芯片测试系统还包括HTOL测试主板30，HTOL测试主板30，与测试子板10可拆卸连接，并与测试子板10上的待测试芯片电连接，用于对待测试芯片进行HTOL测试。
其中，HTOL测试主板30，是用于实现HTOL测试的主板，具体可以理解为对待测试芯片能否满足HTOL测试需求的主板。HTOL测试主板30可与测试子板10可拆卸连接，可实 现在待测试芯片处于HTOL测试环境中的测试时长达到预先设置的目标时长(如128h、256h、512h或者1000h)且完成HTOL测试之后，将测试子板10从HTOL测试主板30中取出，利用性能测试主板20对待测试芯片进行功能测试；在每次完成功能测试之后，还可再将测试子板10与HTOL测试主板可拆卸连接，重复执行上述过程，从而保障HTOL测试的准确性。
本示例中，HTOL测试主板30需与信号采集控制器相连，利用信号采集控制器控制HTOL测试主板30对测试子板10上装载的待测试芯片进行HTOL测试，采集HTOL测试过程中形成的HTOL测试数据，对HTOL测试数据进行分析，获取HTOL测试结果。
采用该芯片测试系统进行HTOL测试过程，具体包括如下步骤：
(1)将待测试芯片装载在测试子板10上，具体可以将待测试芯片焊接或者采用其他方式固定在待测试子板10上。
(2)将测试子板10可拆卸连接在HTOL测试主板30上，将测试子板10上的待测试芯片与HTOL测试主板30电连接，将HTOL测试主板30及测试子板10整体放置在HTOL测试环境中，在待测试芯片处于HTOL测试环境中的测试时长达到预先设置的目标时长(如128h、256h、512h或者1000h)后，将HTOL测试主板30从HTOL测试环境中取出，将HTOL测试主板30与信号采集控制器电连接，利用信号采集控制器控制HTOL测试主板30对待测试芯片进行HTOL测试。例如，利用信号采集控制器给HTOL测试主板30发送HTOL测试指令，控制HTOL测试主板30对待测试芯片进行HTOL测试，采集HTOL测试过程中形成的HTOL测试数据，将HTOL测试数据发送给信号采集控制器。
再将测试子板10从HTOL测试主板30上拆卸下来，将测试子板10贴合到性能测试主板20上，将测试子板10上的待测试芯片与性能测试主板20电连接，即性能测试主板20上的子板连接件22与测试子板10上的测试连接区13上的主板连接件贴合时，性能测试主板20与测试子板10上的待测试芯片实现电连接，将测试子板10信号采集控制器电连接，利用信号采集控制器控制性能测试主板20对待测试芯片进行功能测试。例如，利用信号采集控制器给性能测试主板20发送功能测试指令，控制性能测试主板20对待测试芯片进行功能测试，采集功能测试过程中形成的功能测试数据，将功能测试数据发送给信号采集控制器。
重复执行多次上述步骤(2)-(5)，即在待测试芯片处于HTOL测试环境中的测试时长达到128h、256h、512h或者1000h等目标时长之后，分别进行一次HTOL测试和功能测试，从而采集到多组HTOL测试数据和功能测试数据，对所有HTOL测试数据进行分析，获 取HTOL测试结果，并对所有功能测试数据进行分析，可获取功能测试结果。
本示例中，HTOL测试数据是指待测试芯片在超热或者超高压环境下一段时间后进行HTOL测试，以检测其耐久力的测试数据，可通过对HTOL测试数据进行耐久力分析，若HTOL测试数据中反馈的耐久力不满足预设耐久力要求，则认定待测试芯片不满足HTOL测试要求，获取测试不通过的HTOL测试结果；反之，若HTOL测试数据中反馈的耐久力满足预设耐久力要求，则认定待测试芯片满足HTOL测试要求，获取测试通过的HTOL测试结果。采用性能测试主板20对装载在测试子板10上的待测试芯片进行功能测试，可确定待测试芯片中哪个功能出现问题，有助于提高功能测试结果的准确性。
本实施例中，将待测试芯片装载在测试子板10上，利用测试子板10可拆卸连接HTOL测试主板30上，对待测试芯片进行HTOL测试，采集HTOL测试过程中形成的HTOL测试数据，获取HTOL测试结果，可理解地，采用HTOL测试主板30对装载在测试子板10上的待测试芯片进行HTOL测试，可确定待测试芯片不满足HTOL测试要求，有助于提高功能测试结果的准确性。而且，利用测试子板10装载待测试芯片，该测试子板10可以可拆卸连接在HTOL测试主板30上，相比采用socket将待测试芯片HTOL测试主板30的传统方式，采用测试子板10的方式，更有助于降低测试成本。
在一实施例中，测试子板10上包括芯片装载区12和测试连接区13，芯片装载区12用于装载待测试芯片，测试连接区13上设有主板连接件；性能测试主板20上包括主板基板21和设置在主板基板21上的子板连接件22和信号传输端口，信号传输端口通过信号连接线25与子板连接件22电连接；当性能测试主板20上的子板连接件22与测试子板10中的测试连接区13上的主板连接件贴合时，信号传输端口与测试子板10上的待测试芯片实现电连接。
本示例中，当性能测试主板20上的子板连接件22与测试子板10上的测试连接区13上的主板连接件贴合时，性能测试主板20上的信号传输端口与测试子板10上的待测试芯片实现电连接，在需要对待测试芯片进行功能测试时，将装载有待测试芯片的测试子板10贴合到性能测试主板20上，测试子板10上的待测试芯片与性能测试主板20上的子板连接件22上的主板连接件电连接，从而保障利用性能测试主板20进行功能测试的可行性，使得功能测试过程简单方便，有助于降低功能测试成本。例如，在HTOL测试过程中，可在待测试芯片处于HTOL测试环境中的测试时长达到预先设置的目标时长(如128h、256h、512h或者1000h)之后，再分别对经预先设置的目标时长(如128h、256h、512h或者1000h)HTOL测试后的待测试芯片进行功能测试，获取多组测试数据，再通对每一组测试数据进行 分别，从而确定待测试芯片中哪个功能出现问题，有助于保障芯片测试的准确性。
作为一示例，性能测试主板20上的信号传输端口可与信号采集控制器相连，以使性能测试主板20在信号采集控制器的控制下，对待测试芯片进行功能测试，采集功能测试数据，将功能测试数据发送给信号采集控制器。其中，信号采集控制器是用于控制性能测试主板20对测试子板10上装载的待测试芯片进行功能测试的控制器，该信号采集控制器可采集功能测试过程中形成的功能测试数据，对功能测试数据进行分析，获取功能测试结果。本示例中的功能测试是指对待测试芯片中的所有功能逐一进行测试的过程。
在一实施例中，芯片装载区12设有用于连接待测试芯片的芯片连接引脚；测试连接区13，设置在芯片装载区12的外围，且测试连接区13设有主板连接件，主板连接件与芯片连接引脚通过子板信号走线电连接，主板连接件包括功能主板探针；性能测试主板20上的子板连接件22与功能主板探针贴合时，信号传输端口与测试子板10上的待测试芯片电连接。
作为一示例，在测试子板10的子板基板11上设置用于装载待测试芯片的芯片装载区12，芯片装载区12设有用于连接待测试芯片的芯片连接引脚，在待测试芯片装载在片装载区12上时，通过芯片连接引脚与待测试芯片电连接。
作为一示例，在芯片装载区12的外围设置有测试连接区13，可实现将待测试芯片装载在芯片装载区12上，且测试连接区13设有主板连接件，主板连接件与芯片连接引脚通过子板信号走线电连接，可通过主板连接件与性能测试主板20电连接。本示例中，性能测试主板20上的子板连接件22与主板连接件贴合，使得性能测试主板20与测试子板10上的待测试芯片电连接，利用性能测试主板20，对待测试芯片进行功能测试，保障功能测试结果的准确性并降低测试成本。
本示例中，在芯片装载区12上设有芯片连接引脚，将待测试芯片装载固定到测试子板10的芯片装载区12时，使得芯片连接引脚与待测试芯片电连接，从而使与芯片连接引脚通过子板信号走线相连的主板连接件也与待测试芯片电连接。性能测试主板20上的子板连接件22与测试子板10上的测试连接区13上的主板连接件贴合，以使性能测试主板20与测试子板10上的待测试芯片电连接，可完成功能测试并采集功能测试数据，从而保障测试过程的顺利进行。
在一实施例中，主板连接件还包括HTOL主板探针；测试子板10还包括与HTOL主板探针电连接的引脚插接件；HTOL测试主板上设有与引脚插接件相匹配的子板接口。
其中，HTOL主板探针是测试子板10上设置的用于连接HTOL测试主板30的引脚。引 脚插接件是设置在测试子板10上的与子板接口相匹配的插接件。
其中，子板接口是指设置在HTOL测试主板30上的用于连接测试子板10的接口。作为一示例，在HTOL测试主板30上设置至少一个子板接口，每一子板接口可连接一个测试子板10，以实现对至少一个测试子板10上装载的待测试芯片同时进行HTOL测试。
测试子板10上设有用于连接HTOL测试主板30的HTOL主板探针以及与HTOL主板探针电连接的引脚插接件，该引脚插接件与子板接口相匹配，以将测试子板10可拆卸连接在HTOL测试主板30上。例如，在需要将测试子板10固接在HTOL测试主板30上进行HTOL测试时，可将测试子板10的引脚插接件插入HTOL测试主板30的子板接口中；在HTOL测试完成后，需将测试子板10的引脚插接件从HTOL测试主板30的子板接口中拔出，以便后续将测试子板10可拆卸连接到功能测试板上。可理解地，采用子板接口与引脚插接件配合的方式，实现测试子板10与HTOL测试主板30的可拆卸连接，有助于保障HTOL测试和功能测试的可行性。
在一实施例中，引脚插接件设置在测试子板10的侧面。
由于测试子板10既需要与HTOL测试主板30可拆卸连接，又要与性能测试主板20可拆卸连接，为了方便测试子板10与性能测试主板20的连接，可将引脚插接件设置在测试子板10的侧面，即子板基板11的侧面，以使子板基板11的侧面可拆卸插接到HTOL测试主板30上。
在一实施例中，测试子板10还包括主板连接孔，功能主板探针设置在主板连接孔外围；芯片测试系统还包括信号探针，信号探针装配在主板连接孔内，用于使性能测试主板20上的子板连接件22通与测试子板10上的功能主板探针贴合时，使性能测试主板20与测试子板10上的待测试芯片实现电连接。
其中，功能主板探针是子板基板11上设置的用于连接性能测试主板20的引脚。主板连接孔是设置在子板基板11上的用于连接性能测试主板20的连接孔。本示例中，功能主板探针设置在主板连接孔外围，即功能主板探针环绕主板连接孔外围设置，有助于保障测试子板10与性能测试主板20可拆卸连接的便捷性。
本示例中，在需要进行功能测试时，可将信号探针穿过子板基板11上的主板连接孔，在外力的夹紧作用下，使得信号探针的一端与设置在主板连接孔外围的功能主板探针相连，另一端与性能测试主板20上的子板连接件22相连，通过信号探针实现功能主板探针和子板连接件22电连接，从而实现装载在测试子板10上的待测试芯片与性能测试主板20电连接，有助于保障功能测试的可行性。
在一实施例中，芯片测试系统还包括测试压合治具，测试压合治具包括测试底板、固定板、滑动导轨、滑动连接板和压合组件；固定板沿垂直方向设置在测试底板上；滑动导轨装配在固定板上，与测试底板垂直；滑动连接板与滑动导轨相连，可沿滑动导轨运动；压合组件装配在滑动连接板上，与测试底板之间形成容置测试子板10和性能测试主板20的容置间隙。
芯片测试系统还包括测试压合治具40，测试压合治具40包括测试底板41、固定板42、滑动导轨43、滑动连接板44和压合组件45；固定板42沿垂直方向设置在测试底板41上；滑动导轨43装配在固定板42上，与测试底板41垂直；滑动连接板44与滑动导轨43相连，可沿滑动导轨43运动；压合组件45装配在滑动连接板44上，与测试底板41之间形成容置测试子板10和性能测试主板20的容置间隙。
本示例中，在需要对待测试芯片进行功能测试时，可将信号探针装配在主板连接孔内，再将测试子板10和性能测试主板20整体放置在压合组件45与测试底板41之间形成的容置间隙内，滑动连接板44向下移动，再控制压合组件45压紧测试子板10和性能测试主板20，以使信号探针与功能主板探针和子板连接件22相连，从而保障性能测试主板20与测试子板10上装载的待测试芯片的电连接，以保障功能测试的可靠性和稳定性。
本申请提供一种芯片测试方法，如图4所示，芯片测试方法包括：
S1：将测试子板放置在HTOL测试环境中，使所述测试子板在所述HTOL测试环境的测试时长达到目标时长，其中，所述测试子板的芯片装载区装载有待测试芯片。
S2：将测试子板贴合到性能测试主板上，使性能测试主板与测试子板上的待测试芯片电连接，对待测试芯片进行性能测试。
其中，目标时长是预先设置的需要待测试芯片在HTOL测试环境中的时长。例如，目标时长可以设置为128h、256h、512h或者1000h等，可根据实际需求自主设置。
作为一示例，步骤S1中，需将待测试芯片装载在测试子板10上，具体可以将待测试芯片焊接或者采用其他方式固定在待测试子板10上。接着，将装载有待测试芯片的测试子板放置在HTOL测试环境中，实时检测测试子板在HTOL测试环境的测试时长，判断测试子板在HTOL测试环境的测试时长是否达到目标时长(如128h)；测试时长达到目标时长，则将测试子板从HOTL测试环境中取出。
作为一示例，步骤S2中，将测试子板10贴合到性能测试主板20上，将测试子板10上的待测试芯片与性能测试主板20电连接，即性能测试主板20上的子板连接件22通过与测试子板10上的测试连接区13贴合，以跟测试子板10上的待测试芯片电连接。最后， 通过性能测试主板20对待测试芯片进行功能测试。例如，可采用与性能测试主板20相连的信号采集控制器，控制性能测试主板20完成对待测试芯片的功能测试。即采用信号采集控制器给性能测试主板20发送功能测试指令，控制性能测试主板20对待测试芯片进行功能测试，采集功能测试过程中形成的功能测试数据，将发送给信号采集控制器，以使信号采集控制器对功能测试数据进行分析，获取功能测试结果。
在一实施例中，步骤S2，即将测试子板贴合到性能测试主板上，使性能测试主板与测试子板上的待测试芯片电连接，对待测试芯片进行性能测试，具体包括：将测试子板10放置在性能测试主板20上，使性能测试主板20上的子板连接件22与测试子板10中的测试连接区13上的主板连接件对准，将性能测试主板20和测试子板10，放置到测试压合治具40的测试底板41与压合组件45之间的容置间隙内，控制压合组件45向测试底板41方向压合，以将测试子板10贴合到性能测试主板20上，使性能测试主板20与测试子板10上的待测试芯片电连接，对待测试芯片进行性能测试。
本实施例所提供的芯片测试方法，将待测试芯片装载在测试子板10上，再将性能测试主板20贴合到测试子板上，使性能测试主板20对装载在测试子板10上的待测试芯片进行功能测试，可确定待测试芯片中哪个功能出现问题，有助于提高功能测试结果的准确性。而且，利用测试子板10装载待测试芯片，再将测试子板10贴合到性能测试主板20上，相比采用socket连接方式，采用测试子板10的方式，更有助于降低测试成本。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (13)

  1. 一种芯片测试组件，其特征在于，包括测试子板和性能测试主板；
    所述测试子板上包括芯片装载区和测试连接区，所述芯片装载区用于装载待测试芯片，所述测试连接区上设有主板连接件；
    所述性能测试主板上包括主板基板和设置在所述主板基板上的子板连接件和信号传输端口，所述信号传输端口通过信号连接线与所述子板连接件电连接；
    当所述性能测试主板上的子板连接件与所述测试子板中的所述测试连接区上的主板连接件贴合时，所述信号传输端口与所述测试子板上的待测试芯片实现电连接。
  2. 如权利要求1所述的芯片测试组件，其特征在于，所述主板连接件为主板连接探针，所述子板连接件为子板连接端子，或者，所述主板连接件为主板连接端子，所述子板连接件为子板连接探针。
  3. 如权利要求1所述的芯片测试组件，其特征在于，所述芯片装载区设有用于连接所述待测试芯片的芯片连接引脚；
    所述测试连接区，设置在所述芯片装载区的外围，所述测试连接区上的所述主板连接件与所述芯片连接引脚通过所述子板信号走线电连接。
  4. 一种芯片测试系统，其特征在于，包括测试子板和性能测试主板；所述测试子板，用于装载待测试芯片；当所述性能测试主板与所述测试子板贴合时，所述性能测试主板与所述测试子板上的待测试芯片实现电连接。
  5. 如权利要求4所述的芯片测试系统，其特征在于，所述芯片测试系统还包括HTOL测试主板，所述HTOL测试主板，与所述测试子板可拆卸连接，并与所述测试子板上的待测试芯片电连接，用于对所述待测试芯片进行HTOL测试。
  6. 如权利要求5所述的芯片测试系统，其特征在于，所述测试子板上设有芯片装载区和测试连接区，所述芯片装载区用于装载所述待测试芯片，所述测试连接区上设有主板连接件；
    所述性能测试主板上包括主板基板和设置在所述主板基板上的子板连接件和信号传输端口，所述信号传输端口通过信号连接线与所述子板连接件电连接；
    当所述性能测试主板上的子板连接件与所述测试子板中的测试连接区上的主板连接件贴合时，所述信号传输端口与所述测试子板上的待测试芯片电连接。
  7. 如权利要求6所述的芯片测试系统，其特征在于，所述芯片装载区设有用于连接所 述待测试芯片的芯片连接引脚；
    所述测试连接区，设置在所述芯片装载区的外围，且所述测试连接区设有主板连接件，所述主板连接件与所述芯片连接引脚通过所述子板信号走线电连接，所述主板连接件包括功能主板探针；
    当所述性能测试主板上的子板连接件与所述功能主板探针贴合时，所述信号传输端口与所述测试子板上的待测试芯片电连接。
  8. 如权利要求7所述的芯片测试系统，其特征在于，所述主板连接件还包括HTOL主板探针；
    所述测试子板还包括与所述HTOL主板探针电连接的引脚插接件；
    所述HTOL测试主板上设有与所述引脚插接件相匹配的子板接口。
  9. 如权利要求8所述的芯片测试系统，其特征在于，所述引脚插接件设置在所述测试子板的侧面。
  10. 如权利要求8所述的芯片测试系统，其特征在于，所述测试子板还包括主板连接孔，所述功能主板探针设置在所述主板连接孔外围；
    所述芯片测试系统还包括信号探针，所述信号探针装配在所述主板连接孔内，用于使所述性能测试主板上的子板连接件与所述测试子板上的功能主板探针贴合时，使所述性能测试主板与所述测试子板上的待测试芯片实现电连接。
  11. 如权利要求10所述的芯片测试系统，其特征在于，所述芯片测试系统还包括测试压合治具，所述测试压合治具包括测试底板、固定板、滑动导轨、滑动连接板和压合组件；所述固定板沿垂直方向设置在所述测试底板上；所述滑动导轨装配在所述固定板上，与所述测试底板垂直；所述滑动连接板与所述滑动导轨相连，可沿所述滑动导轨运动；所述压合组件装配在所述滑动连接板上，与所述测试底板之间形成容置所述测试子板和所述性能测试主板的容置间隙。
  12. 一种芯片测试方法，其特征在于，包括：
    将测试子板放置在HTOL测试环境中，使所述测试子板在所述HTOL测试环境的测试时长达到目标时长，所述测试子板的芯片装载区装载有待测试芯片；
    将所述测试子板贴合到性能测试主板上，使所述性能测试主板与所述测试子板上的待测试芯片电连接，对所述待测试芯片进行性能测试。
  13. 如权利要求12所述的芯片测试方法，其特征在于，包括：将所述测试子板贴合到性能测试主板上，使所述性能测试主板与所述测试子板上的待测试芯片电连接，包括：
    将所述测试子板放置在所述性能测试主板上，使所述性能测试主板上的子板连接件与所述测试子板中的测试连接区上的主板连接件对准，将所述性能测试主板和所述测试子板，放置到测试压合治具的测试底板与压合组件之间的容置间隙内，控制所述压合组件向所述测试底板方向压合，以将所述测试子板贴合到性能测试主板上，使所述性能测试主板与所述测试子板上的待测试芯片电连接，对所述待测试芯片进行性能测试。
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