WO2022142700A1 - 一种半导体器件 - Google Patents

一种半导体器件 Download PDF

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Publication number
WO2022142700A1
WO2022142700A1 PCT/CN2021/127879 CN2021127879W WO2022142700A1 WO 2022142700 A1 WO2022142700 A1 WO 2022142700A1 CN 2021127879 W CN2021127879 W CN 2021127879W WO 2022142700 A1 WO2022142700 A1 WO 2022142700A1
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Prior art keywords
magnetic shielding
material layer
contact plug
layer
pattern
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PCT/CN2021/127879
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English (en)
French (fr)
Inventor
韩谷昌
哀立波
杨晓蕾
王明
张恺烨
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浙江驰拓科技有限公司
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Publication of WO2022142700A1 publication Critical patent/WO2022142700A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device.
  • Magnetic random access memory MRAM Magnetic Random Access Memory, a non-volatile magnetic random access memory
  • SRAM Static Random-Access Memory
  • DRAM Dynamic Random-Access Memory
  • magnetic random access memory MRAM has several orders of magnitude superior read and write time and read and write times.
  • Magnetic Tunnel Junction (MTJ) is used as a carrier for information storage in MRAM, and the relative magnetization states of the free layer and the reference layer of the magnetic tunnel junction are used to record information.
  • the magnetic tunnel junction has many significant advantages under the current process conditions, the core storage unit of the current MRAM memory generally adopts the magnetic tunnel junction with perpendicular magnetization characteristics. Therefore, it is susceptible to interference from external magnetic fields.
  • the present invention provides a semiconductor device for improving the magnetic shielding effect while simplifying the process.
  • the present invention provides a semiconductor device, the semiconductor device includes a substrate, a first conductive structure pattern is disposed on the substrate, and a magnetic tunnel junction array located above the first conductive structure pattern, wherein the magnetic tunnel junction array includes A plurality of magnetic tunnel junctions are arranged in an array, and each magnetic tunnel junction is electrically connected to the first conductive structure pattern through a first contact plug.
  • a second conductive structure pattern is also disposed on the substrate, the second conductive structure pattern is located on the second conductive structure pattern above the magnetic tunnel junction array, and each magnetic tunnel junction is electrically connected to the second conductive structure pattern through a second contact plug .
  • some or all of the structures of the first conductive structure pattern, the second conductive structure pattern, the first contact plug, and the second contact plug include a magnetic shielding material.
  • the first conductive structure pattern is a bottom metal layer array, wherein the bottom metal layer array includes a plurality of bottom metal layers corresponding to a plurality of magnetic tunnel junctions one-to-one, and each bottom metal layer passes through the first metal layer.
  • a contact plug is electrically connected to the corresponding magnetic tunnel junction.
  • a transistor array is also provided on the substrate, and the transistor array is located below the bottom metal layer array. The transistor array includes a plurality of transistors in one-to-one correspondence with the plurality of bottom metal layers, and the drain of each transistor is electrically connected to the corresponding bottom metal layer through a third contact plug.
  • Each bottom metal layer in the bottom metal layer array is a magnetic shielding material layer, or a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding effect of each magnetic tunnel junction is improved by adding a magnetic shielding material on the bottom metal layer that is closer to each magnetic tunnel junction.
  • a word line pattern is further provided in the substrate, and the word line pattern is located above the transistor array and below the bottom metal layer array.
  • the word line pattern includes a plurality of word lines arranged in parallel and extending along the first direction, and the gate of each transistor in the transistor array is electrically connected to one word line through a fourth contact plug.
  • Each word line in the word line pattern is a magnetic shielding material layer, or a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding effect of each magnetic tunnel junction is further improved by adding a magnetic shielding material to the word line pattern.
  • the magnetic shielding material can be added therein, thereby simplifying the process.
  • the second conductive structure pattern is a bit line pattern
  • the bit line pattern includes a plurality of bit lines arranged in parallel and extending along the second direction, and the first direction and the second direction are not parallel;
  • the tunnel junction is electrically connected to a bit line through the second contact plug.
  • each bit line in the bit line pattern is a magnetic shielding material layer or a composite material layer including a magnetic shielding material layer and a low resistivity material layer. The magnetic shielding effect is improved by adding a magnetic shielding material to the bit line that is closer to the magnetic tunnel junction.
  • redundant structures surrounding the magnetic tunnel junction are further provided on the substrate, and each redundant structure includes at least two redundant layers arranged one above the other. Any adjacent two redundant layers are arranged at intervals, and redundant contact plugs are connected between any adjacent two redundant layers.
  • each redundant layer is a magnetic shielding material layer, or a composite material layer including a magnetic shielding material layer and a low resistivity material layer; the material of the redundant contact plug is a magnetic shielding material.
  • the redundancy layer located at the lowermost layer is located at the same layer as the bottom metal layer pattern
  • the redundancy layer located at the uppermost layer is located at the same layer as the bit line pattern.
  • a source line pattern is further provided in the substrate, and the source line pattern is located above the transistor and below the word line pattern.
  • the source line pattern includes a plurality of source lines arranged in parallel and extending along the third direction, and the source of each transistor is electrically connected to a source line through a fifth contact plug.
  • each source line in the source line pattern is a magnetic shielding material layer or a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding effect of each magnetic tunnel junction is further improved by adding a magnetic shielding material to the source line pattern. And when the source line is processed, a magnetic shielding material can be added therein, thereby simplifying the process.
  • the composite material layer further comprises a barrier layer sandwiched between the magnetic shielding material layer and the low-resistivity material layer to prevent mutual penetration between the magnetic shielding material layer and the low-resistivity material layer, thereby affecting their performance.
  • the materials of some or all of the first contact plugs, the second contact plugs, the third contact plugs, the fourth contact plugs, and the fifth contact plugs are low-resistivity materials or materials, which can ensure The electrical conductivity of the contact plug reduces the occurrence of defects.
  • the material of some or all of the first contact plug, the second contact plug, the third contact plug, the fourth contact plug, and the fifth contact plug is a magnetic shielding material, which can further improve the magnetic field. shielding effect.
  • the magnetic shielding material is one or several materials selected from iron, cobalt, and nickel
  • the low-resistivity material is one or several materials selected from copper, tungsten, and aluminum.
  • the conductive effect of the conductive structure is improved.
  • the semiconductor device is an MRAM, so as to improve the magnetic shielding effect of the MRAM.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a top view of a semiconductor device according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of another semiconductor device provided by an embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of another semiconductor device provided by an embodiment of the present invention.
  • 5a is a cross-sectional view of one step of processing a contact plug and a wire structure according to an embodiment of the present invention
  • 5b is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • 5c is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • 5d is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • 5e is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • 6a is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention
  • 6b is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • 6c is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • FIG. 7a is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • 7b is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • 7c is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • 7d is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • FIG. 7e is a cross-sectional view of another step of processing a contact plug and a wire structure according to an embodiment of the present invention.
  • the semiconductor device is in a memory using a magnetic tunnel junction as a storage array.
  • the semiconductor device will be described in detail below with reference to the accompanying drawings.
  • a semiconductor device provided by an embodiment of the present invention includes a substrate 10 on which a pattern of a first conductive structure 31 and an array of magnetic tunnel junctions 20 located above the pattern of the first conductive structure 31 are provided , wherein the array of magnetic tunnel junctions 20 includes a plurality of magnetic tunnel junctions 20 arranged in an array, and each of the magnetic tunnel junctions 20 is electrically connected to the pattern of the first conductive structure 31 through the first contact plug 41 .
  • a second conductive structure 32 pattern is further disposed on the substrate 10 , the second conductive structure 32 pattern is located on the second conductive structure 32 pattern above the array of magnetic tunnel junctions 20 , and each magnetic tunnel junction 20 is connected to the second contact plug 42 through the second contact plug 42 .
  • the second conductive structures 32 are electrically connected in pattern. Wherein, some or all of the structures of the first conductive structure 31 pattern, the second conductive structure 32 pattern, the first contact plug 41 and the second contact plug 42 include magnetic shielding material. Specifically, only the pattern of the first conductive structure 31 may contain the magnetic shielding material, or only the pattern of the second conductive structure 32 may contain the magnetic shielding material, or only the first contact plug 41 may contain the magnetic shielding material, or only the first contact plug 41 may contain the magnetic shielding material. The two contact plugs 42 contain magnetic shielding material.
  • a magnetic shielding material may also be included in any two structures of the first conductive structure 31 pattern, the second conductive structure 32 pattern, the first contact plug 41, and the second contact plug 42, and the first conductive structure
  • Magnetic shielding material is included in any three structures of the 31 pattern, the second conductive structure 32 pattern, the first contact plug 41 and the second contact plug 42, and the first conductive structure 31 pattern and the second conductive structure 32 pattern can also be included.
  • the magnetic shielding material is included in all structures of the first contact plug 41 and the second contact plug 42 . Wherein, each structure contains a magnetic shielding material, the material of the structure may be entirely composed of the magnetic shielding material, or the material of the structure may contain a part of the magnetic shielding material.
  • some or all of the structures of the first conductive structure 31 pattern, the second conductive structure 32 pattern, the first contact plug 41 and the second contact plug 42 below and above the magnetic tunnel junction 20 array include There is a magnetic shielding material, and there is a magnetic shielding material in the vicinity of each magnetic tunnel junction 20 for magnetic shielding, so that the effect of magnetic shielding on each magnetic tunnel junction 20 can be improved. And when the conductive structure pattern and the contact plug are processed, the magnetic shielding material can be added therein, so that the processing technology can be simplified.
  • the substrate 10 serves as a carrier for supporting each structure, and also has a dielectric layer 11 for isolating each conductive structure.
  • the semiconductor device may be an MRAM including an array of magnetic tunnel junctions 20 to improve the magnetic shielding effect of the MRAM.
  • the semiconductor device can also be other memories including an array of magnetic tunnel junctions 20 .
  • the first conductive structure 31 pattern may be a bottom metal layer array, wherein the bottom metal layer array includes a plurality of bottom metal layers corresponding to the plurality of magnetic tunnel junctions 20 one-to-one , and each bottom metal layer is electrically connected to the corresponding magnetic tunnel junction 20 through the first contact plug 41 .
  • the first conductive pattern is electrically connected to the bottom electrode 21 through the first contact plug 41, and the bottom electrode 21 is in contact with the magnetic tunnel junction 20.
  • the electrical connection between the pattern of the first conductive structure 31 and the magnetic tunnel junction 20 is realized.
  • a transistor array (not shown in the figure) is also provided on the substrate 10, and the transistor array is located below the bottom metal layer array.
  • the transistor array includes a plurality of transistors corresponding to the plurality of bottom metal layers one-to-one, and the drain of each transistor is electrically connected to the corresponding bottom metal layer through the third contact plug 43 .
  • Each bottom metal layer in the bottom metal layer array is a magnetic shielding material layer, or a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding effect of each magnetic tunnel junction 20 is improved by adding a magnetic shielding material on the bottom metal layer that is closer to each magnetic tunnel junction 20 .
  • the low resistivity material in this article refers to the material whose resistivity is less than the set value.
  • the set value is specifically related to the processing technology, product requirements and other factors.
  • the low resistivity material may be one or several materials selected from copper, tungsten, and aluminum, so as to improve the conductive effect of the conductive structure.
  • the low-resistivity material layer refers to a layer structure composed of low-resistivity materials.
  • the magnetic shielding material may be one or several materials among iron, cobalt, and nickel, so as to improve the magnetic shielding effect. Of course, other materials with magnetic shielding effect can also be selected as the magnetic shielding material.
  • the bottom metal layer may be a composite material layer, and the composite material layer includes a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding material layer can be located above the low resistivity material layer, and the magnetic shielding material layer can be arranged at a position closer to the magnetic tunnel junction 20 to improve the magnetic shielding effect.
  • the magnetic shielding material layer can also be arranged below the low resistivity material layer.
  • the composite material layer can also include a barrier layer, which is sandwiched between the magnetic shielding material layer and the low-resistivity material layer to prevent mutual penetration between the two material layers, thereby preventing the respective performances from being affected.
  • the material of the barrier layer can be Ta, TaN, Ti, TiN and the like.
  • the bottom metal layer may also be entirely composed of a magnetic shielding material layer, so as to increase the thickness of the magnetic shielding material layer and improve the magnetic shielding effect.
  • the magnetic shielding material layer can also conduct electricity, the normal electrical function is not affected.
  • the materials of the first contact plug 41 and the third contact plug 43 can be made of low resistivity materials, so as to improve the conductive effect and prevent the occurrence of electrical defects.
  • FIG. 1 and FIG. 4 the materials of the first contact plug 41 and the third contact plug 43 can be made of low resistivity materials, so as to improve the conductive effect and prevent the occurrence of electrical defects.
  • the first contact plugs 41 and the third contact plugs 43 may also be made of magnetic shielding materials to improve the magnetic shielding effect.
  • the material of the first contact plug 41 may be a low resistivity material
  • the material of the third contact plug 43 may be a magnetic shielding material
  • the material of the first contact plug 41 may be a magnetic shielding material
  • the material of the third contact plug 43 may be a magnetic shielding material.
  • the material is a low resistivity material
  • the materials of the first contact plug 41 and the third contact plug 43 can also be made of magnetic shielding materials.
  • the above-mentioned pattern of the first conductive structure 31 may also be other conductive structure patterns.
  • a word line 33 pattern may also be provided in the substrate 10 , and the word line 33 pattern is located above the transistor array and below the bottom metal layer array.
  • the word line 33 pattern includes a plurality of word lines 33 arranged in parallel and extending along the first direction.
  • the gate of each transistor in the transistor array is electrically connected to one word line 33 through the fourth contact plug 44 .
  • Each word line 33 in the pattern of word lines 33 is a magnetic shielding material layer, or a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding effect of each magnetic tunnel junction 20 is further improved by adding magnetic shielding material to the pattern of the word line 33 .
  • each word line 33 can be made of a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding material can be stacked on the Above the low resistivity material layer, the distance between the magnetic shielding material layer and the magnetic tunnel junction 20 is made closer to improve the magnetic shielding effect.
  • the magnetic shielding material layer can also be positioned below the low resistivity material layer.
  • the composite material layer can also include a barrier layer, which is sandwiched between the magnetic shielding material layer and the low-resistivity material layer to prevent mutual penetration between the two material layers, thereby preventing the respective performances from being affected.
  • each word line 33 may also be entirely composed of a magnetic shielding material layer, so as to increase the thickness of the magnetic shielding material layer and improve the magnetic shielding effect.
  • the magnetic shielding material layer can also conduct electricity, the normal electrical function is not affected.
  • the material of the fourth contact plug 44 may be a low-resistivity material, so as to improve the conduction effect and prevent the occurrence of electrical defects.
  • the material of the fourth contact plug 44 can also be a magnetic shielding material to improve the magnetic shielding effect.
  • the pattern of the second conductive structure 32 may be a bit line pattern, and the bit line pattern includes a plurality of bit lines arranged in parallel and extending along the second direction, And the first direction is not parallel to the second direction.
  • Each magnetic tunnel junction 20 is electrically connected to a bit line through the second contact plug 42 .
  • each magnetic tunnel junction 20 is in contact with the top electrode 22
  • the top electrode 22 is electrically connected to a bit line through the second contact plug 42 . connection, so as to realize the electrical connection between each magnetic tunnel junction 20 and the bit line pattern.
  • Each bit line in the bit line pattern may be a magnetic shielding material layer, or a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding effect is improved by adding a magnetic shielding material to the bit line that is closer to the magnetic tunnel junction 20 .
  • each bit line can be made of a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding material can be stacked on a low resistance material layer. above the rate material layer.
  • the magnetic shielding material layer can also be located below the low-resistivity material layer, so that the distance between the magnetic shielding material layer and the magnetic tunnel junction 20 is closer to improve the magnetic shielding effect.
  • the composite material layer can also include a barrier layer, which is sandwiched between the magnetic shielding material layer and the low-resistivity material layer to prevent mutual penetration between the two material layers, thereby preventing the respective performances from being affected.
  • each bit line may also be entirely composed of a magnetic shielding material layer, so as to increase the thickness of the magnetic shielding material layer and improve the magnetic shielding effect.
  • the magnetic shielding material layer can also conduct electricity, the normal electrical function is not affected.
  • the material of the second contact plug 42 may be a low-resistivity material, so as to improve the conduction effect and prevent the occurrence of electrical defects.
  • the material of the second contact plug 42 can also be a magnetic shielding material to improve the magnetic shielding effect.
  • redundant structures 50 surrounding the magnetic tunnel junction 20 may also be provided on the substrate 10 , and each redundant structure 50 includes at least two layers arranged in sequence up and down Redundancy layer 51 . Any adjacent two redundant layers 51 are arranged at intervals, and redundant contact plugs 52 are connected between any adjacent two redundant layers 51 .
  • each redundant layer 51 is a magnetic shielding material layer or a composite material layer including a magnetic shielding material layer and a low resistivity material layer; the material of the redundant contact plug 52 is a magnetic shielding material.
  • the number of redundant layers 51 may be two as shown in FIG. 1 , and the number of redundant layers 51 may also be three, four, or five. At least two redundant layers 51 are deposited sequentially from bottom to top, and two adjacent redundant layers 51 are separated by a dielectric layer 11 , and two adjacent redundant layers 51 are connected by redundant contact plugs 52 , Therefore, at least two redundant layers 51 are interconnected as a whole, and the magnetic shielding effect is improved.
  • the shape of each redundant layer 51 is specifically determined, the shape of each redundant layer 51 can be a rectangle, a circle, etc., and the redundant layers 51 distributed on the same layer are spaced around the magnetic tunnel junction 20 array to prevent The redundancy layer 51 interferes with the arrangement of interconnect lines.
  • the redundant layer 51 located at the lowermost layer of the at least two redundant layers 51 may be located at the same layer as the bottom metal layer pattern, and the redundant layer located at the uppermost layer may be located at the same layer. 51 is located on the same layer as the bit line pattern.
  • each redundant layer 51 may be a magnetic shielding material, and each redundant layer 51 may be made of a magnetic shielding material layer. composition, thereby improving the magnetic shielding effect.
  • the materials of the redundant contact plugs 52 connected between the two adjacent redundant layers 51 can also be made of magnetic shielding materials to further improve the magnetic shielding effect.
  • the surface area of each redundant layer 51 can be increased, and the magnetic shielding effect can be improved.
  • a source line 34 pattern may also be provided in the substrate 10 , and the source line 34 pattern is located above the transistor and below the word line 33 pattern.
  • the pattern of the source lines 34 includes a plurality of source lines 34 arranged in parallel and extending along the third direction.
  • the source of each transistor is electrically connected to a source line 34 through the fifth contact plug 45 .
  • each source line 34 in the pattern of the source lines 34 is a magnetic shielding material layer, or a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding effect of each magnetic tunnel junction 20 is further improved by adding magnetic shielding material to the pattern of the source line 34 .
  • each source pole line 34 can be made of a composite material layer including a magnetic shielding material layer and a low resistivity material layer.
  • the magnetic shielding material can be stacked on the Above the low resistivity material layer, the distance between the magnetic shielding material layer and the magnetic tunnel junction 20 is made closer to improve the magnetic shielding effect.
  • the magnetic shielding material layer can also be positioned below the low resistivity material layer.
  • the composite material layer can also include a barrier layer, which is sandwiched between the magnetic shielding material layer and the low-resistivity material layer to prevent mutual penetration between the two material layers, thereby preventing the respective performances from being affected.
  • each source pole line 34 may also be entirely composed of a magnetic shielding material layer, so as to increase the thickness of the magnetic shielding material layer and improve the magnetic shielding effect.
  • the magnetic shielding material layer can also conduct electricity, the normal electrical function is not affected. Referring to FIG. 1 , FIG. 3 and FIG.
  • the material of the fifth contact plug 45 may be a low-resistivity material, so as to improve the conductive effect, ensure the conductive performance of the contact plug, and prevent electrical defects from occurring.
  • the material of the fifth contact plug 45 can also be a magnetic shielding material to improve the magnetic shielding effect.
  • each of the above-mentioned conductive structures and contact plugs may be separated from the dielectric layer 11 in the substrate 10 by a barrier layer to prevent mutual penetration, thereby affecting the respective performance.
  • FIGS. 5 a to 5 e there are many ways, such as a method for processing the contact plug and wire structure as shown in FIGS. 5 a to 5 e .
  • a contact hole and a wire groove are processed on the substrate 10, wherein the contact hole is used for filling to form a contact plug, and the wire groove is used for filling and forming a composite material layer.
  • a barrier layer is formed in the contact holes and wire grooves.
  • FIG. 5c a low-resistivity material layer is formed on the barrier layer, and the low-resistivity material layer fills the contact holes but not the wire grooves.
  • the barrier layer, the low resistivity material layer and the magnetic shielding material layer outside the wire grooves on the surface of the substrate 10 are removed to obtain a contact plug and wire structure.
  • the specific removal method can be removed by CMP planarization.
  • the composite material further includes a barrier layer sandwiched between the magnetic shielding material layer and the low-resistivity material layer, referring to FIG. A barrier layer.
  • the layer of magnetic shielding material is filled.
  • two layers of barrier layers, low resistivity material layers and magnetic shielding material layers are removed by one CMP planarization to obtain a contact plug and a line structure.
  • a single damascene process can also be used to process the contact plug and the wire structure, with specific reference to FIGS. 7 a to 7 e .
  • contact holes are processed on the substrate 10 .
  • a barrier layer is formed in the contact holes.
  • the low-resistivity material layer is filled, and the low-resistivity material layer outside the substrate 10 is removed by a CMP planarization process to obtain a contact plug composed of the low-resistivity material.
  • a dielectric layer 11 is further deposited on the substrate 10, and a wire groove communicating with the contact plug is processed.
  • the magnetic shielding material layer is filled, and the magnetic shielding material layer outside the substrate 10 is removed by a CMP planarization process to obtain a line structure.
  • a region near each magnetic tunnel junction 20 is provided with a magnetic shielding material for magnetic shielding, so that the effect of magnetic shielding on each magnetic tunnel junction 20 can be improved. And when the conductive structure pattern and the contact plug are processed, the magnetic shielding material can be added therein, so that the processing technology can be simplified.

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  • Mram Or Spin Memory Techniques (AREA)

Abstract

本发明提供了一种半导体器件，该半导体器件包括衬底，在衬底上设置有第一导电结构图案、位于第一导电结构图案上方的磁隧道结阵列，且每个磁隧道结通过第一接触塞与第一导电结构图案电连接。在衬底上还设置有第二导电结构图案，第二导电结构图案位于磁隧道结阵列上方的第二导电结构图案，且每个磁隧道结通过第二接触塞与第二导电结构图案电连接。第一导电结构图案、第二导电结构图案、第一接触塞及第二接触塞中的部分或全部结构中包含有磁屏蔽材料。在每个磁隧道结附近区域都有磁屏蔽材料进行磁屏蔽，从而能够提高对每个磁隧道结进行磁屏蔽的效果。且可以在加工导电结构图案和接触塞时，将磁屏蔽材料加入其内，从而能够简化加工工艺。

Description

一种半导体器件 技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体器件。
背景技术
近年来发展迅速的磁性随机存储器MRAM(Magnetic Random Access Memory，一种非易失性的磁性随机存储器)具有优异的特性。其克服了SRAM(Static Random-Access Memory，静态随机存取存储器)面积大、尺寸微缩后漏电大的缺点；其还克服了DRAM(Dynamic Random Access Memory，动态随机存取存储器)需要一直进行数据刷新，功耗大的缺点。磁性随机存储器MRAM相对Flash memory(闪存)，其读写时间和可读写次数优越几个数量级。
磁隧道结(Magnetic Tunnel Junction，MTJ)作为MRAM中信息存储的载体，使用磁隧道结的自由层和参考层相对磁化状态记录信息。在当前工艺条件下磁隧道结虽然具有多项显著优点，但当前MRAM存储器的核心存储单元普遍采用具有垂直磁化特性的磁性隧道结，其产生0、1态的原理为器件磁矩方向的不同，因此，其易受外部磁场的干扰。
发明内容
本发明提供了一种半导体器件，用于提高磁屏蔽效果，同时简化工艺。
本发明提供了一种半导体器件，该半导体器件包括一衬底，在衬底上设置有第一导电结构图案、以及位于第一导电结构图案上方的磁隧道结阵列，其中，磁隧道结阵列包含多个阵列排列的磁隧道结，且每个磁隧道结通过第一接触塞与第一导电结构图案电连接。在衬底上还设置有第二导电结构图案，第二导电结构图案位于磁隧道结阵列上方的第二导电结构图案，且每个磁隧道结通过第二接触塞与第二导电结构图案电连接。其中，第一导电结构图案、第二导电结 构图案、第一接触塞及第二接触塞中的部分或全部结构中包含有磁屏蔽材料。
在上述的方案中，通过在磁隧道结阵列下方和上方的第一导电结构图案、第二导电结构图案、第一接触塞及第二接触塞中的部分或全部结构中包含有磁屏蔽材料，在每个磁隧道结附近区域都有磁屏蔽材料进行磁屏蔽，从而能够提高对每个磁隧道结进行磁屏蔽的效果。且可以在加工导电结构图案和接触塞时，将磁屏蔽材料加入其内，从而能够简化加工工艺。
在一个具体的实施方式中，第一导电结构图案为底金属层阵列，其中，底金属层阵列包含多个与多个磁隧道结一一对应的底金属层，且每个底金属层通过第一接触塞与对应的磁隧道结电连接。在衬底上还设置有晶体管阵列，且晶体管阵列位于底金属层阵列的下方。晶体管阵列包含多个与多个底金属层一一对应的晶体管，且每个晶体管的漏极通过第三接触塞与对应的底金属层电连接。底金属层阵列中的每个底金属层为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。通过在距离每个磁隧道结距离较近的底金属层上加入磁屏蔽材料，以提高对每个磁隧道结进行磁屏蔽的效果。
在一个具体的实施方式中，衬底中还设置有字线图案，字线图案位于晶体管阵列的上方，且位于底金属层阵列的下方。字线图案包含多根平行排列并沿第一方向延伸的字线，晶体管阵列中的每个晶体管的栅极通过第四接触塞与一根字线电连接。字线图案中的每根字线为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。通过在字线图案中也加入磁屏蔽材料，以进一步提高对每个磁隧道结进行磁屏蔽的效果。且可以在加工字线时，将磁屏蔽材料加入其内，从而简化工艺。
在一个具体的实施方式中，第二导电结构图案为位线图案，位线图案包含多根平行排列且沿第二方向延伸的位线，且第一方向与第二方向不平行；每根 磁隧道结通过第二接触塞与一根位线电连接。且位线图案中的每根位线为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。通过在距离磁隧道结距离较近的位线上也加入磁屏蔽材料，从而提高磁屏蔽效果。
在一个具体的实施方式中，衬底上还设置有环绕在磁隧道结四周的冗余结构，每个冗余结构包括上下依次排布的至少两层冗余层。任意相邻的两层冗余层间隔设置，且在任意相邻的两层冗余层之间连接有冗余接触塞。其中，每层冗余层均为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层；冗余接触塞的材料为磁屏蔽材料。通过在磁隧道结四周设置有包含有磁屏蔽材料的冗余结构，使得磁屏蔽的面积大于磁隧道结阵列的面积，提高磁屏蔽效果。
在一个具体的实施方式中，至少两层冗余层中位于最下层的冗余层与底金属层图案位于同一层，位于最上层的冗余层与位线图案位于同一层。通过使冗余结构中的冗余层都位于位线图案和底金属层之间的区域，将磁隧道结阵列围在一个较小的空间内，从而提高磁屏蔽效果。
在一个具体的实施方式中，衬底中还设置有源极线图案，源极线图案位于晶体管的上方，且位于字线图案的下方。源极线图案包含多根平行排列且沿第三方向延伸的源极线，每个晶体管的源极通过第五接触塞与一根源极线电连接。且源极线图案中的每根源极线为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。通过在源极线图案中也加入磁屏蔽材料，以进一步提高对每个磁隧道结进行磁屏蔽的效果。且可以在加工源极线时，将磁屏蔽材料加入其内，从而简化工艺。
在一个具体的实施方式中，复合材料层还包含有夹设在磁屏蔽材料层和低电阻率材料层之间的阻挡层，以防止磁屏蔽材料层和低电阻率材料层之间相互 渗透，从而影响各自的性能。
在一个具体的实施方式中，第一接触塞、第二接触塞、第三接触塞、第四接触塞、第五接触塞中的部分或全部接触塞的材料为低电阻率材料或，能够保证接触塞的导电性能，减少缺陷产生。
在一个具体的实施方式中，第一接触塞、第二接触塞、第三接触塞、第四接触塞、第五接触塞中的部分或全部接触塞的材料为磁屏蔽材料，能够进一步提高磁屏蔽效果。
在一个具体的实施方式中，磁屏蔽材料为铁、钴、镍中的一种材料或几种材料，低电阻率材料为铜、钨、铝中的一种材料或几种材料。以提高磁屏蔽效果，提高导电结构的导电效果。
在一个具体的实施方式中，半导体器件为MRAM，以提高MRAM的磁屏蔽效果。
附图说明
图1为本发明实施例提供的一种半导体器件的剖视图；
图2为本发明实施例提供的一种半导体器件的俯视图；
图3为本发明实施例提供的另一种半导体器件的剖视图；
图4为本发明实施例提供的另一种半导体器件的剖视图；
图5a为本发明实施例提供的一种加工接触塞及线结构的其中一步的剖视图；
图5b为本发明实施例提供的一种加工接触塞及线结构的另一步的剖视图；
图5c为本发明实施例提供的一种加工接触塞及线结构的另一步的剖视图；
图5d为本发明实施例提供的一种加工接触塞及线结构的另一步的剖视图；
图5e为本发明实施例提供的一种加工接触塞及线结构的另一步的剖视图；
图6a为本发明实施例提供的另一种加工接触塞及线结构的另一步的剖视图；
图6b为本发明实施例提供的另一种加工接触塞及线结构的另一步的剖视图；
图6c为本发明实施例提供的另一种加工接触塞及线结构的另一步的剖视图；
图7a为本发明实施例提供的另一种加工接触塞及线结构的其中一步的剖视图；
图7b为本发明实施例提供的另一种加工接触塞及线结构的另一步的剖视图；
图7c为本发明实施例提供的另一种加工接触塞及线结构的另一步的剖视图；
图7d为本发明实施例提供的另一种加工接触塞及线结构的另一步的剖视图；
图7e为本发明实施例提供的另一种加工接触塞及线结构的另一步的剖视图。
附图标记：
10-衬底 11-介质层 20-磁隧道结 21-底电极 22-顶电极
31-第一导电结构 32-第二导电结构 33-字线 34-源极线
41-第一接触塞 42-第二接触塞 43-第三接触塞 44-第四接触塞
45-第五接触塞 50-冗余结构 51-冗余层 52-冗余接触塞
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明 实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为了方便理解本发明实施例提供的半导体器件，下面首先说明一下本发明实施例提供的半导体器件的应用场景，该半导体器件为采用磁隧道结作为存储阵列的存储器中。下面结合附图对该半导体器件进行详细的叙述。
参考图1及图2，本发明实施例提供的半导体器件包括一衬底10，在衬底10上设置有第一导电结构31图案、以及位于第一导电结构31图案上方的磁隧道结20阵列，其中，磁隧道结20阵列包含多个阵列排列的磁隧道结20，且每个磁隧道结20通过第一接触塞41与第一导电结构31图案电连接。在衬底10上还设置有第二导电结构32图案，第二导电结构32图案位于磁隧道结20阵列上方的第二导电结构32图案，且每个磁隧道结20通过第二接触塞42与第二导电结构32图案电连接。其中，第一导电结构31图案、第二导电结构32图案、第一接触塞41及第二接触塞42中的部分或全部结构中包含有磁屏蔽材料。具体的，可以只有第一导电结构31图案包含有磁屏蔽材料，也可以只有第二导电结构32图案包含有磁屏蔽材料，还可以只有第一接触塞41包含有磁屏蔽材料，还可以只有第二接触塞42包含有磁屏蔽材料。当然，还可以在第一导电结构31图案、第二导电结构32图案、第一接触塞41、第二接触塞42中的任意两个结构中包含有磁屏蔽材料，还可以在第一导电结构31图案、第二导电结构32图案、第一接触塞41、第二接触塞42中的任意三个结构中包含有磁屏蔽材料，还可以在第一导电结构31图案、第二导电结构32图案、第一接触塞41、第二接触塞42中的全部结构中均包含有磁屏蔽材料。其中，每个结构包含有磁屏蔽材料可以是该结构的材料全部 由磁屏蔽材料组成，还可以是该结构的材料中包含有部分磁屏蔽材料。
在上述的方案中，通过在磁隧道结20阵列下方和上方的第一导电结构31图案、第二导电结构32图案、第一接触塞41及第二接触塞42中的部分或全部结构中包含有磁屏蔽材料，在每个磁隧道结20附近区域都有磁屏蔽材料进行磁屏蔽，从而能够提高对每个磁隧道结20进行磁屏蔽的效果。且可以在加工导电结构图案和接触塞时，将磁屏蔽材料加入其内，从而能够简化加工工艺。下面结合附图对上述各个结构进行详细的介绍。
在设置衬底10时，参考图1，衬底10作为支撑各个结构的载体，还具有隔离各个导电结构的介质层11。在确定半导体器件时，该半导体器件可以为包含有磁隧道结20阵列的MRAM，以提高MRAM的磁屏蔽效果。当然，该半导体器件还可以为其他包含有磁隧道结20阵列的存储器。
在设置第一导电结构31图案时，参考图1，第一导电结构31图案可以为底金属层阵列，其中，底金属层阵列包含多个与多个磁隧道结20一一对应的底金属层，且每个底金属层通过第一接触塞41与对应的磁隧道结20电连接。具体实现第一导电结构31图案通过第一接触塞41与磁隧道结20电连接时，第一导电图案通过第一接触塞41与底电极21电连接，底电极21与磁隧道结20接触，从而实现第一导电结构31图案与磁隧道结20的电连接。在衬底10上还设置有晶体管阵列(图中未示出)，且晶体管阵列位于底金属层阵列的下方。晶体管阵列包含多个与多个底金属层一一对应的晶体管，且每个晶体管的漏极通过第三接触塞43与对应的底金属层电连接。底金属层阵列中的每个底金属层为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。通过在距离每个磁隧道结20距离较近的底金属层上加入磁屏蔽材料，以提高对每个磁隧道结20进行磁屏蔽的效果。
需要解释的是，本文中的低电阻率材料是指电阻率小于设定值的材料，具体确定设定值时，设定值的大小具体与加工工艺、产品要求等多个因素有关。在具体选择底电阻率材料时，低电阻率材料可以为铜、钨、铝中的一种材料或几种材料，以提高导电结构的导电效果。对应的，低电阻率材料层指的是由低电阻率材料组成的层结构。在确定磁屏蔽材料时，磁屏蔽材料可以为铁、钴、镍中的一种材料或几种材料，以提高磁屏蔽效果。当然，磁屏蔽材料还可以选择其他具有磁屏蔽效果的材料。
在具体设置底金属层阵列中的每个底金属层时，参考图1，底金属层可以为复合材料层，复合材料层包含有磁屏蔽材料层和低电阻率材料层。具体的，可以使磁屏蔽材料层位于低电阻率材料层的上方，使磁屏蔽材料层设置在距离磁隧道结20更近的位置，以提高磁屏蔽效果。当然，还可以使磁屏蔽材料层设置在低电阻率材料层的下方。还可以使复合材料层包含有阻挡层，阻挡层夹设在磁屏蔽材料层和低电阻率材料层之间，防止两层材料层之间相互渗透，从而防止影响各自的性能。阻挡层的材料可以为Ta、TaN、Ti、TiN等。另外，参考图3，底金属层还可以全部由磁屏蔽材料层组成，以增加磁屏蔽材料层的厚度，提高磁屏蔽效果。同时由于磁屏蔽材料层也能够导电，从而不影响正常的电学功能。如图1及图4所示，可以使第一接触塞41和第三接触塞43的材料均为低电阻率材料，以提高导电效果，防止发生电学缺陷。当然，参考图3，还可以使第一接触塞41和第三接触塞43中的部分或全部接触塞的材料为磁屏蔽材料，以提高磁屏蔽效果。具体的，可以使第一接触塞41的材料为低电阻率材料，第三接触塞43的材料为磁屏蔽材料；可以使第一接触塞41的材料为磁屏蔽材料，第三接触塞43的材料为低电阻率材料；还可以使第一接触塞41及第三接触塞43的材料均为磁屏蔽材料。当然，上述的第一导电结构31图案还可以为其他 的导电结构图案。
参考图4，在衬底10中还可以设置有字线33图案，字线33图案位于晶体管阵列的上方，且位于底金属层阵列的下方。字线33图案包含多根平行排列并沿第一方向延伸的字线33，晶体管阵列中的每个晶体管的栅极通过第四接触塞44与一根字线33电连接。字线33图案中的每根字线33为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。通过在字线33图案中也加入磁屏蔽材料，以进一步提高对每个磁隧道结20进行磁屏蔽的效果。且可以在加工字线33时，将磁屏蔽材料加入其内，从而简化工艺。在具体设置每根字线33时，参考图4，可以使每根字线33由包含有磁屏蔽材料层和低电阻率材料层的复合材料层，具体的，可以使磁屏蔽材料层叠设在低电阻率材料层上方，使磁屏蔽材料层距离磁隧道结20的距离更近，提高磁屏蔽效果。当然，还可以使磁屏蔽材料层位于低电阻率材料层的下方。还可以使复合材料层包含有阻挡层，阻挡层夹设在磁屏蔽材料层和低电阻率材料层之间，防止两层材料层之间相互渗透，从而防止影响各自的性能。当然，每根字线33还可以全部由磁屏蔽材料层组成，以增加磁屏蔽材料层的厚度，提高磁屏蔽效果。同时由于磁屏蔽材料层也能够导电，从而不影响正常的电学功能。参考图4，第四接触塞44的材料可以为低电阻率材料，以提高导电效果，防止发生电学缺陷。当然，第四接触塞44的材料还可以为磁屏蔽材料，以提高磁屏蔽效果。
在设置第二导电结构32图案时，参考图1、图2及图4，第二导电结构32图案可以为位线图案，位线图案包含多根平行排列且沿第二方向延伸的位线，且第一方向与第二方向不平行。每根磁隧道结20通过第二接触塞42与一根位线电连接，具体的，每根磁隧道结20与顶电极22接触，顶电极22通过第二接触塞42与一根位线电连接，从而实现每根磁隧道结20与位线图案的电连接。
可以使位线图案中的每根位线为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。通过在距离磁隧道结20距离较近的位线上也加入磁屏蔽材料，从而提高磁屏蔽效果。在具体设置每根位线时，参考图1，可以使每根位线由包含有磁屏蔽材料层和低电阻率材料层的复合材料层，具体的，可以使磁屏蔽材料层叠设在低电阻率材料层上方。当然，还可以使磁屏蔽材料层位于低电阻率材料层的下方，使磁屏蔽材料层距离磁隧道结20的距离更近，提高磁屏蔽效果。还可以使复合材料层包含有阻挡层，阻挡层夹设在磁屏蔽材料层和低电阻率材料层之间，防止两层材料层之间相互渗透，从而防止影响各自的性能。当然，参考图3，每根位线还可以全部由磁屏蔽材料层组成，以增加磁屏蔽材料层的厚度，提高磁屏蔽效果。同时由于磁屏蔽材料层也能够导电，从而不影响正常的电学功能。参考图1、图3及图4，第二接触塞42的材料可以为低电阻率材料，以提高导电效果，防止发生电学缺陷。当然，第二接触塞42的材料还可以为磁屏蔽材料，以提高磁屏蔽效果。
参考图1、图2、图3及图4，还可以在衬底10上设置有环绕在磁隧道结20四周的冗余结构50，每个冗余结构50包括上下依次排布的至少两层冗余层51。任意相邻的两层冗余层51间隔设置，且在任意相邻的两层冗余层51之间连接有冗余接触塞52。其中，每层冗余层51均为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层；冗余接触塞52的材料为磁屏蔽材料。通过在磁隧道结20四周设置有包含有磁屏蔽材料的冗余结构50，使得磁屏蔽的面积大于磁隧道结20阵列的面积，提高磁屏蔽效果。
具体确定冗余层51的层数时，冗余层51的层数可以为如图1所示出的两层，冗余层51的层数还可以为3层、4层、5层等。至少两层冗余层51由下向上依次沉淀，且相邻的两层冗余层51之间通过介质层11隔开，且相邻的两层冗余层51 通过冗余接触塞52连接，从而使至少两层冗余层51互连为一个整体，提高磁屏蔽效果。在具体确定每层冗余层51的形状时，每层冗余层51的形状可以矩形、圆形等，且分布在相同层上的冗余层51环绕磁隧道结20阵列间隔分布，以防止冗余层51干扰互连线的布置。
在具体布置至少两层冗余层51时，参考图1，可以使至少两层冗余层51中位于最下层的冗余层51与底金属层图案位于同一层，位于最上层的冗余层51与位线图案位于同一层。通过使冗余结构50中的冗余层51都位于位线图案和底金属层之间的区域，将磁隧道结20阵列围在一个较小的空间内，从而提高磁屏蔽效果。同时可以在加工底金属层图案和位线图案时，一起加工出来，从而简化工艺。
在具体确定冗余结构50的材料时，参考图1、图2及图4，可以使每层冗余层51的材料均为磁屏蔽材料，使每层冗余层51均由磁屏蔽材料层组成，从而提高磁屏蔽效果。且还可以使连接在相邻的两层冗余层51之间的冗余接触塞52的材料也全部由磁屏蔽材料组成，进一步提高磁屏蔽效果。且通过采用冗余结构50由冗余层51和冗余接触塞52的形式组成，从而能够增大每层冗余层51的表面积，提高磁屏蔽效果。
参考图4，还可以在衬底10中设置有源极线34图案，源极线34图案位于晶体管的上方，且位于字线33图案的下方。源极线34图案包含多根平行排列且沿第三方向延伸的源极线34，每个晶体管的源极通过第五接触塞45与一根源极线34电连接。且源极线34图案中的每根源极线34为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。通过在源极线34图案中也加入磁屏蔽材料，以进一步提高对每个磁隧道结20进行磁屏蔽的效果。且可以在加工源极线34时，将磁屏蔽材料加入其内，从而简化工艺。在具体设置每根源极线34 时，参考图1，可以使每根源极线34由包含有磁屏蔽材料层和低电阻率材料层的复合材料层，具体的，可以使磁屏蔽材料层叠设在低电阻率材料层上方，使磁屏蔽材料层距离磁隧道结20的距离更近，提高磁屏蔽效果。当然，还可以使磁屏蔽材料层位于低电阻率材料层的下方。还可以使复合材料层包含有阻挡层，阻挡层夹设在磁屏蔽材料层和低电阻率材料层之间，防止两层材料层之间相互渗透，从而防止影响各自的性能。当然，参考图3，每根源极线34还可以全部由磁屏蔽材料层组成，以增加磁屏蔽材料层的厚度，提高磁屏蔽效果。同时由于磁屏蔽材料层也能够导电，从而不影响正常的电学功能。参考图1、图3及图4，第五接触塞45的材料可以为低电阻率材料，以提高导电效果，能够保证接触塞的导电性能，防止发生电学缺陷。当然，第五接触塞45的材料还可以为磁屏蔽材料，以提高磁屏蔽效果。
另外，需要注意的是，上述每个导电结构和接触塞可以通过阻挡层与衬底10中的介质层11隔开，以防止相互渗透，从而影响各自的性能。
在具体加工上述的接触塞和线结构时，存在多种方式，如图5a～图5e所示出的一种加工接触塞及线结构的方式。首先，参考图5a，在衬底10上加工出用于接触孔和线槽，其中，接触孔用于填充形成接触塞，线槽用于填充形成复合材料层。接下来，参考图5b，在接触孔和线槽中生成出一层阻挡层。接下来，参考图5c，在阻挡层上生成出一层低电阻率材料层，且低电阻率材料层填充满接触孔，但未填充满线槽。接下来，参考图5d，填充磁屏蔽材料，使用磁屏蔽材料填满线槽。接下来，参考图5e，去除衬底10表面线槽外的阻挡层、低电阻率材料层和磁屏蔽材料层，得到接触塞和线结构。具体的去除方法可以采用CMP平坦化的方式去除。
在复合材料还还包括夹设在磁屏蔽材料层和低电阻率材料层之间的阻挡 层时，参考图6a，在生成出一层低电阻率材料层之后，在低电阻率材料层上生成一层阻挡层。之后，参考图6b，填充磁屏蔽材料层。之后，参考图6c，一次CMP平坦化去除两层阻挡层、低电阻率材料层和磁屏蔽材料层，得到接触塞和线结构。
另外，还可以采用单大马士革工艺的方式加工接触塞及线结构，具体参考图7a～图7e。首先，参考图7a，在衬底10上加工出接触孔。参考图7b，在接触孔中生成一层阻挡层。参考图7c，填充低电阻率材料层，并采用CMP平坦化工艺去除衬底10外的低电阻率材料层，得到由低电阻率材料组成的接触塞。接下来，参考图7d，在衬底10上继续沉积一层介质层11，并加工出与接触塞连通的线槽。接下来，参考图7e，填充磁屏蔽材料层，并采用CMP平坦化工艺去除衬底10外的磁屏蔽材料层，得到线结构。
通过在磁隧道结20阵列下方和上方的第一导电结构31图案、第二导电结构32图案、第一接触塞41及第二接触塞42中的部分或全部结构中包含有磁屏蔽材料，在每个磁隧道结20附近区域都有磁屏蔽材料进行磁屏蔽，从而能够提高对每个磁隧道结20进行磁屏蔽的效果。且可以在加工导电结构图案和接触塞时，将磁屏蔽材料加入其内，从而能够简化加工工艺。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (12)

  1. 一种半导体器件，其特征在于，包括：
    衬底；
    设置在所述衬底上的第一导电结构图案；
    设置在所述第一导电结构图案上方的磁隧道结阵列，所述磁隧道结阵列包含多个阵列排列的磁隧道结，且每个磁隧道结通过第一接触塞与所述第一导电结构图案电连接；
    设置在所述磁隧道结阵列上方的第二导电结构图案，且每个磁隧道结通过第二接触塞与所述第二导电结构图案电连接；
    其中，所述第一导电结构图案、第二导电结构图案、第一接触塞及第二接触塞中的部分或全部结构中包含有磁屏蔽材料。
  2. 如权利要求1所述的半导体器件，其特征在于，所述第一导电结构图案为底金属层阵列，其中，所述底金属层阵列包含多个与所述多个磁隧道结一一对应的底金属层，且每个底金属层通过所述第一接触塞与对应的磁隧道结电连接；
    所述衬底上还设置有晶体管阵列，且所述晶体管阵列位于所述底金属层阵列的下方；所述晶体管阵列包含多个与所述多个底金属层一一对应的晶体管，且每个晶体管的漏极通过第三接触塞与对应的底金属层电连接；
    所述底金属层阵列中的每个底金属层为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。
  3. 如权利要求2所述的半导体器件，其特征在于，所述衬底中还设置有字线图案，所述字线图案位于所述晶体管阵列的上方，且位于所述底金属层阵 列的下方；所述字线图案包含多根平行排列并沿第一方向延伸的字线，所述晶体管阵列中的每个晶体管的栅极通过第四接触塞与所述一根字线电连接；
    所述字线图案中的每根字线为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。
  4. 如权利要求2所述的半导体器件，其特征在于，所述第二导电结构图案为位线图案，所述位线图案包含多根平行排列且沿第二方向延伸的位线，其中，所述第一方向与所述第二方向不平行；每个磁隧道结通过所述第二接触塞与所述一根位线电连接；
    且所述位线图案中的每根位线为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。
  5. 如权利要求4所述的半导体器件，其特征在于，所述衬底上还设置有环绕在所述磁隧道结四周的冗余结构，每个冗余结构包括上下依次排布的至少两层冗余层；任意相邻的两层冗余层间隔设置，且在任意相邻的两层冗余层之间连接有冗余接触塞；
    其中，每层冗余层均为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层；所述冗余接触塞的材料为磁屏蔽材料。
  6. 如权利要求5所述的半导体器件，其特征在于，所述至少两层冗余层中位于最下层的冗余层与所述底金属层图案位于同一层，位于最上层的冗余层与所述位线图案位于同一层。
  7. 如权利要求2所述的半导体器件，其特征在于，所述衬底中还设置有源极线图案；所述源极线图案位于所述晶体管的上方，且位于所述字线图案的下方；所述源极线图案包含多根平行排列且沿第三方向延伸的源极线，每个晶体管的源极通过第五接触塞与所述一根源极线电连接；
    且所述源极线图案中的每根源极线为磁屏蔽材料层、或包含有磁屏蔽材料层和低电阻率材料层的复合材料层。
  8. 如权利要求2～7任一项所述的半导体器件，其特征在于，所述复合材料层还包含有夹设在所述磁屏蔽材料层和低电阻率材料层之间的阻挡层。
  9. 如权利要求7所述的半导体器件，其特征在于，所述第一接触塞、第二接触塞、第三接触塞、第四接触塞、第五接触塞中的部分或全部接触塞的材料为低电阻率材料。
  10. 如权利要求7所述的半导体器件，其特征在于，所述第一接触塞、第二接触塞、第三接触塞、第四接触塞、第五接触塞中的部分或全部接触塞的材料为磁屏蔽材料。
  11. 如权利要求1所述的半导体器件，其特征在于，所述磁屏蔽材料为铁、钴、镍中的一种材料或几种材料，所述低电阻率材料为铜、钨、铝中的一种材料或几种材料。
  12. 如权利要求1所述的半导体器件，其特征在于，所述半导体器件为MRAM。
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CN101978426A (zh) * 2008-03-20 2011-02-16 国际商业机器公司 磁性去耦合磁存储器单元和用于减少位选择错误的位线/字线

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101978426A (zh) * 2008-03-20 2011-02-16 国际商业机器公司 磁性去耦合磁存储器单元和用于减少位选择错误的位线/字线

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