WO2022141822A1 - 一种像素电路及全局cmos图像传感器 - Google Patents

一种像素电路及全局cmos图像传感器 Download PDF

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Publication number
WO2022141822A1
WO2022141822A1 PCT/CN2021/082040 CN2021082040W WO2022141822A1 WO 2022141822 A1 WO2022141822 A1 WO 2022141822A1 CN 2021082040 W CN2021082040 W CN 2021082040W WO 2022141822 A1 WO2022141822 A1 WO 2022141822A1
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storage node
signal
pixel circuit
photoelectric
node
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PCT/CN2021/082040
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English (en)
French (fr)
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胡欢
陈世杰
张斌
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联合微电子中心有限责任公司
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Publication of WO2022141822A1 publication Critical patent/WO2022141822A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith

Definitions

  • the invention relates to the field of CMOS image sensors, in particular to a pixel circuit and a global CMOS image sensor.
  • CMOS image sensors can be divided into RS (Rolling Shutter, rolling shutter) shutters and GS (Global Shutter, global) shutters according to their different exposure methods.
  • Rolling shutter as the name implies, is that the pixels are exposed row by row. Due to the different exposure time points of each row of pixels, there is a certain time difference between each row. Therefore, it is often used for the shooting of fast-moving objects or the objects shot by the camera when moving rapidly. Deformation occurs.
  • the global shutter exposure mode each row of pixel units is exposed at the same time, and the signal is simultaneously transmitted by the photodiodes in the pixel units, thus avoiding the image distortion problem in the rolling shutter exposure mode.
  • GS CIS Global CMOS Image Sensor
  • GS CIS Global CMOS Image Sensor
  • the charge signal of the voltage domain GS CIS is first converted into a voltage signal by an amplifier and then stored in the storage unit; the charge signal of the charge domain GS CIS is directly stored in the storage unit; however, the charge domain GS CIS is usually seriously affected by parasitic light signals, This will seriously affect its imaging quality.
  • GS CIS needs to prevent overexposure in strong light environment, so GS CIS should have a large dynamic range.
  • the purpose of the present invention is to provide a pixel circuit and a global CMOS image sensor to solve the problem that the charge domain GS CIS in the prior art affects the imaging quality due to parasitic light effects and the dynamic range is small.
  • the problem of easy overexposure in bright light is to provide a pixel circuit and a global CMOS image sensor to solve the problem that the charge domain GS CIS in the prior art affects the imaging quality due to parasitic light effects and the dynamic range is small.
  • the present invention provides a pixel circuit, which includes:
  • the main photosensitive photoelectric module is used for transmitting the main photoelectric signal to the first storage node in the exposure stage; in the readout stage, reading the signal stored in the first storage node and transmitting it to the floating diffusion node;
  • the strong photosensitive photoelectric module when the pixel circuit works in the low parasitic light effect mode, is used for collecting the parasitic light signal to the second storage node in the exposure stage, and in the readout stage, reading the memory stored in the second storage node
  • the signal is transmitted to the floating diffusion node; when the pixel circuit works in the wide dynamic range mode, it is used to transmit a strong photoelectric signal to the second storage node in the exposure stage, and in the readout stage, read The signal stored in the second storage node is transmitted to the floating diffusion node.
  • the main photosensitive photoelectric module includes:
  • a first photoelectric conversion unit used for generating the main photoelectric signal based on photoelectric conversion in the exposure stage
  • the first storage node is used for storing the main photoelectric signal and the parasitic light signal when the pixel circuit works in a low parasitic light effect mode; when the pixel circuit works in a wide dynamic range mode, it is used for storing the main photoelectric signal;
  • a first transmission unit connected between the first photoelectric conversion unit and the first storage node, and used for transmitting the main photoelectric signal to the first storage node in the exposure stage;
  • a second transmission unit connected between the first storage node and the floating diffusion node, and configured to read the signal stored in the first storage node and transmit it to the floating diffusion node in the readout stage;
  • the first global reset unit is connected between the power supply voltage and the first photoelectric conversion unit, and is used for resetting the first photoelectric conversion unit before the exposure operation.
  • the strong photosensitive photoelectric module includes:
  • a second photoelectric conversion unit configured to generate the strong photoelectric signal based on photoelectric conversion in the exposure stage when the pixel circuit operates in a wide dynamic range mode
  • the second storage node is used to store the collected parasitic light signal when the pixel circuit operates in a low parasitic light effect mode; and is used to store the strong light when the pixel circuit operates in a wide dynamic range mode electric signal;
  • the third transmission unit is connected between the second photoelectric conversion unit and the second storage node, and is used for transmitting the strong photoelectric signal in the exposure stage when the pixel circuit works in the wide dynamic range mode to the second storage node;
  • a fourth transmission unit connected between the second storage node and the floating diffusion node, and configured to read the signal stored in the second storage node and transmit it to the floating diffusion node in the readout stage;
  • a second global reset unit connected between the power supply voltage and the second photoelectric conversion unit, for resetting the second photoelectric conversion unit before the exposure operation
  • the sensitivity of the second photoelectric conversion unit is lower than the sensitivity of the first photoelectric conversion unit.
  • both the first photoelectric conversion unit and the second photoelectric conversion unit are implemented by photodiodes; wherein, the photodiode area corresponding to the second photoelectric conversion unit is smaller than the photoelectric conversion unit corresponding to the first photoelectric conversion unit. diode area, so that the sensitivity of the second photoelectric conversion unit is lower than that of the first photoelectric conversion unit.
  • the first storage nodes and the second storage nodes are symmetrically distributed.
  • the main photosensitive photoelectric module further includes: a first storage capacitor, connected between the first storage node and a reference ground, for increasing the charge storage capability of the first storage node;
  • the strong light-sensing photoelectric module further includes: a second storage capacitor, connected between the second storage node and the reference ground, for increasing the charge storage capability of the second storage node.
  • both the first storage capacitor and the second storage capacitor are implemented with MIM capacitors, so as to shield the first storage node and the second storage node from light.
  • the main photosensitive photoelectric module further includes: a first control switch, connected between the first storage node and the first storage capacitor, for controlling the first storage node and the first storage node The connection between the storage capacitors is on and off;
  • the strong photosensitive photoelectric module further includes: a second control switch, connected between the second storage node and the second storage capacitor, for controlling the connection between the second storage node and the second storage capacitor connection on and off.
  • the pixel circuit further includes:
  • a floating reset module connected between a power supply voltage and the floating diffusion node, for resetting the floating diffusion node before a read operation
  • a source follower module connected to the floating diffusion node, for following the voltage of the floating diffusion node
  • the row selection module is connected between the source follower module and the vertical signal line, and is used for outputting the signal of the row where the pixel circuit is located to the vertical signal line when the row selection signal is valid.
  • the present invention also provides a global CMOS image sensor, the global CMOS image sensor comprising: the above pixel circuit.
  • the global CMOS image sensor is a front-illuminated charge-domain global CMOS image sensor.
  • a pixel circuit and a global CMOS image sensor of the present invention through the design of a strong photosensitive photoelectric module, can almost eliminate the influence of the parasitic light effect on the imaging quality in a low parasitic light effect mode; in a wide dynamic range In the mode, the dynamic range of the global CMOS image sensor can be greatly improved; moreover, the control difference between the two operating modes is very small (compared to the low parasitic light effect mode, the wide dynamic range mode only has one more control after the exposure ends, and the third The action of turning off the transmission unit after it is turned on) will not significantly increase the design difficulty of the corresponding control circuit.
  • the first storage node and the second storage node are symmetrically distributed, so that in the low parasitic light effect mode, the parasitic light charges collected in the first storage node and the second storage node are almost the same, so as to more effectively Eliminate the influence of parasitic light effects on imaging quality.
  • the present invention also increases the storage charge capacity of the first storage node and the second storage node by adding the first storage capacitor and the second storage capacitor; moreover, the first storage capacitor and the second storage capacitor are realized by using the MIM capacitor, which can shield the light.
  • the function of the plate is to shield the first storage node and the second storage node from light, thereby reducing the influence of the parasitic light effect on the first storage node and the second storage node.
  • the first control switch and the second control switch are added to control whether the first storage capacitor and the second storage capacitor are connected to the circuit, thereby greatly improving the application flexibility.
  • FIG. 1 is a specific circuit diagram of the pixel circuit according to the first embodiment of the present invention.
  • FIG. 2 is a schematic diagram of the circuit layout of the pixel circuit according to the first embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a circuit layout of two adjacent pixel circuits in Embodiment 1 of the present invention.
  • FIG. 4 shows the timing diagram of each control signal when the pixel circuit according to the first embodiment of the present invention operates in the low parasitic light effect mode;
  • (b) shows the operation of the pixel circuit according to the first embodiment of the present invention Timing diagram of each control signal in the wide dynamic range mode.
  • FIG. 5 is a specific circuit diagram of the pixel circuit according to the second embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the circuit layout of the pixel circuit according to the second embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a circuit layout of two adjacent pixel circuits according to the second embodiment of the present invention.
  • FIG. 8 is a specific circuit diagram of the pixel circuit according to the third embodiment of the present invention.
  • the first photoelectric conversion unit 101 The first photoelectric conversion unit
  • this embodiment provides a pixel circuit, and the pixel circuit includes:
  • the main photosensitive photoelectric module 100 is used to transmit the main photoelectric signal to the first storage node MEM L in the exposure stage; in the readout stage, read the signal stored in the first storage node MEM L and transmit it to the floating diffusion node FD ;
  • the strong photosensitive photoelectric module 200 when the pixel circuit works in a low parasitic light effect mode, is used to collect parasitic light signals to the second storage node MEMs in the exposure stage, and read the second storage node in the readout stage.
  • the signal stored in the node MEMS is transmitted to the floating diffusion node FD; when the pixel circuit operates in a wide dynamic range mode, it is used to transmit a strong photoelectric signal to the second storage node MEMS during the exposure stage , in the readout phase, the signal stored in the second storage node MEMS is read and transmitted to the floating diffusion node FD.
  • the main photosensitive photoelectric module 100 transmits the main photoelectric signal to the first storage node MEM L
  • the strong photosensitive photoelectric module 200 collects parasitic
  • the optical signal is sent to the second storage node MEM S ; in the readout stage, the main photosensitive photoelectric module 100 reads the signal stored in the first storage node MEM L (the signal is actually the main photoelectric signal + parasitic light signal) and transmit it to the floating diffusion node FD, the strong photosensitive photoelectric module 200 reads the signal stored in the second storage node MEMS (the signal is actually a parasitic light signal) and transmits it to the floating diffusion node FD;
  • This implementation utilizes the parasitic light signal collected by the strong photosensitive photoelectric module 200 to reduce or even eliminate the parasitic light part in the output signal of the main photosensitive photoelectric module 100, thereby avoiding the influence of the parasitic light effect on the subsequent imaging quality.
  • the main photosensitive photoelectric module 100 transmits the main photoelectric signal to the first storage node MEM L
  • the strong photosensitive photoelectric module 200 transmits the strong photoelectric signal to all the second storage node MEM S
  • the main photosensitive photoelectric module 100 reads the signal stored in the first storage node MEM L (the signal is actually the main photoelectric signal) and transmits it to the floating diffusion node FD
  • the strong photosensitive photoelectric module 200 reads the signal stored in the second storage node MEMS (the signal is actually a strong photoelectric signal) and transmits it to the floating diffusion node FD
  • the main photoelectric signal and the strong photoelectric signal are combined to improve the dynamic range of the entire pixel circuit, so that the dynamic range of the entire GS CIS is greatly improved.
  • the main photosensitive photoelectric module 100 includes:
  • a first photoelectric conversion unit 101 configured to generate the main photoelectric signal based on photoelectric conversion in the exposure stage
  • the first storage node MEM L is used to store the main photoelectric signal and the parasitic light signal when the pixel circuit works in a low parasitic light effect mode; when the pixel circuit works in a wide dynamic range mode, it is used for storing the main photoelectric signal;
  • a first transmission unit 102 connected between the first photoelectric conversion unit 101 and the first storage node MEM L , for transmitting the main photoelectric signal to the first storage node MEM L in the exposure stage;
  • the second transmission unit 103 is connected between the first storage node MEM L and the floating diffusion node FD, and is used for reading the signal stored in the first storage node MEM L and transmitting it to the readout stage. the floating diffusion node FD;
  • the first global reset unit 104 is connected between the power supply voltage VDD and the first photoelectric conversion unit 101, and is used for resetting the first photoelectric conversion unit 101 before the exposure operation.
  • the first photoelectric conversion unit 101 is implemented by a photodiode; wherein the anode end of the photodiode is grounded, and the cathode end of the photodiode is connected to the first storage unit through the first transmission unit 102 Node MEM L ; used for converting the optical signal into an electrical signal in the exposure stage, thereby obtaining the main photoelectric signal.
  • the first transmission unit 102 is implemented by an NMOS transistor; wherein the gate terminal of the NMOS transistor is connected to the first transmission control signal TG L , and the first connection terminal of the NMOS transistor is connected to the photodiode
  • the cathode terminal of the NMOS is connected to the first storage node MEM L ; the NMOS transistor is turned on when the first transmission control signal TG L is valid, so that the The main photoelectric signal is transmitted to the first storage node MEM L .
  • the first connection end of the NMOS tube is the source end, and the second connection end thereof is the drain end.
  • the first connection end of the NMOS tube may also be the drain end, and the second connection end of the NMOS tube is the source end, This has no effect on this example.
  • the second transmission unit 103 is implemented by an NMOS transistor; wherein the gate terminal of the NMOS transistor is connected to the second transmission control signal SW L , and the first connection terminal of the NMOS transistor is connected to the first transmission control signal SW L .
  • storage node MEM L the second connection end of which is connected to the floating diffusion node FD; for when the second transfer control signal SW L is valid, the NMOS transistor is turned on to read the first storage node The signal stored in MEM L is transmitted to the floating diffusion node FD.
  • the first connection end of the NMOS tube is the source end, and the second connection end thereof is the drain end.
  • the first connection end of the NMOS tube may also be the drain end, and the second connection end of the NMOS tube is the source end, This has no effect on this example.
  • the first global reset unit 104 is implemented by an NMOS transistor; wherein the gate terminal of the NMOS transistor is connected to the first global reset control signal OFG L , and the drain terminal of the NMOS transistor is connected to the power supply voltage VDD, Its source terminal is connected to the cathode terminal of the photodiode; when the first global reset control signal OFGL is valid, the NMOS transistor is turned on, thereby resetting the photodiode.
  • the first transmission unit 102 is also controlled so that the first global reset unit 104 resets the first photoelectric conversion unit 104 .
  • Storage node MEM L when the first photoelectric conversion unit 101 is reset by the first global reset unit 104 , the first transmission unit 102 is also controlled so that the first global reset unit 104 resets the first photoelectric conversion unit 104 .
  • the strong photosensitive photoelectric module 200 includes:
  • the second photoelectric conversion unit 201 is configured to generate the strong photoelectric signal based on photoelectric conversion in the exposure stage when the pixel circuit operates in the wide dynamic range mode;
  • the second storage node MEM S is used to store the collected parasitic light signal when the pixel circuit works in a low parasitic light effect mode; and is used to store the collected parasitic light signal when the pixel circuit works in a wide dynamic range mode Strong photoelectric signal;
  • the third transmission unit 202 is connected between the second photoelectric conversion unit 201 and the second storage node MEMS , and when the pixel circuit works in the wide dynamic range mode, is used to transmit the strong photoelectric signal to the second storage node MEMS ;
  • the fourth transmission unit 203 is connected between the second storage node MEMS and the floating diffusion node FD, and is used for reading the signal stored in the second storage node MEMS and transmitting it to the readout stage. the floating diffusion node FD;
  • the second global reset unit 204 is connected between the power supply voltage VDD and the second photoelectric conversion unit 201, and is used for resetting the second photoelectric conversion unit 201 before the exposure operation;
  • the sensitivity of the second photoelectric conversion unit 201 is lower than the sensitivity of the first photoelectric conversion unit 101 .
  • the second photoelectric conversion unit 201 is implemented by a photodiode; wherein, the anode end of the photodiode is grounded, and the cathode end of the photodiode is connected to the second storage unit through the third transmission unit 202
  • the node MEM S is used for converting an optical signal into an electrical signal in an exposure stage when the pixel circuit operates in a wide dynamic range mode, thereby obtaining the strong photoelectric signal.
  • the photodiode area corresponding to the second photoelectric conversion unit 201 is smaller than the photodiode area corresponding to the first photoelectric conversion unit 101, so that the sensitivity of the second photoelectric conversion unit 201 is lower than that of the first photoelectric conversion unit
  • the sensitivity of the unit 101 is favorable for the collection and conversion of the strong light signal by the second photoelectric conversion unit 201; of course, the sensitivity of the second photoelectric conversion unit 201 can be lower than that of the first photoelectric conversion unit 101.
  • the method for the sensitivity of also applies to this example. It should be noted that, in order to distinguish it from the photodiodes in the main photosensitive photoelectric module 100, the photodiodes in this example are all represented by low-sensitivity photodiodes in the following text.
  • the third transmission unit 202 is implemented by an NMOS transistor; wherein the gate terminal of the NMOS transistor is connected to the third transmission control signal TG S , and the first connection terminal of the NMOS transistor is connected to the low-sensitivity photodiode the cathode terminal, the second connection terminal of which is connected to the second storage node MEMS; for when the pixel circuit works in the wide dynamic range mode and the third transmission control signal TG S is valid, the NMOS tube conducts is turned on, thereby transmitting the strong photoelectric signal generated by the low-sensitivity photodiode to the second storage node MEMS .
  • the first connection end of the NMOS tube is the source end, and the second connection end thereof is the drain end.
  • the first connection end of the NMOS tube may also be the drain end, and the second connection end of the NMOS tube is the source end, This has no effect on this example.
  • the fourth transmission unit 203 is implemented by an NMOS transistor; wherein the gate terminal of the NMOS transistor is connected to the fourth transmission control signal SW S , and the first connection terminal of the NMOS transistor is connected to the second transmission control signal SW S .
  • storage node MEM S the second connection end of which is connected to the floating diffusion node FD; used for reading the second storage node when the fourth transmission control signal S S S is valid, the NMOS transistor is turned on The signal stored in the MEMS is transmitted to the floating diffusion node FD.
  • the first connection end of the NMOS tube is the source end, and the second connection end thereof is the drain end.
  • the first connection end of the NMOS tube may also be the drain end, and the second connection end of the NMOS tube is the source end, This has no effect on this example.
  • the second global reset unit 204 is implemented by an NMOS transistor; wherein the gate terminal of the NMOS transistor is connected to the second global reset control signal OFGS , and the drain terminal of the NMOS transistor is connected to the power supply voltage VDD, The source terminal is connected to the cathode terminal of the low-sensitivity photodiode; when the second global reset control signal OFGS is valid, the NMOS transistor is turned on, thereby resetting the low-sensitivity photodiode.
  • the second global reset unit 204 is also controlled by the third transmission unit 202 to reset the second photoelectric conversion unit 204.
  • Storage node MEMs when the second photoelectric conversion unit 201 is reset by the second global reset unit 204, the second global reset unit 204 is also controlled by the third transmission unit 202 to reset the second photoelectric conversion unit 204.
  • the layout design can be carried out as shown in Figure 3.
  • the pixel circuit further includes:
  • a floating reset module 300 connected between the power supply voltage VDD and the floating diffusion node FD, for resetting the floating diffusion node FD before the read operation;
  • a source follower module 400 connected to the floating diffusion node FD, for following the voltage of the floating diffusion node FD;
  • the row selection module 500 is connected between the source follower module 400 and the vertical signal line 600 , and is used for outputting the signal of the row where the pixel circuit is located to the vertical signal line 600 when the row selection signal RS is valid.
  • the floating reset module 300 is implemented by an NMOS transistor; wherein the gate terminal of the NMOS transistor is connected to the floating reset control signal RST, the drain terminal of the NMOS transistor is connected to the power supply voltage VDD, and the source terminal of the NMOS transistor is connected to The floating diffusion node FD is used for turning on the NMOS transistor when the floating reset control signal RST is valid, thereby resetting the floating diffusion node FD.
  • the source follower module 400 is implemented by an NMOS transistor; wherein the gate terminal of the NMOS transistor is connected to the floating diffusion node FD, the drain terminal of the NMOS transistor is connected to the power supply voltage VDD, and the source terminal of the NMOS transistor is connected to the power supply voltage VDD.
  • the NMOS transistor is controlled by the voltage at the floating diffusion node FD, when the voltage at the floating diffusion node FD is greater than its turn-on threshold, the NMOS tube is turned on, and follow the voltage of the floating diffusion node FD.
  • the row selection module 500 is implemented by an NMOS transistor; wherein the gate terminal of the NMOS transistor is connected to the row selection signal RS, and the drain terminal of the NMOS transistor is connected to the NMOS transistor corresponding to the source follower module 400 .
  • the source terminal of the source terminal of which is connected to the vertical signal line 600; for when the row selection signal RS is valid, the NMOS transistor is turned on, so as to output the signal of the row where the pixel circuit is located to the vertical signal line 600; on the signal line 600.
  • the first global reset unit 104 and the second global reset unit 204 are controlled to be turned on by the first global reset control signal OFGL and the second global reset control signal OFGS respectively, and the first transfer control signal TG L and the third transmission control signal TGS respectively control the first transmission unit 102 and the third transmission unit 202 to be turned on and then turned off; at this time, the first photoelectric conversion unit 101, the second photoelectric conversion unit 201, the first storage node MEM L and the second storage node MEMs are reset.
  • the first global reset unit 104 and the second global reset unit 204 are respectively controlled to be turned off by the first global reset control signal OFGL and the second global reset control signal OFG S , and the exposure starts; after the exposure, the first transmission control The signal TGL controls the first transmission unit 102 to be turned on and then turned off; at this time, the main photoelectric signal generated by the first photoelectric conversion unit 101 is transmitted to the first storage node MEM L through the first transmission unit 102 .
  • the row selection module 500 is controlled to be turned on by the row selection signal RS, and then the floating reset module 300 is controlled to be turned on by the floating reset control signal RST and then turned off; at this time, the floating diffusion node FD is reset, and the floating The voltage of the diffusion node FD serves as signal 1 (signal 1 is actually reset signal 1).
  • the second transmission unit 103 is controlled to be turned on and then turned off by the second transmission control signal SW L , so as to transmit the signal stored in the first storage node MEM L (the signal is actually the main photoelectric signal + the parasitic light signal) to the Floating diffusion node FD; at this time, the voltage of floating diffusion node FD is read as signal 2 (signal 2 is actually main photoelectric signal + parasitic light signal + reset signal 1).
  • the floating reset module 300 is controlled to be turned on and turned off by the floating reset control signal RST; at this time, the floating diffusion node FD is reset, and the voltage of the floating diffusion node FD is read as signal 3 (signal 3 is actually reset signal 2 ).
  • the fourth transmission unit 203 is controlled to be turned on and then turned off by the fourth transmission control signal SWS , so as to transmit the signal stored in the second storage node MEMS (the signal is actually a parasitic light signal) to the floating diffusion node FD ;
  • the first global reset unit 104 and the second global reset unit 204 are controlled to be turned on by the first global reset control signal OFGL and the second global reset control signal OFGS respectively, and the first transfer control signal TG L and the third transmission control signal TGS respectively control the first transmission unit 102 and the third transmission unit 202 to be turned on and then turned off; at this time, the first photoelectric conversion unit 101, the second photoelectric conversion unit 201, the first storage node MEM L and the second storage node MEMs are reset.
  • the first global reset unit 104 and the second global reset unit 204 are respectively controlled to be turned off by the first global reset control signal OFGL and the second global reset control signal OFG S , and the exposure starts; after the exposure, the first transmission control
  • the signal TGL controls the first transmission unit 102 to be turned on and then turned off.
  • the main photoelectric signal generated by the first photoelectric conversion unit 101 is transmitted to the first storage node MEM L through the first transmission unit 102, and the third transmission control signal TGS is used .
  • the third transmission unit 202 is controlled to be turned on and then turned off, and the strong photoelectric signal generated by the second photoelectric conversion unit 201 is transmitted to the second storage node MEMS through the third transmission unit 202 .
  • the row selection module 500 is controlled to be turned on by the row selection signal RS, and then the floating reset module 300 is controlled to be turned on by the floating reset control signal RST and then turned off; at this time, the floating diffusion node FD is reset, and the floating The voltage of the diffusion node FD serves as signal 1 (signal 1 is actually reset signal 1).
  • the second transfer unit 103 is controlled to be turned on and then turned off by the second transfer control signal SW L , so as to transfer the signal stored in the first storage node MEM L (the signal is actually the main photoelectric signal) to the floating diffusion node FD ;
  • the voltage of the floating diffusion node FD is read as signal 2 (signal 2 is actually the main photoelectric signal + reset signal 1).
  • the floating reset module 300 is controlled to be turned on and turned off by the floating reset control signal RST; at this time, the floating diffusion node FD is reset, and the voltage of the floating diffusion node FD is read as signal 3 (signal 3 is actually reset signal 2 ).
  • the main photosensitive photoelectric module 100 further includes: a first storage capacitor CL connected to the first storage node MEM L and Between the reference ground, it is used to increase the storage charge capacity of the first storage node MEM L ;
  • the strong photosensitive photoelectric module 200 further includes: a second storage capacitor C S , connected to the second storage node MEM S and a reference between the ground and the ground for increasing the charge storage capability of the second storage node MEMS .
  • the first storage capacitor CL and the second storage capacitor CS are both implemented with MIM capacitors, so as to shield the first storage node MEM L and the second storage node MEM S from light.
  • the selection modules 500 are all formed on the same layer, and the first storage capacitor CL and the second storage capacitor CS are formed above this layer because they are implemented by MIM capacitors, that is, the first storage capacitor CL is formed Above the first storage node MEM L , the second storage capacitor C S is formed above the second storage node MEM L
  • the main photosensitive photoelectric module 100 further includes: a first control switch KL connected to the first storage node MEM L and The first storage capacitor CL is used to control the connection between the first storage node MEM L and the first storage capacitor CL , so as to control whether the first storage capacitor CL is connected .
  • the strong photosensitive photoelectric module 200 further includes: a second control switch K S , connected between the second storage node MEMS and the second storage capacitor C S , It is used to control the connection between the second storage node MEMS and the second storage capacitor CS , so as to control whether the second storage capacitor CS is connected to the strong light-sensing photoelectric module 200 .
  • a second control switch K S connected between the second storage node MEMS and the second storage capacitor C S , It is used to control the connection between the second storage node MEMS and the second storage capacitor CS , so as to control whether the second storage capacitor CS is connected to the strong light-sensing photoelectric module 200 .
  • the charge storage capacity of the first storage node MEM L and the charge storage capacity of the second storage node MEM S can not be
  • the first storage capacitor CL is connected to the first control switch KL
  • the second storage capacitor C S is connected to the second control switch KS, so as to improve the overall performance.
  • the storage charge capacity of the first storage node MEM L and the second storage node MEM S ; and the charge storage capacity of the first storage node MEM L and the storage charge capacity of the second storage node MEMS can satisfy
  • the connection between the second storage node MEM S and the second storage capacitor CS so as to avoid the floating diffusion caused by the connection of the first storage capacitor CL and the second storage capacitor CS
  • the problem that the conversion efficiency of the node FD is reduced. It can be seen that, compared with the second embodiment, the application flexibility of the pixel circuit of this embodiment is greatly improved.
  • This embodiment provides a global CMOS image sensor, where the global CMOS image sensor includes: the pixel circuit described in the first embodiment, the second embodiment or the third embodiment.
  • the global CMOS image sensor is a front-illuminated charge-domain global CMOS image sensor.
  • the pixel circuit and the global CMOS image sensor of the present invention can almost eliminate the influence of the parasitic light effect on the imaging quality under the low parasitic light effect mode through the design of the strong photosensitive photoelectric module;
  • the dynamic range of the global CMOS image sensor can be greatly improved; moreover, the control difference between the two operating modes is very small (compared to the low parasitic light effect mode, the wide dynamic range mode only has one more control step after the exposure ends. The action of turning off the three transmission units after turning on) will not significantly increase the design difficulty of the corresponding control circuit.
  • the first storage node and the second storage node are symmetrically distributed, so that in the low parasitic light effect mode, the parasitic light charges collected in the first storage node and the second storage node are almost the same, so as to more effectively Eliminate the influence of parasitic light effects on imaging quality.
  • the present invention also increases the storage charge capacity of the first storage node and the second storage node by adding the first storage capacitor and the second storage capacitor; moreover, the first storage capacitor and the second storage capacitor are realized by using the MIM capacitor, which can shield the light.
  • the function of the plate is to shield the first storage node and the second storage node from light, thereby reducing the influence of the parasitic light effect on the first storage node and the second storage node.
  • the first control switch and the second control switch are added to control whether the first storage capacitor and the second storage capacitor are connected to the circuit, thereby greatly improving the application flexibility. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

提供了一种像素电路及全局CMOS图像传感器，像素电路包括：主感光光电模块（100），用于在曝光阶段，传输主光电信号至第一存储节点；在读出阶段，读取第一存储节点中存储的信号并传输至浮动扩散节点；强感光光电模块（200），当像素电路工作于低寄生光效应模式时，用于在曝光阶段，收集寄生光信号至第二存储节点，在读出阶段，读取第二存储节点中存储的信号并传输至浮动扩散节点；当像素电路工作于宽动态范围模式时，用于在曝光阶段，传输强光电信号至第二存储节点，在读出阶段，读取第二存储节点中存储的信号并传输至浮动扩散节点。解决了现有电荷域GS CIS因寄生光效应影响成像质量及因动态范围较小在强光下易过曝光的问题。

Description

一种像素电路及全局CMOS图像传感器 技术领域
本发明涉及CMOS图像传感器领域，特别是涉及一种像素电路及全局CMOS图像传感器。
背景技术
CMOS图像传感器按照其曝光方式的不同，可以分为RS(Rolling Shutter，卷帘)快门及GS(Global Shutter，全局)快门。卷帘快门，顾名思义就是像素逐行进行曝光，由于各行像素的曝光时间点不同，每行之间存在一定的时差，因此，其对于快速运动物体的拍摄或者相机在快速移动时所拍摄的物体往往会出现变形。而在全局快门曝光模式下，每一行像素单元同时开启曝光，信号同时由像素单元中的光电二极管向外传输，这样就避免卷帘快门曝光模式下的图像失真问题。
GS CIS(全局CMOS图像传感器)为了能存储电信号需要额外的存储单元，根据信号存储的方式可分为电压域GS CIS和电荷域GS CIS。电压域GS CIS的电荷信号先通过放大器转换成电压信号后存储在存储单元中；电荷域GS CIS的电荷信号直接存储在存储单元中；但是电荷域GS CIS通常受到寄生光信号的影响较严重，这将导致其成像质量受到严重影响。另外，GS CIS为了拓展其应用场景，在强光环境下要防止过曝光，故GS CIS应具有大动态范围。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种像素电路及全局CMOS图像传感器，用以解决现有技术中电荷域GS CIS因寄生光效应影响成像质量及因动态范围较小在强光下易过曝光的问题。
为实现上述目的及其他相关目的，本发明提供一种像素电路，所述像素电路包括：
主感光光电模块，用于在曝光阶段，传输主光电信号至第一存储节点；在读出阶段，读取所述第一存储节点中存储的信号并传输至浮动扩散节点；
强感光光电模块，当所述像素电路工作于低寄生光效应模式时，用于在曝光阶段，收集寄生光信号至第二存储节点，在读出阶段，读取所述第二存储节点中存储的信号并传输至所述浮动扩散节点；当所述像素电路工作于宽动态范围模式时，用于在曝光阶段，传输强光电信号至所述第二存储节点，在读出阶段，读取所述第二存储节点中存储的信号并传输至所述浮动扩散节点。
可选地，所述主感光光电模块包括：
第一光电转换单元，用于在曝光阶段，基于光电转换产生所述主光电信号；
第一存储节点，当所述像素电路工作于低寄生光效应模式时，用于存储所述主光电信号及所述寄生光信号；当所述像素电路工作于宽动态范围模式时，用于存储所述主光电信号；
第一传输单元，连接于所述第一光电转换单元和所述第一存储节点之间，用于在曝光阶段，传输所述主光电信号至所述第一存储节点；
第二传输单元，连接于所述第一存储节点和所述浮动扩散节点之间，用于在读出阶段，读取所述第一存储节点中存储的信号并传输至所述浮动扩散节点；
第一全局复位单元，连接于电源电压和所述第一光电转换单元之间，用于在曝光操作之前，复位所述第一光电转换单元。
可选地，所述强感光光电模块包括：
第二光电转换单元，当所述像素电路工作于宽动态范围模式时，用于在曝光阶段，基于光电转换产生所述强光电信号；
第二存储节点，当所述像素电路工作于低寄生光效应模式时，用于存储收集的所述寄生光信号；当所述像素电路工作于宽动态范围模式时，用于存储所述强光电信号；
第三传输单元，连接于所述第二光电转换单元和所述第二存储节点之间，当所述像素电路工作于宽动态范围模式时，用于在曝光阶段，传输所述强光电信号至所述第二存储节点；
第四传输单元，连接于所述第二存储节点和所述浮动扩散节点之间，用于在读出阶段，读取所述第二存储节点中存储的信号并传输至所述浮动扩散节点；
第二全局复位单元，连接于电源电压和所述第二光电转换单元之间，用于在曝光操作之前，复位所述第二光电转换单元；
其中，所述第二光电转换单元的灵敏度低于所述第一光电转换单元的灵敏度。
可选地，所述第一光电转换单元及所述第二光电转换单元均采用光电二极管实现；其中，所述第二光电转换单元对应的光电二极管面积小于所述第一光电转换单元对应的光电二极管面积，以使所述第二光电转换单元的灵敏度低于所述第一光电转换单元的灵敏度。
可选地，所述第一存储节点和所述第二存储节点对称分布。
可选地，所述主感光光电模块还包括：第一存储电容，连接于所述第一存储节点和参考地之间，用于增加所述第一存储节点的存储电荷能力；
所述强感光光电模块还包括：第二存储电容，连接于所述第二存储节点和参考地之间，用于增加所述第二存储节点的存储电荷能力。
可选地，所述第一存储电容及所述第二存储电容均采用MIM电容实现，以对所述第一存储节点及所述第二存储节点进行遮光。
可选地，所述主感光光电模块还包括：第一控制开关，连接于所述第一存储节点和所述第一存储电容之间，用于控制所述第一存储节点与所述第一存储电容之间连接的通断；
所述强感光光电模块还包括：第二控制开关，连接于所述第二存储节点和所述第二存储电容之间，用于控制所述第二存储节点与所述第二存储电容之间连接的通断。
可选地，所述像素电路还包括：
浮动复位模块，连接于电源电压和所述浮动扩散节点之间，用于在读取操作之前，复位所述浮动扩散节点；
源跟随模块，连接于所述浮动扩散节点，用于对所述浮动扩散节点的电压进行跟随；
行选择模块，连接于所述源跟随模块和垂直信号线之间，用于在行选择信号有效时，将所述像素电路所在行的信号输出至所述垂直信号线上。
本发明还提供了一种全局CMOS图像传感器，所述全局CMOS图像传感器包括：如上所述的像素电路。
可选地，所述全局CMOS图像传感器为正照式电荷域全局CMOS图像传感器。
如上所述，本发明的一种像素电路及全局CMOS图像传感器，通过强感光光电模块的设计，实现在低寄生光效应模式下，几乎可以消除寄生光效应对成像质量的影响；在宽动态范围模式下，可以大幅提升全局CMOS图像传感器的动态范围；而且，两种工作模式的控制差异很小(相较于低寄生光效应模式，宽动态范围模式仅在曝光结束后多了一个控制第三传输单元开启后关断的动作)，不会明显增加相应控制电路的设计难度。本发明还通过使第一存储节点和第二存储节点对称分布，以此实现在低寄生光效应模式下，第一存储节点和第二存储节点中收集的寄生光电荷几乎相同，从而更有效地消除寄生光效应对成像质量的影响。本发明还通过增设第一存储电容和第二存储电容来增加第一存储节点和第二存储节点的存储电荷能力；更通过将第一存储电容和第二存储电容采用MIM电容实现，起到遮光板的作用，以对第一存储节点及第二存储节点进行遮光，从而降低寄生光效应对第一存储节点及第二存储节点的影响。本发明更通过增设第一控制开关和第二控制开关，来控制第一存储电容和第二存储电容是否接入电路，从而大大提高了应用灵活性。
附图说明
图1显示为本发明实施例一所述像素电路的具体电路图。
图2显示为本发明实施例一所述像素电路的电路布局示意图。
图3显示为本发明实施例一中相邻两个所述像素电路的电路布局示意图。
图4中(a)显示为本发明实施例一所述像素电路工作于低寄生光效应模式下时，其各控制信号的时序图；(b)显示为本发明实施例一所述像素电路工作于宽动态范围模式下时，其各控制信号的时序图。
图5显示为本发明实施例二所述像素电路的具体电路图。
图6显示为本发明实施例二所述像素电路的电路布局示意图。
图7显示为本发明实施例二中相邻两个所述像素电路的电路布局示意图。
图8显示为本发明实施例三所述像素电路的具体电路图。
元件标号说明
100               主感光光电模块
101               第一光电转换单元
102               第一传输单元
103               第二传输单元
104               第一全局复位单元
200               强感光光电模块
201               第二光电转换单元
202               第三传输单元
203               第四传输单元
204               第二全局复位单元
300               浮动复位模块
400               源跟随模块
500               行选择模块
600               垂直信号线
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图8。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量及比例可为一种随意的改变，且其组件布局形态也可能更为复杂。
实施例一
如图1所示，本实施例提供一种像素电路，所述像素电路包括：
主感光光电模块100，用于在曝光阶段，传输主光电信号至第一存储节点MEM L；在读出阶段，读取所述第一存储节点MEM L中存储的信号并传输至浮动扩散节点FD；
强感光光电模块200，当所述像素电路工作于低寄生光效应模式时，用于在曝光阶段，收集寄生光信号至第二存储节点MEM S，在读出阶段，读取所述第二存储节点MEM S中存储的信号并传输至所述浮动扩散节点FD；当所述像素电路工作于宽动态范围模式时，用于在曝光阶段，传输强光电信号至所述第二存储节点MEM S，在读出阶段，读取所述第二存储节点MEM S中存储的信号并传输至所述浮动扩散节点FD。
本示例中，当所述像素电路工作于低寄生光效应模式时：在曝光阶段，所述主感光光电模块100传输主光电信号至第一存储节点MEM L，所述强感光光电模块200收集寄生光信号至第二存储节点MEM S；在读出阶段，所述主感光光电模块100读取所述第一存储节点MEM L中存储的信号(该信号实际上为主光电信号+寄生光信号)并传输至浮动扩散节点FD，所述强感光光电模块200读取所述第二存储节点MEM S中存储的信号(该信号实际上为寄生光信号)并传输至所述浮动扩散节点FD；以此实现利用所述强感光光电模块200收集的寄生光信号来降低甚至消除所述主感光光电模块100输出信号中的寄生光部分，从而避免寄生光效应对后续成像质量的影响。
当所述像素电路工作于宽动态范围模式时：在曝光阶段，所述主感光光电模块100传输主光电信号至第一存储节点MEM L，所述强感光光电模块200传输强光电信号至所述第二存储节点MEM S；在读出阶段，所述主感光光电模块100读取所述第一存储节点MEM L中存储的信号(该信号实际上为主光电信号)并传输至浮动扩散节点FD，所述强感光光电模块200读取所述第二存储节点MEM S中存储的信号(该信号实际上为强光电信号)并传输至所述浮动扩散节点FD；以此通过将所述主光电信号和所述强光电信号结合，来提高整个像素电路的动态范围，从而使整个GS CIS的动态范围得到极大提升。
作为示例，如图1所示，所述主感光光电模块100包括：
第一光电转换单元101，用于在曝光阶段，基于光电转换产生所述主光电信号；
第一存储节点MEM L，当所述像素电路工作于低寄生光效应模式时，用于存储所述主光电信号及所述寄生光信号；当所述像素电路工作于宽动态范围模式时，用于存储所述主光电信号；
第一传输单元102，连接于所述第一光电转换单元101和所述第一存储节点MEM L之间，用于在曝光阶段，传输所述主光电信号至所述第一存储节点MEM L；
第二传输单元103，连接于所述第一存储节点MEM L和所述浮动扩散节点FD之间，用于在读出阶段，读取所述第一存储节点MEM L中存储的信号并传输至所述浮动扩散节点FD；
第一全局复位单元104，连接于电源电压VDD和所述第一光电转换单元101之间，用于在曝光操作之前，复位所述第一光电转换单元101。
具体的，如图1所示，所述第一光电转换单元101采用光电二极管实现；其中，该光电二极管的阳极端接地，其阴极端通过所述第一传输单元102连接于所述第一存储节点MEM L；用于在曝光阶段，将光信号转换为电信号，以此得到所述主光电信号。
具体的，如图1所示，所述第一传输单元102采用NMOS管实现；其中，该NMOS管的栅极端接入第一传输控制信号TG L，其第一连接端连接于所述光电二极管的阴极端，其第二连接端连接于所述第一存储节点MEM L；用于在所述第一传输控制信号TG L有效时，该NMOS管导通，以此将光电二极管产生的所述主光电信号传输至所述第一存储节点MEM L。可选地，该NMOS管的第一连接端为源极端、其第二连接端为漏极端，当然，该NMOS管的第一连接端也可以为漏极端、其第二连接端为源极端，这对本示例没有影响。
具体的，如图1所示，所述第二传输单元103采用NMOS管实现；其中，该NMOS管的栅极端接入第二传输控制信号SW L，其第一连接端连接于所述第一存储节点MEM L，其第二连接端连接于所述浮动扩散节点FD；用于在所述第二传输控制信号SW L有效时，该NMOS管导通，以此读取所述第一存储节点MEM L中存储的信号并传输至所述浮动扩散节点FD。可选地，该NMOS管的第一连接端为源极端、其第二连接端为漏极端，当然，该NMOS管的第一连接端也可以为漏极端、其第二连接端为源极端，这对本示例没有影响。
具体的，如图1所示，所述第一全局复位单元104采用NMOS管实现；其中，该NMOS管的栅极端接入第一全局复位控制信号OFG L，其漏极端接入电源电压VDD，其源极端连接于光电二极管的阴极端；用于在所述第一全局复位控制信号OFG L有效时，该NMOS管导通，以此复位所述光电二极管。实际应用中，在通过所述第一全局复位单元104复位所述第一光电转换单元101时，还通过控制所述第一传输单元102，使所述第一全局复位单元104复位所述第一存储节点MEM L。
作为示例，如图1所示，所述强感光光电模块200包括：
第二光电转换单元201，当所述像素电路工作于宽动态范围模式时，用于在曝光阶段，基于光电转换产生所述强光电信号；
第二存储节点MEM S，当所述像素电路工作于低寄生光效应模式时，用于存储收集的所述寄生光信号；当所述像素电路工作于宽动态范围模式时，用于存储所述强光电信号；
第三传输单元202，连接于所述第二光电转换单元201和所述第二存储节点MEM S之间，当所述像素电路工作于宽动态范围模式时，用于在曝光阶段，传输所述强光电信号至所述第二存储节点MEM S；
第四传输单元203，连接于所述第二存储节点MEM S和所述浮动扩散节点FD之间，用于在读出阶段，读取所述第二存储节点MEM S中存储的信号并传输至所述浮动扩散节点FD；
第二全局复位单元204，连接于电源电压VDD和所述第二光电转换单元201之间，用于在曝光操作之前，复位所述第二光电转换单元201；
其中，所述第二光电转换单元201的灵敏度低于所述第一光电转换单元101的灵敏度。
具体的，如图1所示，所述第二光电转换单元201采用光电二极管实现；其中，该光电二极管的阳极端接地，其阴极端通过所述第三传输单元202连接于所述第二存储节点MEM S；用于当所述像素电路工作于宽动态范围模式时，在曝光阶段，将光信号转换为电信号，以此得到所述强光电信号。其中，所述第二光电转换单元201对应的光电二极管面积小于所述第一光电转换单元101对应的光电二极管面积，以使所述第二光电转换单元201的灵敏度低于所述第一光电转换单元101的灵敏度，从而有利于所述第二光电转换单元201对强光信号的采集与转换；当然，其它可以使所述第二光电转换单元201的灵敏度低于所述第一光电转换单元101的灵敏度的方法同样适用于本示例。需要注意的是，为了与所述主感光光电模块100中的光电二极管作区分，本示例所述光电二极管在后文中均使用低灵敏度光电二极管来表示。
具体的，如图1所示，所述第三传输单元202采用NMOS管实现；其中，该NMOS管的栅极端接入第三传输控制信号TG S，其第一连接端连接于低灵敏度光电二极管的阴极端，其第二连接端连接于所述第二存储节点MEM S；用于当所述像素电路工作于宽动态范围模式且所述第三传输控制信号TG S有效时，该NMOS管导通，以此将低灵敏度光电二极管产生的所述强光电信号传输至所述第二存储节点MEM S。可选地，该NMOS管的第一连接端为源极端、其第二连接端为漏极端，当然，该NMOS管的第一连接端也可以为漏极端、其第二连接端为源极端，这对本示例没有影响。
具体的，如图1所示，所述第四传输单元203采用NMOS管实现；其中，该NMOS管 的栅极端接入第四传输控制信号SW S，其第一连接端连接于所述第二存储节点MEM S，其第二连接端连接于所述浮动扩散节点FD；用于在所述第四传输控制信号SW S有效时，该NMOS管导通，以此读取所述第二存储节点MEM S中存储的信号并传输至所述浮动扩散节点FD。可选地，该NMOS管的第一连接端为源极端、其第二连接端为漏极端，当然，该NMOS管的第一连接端也可以为漏极端、其第二连接端为源极端，这对本示例没有影响。
具体的，如图1所示，所述第二全局复位单元204采用NMOS管实现；其中，该NMOS管的栅极端接入第二全局复位控制信号OFG S，其漏极端接入电源电压VDD，其源极端连接于低灵敏度光电二极管的阴极端；用于在所述第二全局复位控制信号OFG S有效时，该NMOS管导通，以此复位低灵敏度光电二极管。实际应用中，在通过所述第二全局复位单元204复位所述第二光电转换单元201时，还通过控制所述第三传输单元202，使所述第二全局复位单元204复位所述第二存储节点MEM S。
作为示例，如图2所示，在对本实施例所述像素电路进行布局时，所述第一存储节点MEM L和所述第二存储节点MEM S对称分布，以此实现当所述像素电路工作于低寄生光效应模式时，所述第一存储节点MEM L和所述第二存储节点MEM S中收集的寄生光电荷几乎相同，从而更有效地消除寄生光效应对后续成像质量的影响。实际应用中，为了更好地消除寄生光效应对后续成像质量的影响，在对GS CIS中多个像素电路进行布局时，可按照图3所示方式进行布局设计。
作为示例，如图1所示，所述像素电路还包括：
浮动复位模块300，连接于电源电压VDD和所述浮动扩散节点FD之间，用于在读取操作之前，复位所述浮动扩散节点FD；
源跟随模块400，连接于所述浮动扩散节点FD，用于对所述浮动扩散节点FD的电压进行跟随；
行选择模块500，连接于所述源跟随模块400和垂直信号线600之间，用于在行选择信号RS有效时，将所述像素电路所在行的信号输出至所述垂直信号线600上。
具体的，如图1所示，所述浮动复位模块300采用NMOS管实现；其中，该NMOS管的栅极端接入浮动复位控制信号RST，其漏极端接入电源电压VDD，其源极端连接于所述浮动扩散节点FD；用于在所述浮动复位控制信号RST有效时，该NMOS管导通，以此复位所述浮动扩散节点FD。
具体的，如图1所示，所述源跟随模块400采用NMOS管实现；其中，该NMOS管的栅极端连接于所述浮动扩散节点FD，其漏极端接入电源电压VDD，其源极端连接于所述行 选择模块500的输入端；该NMOS管受控于所述浮动扩散节点FD处的电压，在所述浮动扩散节点FD处的电压大于其导通阈值时，该NMOS管导通，并对所述浮动扩散节点FD的电压进行跟随。
具体的，如图1所示，所述行选择模块500采用NMOS管实现；其中，该NMOS管的栅极端接入行选择信号RS，其漏极端连接于所述源跟随模块400对应的NMOS管的源极端，其源极端连接于所述垂直信号线600；用于在所述行选择信号RS有效时，该NMOS管导通，以此将所述像素电路所在行的信号输出至所述垂直信号线600上。
下面请结合图1和4，对本实施例所述像素电路在低寄生光效应模式和宽动态范围模式的工作情况进行详细说明。
当所述像素电路工作于低寄生光效应模式时，
在曝光阶段：首先，通过第一全局复位控制信号OFG L和第二全局复位控制信号OFG S分别控制第一全局复位单元104和第二全局复位单元204导通，通过第一传输控制信号TG L和第三传输控制信号TG S分别控制第一传输单元102和第三传输单元202导通后关断；此时，第一光电转换单元101、第二光电转换单元201、第一存储节点MEM L及第二存储节点MEM S均被重置。随后，通过第一全局复位控制信号OFG L和第二全局复位控制信号OFG S分别控制第一全局复位单元104和第二全局复位单元204关断，曝光开始；曝光结束后，通过第一传输控制信号TG L控制第一传输单元102导通后关断；此时，第一光电转换单元101产生的主光电信号通过第一传输单元102传输至第一存储节点MEM L中。
在读出阶段：先通过行选择信号RS控制行选择模块500导通，然后通过浮动复位控制信号RST控制浮动复位模块300导通后关断；此时，浮动扩散节点FD被复位，读取浮动扩散节点FD的电压作为信号1(信号1实际上为复位信号1)。之后，通过第二传输控制信号SW L控制第二传输单元103导通后关断，以将第一存储节点MEM L中存储的信号(该信号实际上为主光电信号+寄生光信号)传输至浮动扩散节点FD；此时，读取浮动扩散节点FD的电压作为信号2(信号2实际上为主光电信号+寄生光信号+复位信号1)。再之后，通过浮动复位控制信号RST控制浮动复位模块300导通后关断；此时，浮动扩散节点FD被复位，读取浮动扩散节点FD的电压作为信号3(信号3实际上为复位信号2)。最后，通过第四传输控制信号SW S控制第四传输单元203导通后关断，以将第二存储节点MEM S中存储的信号(该信号实际上为寄生光信号)传输至浮动扩散节点FD；此时，读取浮动扩散节点FD的电压作为信号4(信号4实际上为寄生光信号+复位信号2)；由此，主光电信号可以根据以下公式得 到：主光电信号＝(信号2-信号1)-(信号4-信号3)。
当所述像素电路工作于宽动态范围模式时：
在曝光阶段：首先，通过第一全局复位控制信号OFG L和第二全局复位控制信号OFG S分别控制第一全局复位单元104和第二全局复位单元204导通，通过第一传输控制信号TG L和第三传输控制信号TG S分别控制第一传输单元102和第三传输单元202导通后关断；此时，第一光电转换单元101、第二光电转换单元201、第一存储节点MEM L及第二存储节点MEM S均被重置。随后，通过第一全局复位控制信号OFG L和第二全局复位控制信号OFG S分别控制第一全局复位单元104和第二全局复位单元204关断，曝光开始；曝光结束后，通过第一传输控制信号TG L控制第一传输单元102导通后关断，第一光电转换单元101产生的主光电信号通过第一传输单元102传输至第一存储节点MEM L中，通过第三传输控制信号TG S控制第三传输单元202导通后关断，第二光电转换单元201产生的强光电信号通过第三传输单元202传输至第二存储节点MEM S中。
在读出阶段：先通过行选择信号RS控制行选择模块500导通，然后通过浮动复位控制信号RST控制浮动复位模块300导通后关断；此时，浮动扩散节点FD被复位，读取浮动扩散节点FD的电压作为信号1(信号1实际上为复位信号1)。之后，通过第二传输控制信号SW L控制第二传输单元103导通后关断，以将第一存储节点MEM L中存储的信号(该信号实际上为主光电信号)传输至浮动扩散节点FD；此时，读取浮动扩散节点FD的电压作为信号2(信号2实际上为主光电信号+复位信号1)。再之后，通过浮动复位控制信号RST控制浮动复位模块300导通后关断；此时，浮动扩散节点FD被复位，读取浮动扩散节点FD的电压作为信号3(信号3实际上为复位信号2)。最后，通过第四传输控制信号SW S控制第四传输单元203导通后关断，以将第二存储节点MEM S中存储的信号(该信号实际上为强光电信号)传输至浮动扩散节点FD；此时，读取浮动扩散节点FD的电压作为信号4(信号4实际上为强光电信号+复位信号2)；由此，主光电信号可以根据以下公式得到：主光电信号＝(信号2-信号1)，强光电信号可以根据以下公式得到：强光电信号＝(信号4-信号3)。
实施例二
如图5所示，相较于实施例一，本实施例所述像素电路中，所述主感光光电模块100还包括：第一存储电容C L，连接于所述第一存储节点MEM L和参考地之间，用于增加所述第一存储节点MEM L的存储电荷能力；所述强感光光电模块200还包括：第二存储电容C S，连接于所述第二存储节点MEM S和参考地之间，用于增加所述第二存储节点MEM S的存储电荷能 力。
作为示例，所述第一存储电容C L及所述第二存储电容C S均采用MIM电容实现，以对所述第一存储节点MEM L及所述第二存储节点MEM S进行遮光。如图6所示，在对本实施例所述像素电路进行布局时，第一光电转换单元101、第一存储节点MEM L、第一传输单元102、第二传输单元103、第一全局复位单元104、第二光电转换单元201、第二存储节点MEM S、第三传输单元202、第四传输单元203、第二全局复位单元204、浮动扩散节点FD、浮动复位模块300、源跟随模块400及行选择模块500均形成于同一层，而所述第一存储电容C L及所述第二存储电容C S因采用MIM电容实现，故形成于该层上方，即所述第一存储电容C L形成于所述第一存储节点MEM L上方、所述第二存储电容C S形成于所述第二存储节点MEM S上方，以此起到遮光板的作用，对所述第一存储节点MEM L及所述第二存储节点MEM S进行遮光，从而降低寄生光效应对所述第一存储节点MEM L及所述第二存储节点MEM S的影响。实际应用中，在对GS CIS中多个像素电路进行布局时，可按照图7所示方式进行布局设计。
实施例三
如图8所示，相较于实施例二，本实施例所述像素电路中，所述主感光光电模块100还包括：第一控制开关K L，连接于所述第一存储节点MEM L和所述第一存储电容C L之间，用于控制所述第一存储节点MEM L与所述第一存储电容C L之间连接的通断，以此控制所述第一存储电容C L是否接入所述主感光光电模块100中；所述强感光光电模块200还包括：第二控制开关K S，连接于所述第二存储节点MEM S和所述第二存储电容C S之间，用于控制所述第二存储节点MEM S与所述第二存储电容C S之间连接的通断，以此控制所述第二存储电容C S是否接入所述强感光光电模块200中。
本示例通过所述第一控制开关K L及所述第二控制开关K S的设计，在所述第一存储节点MEM L的存储电荷能力及所述第二存储节点MEM S的存储电荷能力无法满足当前应用需求时，利用所述第一控制开关K L接入所述第一存储电容C L，同时利用所述第二控制开关K S接入所述第二存储电容C S，从而提高所述第一存储节点MEM L及所述第二存储节点MEM S的存储电荷能力；而在所述第一存储节点MEM L的存储电荷能力及所述第二存储节点MEM S的存储电荷能力能够满足当前应用需求时，利用所述第一控制开关K L切断所述第一存储节点MEM L和所述第一存储电容C L之间的连接，同时利用所述第二控制开关K S切断所述第二存储节点MEM S和所述第二存储电容C S之间的连接，以此避免因所述第一存储电容C L和所述第二存储电容C S的接入，导致所述浮动扩散节点FD转换效率降低的问题。可见，本实施例 所述像素电路相较于实施例二，其应用灵活性得到极大提高。
实施例四
本实施例提供一种全局CMOS图像传感器，所述全局CMOS图像传感器包括：如实施例一、实施例二或实施例三所述的像素电路。可选地，所述全局CMOS图像传感器为正照式电荷域全局CMOS图像传感器。
综上所述，本发明的一种像素电路及全局CMOS图像传感器，通过强感光光电模块的设计，实现在低寄生光效应模式下，几乎可以消除寄生光效应对成像质量的影响；在宽动态范围模式下，可以大幅提升全局CMOS图像传感器的动态范围；而且，两种工作模式的控制差异很小(相较于低寄生光效应模式，宽动态范围模式仅在曝光结束后多了一个控制第三传输单元开启后关断的动作)，不会明显增加相应控制电路的设计难度。本发明还通过使第一存储节点和第二存储节点对称分布，以此实现在低寄生光效应模式下，第一存储节点和第二存储节点中收集的寄生光电荷几乎相同，从而更有效地消除寄生光效应对成像质量的影响。本发明还通过增设第一存储电容和第二存储电容来增加第一存储节点和第二存储节点的存储电荷能力；更通过将第一存储电容和第二存储电容采用MIM电容实现，起到遮光板的作用，以对第一存储节点及第二存储节点进行遮光，从而降低寄生光效应对第一存储节点及第二存储节点的影响。本发明更通过增设第一控制开关和第二控制开关，来控制第一存储电容和第二存储电容是否接入电路，从而大大提高了应用灵活性。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (11)

  1. 一种像素电路，其特征在于，所述像素电路包括：
    主感光光电模块，用于在曝光阶段，传输主光电信号至第一存储节点；在读出阶段，读取所述第一存储节点中存储的信号并传输至浮动扩散节点；
    强感光光电模块，当所述像素电路工作于低寄生光效应模式时，用于在曝光阶段，收集寄生光信号至第二存储节点，在读出阶段，读取所述第二存储节点中存储的信号并传输至所述浮动扩散节点；当所述像素电路工作于宽动态范围模式时，用于在曝光阶段，传输强光电信号至所述第二存储节点，在读出阶段，读取所述第二存储节点中存储的信号并传输至所述浮动扩散节点。
  2. 根据权利要求1所述的像素电路，其特征在于，所述主感光光电模块包括：
    第一光电转换单元，用于在曝光阶段，基于光电转换产生所述主光电信号；
    第一存储节点，当所述像素电路工作于低寄生光效应模式时，用于存储所述主光电信号及所述寄生光信号；当所述像素电路工作于宽动态范围模式时，用于存储所述主光电信号；
    第一传输单元，连接于所述第一光电转换单元和所述第一存储节点之间，用于在曝光阶段，传输所述主光电信号至所述第一存储节点；
    第二传输单元，连接于所述第一存储节点和所述浮动扩散节点之间，用于在读出阶段，读取所述第一存储节点中存储的信号并传输至所述浮动扩散节点；
    第一全局复位单元，连接于电源电压和所述第一光电转换单元之间，用于在曝光操作之前，复位所述第一光电转换单元。
  3. 根据权利要求2所述的像素电路，其特征在于，所述强感光光电模块包括：
    第二光电转换单元，当所述像素电路工作于宽动态范围模式时，用于在曝光阶段，基于光电转换产生所述强光电信号；
    第二存储节点，当所述像素电路工作于低寄生光效应模式时，用于存储收集的所述寄生光信号；当所述像素电路工作于宽动态范围模式时，用于存储所述强光电信号；
    第三传输单元，连接于所述第二光电转换单元和所述第二存储节点之间，当所述像素电路工作于宽动态范围模式时，用于在曝光阶段，传输所述强光电信号至所述第二存储节点；
    第四传输单元，连接于所述第二存储节点和所述浮动扩散节点之间，用于在读出阶段，读取所述第二存储节点中存储的信号并传输至所述浮动扩散节点；
    第二全局复位单元，连接于电源电压和所述第二光电转换单元之间，用于在曝光操作之前，复位所述第二光电转换单元；
    其中，所述第二光电转换单元的灵敏度低于所述第一光电转换单元的灵敏度。
  4. 根据权利要求3所述的像素电路，其特征在于，所述第一光电转换单元及所述第二光电转换单元均采用光电二极管实现；其中，所述第二光电转换单元对应的光电二极管面积小于所述第一光电转换单元对应的光电二极管面积，以使所述第二光电转换单元的灵敏度低于所述第一光电转换单元的灵敏度。
  5. 根据权利要求3所述的像素电路，其特征在于，所述第一存储节点和所述第二存储节点对称分布。
  6. 根据权利要求3所述的像素电路，其特征在于，所述主感光光电模块还包括：第一存储电容，连接于所述第一存储节点和参考地之间，用于增加所述第一存储节点的存储电荷能力；
    所述强感光光电模块还包括：第二存储电容，连接于所述第二存储节点和参考地之间，用于增加所述第二存储节点的存储电荷能力。
  7. 根据权利要求6所述的像素电路，其特征在于，所述第一存储电容及所述第二存储电容均采用MIM电容实现，以对所述第一存储节点及所述第二存储节点进行遮光。
  8. 根据权利要求6所述的像素电路，其特征在于，所述主感光光电模块还包括：第一控制开关，连接于所述第一存储节点和所述第一存储电容之间，用于控制所述第一存储节点与所述第一存储电容之间连接的通断；
    所述强感光光电模块还包括：第二控制开关，连接于所述第二存储节点和所述第二存储电容之间，用于控制所述第二存储节点与所述第二存储电容之间连接的通断。
  9. 根据权利要求1-8任一项所述的像素电路，其特征在于，所述像素电路还包括：
    浮动复位模块，连接于电源电压和所述浮动扩散节点之间，用于在读取操作之前，复位所述浮动扩散节点；
    源跟随模块，连接于所述浮动扩散节点，用于对所述浮动扩散节点的电压进行跟随；
    行选择模块，连接于所述源跟随模块和垂直信号线之间，用于在行选择信号有效时，将所述像素电路所在行的信号输出至所述垂直信号线上。
  10. 一种全局CMOS图像传感器，其特征在于，所述全局CMOS图像传感器包括：如权利要求1-9任一项所述的像素电路。
  11. 根据权利要求10所述的全局CMOS图像传感器，其特征在于，所述全局CMOS图像传感器为正照式电荷域全局CMOS图像传感器。
PCT/CN2021/082040 2020-12-28 2021-03-22 一种像素电路及全局cmos图像传感器 WO2022141822A1 (zh)

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