WO2022133769A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022133769A1
WO2022133769A1 PCT/CN2020/138504 CN2020138504W WO2022133769A1 WO 2022133769 A1 WO2022133769 A1 WO 2022133769A1 CN 2020138504 W CN2020138504 W CN 2020138504W WO 2022133769 A1 WO2022133769 A1 WO 2022133769A1
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Prior art keywords
layer
isolation
substrate
area
insulating layer
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PCT/CN2020/138504
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English (en)
French (fr)
Inventor
余兆伟
韦钦河
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN202080003522.0A priority Critical patent/CN114981972A/zh
Priority to PCT/CN2020/138504 priority patent/WO2022133769A1/zh
Priority to US17/602,780 priority patent/US12127439B2/en
Publication of WO2022133769A1 publication Critical patent/WO2022133769A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/868—Arrangements for polarized light emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • Exemplary embodiments of the present disclosure provide a display substrate including a display area, a first transition area in the display area, a second transition area in the first transition area, and a second transition area
  • the void area in wherein: the first transition area includes a substrate, a buffer layer disposed on the substrate, an insulating layer disposed on the buffer layer, and a plurality of isolation dams disposed on the insulating layer ; the second transition zone comprises a substrate, a buffer layer arranged on the substrate and a plurality of isolation columns arranged on the buffer layer; the plurality of isolation dams and the plurality of isolation columns surround the Blank area settings.
  • the display area includes a substrate, a drive structure layer disposed on the substrate, a planarization layer disposed on the drive structure layer, and a pixel definition layer defining a pixel opening area;
  • the driving structure layer includes a buffer layer on the substrate, an active layer on the buffer layer, a first insulating layer covering the active layer, and a first gate on the first insulating layer An electrode layer, a second insulating layer covering the first gate electrode layer, a second gate electrode layer on the second insulating layer, a third insulating layer covering the second gate electrode layer, and a second insulating layer on the second gate electrode layer a first source-drain electrode layer on three insulating layers;
  • the insulating layer includes a first insulating layer on the buffer layer, a second insulating layer on the first insulating layer, and a third insulating layer on the second insulating layer.
  • the plurality of isolation dams include a plurality of first isolation dams and a plurality of second isolation dams
  • the first isolation dams include a first dam foundation and a first protrusion
  • the second isolation dams Including a second protrusion, the closest distance between the first isolation dam and the empty area is greater than the closest distance between the second isolation dam and the empty area, wherein:
  • the first dam foundation and the planarization layer are arranged in the same layer, and the first protrusions and the second protrusions are defined in the same layer as the pixels.
  • the height of the end of the first isolation dam away from the base is greater than or equal to the height of the end of the second isolation dam away from the base height from the base.
  • a distance between an end of the second isolation dam close to the base and an end of the isolation pillar close to the base is 5 ⁇ m to 40 ⁇ m
  • the distance between one end of the first isolation dam close to the base and one end of the second isolation dam close to the base is 10 ⁇ m to 40 ⁇ m.
  • the isolation column includes a second dam foundation and a third protrusion, wherein:
  • the second dam foundation and the planarization layer are arranged in the same layer, and the third protrusions and the pixels are defined as arranged in the same layer.
  • the height of one end of the isolation dam away from the base is greater than or equal to the distance between the end of the isolation column away from the base and the base the height of.
  • the width of the end of the isolation pillar away from the substrate is smaller than the width of the end of the isolation pillar close to the substrate.
  • the closest distance from one end of the isolation column away from the substrate to the void area is 10 to 20 microns; the closest distance from the end of the isolation column close to the substrate to the void area is 1 to 5 microns.
  • the width of the end of the isolation dam remote from the base is smaller than the width of the end of the isolation dam near the base.
  • the display area further includes a light emitting structure layer disposed on the planarization layer and an encapsulation layer disposed on the light emitting structure layer, the encapsulation layer including a first inorganic layer, a second an inorganic layer and an organic encapsulation layer disposed between the first inorganic layer and the second inorganic layer, the first inorganic layer and the second inorganic layer both extending to the first transition region and the A second transition zone covers the plurality of isolation dams and the plurality of isolation pillars.
  • the display substrate further includes a polarizer on the encapsulation layer, and a contact area of the second inorganic layer and the polarizer in the second transition region is on the substrate is located within the range of the orthographic projection of the isolation column on the substrate, in a plane parallel to the substrate, and the second inorganic layer and the polarizer are in the second transition region
  • the area of the inner contact area is greater than or equal to the area of one end of the isolation pillar away from the substrate.
  • Exemplary embodiments of the present disclosure also provide a display device including the aforementioned display substrate, wherein the void area is used for installing a hardware structure.
  • Exemplary embodiments of the present disclosure also provide a method for fabricating a display substrate, the display substrate includes a display area, a first transition area located in the display area, and a second transition area located in the first transition area And a void area located in the second transition area, the preparation method includes:
  • An insulating layer covering the buffer layer is formed on the first transition area, the second transition area and the dummy area, and a patterning process is performed on the insulating layer of the second transition area and the dummy area , forming a first groove exposing the buffer layer, and the orthographic projection of the first groove on the substrate covers the orthographic projection of the second transition area and the void area on the substrate;
  • a plurality of isolation dams are formed on the insulating layer, a plurality of isolation pillars are formed in the first groove, and the plurality of isolation dams and the plurality of isolation pillars are arranged around the void area.
  • the isolation dam and the isolation pillar are provided in the same layer, are formed of the same material and are formed by the same process; or, the isolation dam and the isolation pillar are provided in a different layer.
  • the preparation method further includes: forming a driving structure layer provided on the substrate, a planarization layer provided on the driving structure layer, and a pixel opening region defining a driving structure layer in the display region. pixel definition layer;
  • the driving structure layer includes a buffer layer on the substrate, an active layer on the buffer layer, a first insulating layer covering the active layer, and a first gate on the first insulating layer An electrode layer, a second insulating layer covering the first gate electrode layer, a second gate electrode layer on the second insulating layer, a third insulating layer covering the second gate electrode layer, and a second insulating layer on the second gate electrode layer a first source-drain electrode layer on three insulating layers;
  • the insulating layer includes a first insulating layer on the buffer layer, a second insulating layer on the first insulating layer, and a third insulating layer on the second insulating layer.
  • the plurality of isolation dams include a plurality of first isolation dams and a plurality of second isolation dams
  • the first isolation dams include a first dam foundation and a first protrusion
  • the second isolation dams Including a second protrusion, the closest distance between the first isolation dam and the empty area is greater than the closest distance between the second isolation dam and the empty area;
  • the first dam foundation and the planarization layer are arranged in the same layer, and the first protrusions and the second protrusions are defined in the same layer as the pixels.
  • the isolation column includes a second dam foundation and a third protrusion, wherein:
  • the second dam foundation and the planarization layer are arranged in the same layer, and the third protrusions and the pixels are defined as arranged in the same layer.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the disclosure
  • Fig. 2 is the sectional view of A-A in Fig. 1;
  • FIG. 3 is a schematic diagram of a display substrate after an active layer pattern is formed according to an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a display substrate after forming a gate electrode pattern according to an exemplary embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a display substrate after forming a capacitive electrode pattern according to an exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a display substrate after forming a third insulating layer pattern according to an exemplary embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a display substrate after forming source electrode and drain electrode patterns according to an exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a display substrate after a planarization layer pattern is formed according to an exemplary embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a display substrate after forming an anode pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a display substrate after forming an organic light-emitting layer and a cathode pattern according to an exemplary embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a display substrate after forming an encapsulation layer pattern according to an exemplary embodiment of the present disclosure
  • FIG. 13 is a schematic flowchart of a method for fabricating a display substrate according to an exemplary embodiment of the present disclosure.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by means of elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • OLED display device is a self-luminous display device. Compared with traditional liquid crystal display, it has significant advantages such as high brightness, high contrast, high saturated color and high response rate, and has gradually become the mainstream product in the display field.
  • some terminal manufacturers In the actual application process, in order to pursue a larger effective display area and reduce the frame, some terminal manufacturers have begun to set the installation holes used to reserve the installation position of the front camera and other hardware on the effective display (Active Display) on the display panel. Area, AA) area.
  • the surface of flexible display products needs to be attached with a polarizer to prevent the influence of natural light on the display device.
  • the polarizer can also The integrated black effect of the display device is realized.
  • the main component of the polarizer is polyvinyl acetate to absorb dyeing substances (iodine-based compounds).
  • the upper and lower layers of the polarizer are provided with protective films. It is damaged during transportation and affects the use. Therefore, when attaching the polarizer to the display device, it is necessary to tear off the lower protective film. After attaching the polarizer, use a laser to cut the mounting hole (AA hole) area. After the through hole is formed, the upper protective film of the polarizer is torn off, and the subsequent cover plate lamination work is carried out.
  • Laser cutting is to irradiate the workpiece with a focused high-power density laser beam, so that the irradiated material quickly melts, vaporizes, ablates or reaches the ignition point, and at the same time, the molten material is blown away by the high-speed airflow coaxial with the beam, so as to realize the cutting of the workpiece. open.
  • the display substrate is composed of multiple layers of materials with different thermal expansion coefficients, and under the action of heat, the upper and lower stacked layers in the AA hole area are split to different degrees.
  • the existing structural design leads to a relatively large cutting angle of the inorganic encapsulation layer at the edge of the AA hole, which is prone to stress concentration.
  • the edge of the AA hole is not easily wetted by ink. Therefore, in the subsequent film tearing process, due to The effect of film adhesion further increases the degree of splitting of the AA hole, which in turn destroys the packaging structure of the AA hole area, causing the growing black spots (GDS) phenomenon on the display screen, which seriously affects the product. yield and display quality.
  • GDS growing black spots
  • Embodiments of the present disclosure provide a display substrate, a method for fabricating the same, and a display device. Without changing the existing process flow, by arranging a plurality of isolation columns around the void area, the stack structure of the cutting front void area is retracted inward. , to avoid the interlayer splitting phenomenon caused by the thermal expansion of the film layer caused by the heat conduction of the cutting edge, thus solving the problem of cracking of the edge structure (Crack) caused by the adhesive stress in the subsequent film tearing process.
  • Rack cracking of the edge structure
  • the contact area between the inorganic encapsulation layer and the polarizer is increased, the angle formed by the cutting edge of the AA hole is reduced, the stress concentration at the cutting edge of the AA hole is reduced, and the edge caused by the adhesive stress in the subsequent film tearing process is avoided. Structure Crack, GDS problem formed.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view taken along A-A in FIG. 1 , illustrating a display area, a first transition area, a second transition area, and a display area on a plane perpendicular to the display substrate The structure of the empty area. As shown in FIG.
  • the main structure of the display substrate includes a display area 100, a first transition area 200, a second transition area 300 and a blank area 400, and the first transition area 200 is located in the display area 100, the second transition area 300 is located in the first transition area 200, and the void area 400 is located in the second transition area 300, that is, the first transition area 200 is an annular area surrounding the second transition area 300, and the second transition area 300 is an annular area surrounding the void area 400 .
  • the position and shape of the empty area 400 in the display area 100 are not limited, and may be a circle as shown in FIG. 1 , or an ellipse, a square, a diamond, or other polygons.
  • the main structure of the display area 100 includes a plurality of light-emitting units distributed in an array, and each light-emitting unit includes a driving structure layer and a light-emitting structure layer disposed on the substrate 10,
  • the driving structure layer includes a plurality of thin film transistors, and FIG. 2 only takes two light-emitting units and two thin film transistors as an example for illustration.
  • the driving structure layer mainly includes a buffer layer 11 disposed on the substrate 10 and a thin film transistor 101 disposed on the buffer layer 11 .
  • the light emitting structure layer mainly includes an anode 31 connected to the drain electrode of the thin film transistor 101, a pixel definition layer 32 defining a pixel opening area, an organic light emitting layer 33 formed in the pixel opening area and on the pixel defining layer 32, and formed on the organic light emitting layer.
  • the encapsulation layer includes a stacked first inorganic layer 35 , an organic encapsulation layer 36 and a second inorganic layer 37 .
  • the main structure of the first transition region 200 includes the buffer layer 11 disposed on the substrate 10 , the insulating layer 201 disposed on the buffer layer 11 , and the insulating layer 201 disposed on the buffer layer 11 .
  • the insulating layer 201 disposed on the substrate 10 includes a first insulating layer, a second insulating layer and a third insulating layer formed at the same time as the driving structure layer.
  • the main structure of the second transition region 300 includes a buffer layer 11 disposed on the substrate 10 , a plurality of isolation pillars 203 disposed on the buffer layer 11 , and a plurality of isolation pillars 203 disposed on the plurality of isolation pillars 203 .
  • the plurality of isolation dams 202 and the plurality of isolation pillars 203 are arranged around the empty area 400 , the multiple isolation dams 202 are arranged between the isolation pillars 203 and the display area 100 , and the orthographic projection of the isolation pillars 203 on the substrate 10 is the same as that of the placement.
  • the orthographic projections of the empty regions 400 on the substrate 10 do not overlap.
  • the width of the end of the isolation pillar 203 away from the substrate 10 is smaller than the width of the end of the isolation pillar 203 close to the substrate 10 .
  • the width of one end of the isolation column 203 away from the substrate 10 is smaller than the width of the end of the isolation column 203 close to the substrate 10 , so that the stack structure near the void area is further retracted, thereby reducing heat conduction at the cutting edge.
  • the width of the end of the isolation dam 202 remote from the substrate 10 is smaller than the width of the end of the isolation dam 202 near the substrate 10 .
  • the cross-sectional shape of each isolation dam 202 is a regular trapezoid.
  • the width of the end of the isolation dam 202 away from the substrate 10 may be smaller than the width of the end of the isolation dam 202 close to the substrate 10 .
  • the process is relatively simple, and the organic encapsulation layer 36 is not easy to cross the isolation dam 202 to avoid encapsulation failure.
  • the width of the end of the isolation dam 202 remote from the substrate 10 is greater than the width of the end of the isolation dam 202 close to the substrate 10 .
  • the cross-sectional shape of each isolation dam 202 is an inverted trapezoid.
  • the isolation dam 202 can be used to disconnect the organic light emitting layer 33 and the cathode 34 to be subsequently evaporated in the transition region 200 to block the water and oxygen intrusion path from the empty region 400 to the display region 100 .
  • the height of one end of the isolation dam 202 away from the substrate 10 from the substrate 10 is greater than or equal to the height of the end of the isolation pillar 203 away from the substrate 10 from the substrate 10 .
  • the height of the end of the isolation dam 202 away from the base 10 from the base 10 is greater than or equal to the height of the isolation column 203 away from the base
  • the height of one end of 10 from the base 10 can reduce the laser cutting thickness of the mounting hole area.
  • the encapsulation layer includes a stacked first inorganic layer 35 , an organic encapsulation layer 36 and a second inorganic layer 37 .
  • the isolation dam 202 is far away from one end of the substrate 10 .
  • the height of the substrate 10 is greater than the height of the end of the first inorganic layer 35 away from the substrate 10 from the substrate 10 . This can prevent leakage of the organic encapsulation layer 36 side to the other side of the isolation dam 202 .
  • the plurality of isolation dams include a first isolation dam 202a and a second isolation dam 202b, the first isolation dam 202a and the second isolation dam 202b are spaced around the void 400, and the first isolation dam The closest distance between 202 a and the empty area 400 is greater than the closest distance between the second isolation dam 202 b and the empty area 400 .
  • the first isolation dam 202a includes a first dam base and a first protrusion
  • the second isolation dam 202b includes a second protrusion
  • the first dam base and the planarization layer are disposed in the same layer
  • the first protrusion And the second bump is defined as the same layer as the pixel.
  • the isolation pillar 203 includes a second dam base and a third protrusion, wherein: the second dam base and the planarization layer are disposed in the same layer, and the third protrusion and the pixel definition are disposed in the same layer.
  • the height of one end of the first isolation dam 202 a away from the substrate 10 from the substrate 10 is greater than or equal to the height of the end of the second isolation dam 202 b away from the substrate 10 from the substrate 10
  • the height difference between the two can be 1-15 microns.
  • the void area 400 is a through hole, and each structural film layer and substrate in the through hole are removed by laser cutting.
  • the structure of the display substrate of the present disclosure will be described below through an example of a preparation process of the display substrate.
  • the "patterning process” referred to in the present disclosure includes processes such as depositing film layers, coating photoresist, mask exposure, developing, etching and stripping photoresist.
  • Deposition can be selected from any one or more of sputtering, evaporation and chemical vapor deposition, coating can be selected from any one or more of spray coating and spin coating, and etching can be selected from dry etching. and any one or more of wet engraving.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process.
  • the "film” can also be referred to as a "layer”.
  • the "film” before the patterning process it is called a "film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B” means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.
  • the manufacturing process of the display substrate of FIG. 2 may include the following steps:
  • An active layer pattern is formed on a substrate.
  • Forming the active layer pattern on the substrate includes: firstly depositing a buffer film on the substrate 10 to form a buffer layer 11 pattern covering the entire substrate 10 . Then, a layer of active layer thin film is deposited, and the active layer thin film is patterned through a patterning process to form a pattern of the active layer 12 disposed on the buffer layer 11 in the display area 100 , as shown in FIG. 3 .
  • the pattern of the active layer 12 is only formed in the display area 100 , and only the buffer layer 11 is formed in the first transition area 200 , the second transition area 300 and the empty area 400 at this time.
  • the substrate can be a flexible substrate, using materials such as polyimide PI, polyethylene terephthalate PET or surface-treated soft polymer film.
  • the buffer film may be silicon nitride SiNx or silicon oxide SiOx, etc., and may be a single layer or a multi-layer structure of silicon nitride/silicon oxide.
  • a gate electrode pattern is formed.
  • Forming the gate electrode pattern includes: depositing a first insulating film and a first metal film in sequence on the substrate 10 formed with the above-mentioned structure, and patterning the first metal film through a patterning process to form a first layer covering the active layer 12 and the buffer layer 11.
  • the first gate electrode 14 , the second gate electrode 15 and the gate line are only formed in the display area 100 , and the buffer layer 11 and the first transition area 200 , the second transition area 300 and the blank area 400 are formed at this time.
  • insulating layer 13 .
  • a capacitor electrode pattern is formed.
  • Forming the capacitor electrode pattern includes: sequentially depositing a second insulating film and a second metal film on the substrate 10 formed with the above structure, and patterning the second metal film through a patterning process to form covering the first gate electrode 14 and the second gate electrode.
  • 15 and the second insulating layer 16 of the first insulating layer 13 and the pattern of the capacitor electrode 17 disposed on the second insulating layer 16 the position of the capacitor electrode 17 corresponds to the position of the second gate electrode 15, and the capacitor electrode 17 corresponds to the second gate electrode 15.
  • the gate electrode 15 constitutes a capacitor, as shown in FIG. 5 .
  • the capacitor electrode 17 is only formed in the display area 100 , and the buffer layer 11 , the first insulating layer 13 and the second insulating layer 16 are formed in the first transition area 200 , the second transition area 300 and the empty area 400 at this time.
  • a third insulating layer pattern with via holes and grooves is formed.
  • Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate 10 formed with the above-mentioned structure, patterning the third insulating film through a patterning process to form a pattern of the third insulating layer 18, and the third insulating layer 18 is in the display area.
  • 100 is provided with at least two first vias K1, the third insulating layer 18, the second insulating layer 16 and the first insulating layer 13 in the two first vias K1 are etched away, exposing the active layer 12,
  • the third insulating layer 18 further defines a first groove K2.
  • the orthographic projection of the first groove K2 on the substrate covers the orthographic projection of the second transition region 300 and the void region 400 on the substrate.
  • the third insulating layer 18 , the second insulating layer 16 and the first insulating layer 13 are etched away to expose the buffer layer 11 , as shown in FIG. 6 . That is, the two first via holes are only formed in the display area 100 , the first groove K2 is formed in the second transition area 300 and the dummy area 400 , and the buffer layer 11 and the first insulating layer are formed in the first transition area 200 at this time.
  • layer 13 , second insulating layer 16 and third insulating layer 18 are examples of the buffer layer 11 and the first insulating layer.
  • Source and drain electrode patterns are formed. Forming the source and drain electrode patterns includes: depositing a third metal film on the substrate 10 formed with the above structure, patterning the third metal film through a patterning process, and forming the source electrode 19 , the drain electrode 20 and the data line in the display area 100 (not shown) pattern, the source electrode 19 and the drain electrode 20 are respectively connected to the active layer 12 through two first via holes, as shown in FIG. 7 .
  • the source electrode 19, the drain electrode 20 and the data line are only formed in the display area 100
  • the buffer layer 11 and the first groove K2 are formed in the second transition area 300 and the empty area 400 at this time
  • the first transition area 200 is formed
  • the driving structure layer in the display region 100 includes the active layer 12, the first gate electrode 14, the second gate electrode 15, the capacitor electrode 17, the source electrode 19, the drain electrode 20, the gate line and the data line, the gate line and the data line
  • the vertical intersection of lines defines a sub-pixel, and a thin film transistor composed of an active layer 12, a first gate electrode 14, a source electrode 19, and a drain electrode 20 is disposed within the sub-pixel.
  • the insulating layers located in the first transition region 200 include the first insulating layer 13 , the second insulating layer 16 and the third insulating layer 18 .
  • the first insulating layer and the second insulating layer are also called gate insulating layers (GI), and the third insulating layer is also called interlayer insulating layer (ILD).
  • GI gate insulating layers
  • ILD interlayer insulating layer
  • a planarization layer pattern is formed. Forming the planarization layer pattern includes: coating a fourth insulating film on the substrate on which the aforementioned pattern is formed, and forming a fourth insulating layer 21 pattern covering the source electrode 19 and the drain electrode 20 in the display area 100 by a photolithography process of mask exposure and development , the fourth insulating layer 21 is provided with a second via hole K3 , and the second via hole K3 exposes the drain electrode 20 , as shown in FIG. 8 .
  • the fourth insulating layer 21 is formed on the display area 100 , the first transition area 200 and the second transition area 300 , and the orthographic projection of the fourth insulating layer 21 on the first transition area 200 and the subsequently formed first isolation dam 202 a are on the substrate
  • the dummy region 400 is formed with the buffer layer 11 .
  • the fourth insulating layer is also called a planarization layer (PLN).
  • Forming the anode pattern includes: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the transparent conductive film through a patterning process, and forming an anode 31 pattern in the display area 100, and the anode 31 is connected to the drain electrode 20 through a second via hole, such as shown in Figure 9.
  • the anode 31 is only formed in the display area 100, the transparent conductive films of the first transition area 200, the second transition area 300 and the empty area 400 are etched away, and the first transition area 200 is formed with the buffer layer 11,
  • the first insulating layer 13 , the second insulating layer 16 , the third insulating layer 18 and the fourth insulating layer 21 disposed on the third insulating layer 18 , the second transition region 300 is formed with the buffer layer 11 and disposed on the buffer layer 11
  • the fourth insulating layer 21 is formed, and the buffer layer 11 is formed in the void region 400 .
  • the transparent conductive film can be indium tin oxide ITO or indium zinc oxide IZO.
  • a pixel definition layer pattern is formed.
  • Forming the pixel definition layer pattern includes: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and forming a pixel definition layer (Pixel Define Layer) 32 pattern by a photolithography process, and the pixel definition layer 32 pattern can be located in the display area 100, the first transition In the region 200 and the second transition region 300, the pixel definition layer 32 pattern of the display region 100 defines a pixel opening area exposing the anode 31 in each sub-pixel, and a part of the pixel definition layer 32 pattern of the first transition region 200 is provided on the fourth insulating layer 21, the convex part of the first isolation dam 202a is formed, the other part is disposed on the third insulating layer 18, the convex part of the second isolation dam 202b is formed, and the pattern of the pixel definition layer 32 of the second transition region 300 is disposed on the third insulating layer 18.
  • the pixel definition layer can be made of polyimide, acrylic, polyethylene terephthalate, or the like.
  • the isolation pillars 203 are arranged at intervals around the void region 400 , and the isolation dams 202 are arranged between the isolation pillars 203 and the display area 100 .
  • the isolation dam 202 is formed in the first transition region 200
  • the isolation pillar 203 is formed in the second transition region 300 .
  • a plurality of isolation dams 202 and a plurality of isolation pillars 203 are used to block water and oxygen intrusion and crack propagation paths from the void area 400 to the display area 100 .
  • each isolation column 203 has the characteristics of being narrow at the top and wide at the bottom, that is, one end of the isolation column 203 away from the base 10 ( The width a1 of the upper end) is smaller than the width b1 of one end (lower end) of the isolation pillar 203 close to the substrate 10 .
  • the cross-sectional shape of each isolation pillar 203 may be a regular trapezoid.
  • the closest distance from one end (upper end) of the isolation pillar 203 away from the substrate 10 to the void region 400 is the end of the isolation pillar 203 close to the substrate 10 (Lower end) is between 2 times and 6 times the closest distance from the empty area 400 .
  • the closest distance from one end (upper end) of the isolation pillar 203 away from the substrate 10 to the void area 400 may be 10 to 20 microns to prevent thermal expansion failure of the encapsulation layer during laser cutting of the void area 400 .
  • the closest distance between one end (lower end) of the isolation column 203 close to the substrate 10 and the empty area 400 can be 1 to 5 microns, so as to prevent the transition area 200 from being too wide to affect the display effect.
  • each isolation dam 202 has the characteristics of being narrow in the upper part and wide in the lower part, that is, one end of the isolation dam 202 away from the substrate 10 ( The width a2 or a3 of the upper end) is smaller than the width b2 or b3 of one end (lower end) of the isolation dam 202 close to the substrate 10 .
  • the cross-sectional shape of each isolation pillar 203 may be a regular trapezoid.
  • the cross-sectional shape of each isolation dam 202 has the characteristics of being wide in the upper part and narrow in the lower part, that is, the width a2 of one end (upper end) of the isolation dam 202 away from the substrate 10 Or a3 is greater than the width b2 or b3 of one end (lower end) of the isolation dam 202 close to the substrate 10 .
  • the cross-sectional shape of each isolation pillar 203 may be an inverted trapezoid.
  • the height h2 or h3 of the end of the isolation dam 202 away from the substrate 10 from the substrate 10 is greater than or equal to the height h1 of the end of the isolation pillar 203 away from the substrate 10 from the substrate 10 .
  • each isolation pillar 203 may be a rectangle, a circle, or an ellipse.
  • the plurality of isolation dams 202 includes a plurality of first isolation dams 202a and a plurality of second isolation dams 202b, the plurality of first isolation dams 202a and the plurality of second isolation dams 202b respectively surrounding isolation columns 203 is set, and the closest distance between the first isolation dam 202a and the isolation column 203 is greater than the closest distance between the second isolation dam 202b and the isolation column 203 .
  • the second isolation dam 202b in a plane perpendicular to the substrate 10, is located between one end (lower end) of the second isolation dam 202b close to the substrate 10 and one end (lower end) of the isolation pillar 203 close to the substrate 10
  • the distance can be 5 to 40 microns.
  • the distance between them may be 10 to 40 microns to prevent poor display caused by the organic encapsulation layer 36 climbing over the first isolation dam 202a.
  • the isolation dam 202 and the isolation pillar 203 may be fabricated in the same layer, or may be fabricated in a different layer.
  • the embodiments of the present disclosure do not limit the materials of the isolation dams 202 and the isolation pillars 203 , and do not limit which layer of the display substrate forms the isolation dams 202 and the isolation pillars 203 .
  • the isolation dam 202 may be formed by any one or more layers of a planarization layer, a pixel definition layer or a support pillar layer (not shown in the figure), and the isolation pillar 203 may also be formed by a planarization layer. Any one or more layers of the ionization layer, the pixel definition layer or the support pillar layer are prepared and formed.
  • the support column layer of the display area 100 is used to maintain the distance between the display substrate and the cover plate (not shown in the figure), so as to prevent the OLED film layer from being scratched or generating Newton's rings.
  • the display substrate further includes at least one Crack Dam (not shown in the figure), which is used to prevent the insulating layer 201 of the first transition region 200 from being broken and thus damaged due to the laser cutting the mounting hole.
  • the anti-crack dam can be formed between the isolation pillar 203 and the isolation dam 202b, and the anti-crack dam can include any one or more of the following: a first anti-crack dam prepared in the same layer as the source-drain electrode layer. A crack dam, a second crack prevention dam prepared in the same layer as the first gate electrode layer, and a third crack prevention dam prepared in the same layer as the second gate electrode layer.
  • the dam foundation of the isolation pillars 203 is set on the buffer layer 11 , the step of preparing the anti-crack dam can be omitted, and the isolation pillars 203 can simultaneously serve as a driving structure layer to protect the display area 100 when the mounting holes are cut by laser. and the structure of the light-emitting layer.
  • Forming an organic light-emitting layer and a cathode pattern includes: sequentially evaporating the organic light-emitting material and the cathode metal thin film on the substrate on which the aforementioned pattern is formed, to form the organic light-emitting layer 33 and the cathode 34 pattern.
  • the organic light-emitting layer 33 is connected to the anode 31 in the pixel opening area defined by the pixel definition layer 32 , and the cathode 34 is disposed on the organic light-emitting layer 33 .
  • the organic light emitting layer 33 and the cathode 34 are formed on the support pillar layer; in the first transition region 200, the organic light emitting layer 33 and the cathode 34 are formed on the isolation dam 202, and in the second transition region 300, the organic light emitting layer 33 and the cathode 34 are formed on the isolation pillar 203; in the void region 400, the organic light-emitting layer 33 and the cathode 34 are formed on the buffer layer 11, as shown in FIG. 11 .
  • the organic light-emitting layer 33 mainly includes an light-emitting layer (EML).
  • the organic light-emitting layer may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer arranged in sequence to improve the efficiency of electron and hole injection into the light-emitting layer.
  • metal materials such as silver Ag, aluminum Al, copper Cu, lithium Li, etc., or an alloy of the above metals.
  • Forming the encapsulation layer pattern includes: firstly depositing a first inorganic thin film on the substrate on which the pattern is formed, the first inorganic thin film covering the display area 100 , the first transition area 200 , the second transition area 300 and the void area 400 to form the first inorganic thin film Layer 35 pattern. Subsequently, the organic encapsulation layer 36 is formed on the display area 100 by means of inkjet printing. Subsequently, a second inorganic thin film is deposited, and the second inorganic thin film covers the display area 100 , the first transition area 200 , the second transition area 300 and the void area 400 to form a pattern of the second inorganic layer 37 , as shown in FIG.
  • the encapsulation layer is an inorganic/organic/inorganic three-layer structure, the organic layer in the middle is only formed in the display area 100 , and the upper and lower inorganic layers cover the display area 100 , the first transition area 200 , the second transition area 300 and the empty space. In area 400, the packaging of the display substrate is completed.
  • the light-emitting structure layer located in the display area 100 includes an anode 31 , a pixel definition layer 32 , an organic light-emitting layer 33 , a cathode 34 and an encapsulation layer.
  • each structural film layer and substrate of the void area 400 are etched away by a related process such as a laser (Laser) to form the embodiment of the present disclosure.
  • a related process such as a laser (Laser) to form the embodiment of the present disclosure.
  • the hole in the OLED display substrate is shown in Figure 2.
  • all the structural film layers and substrates of the void area 400 can be etched away to form through holes, or part of the structural film layers of the void area 400 can be etched away to form blind holes, which can be determined according to actual needs. , the embodiments of the present disclosure do not make specific limitations.
  • the display substrate provided by the present disclosure cuts the pre-empty area by arranging the isolation columns 203 around the void area 400 at intervals.
  • the stacked structure of 400 shrinks inwardly, avoiding the interlayer splitting phenomenon caused by the thermal expansion of the film layer caused by the heat conduction of the cutting edge, thus solving the problem of cracking of the edge structure (Crack) caused by the adhesive stress during the subsequent film tearing process.
  • the contact area between the inorganic encapsulation layer and the polarizer is also increased (as shown in FIG.
  • the polarizer 38 and the display substrate are bonded by roller bonding, the polarizer 38 and the second isolation dam 202b and between the polarizer 38 and the isolation column 203 can actually be completely bonded) , reducing the angle formed by the edge cutting of the AA hole, reducing the stress concentration at the cutting edge of the AA hole, thereby avoiding the GDS problem formed by the edge structure Crack caused by the adhesive stress in the subsequent film tearing process.
  • the preparation process of the embodiment of the present disclosure can be realized by using the existing mature preparation equipment without changing the existing process flow, the process is simple to realize, easy to implement, high production efficiency, easy to realize the process, low in production cost and good quality. It has the advantages of high rate and good application prospect.
  • the structure of the display substrate of the present disclosure and the manufacturing process thereof are merely exemplary illustrations. In actual implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the OLED display substrate can be not only a top emission structure, but also a bottom emission structure.
  • the thin film transistor can be not only a top-gate structure, but also a bottom-gate structure, not only a double-gate structure, but also a single-gate structure.
  • the thin film transistor may be an amorphous silicon (a-Si) thin film transistor, a low temperature polysilicon (LTPS) thin film transistor or an oxide (Oxide) thin film transistor, and other electrodes, leads and structures may also be provided in the driving structure layer and the light emitting structure layer.
  • a-Si amorphous silicon
  • LTPS low temperature polysilicon
  • Oxide oxide
  • the film layer is not specifically limited in this embodiment of the present disclosure.
  • the present disclosure also provides a method for manufacturing a display substrate, the display substrate includes a display area, a first transition area located in the display area, a second transition area located in the first transition area, and a void located in the second transition area Area.
  • the preparation method of the display substrate of the present disclosure includes:
  • the isolation dams and the isolation pillars are disposed in the same layer, using the same material and formed by the same process; or, the isolation dams and the isolation pillars are disposed in different layers.
  • the preparation method further includes: forming a driving structure layer provided on the substrate, a planarization layer provided on the driving structure layer, and a pixel definition layer defining a pixel opening region in the display area;
  • the driving structure layer includes a buffer layer on the flexible substrate, an active layer on the buffer layer, a first insulating layer covering the active layer, a first gate electrode layer on the first insulating layer, and covering the first gate electrode layer a second insulating layer, a second gate electrode layer on the second insulating layer, a third insulating layer covering the second gate electrode layer, and a first source-drain electrode layer on the third insulating layer;
  • the insulating layer includes a first insulating layer on the buffer layer, a second insulating layer on the first insulating layer, and a third insulating layer on the second insulating layer.
  • the plurality of isolation dams includes a plurality of first isolation dams and a plurality of second isolation dams
  • the first isolation dams include a first dam base and a first protrusion
  • the second isolation dams include a second protrusion
  • the closest distance between the first isolation dam and the empty area is greater than the closest distance between the second isolation dam and the empty area.
  • the first dam foundation and the planarization layer are arranged in the same layer, and the first protrusions and the second protrusions are defined as being arranged in the same layer as the pixels.
  • the isolation pillar includes a second dam base and a third protrusion, wherein: the second dam base and the planarization layer are disposed in the same layer, and the third protrusion and the pixel are defined in the same layer.
  • the preparation method further includes: forming a support pillar layer on the pixel definition layer; the isolation dam can be prepared in the same layer as any one or more of the planarization layer, the pixel definition layer and the support pillar layer, and the isolation dam
  • the pillars can be prepared in the same layer as any one or several of the planarization layer, the pixel definition layer, and the support pillar layer.
  • the present disclosure provides a preparation method of a display substrate.
  • the stack structure of the void area before cutting is shrunk inward, avoiding the layer caused by thermal expansion of the film layer caused by the heat conduction of the cutting edge.
  • Inter-split phenomenon thus solving the problem of edge structure crack caused by adhesive stress in the subsequent film tearing process.
  • it also increases the contact area between the inorganic encapsulation layer and the polarizer, and reduces the AA hole edge cutting.
  • the formed angle reduces the stress concentration at the cutting edge of the AA hole, thereby avoiding the GDS problem caused by the edge structure Crack caused by the adhesive stress in the subsequent film tearing process.
  • the preparation process of the present disclosure can be realized by using the existing mature preparation equipment without changing the existing process flow, and the process is simple to realize, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the present disclosure also provides a display device, including the display substrate of the foregoing embodiments, wherein the blank area of the foregoing embodiments is used to install a hardware structure, exemplarily, the hardware structure includes a structure such as a camera.
  • the display device can be any product or component that has a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括显示区域、位于显示区域中的第一过渡区、位于第一过渡区中的第二过渡区以及位于第二过渡区中的置空区，第一过渡区包括基底、设置在基底上的缓冲层、设置在缓冲层上的绝缘层和设置在绝缘层上的多个隔离坝，第二过渡区包括基底、设置在基底上的缓冲层和设置在缓冲层上的多个隔离柱，多个隔离坝和多个隔离柱均围绕置空区设置。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，OLED技术越来越多的应用各种显示装置中，特别是手机和平板电脑等智能终端产品中。
对于智能终端产品，大部分厂商都在追求更高的屏占比，如全面屏和无边框屏，以期给用户带来更炫的视觉冲击。由于智能终端等产品通常需要设置前置摄像头、光线传感器等硬件，因此在OLED显示屏的有效显示区域开设安装孔以设置摄像头等硬件的方案，正备受业内的高度关注。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开示例性实施例提供了一种显示基板，包括显示区域、位于所述显示区域中的第一过渡区、位于所述第一过渡区中的第二过渡区以及位于所述第二过渡区中的置空区，其中：所述第一过渡区包括基底、设置在所述基底上的缓冲层、设置在所述缓冲层上的绝缘层和设置在所述绝缘层上的多个隔离坝；所述第二过渡区包括基底、设置在所述基底上的缓冲层和设置在所述缓冲层上的多个隔离柱；所述多个隔离坝和所述多个隔离柱均围绕所述置空区设置。
在示例性实施方式中，所述显示区域包括基底、设置在所述基底上的驱动结构层、设置在所述驱动结构层上的平坦化层和限定出像素开口区域的像 素定义层；
所述驱动结构层包括位于所述基底上的缓冲层、位于所述缓冲层上的有源层、覆盖所述有源层的第一绝缘层、位于所述第一绝缘层上的第一栅电极层、覆盖所述第一栅电极层的第二绝缘层、位于所述第二绝缘层上的第二栅电极层、覆盖所述第二栅电极层的第三绝缘层以及位于所述第三绝缘层上的第一源漏电极层；
所述绝缘层包括位于所述缓冲层上的第一绝缘层、位于所述第一绝缘层上的第二绝缘层以及位于所述第二绝缘层上的第三绝缘层。
在示例性实施方式中，所述多个隔离坝包括多个第一隔离坝和多个第二隔离坝，所述第一隔离坝包括第一坝基和第一凸起，所述第二隔离坝包括第二凸起，所述第一隔离坝与所述置空区的最近距离大于所述第二隔离坝与所述置空区的最近距离，其中：
所述第一坝基与所述平坦化层同层设置，所述第一凸起和第二凸起与所述像素定义成同层设置。
在示例性实施方式中，在垂直于所述基底的平面内，所述第一隔离坝远离所述基底的一端距离所述基底的高度大于或等于所述第二隔离坝远离所述基底的一端距离所述基底的高度。
在示例性实施方式中，在垂直于所述基底的平面内，所述第二隔离坝靠近所述基底的一端与所述隔离柱靠近所述基底的一端之间的距离为5微米至40微米，所述第一隔离坝靠近所述基底的一端与所述第二隔离坝靠近所述基底的一端之间的距离为10微米至40微米。
在示例性实施方式中，所述隔离柱包括第二坝基和第三凸起，其中：
所述第二坝基与所述平坦化层同层设置，所述第三凸起与所述像素定义成同层设置。
在示例性实施方式中，在垂直于所述基底的平面内，所述隔离坝远离所述基底的一端距离所述基底的高度大于或等于所述隔离柱远离所述基底的一端距离所述基底的高度。
在示例性实施方式中，在垂直于所述基底的平面内，所述隔离柱远离所述基底一端的宽度小于所述隔离柱靠近所述基底一端的宽度。
在示例性实施方式中，所述隔离柱远离所述基底一端距离所述置空区的最近距离为10至20微米；所述隔离柱靠近所述基底一端距离所述置空区的最近距离为1至5微米。
在示例性实施方式中，在垂直于所述基底的平面内，所述隔离坝远离所述基底一端的宽度小于所述隔离坝靠近所述基底一端的宽度。
在示例性实施方式中，所述显示区域还包括设置在所述平坦化层上的发光结构层以及设置在所述发光结构层上的封装层，所述封装层包括第一无机层、第二无机层以及设置在所述第一无机层和所述第二无机层之间的有机封装层，所述第一无机层和所述第二无机层均延伸至所述第一过渡区和所述第二过渡区，且覆盖所述多个隔离坝和所述多个隔离柱。
在示例性实施方式中，所述显示基板还包括位于所述封装层上的偏振片，所述第二无机层与所述偏振片在所述第二过渡区内的接触区域在所述基底上的正投影，位于所述隔离柱在所述基底上的正投影的范围之内，在平行于所述基底的平面内，所述第二无机层与所述偏振片在所述第二过渡区内的接触区域的面积大于或等于所述隔离柱远离所述基底的一端的面积。
本公开示例性实施例还提供了一种显示装置，包括前述的显示基板，其中，所述置空区用于安装硬件结构。
本公开示例性实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域、位于所述显示区域中的第一过渡区、位于所述第一过渡区中的第二过渡区以及位于所述第二过渡区中的置空区，所述制备方法包括：
形成覆盖基底的缓冲层；
在所述第一过渡区、所述第二过渡区和所述置空区形成覆盖所述缓冲层的绝缘层，并对所述第二过渡区和所述置空区的绝缘层进行构图工艺，形成暴露出所述缓冲层的第一凹槽，所述第一凹槽在所述基底上的正投影覆盖第二过渡区和置空区在所述基底上的正投影；
在所述绝缘层上形成多个隔离坝，在所述第一凹槽内形成多个隔离柱，所述多个隔离坝和所述多个隔离柱围绕所述置空区设置。
在示例性实施方式中，所述隔离坝和所述隔离柱同层设置、采用相同材料且通过同一工艺形成；或者，所述隔离坝和所述隔离柱非同层设置。
在示例性实施方式中，所述制备方法还包括：在所述显示区域形成设置在所述基底上的驱动结构层、设置在所述驱动结构层上的平坦化层和限定出像素开口区域的像素定义层；
所述驱动结构层包括位于所述基底上的缓冲层、位于所述缓冲层上的有源层、覆盖所述有源层的第一绝缘层、位于所述第一绝缘层上的第一栅电极层、覆盖所述第一栅电极层的第二绝缘层、位于所述第二绝缘层上的第二栅电极层、覆盖所述第二栅电极层的第三绝缘层以及位于所述第三绝缘层上的第一源漏电极层；
所述绝缘层包括位于所述缓冲层上的第一绝缘层、位于所述第一绝缘层上的第二绝缘层以及位于所述第二绝缘层上的第三绝缘层。
在示例性实施方式中，所述多个隔离坝包括多个第一隔离坝和多个第二隔离坝，所述第一隔离坝包括第一坝基和第一凸起，所述第二隔离坝包括第二凸起，所述第一隔离坝与所述置空区的最近距离大于所述第二隔离坝与所述置空区的最近距离；
所述第一坝基与所述平坦化层同层设置，所述第一凸起和第二凸起与所述像素定义成同层设置。
在示例性实施方式中，所述隔离柱包括第二坝基和第三凸起，其中：
所述第二坝基与所述平坦化层同层设置，所述第三凸起与所述像素定义成同层设置。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部 分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开示例性实施例的显示基板的结构示意图；
图2为图1中A-A向的剖视图；
图3为本公开示例性实施例形成有源层图案后的显示基板示意图；
图4为本公开示例性实施例形成栅电极图案后的显示基板示意图；
图5为本公开示例性实施例形成电容电极图案后的显示基板示意图；
图6为本公开示例性实施例形成第三绝缘层图案后的显示基板示意图；
图7为本公开示例性实施例形成源电极和漏电极图案后的显示基板示意图；
图8为本公开示例性实施例形成平坦化层图案后的显示基板示意图；
图9为本公开示例性实施例形成阳极图案后的显示基板示意图；
图10为本公开示例性实施例形成像素定义层图案后的显示基板示意图；
图11为本公开示例性实施例形成有机发光层和阴极图案后的显示基板示意图；
图12为本公开示例性实施例形成封装层图案后的显示基板示意图；
图13为本公开示例性实施例一种显示基板的制备方法的流程示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接 在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
OLED显示器件是一种自发光显示器件，相比传统液晶显示，具有高亮度、高对比度、高饱和色彩及高响应速率等显著优势，已经逐渐成为显示领域的主流产品。在实际应用过程中，为了追求更大的有效显示区域面积，减少边框，一些终端厂商开始将用于预留前置摄像头等硬件的安装位置的安装孔，设置在显示面板上的有效显示(Active Area，AA)区域。
一般柔性显示产品在自然环境中直接使用时容易受到外部光线的影响，影响正常使用，因此，柔性显示产品的表面需要贴合偏振片，以防止自然光对显示器件的影响，同时，偏振片也能够实现显示器件的一体黑效果。
偏振片的主要成分是聚醋酸乙烯酯吸附染色性物质(碘系化合物)，在偏振片贴合到显示器件上之前，偏振片上下两层都设置有保护膜，保护膜用于防止偏振片在运输过程中受到损伤，影响使用，因此，在将偏振片贴合到显示器件上时，需要先撕掉下保护膜，在贴合完偏振片后，使用激光将安装孔(AA hole)区域切割成通孔后，再撕掉偏振片的上保护膜，进行后续的盖板贴合工作。
激光切割是利用经聚焦的高功率密度激光束照射工件，使被照射的材料迅速熔化、汽化、烧蚀或达到燃点，同时借助与光束同轴的高速气流吹除熔融物质，从而实现将工件割开。然而，显示基板是由多层不同热膨胀系数的材料堆叠而成的，在热量的作用下，AA hole区域的上下堆叠层之间出现不 同程度的分裂。此外，现有的结构设计导致AA hole边缘的无机封装层的切割角度比较大，容易出现应力集中现象，同时AA hole边缘也不容易被油墨所润湿，因此，在后续的撕膜过程中由于薄膜粘合力的作用，进一步增加了AA hole的分裂程度，进而破坏了AA hole区域的封装结构，使得显示屏上出现黑点不断长大的(Growing Black Spots，GDS)现象，严重影响了产品的良率和显示品质。
本公开实施例提供了一种显示基板及其制备方法、显示装置，在不改变现有的工艺流程下，通过将多个隔离柱围绕置空区设置，切割前置空区的堆叠结构内缩，避免了因切割边缘热量传导而引起的膜层热膨胀导致的层间分裂现象，从而解决了在后续的撕膜过程中因为黏合应力导致的边缘结构破裂(Crack)的问题，另一方面，还增大了无机封装层与偏光片的接触面积，减小了AA hole边缘切割形成的角度，降低了AA hole切割边缘的应力集中，进而避免了在后续的撕膜过程中因为黏合应力导致的边缘结构Crack，形成的GDS问题。
图1为本公开实施例一种显示基板的结构示意图，图2为图1中A-A向的剖视图，示意了在垂直于显示基板的平面上显示区域、第一过渡区、第二过渡区和置空区的结构。如图1所示，在平行于显示基板的平面上，显示基板的主体结构包括显示区域100、第一过渡区200、第二过渡区300和置空区400，第一过渡区200位于显示区域100内，第二过渡区300位于第一过渡区200内，置空区400位于第二过渡区300内，即，第一过渡区200为围绕第二过渡区300的环形区域，第二过渡区300为围绕置空区400的环形区域。置空区400在显示区域100中的位置不限，形状也不做限制，可以为图1中所示的圆形，也可以椭圆形或者方形、菱形等其它多边形。
如图2所示，在垂直于显示基板的平面上，显示区域100的主体结构包括呈阵列分布的多个发光单元，每个发光单元包括设置在基底10上的驱动结构层和发光结构层，驱动结构层包括多个薄膜晶体管，图2中仅以两个发光单元和两个薄膜晶体管为例进行示意。具体地，驱动结构层主要包括设置在基底10上的缓冲层11、设置在缓冲层11上的薄膜晶体管101。发光结构层主要包括与薄膜晶体管101的漏电极连接的阳极31、限定像素开口区域的像 素定义层32、形成在像素开口区域内和像素定义层32上的有机发光层33、形成在有机发光层33上的阴极34以及封装层。封装层包括叠设的第一无机层35、有机封装层36和第二无机层37。
如图2所示，在垂直于显示基板的平面上，第一过渡区200的主体结构包括设置在基底10上的缓冲层11、设置在缓冲层11上的绝缘层201、设置在绝缘层201上的多个隔离坝202、设置在多个隔离坝202上的有机发光层33和阴极34，以及覆盖上述结构的第一无机层35和第二无机层37。其中，设置在基底10上的绝缘层201包括与驱动结构层同时形成的第一绝缘层、第二绝缘层和第三绝缘层。
在垂直于显示基板的平面上，第二过渡区300的主体结构包括设置在基底10上的缓冲层11、设置在缓冲层11上的多个隔离柱203、设置在多个隔离柱203上的有机发光层33和阴极34，以及覆盖上述结构的第一无机层35和第二无机层37。其中，多个隔离坝202和多个隔离柱203均围绕置空区400设置，多个隔离坝202设置在隔离柱203和显示区域100之间，隔离柱203在基底10上的正投影与置空区400在基底10上的正投影不重叠。
在一种示例性实施例中，在垂直于基底10的平面内，隔离柱203远离基底10一端的宽度小于隔离柱203靠近基底10一端的宽度。本公开实施例通过设置隔离柱203远离基底10一端的宽度小于隔离柱203靠近基底10一端的宽度，使得置空区附近的堆叠结构进一步内缩，进而减少了切割边缘的热量传导。
在一种示例性实施例中，在垂直于基底10的平面内，隔离坝202远离基底10一端的宽度小于隔离坝202靠近基底10一端的宽度。示例性的，在垂直于基底10的平面上，每个隔离坝202的横截面形状为正梯形。当第一无机层35和第二无机层37之间的有机封装层36的爬坡能力较弱时，可以设置隔离坝202远离基底10一端的宽度小于隔离坝202靠近基底10一端的宽度，此时，工艺比较简单，且有机封装层36不易越过隔离坝202，避免封装失效。
在另一种示例性实施例中，在垂直于基底10的平面内，隔离坝202远离基底10一端的宽度大于隔离坝202靠近基底10一端的宽度。示例性的，在 垂直于基底10的平面上，每个隔离坝202的横截面形状为倒梯形。当第一无机层35和第二无机层37之间的有机封装层36的爬坡能力较强时，可以设置隔离坝202远离基底10一端的宽度大于隔离坝202靠近基底10一端的宽度，此时，隔离坝202可用于在过渡区200断开后续蒸镀的有机发光层33和阴极34，阻断从置空区400到显示区域100的水氧入侵路径。
在一种示例性实施例中，在垂直于基底10的平面内，隔离坝202远离基底10的一端距离基底10的高度大于或等于隔离柱203远离基底10的一端距离基底10的高度。
由于隔离坝202的底部设置有绝缘层201和缓冲层11，而隔离柱203只形成在缓冲层11上，使得隔离坝202远离基底10的一端距离基底10的高度大于或等于隔离柱203远离基底10的一端距离基底10的高度，这样可以减少安装孔区域的激光切割厚度。
在一种示例性实施例中，封装层包括叠设的第一无机层35、有机封装层36和第二无机层37，在垂直于基底10的平面内，隔离坝202远离基底10的一端距离基底10的高度大于第一无机层35远离基底10的一端距离基底10的高度。这样可以防止有机封装层36侧漏至隔离坝202的另一侧。
在一种示例性实施例中，多个隔离坝包括第一隔离坝202a和第二隔离坝202b，第一隔离坝202a和第二隔离坝202b围绕置空区400间隔设置，且第一隔离坝202a与置空区400的最近距离大于第二隔离坝202b与置空区400的最近距离。
在一种示例性实施例中，第一隔离坝202a包括第一坝基和第一凸起，第二隔离坝202b包括第二凸起，第一坝基与平坦化层同层设置，第一凸起和第二凸起与像素定义成同层设置。
在一种示例性实施例中，隔离柱203包括第二坝基和第三凸起，其中：第二坝基与平坦化层同层设置，第三凸起与像素定义成同层设置。
在一种示例性实施例中，在垂直于基底10的平面内，第一隔离坝202a远离基底10的一端距离基底10的高度大于或等于第二隔离坝202b远离基底10的一端距离基底10的高度，当第一隔离坝202a远离基底10的一端距离 基底10的高度大于第二隔离坝202b远离基底10的一端距离基底10的高度时，两者的高度差可以在1～15微米。
如图2所示，在垂直于显示基板的平面上，置空区400为通孔，通孔中的各个结构膜层和基底均被激光切割去掉。
下面通过显示基板的制备过程的示例说明本公开显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
在一些示例性实施例中，图2的显示基板的制备过程可以包括如下步骤：
(1)在基底上形成有源层图案。在基底上形成有源层图案包括：先在基底10上沉积一层缓冲薄膜，形成覆盖整个基底10的缓冲层11图案。随后沉积一层有源层薄膜，通过构图工艺对有源层薄膜进行构图，在显示区域100形成设置在缓冲层11上的有源层12图案，如图3所示。其中，有源层12图案仅形成在显示区域100，此时的第一过渡区200、第二过渡区300和置空区400仅形成有缓冲层11。基底可以为柔性基底，采用聚酰亚胺PI、聚对苯二甲酸乙二酯PET或经表面处理的聚合物软膜等材料。缓冲薄膜可以采用氮化硅SiNx或氧化硅SiOx等，可以是单层，也可以是氮化硅/氧化硅的多层结构。
(2)形成栅电极图案。形成栅电极图案包括：在形成上述结构的基底10上，依次沉积第一绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄 膜进行构图，形成覆盖有源层12和缓冲层11的第一绝缘层13、设置在第一绝缘层13上的第一栅电极14、第二栅电极15和栅线(未示出)图案，如图4所示。其中，第一栅电极14、第二栅电极15和栅线仅形成在显示区域100，此时的第一过渡区200、第二过渡区300和置空区400形成有缓冲层11和第一绝缘层13。
(3)形成电容电极图案。形成电容电极图案包括：在形成上述结构的基底10上，依次沉积第二绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅电极14、第二栅电极15和第一绝缘层13的第二绝缘层16以及设置在第二绝缘层16上的电容电极17图案，电容电极17的位置与第二栅电极15的位置相对应，电容电极17与第二栅电极15构成电容，如图5所示。其中，电容电极17仅形成在显示区域100，此时的第一过渡区200、第二过渡区300和置空区400形成有缓冲层11、第一绝缘层13和第二绝缘层16。
(4)形成开设有过孔和凹槽的第三绝缘层图案。形成第三绝缘层图案包括：在形成上述结构的基底10上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成第三绝缘层18图案，第三绝缘层18在显示区域100开设有至少两个第一过孔K1，两个第一过孔K1中的第三绝缘层18、第二绝缘层16和第一绝缘层13被刻蚀掉，暴露出有源层12，第三绝缘层18还开设有一个第一凹槽K2，第一凹槽K2在基底上的正投影覆盖第二过渡区300和置空区400在基底上的正投影，第一凹槽K2中的第三绝缘层18、第二绝缘层16和第一绝缘层13被刻蚀掉，暴露出缓冲层11，如图6所示。即，两个第一过孔仅形成在显示区域100，第一凹槽K2形成在第二过渡区300和置空区400，此时的第一过渡区200形成有缓冲层11、第一绝缘层13、第二绝缘层16和第三绝缘层18。
(5)形成源电极和漏电极图案。形成源电极和漏电极图案包括：在形成上述结构的基底10上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在显示区域100形成源电极19、漏电极20和数据线(未示出)图案，源电极19和漏电极20分别通过两个第一过孔与有源层12连接，如图7所示。其中，源电极19、漏电极20和数据线仅形成在显示区域100，此时的 第二过渡区300和置空区400形成有缓冲层11和第一凹槽K2，第一过渡区200形成有缓冲层11、第一绝缘层13、第二绝缘层16和第三绝缘层18。
通过上述过程，在基底10上完成了位于显示区域100的驱动结构层、位于第一过渡区200的绝缘层、位于第二过渡区300和置空区400的缓冲层的制备。其中，位于显示区域100的驱动结构层包括有源层12、第一栅电极14、第二栅电极15、电容电极17、源电极19、漏电极20、栅线和数据线，栅线和数据线垂直交叉限定出子像素，由有源层12、第一栅电极14、源电极19和漏电极20构成的薄膜晶体管设置在子像素内。位于第一过渡区200的绝缘层包括第一绝缘层13、第二绝缘层16和第三绝缘层18。其中，第一绝缘层和第二绝缘层也称之为栅绝缘层(GI)，第三绝缘层也称之为层间绝缘层(ILD)。
(6)形成平坦化层图案。形成平坦化层图案包括：在形成前述图案的基底上涂覆第四绝缘薄膜，通过掩膜曝光显影的光刻工艺在显示区域100形成覆盖源电极19和漏电极20的第四绝缘层21图案，第四绝缘层21开设有第二过孔K3，第二过孔K3暴露出漏电极20，如图8所示。其中，第四绝缘层21形成在显示区域100、第一过渡区200和第二过渡区300，第四绝缘层21在第一过渡区200的正投影与后续形成的第一隔离坝202a在基底上的正投影重叠，即，形成在第一过渡区200的第四绝缘层21作为后续形成的第一隔离坝202a的坝基，第四绝缘层21在第二过渡区300的正投影与后续形成的隔离柱203在基底上的正投影重叠，即，形成在第二过渡区300的第四绝缘层21作为后续形成的隔离柱203的坝基，其他地方的第四绝缘薄膜被显影掉，此时的置空区400形成有缓冲层11。其中，第四绝缘层也称之为平坦化层(PLN)。
(7)形成阳极图案。形成阳极图案包括：在形成前述图案的基底上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在显示区域100形成阳极31图案，阳极31通过第二过孔与漏电极20连接，如图9所示。其中，阳极31仅形成在显示区域100，第一过渡区200、第二过渡区300和置空区400的透明导电薄膜被刻蚀掉，此时的第一过渡区200形成有缓冲层11、第一绝缘层13、第二绝缘层16、第三绝缘层18和设置在第三绝缘层18上的第 四绝缘层21，第二过渡区300形成有缓冲层11和设置在缓冲层11上的第四绝缘层21，置空区400形成有缓冲层11。其中，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。
(8)形成像素定义层图案。形成像素定义层图案包括：在形成前述图案的基底上涂覆像素定义薄膜，通过光刻工艺形成像素定义层(Pixel Define Layer)32图案，像素定义层32图案可以位于显示区域100、第一过渡区200和第二过渡区300，显示区域100的像素定义层32图案在每个子像素限定出暴露阳极31的像素开口区域，第一过渡区200的像素定义层32图案一部分设置在第四绝缘层21上，形成第一隔离坝202a的凸起部分，另一部分设置在第三绝缘层18上，形成第二隔离坝202b的凸起部分，第二过渡区300的像素定义层32图案设置在第四绝缘层21上，形成隔离柱203的凸起部分，如图10所示。其中，此时的置空区400形成有缓冲层11。其中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
在一种示例性实施例中，如图10所示，在第二过渡区300，隔离柱203围绕置空区400间隔设置，隔离坝202设置在隔离柱203和显示区域100之间。本实施例中，隔离坝202形成在第一过渡区200，隔离柱203形成在第二过渡区300。本实施例中，多个隔离坝202和多个隔离柱203用于阻断从置空区400到显示区域100的水氧入侵和裂纹伸展路径。
在一种示例性实施例中，如图10所示，在垂直于基底10的平面上，每个隔离柱203的横截面形状具有上窄下宽的特点，即隔离柱203远离基底10一端(上端)的宽度a1小于隔离柱203靠近基底10一端(下端)的宽度b1。示例性的，在垂直于基底10的平面上，每个隔离柱203的横截面形状可以为正梯形。
在一种示例性实施例中，如图10所示，在垂直于基底10的平面内，隔离柱203远离基底10一端(上端)距离置空区400的最近距离为隔离柱203靠近基底10一端(下端)距离置空区400的最近距离的2倍至6倍之间。示例性的，隔离柱203远离基底10一端(上端)距离置空区400的最近距离可以为10至20微米，防止在激光切割置空区400时，造成封装层的受热膨胀失效。隔离柱203靠近基底10一端(下端)距离置空区400的最近距离可以 为1至5微米，防止过渡区200过宽影响显示效果。
在一种示例性实施例中，如图10所示，在垂直于基底10的平面上，每个隔离坝202的横截面形状具有上窄下宽的特点，即隔离坝202远离基底10一端(上端)的宽度a2或a3小于隔离坝202靠近基底10一端(下端)的宽度b2或b3。示例性的，在垂直于基底10的平面上，每个隔离柱203的横截面形状可以为正梯形。
在另一种示例性实施例中，在垂直于基底10的平面上，每个隔离坝202的横截面形状具有上宽下窄的特点，即隔离坝202远离基底10一端(上端)的宽度a2或a3大于隔离坝202靠近基底10一端(下端)的宽度b2或b3。示例性的，在垂直于基底10的平面上，每个隔离柱203的横截面形状可以为倒梯形。
在一种示例性实施例中，在垂直于基底10的平面上，隔离坝202远离基底10一端距离基底10的高度h2或h3大于或等于隔离柱203远离基底10一端距离基底10的高度h1。
在一种示例性实施例中，在平行于基底10的平面上，每个隔离柱203的横截面形状可以为矩形、圆形或椭圆形等形状。
在一种示例性实施例中，多个隔离坝202包括多个第一隔离坝202a和多个第二隔离坝202b，多个第一隔离坝202a和多个第二隔离坝202b分别围绕隔离柱203设置，且第一隔离坝202a与隔离柱203的最近距离大于第二隔离坝202b与隔离柱203的最近距离。
在一种示例性实施例中，如图11所示，在垂直于基底10的平面内，第二隔离坝202b靠近基底10一端(下端)与隔离柱203靠近基底10一端(下端)之间的距离可以为5至40微米。
在一种示例性实施例中，如图11所示，在垂直于基底10的平面内，第一隔离坝202a靠近基底10一端(下端)与第二隔离坝202b靠近基底10一端(下端)之间的距离可以为10至40微米，以防止有机封装层36爬坡越过第一隔离坝202a造成的显示不良。
在一种示例性实施例中，隔离坝202和隔离柱203可以同层制备形成， 也可以非同层制备形成。本公开实施例对隔离坝202和隔离柱203的材料不做限定，且对显示基板具体哪一层形成隔离坝202和隔离柱203不做限定。
在一种示例性实施例中，隔离坝202可以通过平坦化层、像素定义层或支撑柱层(图中未示出)中的任意一层或多层制备形成，隔离柱203也可以通过平坦化层、像素定义层或支撑柱层中的任意一层或多层制备形成。显示区域100的支撑柱层用于维持显示基板和盖板(图中未示出)之间的距离，避免OLED膜层刮伤或产生牛顿环。
在一种示例性实施例中，显示基板还包括至少一个防裂坝(Crack Dam)(图中未示出)，用于防止激光切割安装孔造成第一过渡区200的绝缘层201断裂进而破坏显示区域100的驱动结构层结构，防裂坝可以形成在隔离柱203和隔离坝202b之间，防裂坝可以包括以下任意一种或多种：与源漏电极层同层制备的第一防裂坝、与第一栅电极层同层制备的第二防裂坝、与第二栅电极层同层制备的第三防裂坝。本实施例中，由于隔离柱203的坝基设置在缓冲层11上，可以省去制备防裂坝的步骤，在激光切割安装孔时，隔离柱203可以同时起到保护显示区域100的驱动结构层和发光层的结构的作用。
(9)形成有机发光层和阴极图案。形成有机发光层和阴极图案包括：在形成前述图案的基底上依次蒸镀有机发光材料及阴极金属薄膜，形成有机发光层33和阴极34图案。在显示区域100，有机发光层33与像素定义层32限定出的像素开口区域内的阳极31连接，阴极34设置在有机发光层33上。在过渡区200，有机发光层33和阴极34形成在支撑柱层上；在第一过渡区200，有机发光层33和阴极34形成在隔离坝202上，在第二过渡区300，有机发光层33和阴极34形成在隔离柱203上；在置空区400，有机发光层33和阴极34形成在缓冲层11上，如图11所示。其中，有机发光层33主要包括发光层(EML)。实际实施时，有机发光层可以包括依次设置的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，提高电子和空穴注入发光层的效率，阴极可以采用镁Mg、银Ag、铝Al、铜Cu、锂Li等金属材料的一种，或上述金属的合金。
(10)形成封装层图案。形成封装层图案包括：在形成前述图案的基底上先沉积第一无机薄膜，第一无机薄膜覆盖显示区域100、第一过渡区200、 第二过渡区300和置空区400，形成第一无机层35图案。随后，采用喷墨打印方式在显示区域100形成有机封装层36。随后，沉积第二无机薄膜，第二无机薄膜覆盖显示区域100、第一过渡区200、第二过渡区300和置空区400，形成第二无机层37图案，如图12所示。其中，封装层为无机/有机/无机的三层结构，中间的有机层仅形成在显示区域100，上下两层无机层覆盖显示区域100、第一过渡区200、第二过渡区300和置空区400，完成显示基板的封装。
通过上述过程，完成了位于显示区域100的发光结构层、位于第一过渡区200的隔离坝202以及位于第二过渡区300的隔离柱203的制备。其中，位于显示区域100的发光结构层包括阳极31、像素定义层32、有机发光层33、阴极34以及封装层。
(11)最后，进行模组阶段工艺，贴合偏振片38后，通过激光(Laser)等相关工艺将置空区400的各个结构膜层和基底刻蚀掉，形成本公开实施例开设有安装孔的OLED显示基板，如图2所示。实际实施时，可以将置空区400的各个结构膜层和基底全部刻蚀掉，形成通孔，也可以将置空区400的部分结构膜层刻蚀掉，形成盲孔，根据实际需要确定，本公开实施例不做具体限制。
通过本公开显示基板的结构和制备流程可以看出，本公开所提供的显示基板，在不改变现有的工艺流程下，通过将隔离柱203围绕置空区400间隔设置，切割前置空区400的堆叠结构内缩，避免了因切割边缘热量传导而引起的膜层热膨胀导致的层间分裂现象，从而解决了在后续的撕膜过程中因为黏合应力导致的边缘结构破裂(Crack)的问题，另一方面，还增大了无机封装层与偏光片的接触面积(如图2所示，虽然偏振片38和第二隔离坝202b之间以及偏振片38和隔离柱203之间均存在缝隙，但是，由于偏振片38和显示基板之间采用滚轮贴合的方式贴合，偏振片38和第二隔离坝202b之间以及偏振片38和隔离柱203之间，实际均可以完全贴合)，减小了AA hole边缘切割形成的角度，降低了AA hole切割边缘的应力集中，进而避免了在后续的撕膜过程中因为黏合应力导致的边缘结构Crack，形成的GDS问题。
同时，由于本公开实施例的制备工艺利用现有成熟的制备设备即可实现， 不改变现有的工艺流程，工艺实现简单，易于实施，生产效率高，具有易于工艺实现、生产成本低和良品率高等优点，具有良好的应用前景。
本公开显示基板的结构及其制备过程仅仅是一种示例性说明。实际实施时，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，OLED显示基板不仅可以顶发射结构，也可以是底发射结构。又如，薄膜晶体管不仅可以是顶栅结构，也可以是底栅结构，不仅可以是双栅结构，也可以是单栅结构。再如，薄膜晶体管可以是非晶硅(a-Si)薄膜晶体管、低温多晶硅(LTPS)薄膜晶体管或氧化物(Oxide)薄膜晶体管，驱动结构层和发光结构层中还可以设置其它电极、引线和结构膜层，本公开实施例在此不做具体的限定。
本公开还提供了一种显示基板的制备方法，显示基板包括显示区域、位于显示区域中的第一过渡区、位于第一过渡区中的第二过渡区以及位于第二过渡区中的置空区。如图13所示，本公开显示基板的制备方法包括：
S1、形成覆盖基底的缓冲层；
S2、在第一过渡区、第二过渡区和置空区形成覆盖缓冲层的绝缘层，并对第二过渡区和置空区的绝缘层进行构图工艺，形成暴露出缓冲层的第一凹槽，第一凹槽在基底上的正投影覆盖第二过渡区和置空区在基底上的正投影；
S3、在绝缘层上形成多个隔离坝，在第一凹槽内形成多个隔离柱，多个隔离坝和多个隔离柱围绕置空区设置。
在示例性实施方式中，隔离坝和隔离柱同层设置、采用相同材料且通过同一工艺形成；或者，隔离坝和隔离柱非同层设置。
在示例性实施方式中，所述制备方法还包括：在显示区域形成设置在基底上的驱动结构层、设置在驱动结构层上的平坦化层和限定出像素开口区域的像素定义层；
驱动结构层包括位于柔性基底上的缓冲层、位于缓冲层上的有源层、覆盖有源层的第一绝缘层、位于第一绝缘层上的第一栅电极层、覆盖第一栅电 极层的第二绝缘层、位于第二绝缘层上的第二栅电极层、覆盖第二栅电极层的第三绝缘层以及位于第三绝缘层上的第一源漏电极层；
绝缘层包括位于缓冲层上的第一绝缘层、位于第一绝缘层上的第二绝缘层以及位于第二绝缘层上的第三绝缘层。
在示例性实施方式中，多个隔离坝包括多个第一隔离坝和多个第二隔离坝，第一隔离坝包括第一坝基和第一凸起，第二隔离坝包括第二凸起，第一隔离坝与置空区的最近距离大于第二隔离坝与所述置空区的最近距离。
第一坝基与平坦化层同层设置，第一凸起和第二凸起与像素定义成同层设置。
在示例性实施方式中，隔离柱包括第二坝基和第三凸起，其中：第二坝基与平坦化层同层设置，第三凸起与像素定义成同层设置。
在示例性实施方式中，制备方法还包括：在像素定义层上形成支撑柱层；隔离坝可以与平坦化层、像素定义层以及支撑柱层中的任意一种或几种同层制备，隔离柱可以与平坦化层、像素定义层以及支撑柱层中的任意一种或几种同层制备。
本公开提供了一种显示基板的制备方法，通过将隔离柱围绕置空区间隔设置，切割前置空区的堆叠结构内缩，避免了因切割边缘热量传导而引起的膜层热膨胀导致的层间分裂现象，从而解决了在后续的撕膜过程中因为黏合应力导致的边缘结构Crack的问题，另一方面，还增大了无机封装层与偏光片的接触面积，减小了AA hole边缘切割形成的角度，降低了AA hole切割边缘的应力集中，进而避免了在后续的撕膜过程中因为黏合应力导致的边缘结构Crack，形成的GDS问题。本公开的制备工艺利用现有成熟的制备设备即可实现，不改变现有的工艺流程，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开还提供了一种显示装置，包括前述实施例的显示基板，其中，前述实施例的置空区用于安装硬件结构，示例性的，该硬件结构包括摄像头等结构。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (18)

  1. 一种显示基板，包括显示区域、位于所述显示区域中的第一过渡区、位于所述第一过渡区中的第二过渡区以及位于所述第二过渡区中的置空区，其中：
    所述第一过渡区包括基底、设置在所述基底上的缓冲层、设置在所述缓冲层上的绝缘层和设置在所述绝缘层上的多个隔离坝；
    所述第二过渡区包括基底、设置在所述基底上的缓冲层和设置在所述缓冲层上的多个隔离柱；
    所述多个隔离坝和所述多个隔离柱均围绕所述置空区设置。
  2. 根据权利要求1所述的显示基板，所述显示区域包括基底、设置在所述基底上的驱动结构层、设置在所述驱动结构层上的平坦化层和限定出像素开口区域的像素定义层；
    所述驱动结构层包括位于所述基底上的缓冲层、位于所述缓冲层上的有源层、覆盖所述有源层的第一绝缘层、位于所述第一绝缘层上的第一栅电极层、覆盖所述第一栅电极层的第二绝缘层、位于所述第二绝缘层上的第二栅电极层、覆盖所述第二栅电极层的第三绝缘层以及位于所述第三绝缘层上的第一源漏电极层；
    所述绝缘层包括位于所述缓冲层上的第一绝缘层、位于所述第一绝缘层上的第二绝缘层以及位于所述第二绝缘层上的第三绝缘层。
  3. 根据权利要求2所述的显示基板，其中，所述多个隔离坝包括多个第一隔离坝和多个第二隔离坝，所述第一隔离坝包括第一坝基和第一凸起，所述第二隔离坝包括第二凸起，所述第一隔离坝与所述置空区的最近距离大于所述第二隔离坝与所述置空区的最近距离，其中：
    所述第一坝基与所述平坦化层同层设置，所述第一凸起和第二凸起与所述像素定义成同层设置。
  4. 根据权利要求3所述的显示基板，其中，在垂直于所述基底的平面内， 所述第一隔离坝远离所述基底的一端距离所述基底的高度大于或等于所述第二隔离坝远离所述基底的一端距离所述基底的高度。
  5. 根据权利要求3所述的显示基板，其中，在垂直于所述基底的平面内，所述第二隔离坝靠近所述基底的一端与所述隔离柱靠近所述基底的一端之间的距离为5微米至40微米，所述第一隔离坝靠近所述基底的一端与所述第二隔离坝靠近所述基底的一端之间的距离为10微米至40微米。
  6. 根据权利要求2所述的显示基板，其中，所述隔离柱包括第二坝基和第三凸起，其中：
    所述第二坝基与所述平坦化层同层设置，所述第三凸起与所述像素定义成同层设置。
  7. 根据权利要求6所述的显示基板，其中，在垂直于所述基底的平面内，所述隔离坝远离所述基底的一端距离所述基底的高度大于或等于所述隔离柱远离所述基底的一端距离所述基底的高度。
  8. 根据权利要求1至7任一所述的显示基板，其中，在垂直于所述基底的平面内，所述隔离柱远离所述基底一端的宽度小于所述隔离柱靠近所述基底一端的宽度。
  9. 根据权利要求8所述的显示基板，其中，所述隔离柱远离所述基底一端距离所述置空区的最近距离为10至20微米；所述隔离柱靠近所述基底一端距离所述置空区的最近距离为1至5微米。
  10. 根据权利要求1至7任一所述的显示基板，其中，在垂直于所述基底的平面内，所述隔离坝远离所述基底一端的宽度小于所述隔离坝靠近所述基底一端的宽度。
  11. 根据权利要求2所述的显示基板，所述显示区域还包括设置在所述平坦化层上的发光结构层以及设置在所述发光结构层上的封装层，所述封装层包括第一无机层、第二无机层以及设置在所述第一无机层和所述第二无机层之间的有机封装层，所述第一无机层和所述第二无机层均延伸至所述第一过渡区和所述第二过渡区，且覆盖所述多个隔离坝和所述多个隔离柱。
  12. 根据权利要求11所述的显示基板，所述显示基板还包括位于所述封装层上的偏振片，所述第二无机层与所述偏振片在所述第二过渡区内的接触区域在所述基底上的正投影，位于所述隔离柱在所述基底上的正投影的范围之内，在平行于所述基底的平面内，所述第二无机层与所述偏振片在所述第二过渡区内的接触区域的面积大于或等于所述隔离柱远离所述基底的一端的面积。
  13. 一种显示装置，包括如权利要求1到12任一项所述的显示基板，其中，所述置空区用于安装硬件结构。
  14. 一种显示基板的制备方法，所述显示基板包括显示区域、位于所述显示区域中的第一过渡区、位于所述第一过渡区中的第二过渡区以及位于所述第二过渡区中的置空区，所述制备方法包括：
    形成覆盖基底的缓冲层；
    在所述第一过渡区、所述第二过渡区和所述置空区形成覆盖所述缓冲层的绝缘层，并对所述第二过渡区和所述置空区的绝缘层进行构图工艺，形成暴露出所述缓冲层的第一凹槽，所述第一凹槽在所述基底上的正投影覆盖第二过渡区和置空区在所述基底上的正投影；
    在所述绝缘层上形成多个隔离坝，在所述第一凹槽内形成多个隔离柱，所述多个隔离坝和所述多个隔离柱围绕所述置空区设置。
  15. 根据权利要求14所述的制备方法，其中，所述隔离坝和所述隔离柱同层设置、采用相同材料且通过同一工艺形成；或者，所述隔离坝和所述隔离柱非同层设置。
  16. 根据权利要求14所述的制备方法，所述制备方法还包括：在所述显示区域形成设置在所述基底上的驱动结构层、设置在所述驱动结构层上的平坦化层和限定出像素开口区域的像素定义层；
    所述驱动结构层包括位于所述基底上的缓冲层、位于所述缓冲层上的有源层、覆盖所述有源层的第一绝缘层、位于所述第一绝缘层上的第一栅电极层、覆盖所述第一栅电极层的第二绝缘层、位于所述第二绝缘层上的第二栅电极层、覆盖所述第二栅电极层的第三绝缘层以及位于所述第三绝缘层上的 第一源漏电极层；
    所述绝缘层包括位于所述缓冲层上的第一绝缘层、位于所述第一绝缘层上的第二绝缘层以及位于所述第二绝缘层上的第三绝缘层。
  17. 根据权利要求16所述的制备方法，其中，所述多个隔离坝包括多个第一隔离坝和多个第二隔离坝，所述第一隔离坝包括第一坝基和第一凸起，所述第二隔离坝包括第二凸起，所述第一隔离坝与所述置空区的最近距离大于所述第二隔离坝与所述置空区的最近距离；
    所述第一坝基与所述平坦化层同层设置，所述第一凸起和第二凸起与所述像素定义成同层设置。
  18. 根据权利要求16所述的制备方法，其中，所述隔离柱包括第二坝基和第三凸起，其中：
    所述第二坝基与所述平坦化层同层设置，所述第三凸起与所述像素定义成同层设置。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111081732A (zh) * 2018-10-19 2020-04-28 乐金显示有限公司 显示装置
CN111106146A (zh) * 2018-10-26 2020-05-05 三星显示有限公司 显示设备及其制造方法
US20200144542A1 (en) * 2016-02-16 2020-05-07 Samsung Display Co., Ltd. Organic light-emitting display apparatus and fabrication method thereof
CN111816664A (zh) * 2020-06-24 2020-10-23 合肥维信诺科技有限公司 显示面板及其制备方法
CN211929490U (zh) * 2020-03-31 2020-11-13 京东方科技集团股份有限公司 显示基板及显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200144542A1 (en) * 2016-02-16 2020-05-07 Samsung Display Co., Ltd. Organic light-emitting display apparatus and fabrication method thereof
CN111081732A (zh) * 2018-10-19 2020-04-28 乐金显示有限公司 显示装置
CN111106146A (zh) * 2018-10-26 2020-05-05 三星显示有限公司 显示设备及其制造方法
CN211929490U (zh) * 2020-03-31 2020-11-13 京东方科技集团股份有限公司 显示基板及显示面板
CN111816664A (zh) * 2020-06-24 2020-10-23 合肥维信诺科技有限公司 显示面板及其制备方法

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