WO2022128263A3 - Verfahren zur herstellung eines substrats mit einer strukturierten oberfläche und substrat mit einer strukturierten oberfläche - Google Patents

Verfahren zur herstellung eines substrats mit einer strukturierten oberfläche und substrat mit einer strukturierten oberfläche Download PDF

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Publication number
WO2022128263A3
WO2022128263A3 PCT/EP2021/081231 EP2021081231W WO2022128263A3 WO 2022128263 A3 WO2022128263 A3 WO 2022128263A3 EP 2021081231 W EP2021081231 W EP 2021081231W WO 2022128263 A3 WO2022128263 A3 WO 2022128263A3
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WO
WIPO (PCT)
Prior art keywords
substrate
structured
structured surface
producing
openings
Prior art date
Application number
PCT/EP2021/081231
Other languages
English (en)
French (fr)
Other versions
WO2022128263A2 (de
Inventor
Andreas LEX
Adrian Stefan Avramescu
Martin Herz
Christian Grassl
Sebastian Taeger
Robert Walter
Original Assignee
Ams-Osram International Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ams-Osram International Gmbh filed Critical Ams-Osram International Gmbh
Priority to US18/266,909 priority Critical patent/US20240055267A1/en
Publication of WO2022128263A2 publication Critical patent/WO2022128263A2/de
Publication of WO2022128263A3 publication Critical patent/WO2022128263A3/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)
  • Weting (AREA)
  • Led Devices (AREA)

Abstract

Es wird ein Verfahren zur Herstellung eines Substrats (1) mit einer strukturierten Oberfläche (11) angegeben, mit den Schritten: a) Bereitstellen eines Substrats (1) mit einem Substratkörper (10) und mit einer zu strukturierenden Oberfläche (110); b) Ausbilden einer Absorptionsschicht (2), einer ersten Maskenschicht (3) und einer zweiten Maskenschicht (4) auf der zu strukturierenden Oberfläche (110); b) Ausbilden von Öffnungen (40) in der zweiten Maskenschicht (4), in denen die erste Maskenschicht (3) freigelegt wird; c) Freilegen der zu strukturierenden Oberfläche (110) im Bereich der Öffnungen (40); d) Ausbilden von Vertiefungen (17) in der zu strukturierenden Oberfläche (110) im Bereich der Öffnungen zur Ausbildung der strukturierten Oberfläche (11) des Substrats (1); und e) Entfernen der Absorptionsschicht (2) von dem Substrat (1). Weiterhin wird ein Substrat (1) mit einer strukturierten Oberfläche (11) angegeben.
PCT/EP2021/081231 2020-12-15 2021-11-10 Verfahren zur herstellung eines substrats mit einer strukturierten oberfläche und substrat mit einer strukturierten oberfläche WO2022128263A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/266,909 US20240055267A1 (en) 2020-12-15 2021-11-10 Method for producing a substrate having a structured surface, and substrate having a structured surface

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102020215937.8 2020-12-15
DE102020215937.8A DE102020215937A1 (de) 2020-12-15 2020-12-15 Verfahren zur herstellung eines substrats mit einer strukturierten oberfläche und substrat mit einer strukturierten oberfläche

Publications (2)

Publication Number Publication Date
WO2022128263A2 WO2022128263A2 (de) 2022-06-23
WO2022128263A3 true WO2022128263A3 (de) 2022-08-11

Family

ID=78695700

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2021/081231 WO2022128263A2 (de) 2020-12-15 2021-11-10 Verfahren zur herstellung eines substrats mit einer strukturierten oberfläche und substrat mit einer strukturierten oberfläche

Country Status (3)

Country Link
US (1) US20240055267A1 (de)
DE (1) DE102020215937A1 (de)
WO (1) WO2022128263A2 (de)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130105438A1 (en) * 2011-10-28 2013-05-02 Zhen-Dong Zhu Manufacturing method of grating
US20130207143A1 (en) * 2012-02-14 2013-08-15 Lextar Electronics Corporation Patterned substrate of light emitting semiconductor device and manufacturing method thereof
EP2835836A1 (de) * 2012-04-02 2015-02-11 Asahi Kasei E-Materials Corporation Optisches substrat, lichtemittierendes halbleiterelement und verfahren zur herstellung des lichtemittierenden halbleiterelements
DE102014114109A1 (de) * 2014-09-29 2016-03-31 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Vielzahl von Halbleiterchips und Halbleiterchip
DE102016200953A1 (de) * 2016-01-25 2017-07-27 Osram Opto Semiconductors Gmbh Substrat mit Strukturelementen und Halbleiterbauelement

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2487917B (en) 2011-02-08 2015-03-18 Seren Photonics Ltd Semiconductor devices and fabrication methods
CN104377285A (zh) 2014-10-14 2015-02-25 厦门润晶光电有限公司 一种改善图案化蓝宝石衬底良品率的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130105438A1 (en) * 2011-10-28 2013-05-02 Zhen-Dong Zhu Manufacturing method of grating
US20130207143A1 (en) * 2012-02-14 2013-08-15 Lextar Electronics Corporation Patterned substrate of light emitting semiconductor device and manufacturing method thereof
EP2835836A1 (de) * 2012-04-02 2015-02-11 Asahi Kasei E-Materials Corporation Optisches substrat, lichtemittierendes halbleiterelement und verfahren zur herstellung des lichtemittierenden halbleiterelements
DE102014114109A1 (de) * 2014-09-29 2016-03-31 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Vielzahl von Halbleiterchips und Halbleiterchip
DE102016200953A1 (de) * 2016-01-25 2017-07-27 Osram Opto Semiconductors Gmbh Substrat mit Strukturelementen und Halbleiterbauelement

Also Published As

Publication number Publication date
DE102020215937A1 (de) 2022-06-15
US20240055267A1 (en) 2024-02-15
WO2022128263A2 (de) 2022-06-23

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