WO2022127021A1 - 显示处理方法、显示处理装置及显示面板 - Google Patents

显示处理方法、显示处理装置及显示面板 Download PDF

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Publication number
WO2022127021A1
WO2022127021A1 PCT/CN2021/094569 CN2021094569W WO2022127021A1 WO 2022127021 A1 WO2022127021 A1 WO 2022127021A1 CN 2021094569 W CN2021094569 W CN 2021094569W WO 2022127021 A1 WO2022127021 A1 WO 2022127021A1
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pixels
charge sharing
sub
next row
data channels
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PCT/CN2021/094569
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English (en)
French (fr)
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南帐镇
李大浚
吴佳璋
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北京奕斯伟计算技术有限公司
合肥奕斯伟集成电路有限公司
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Publication of WO2022127021A1 publication Critical patent/WO2022127021A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display processing method, a display processing device, and a display panel.
  • the charge sharing technology is gradually applied to the liquid crystal display panel.
  • the conventional charge sharing technology can set a switch between the odd data channel and the even data channel, and then control the on-off of the switch to achieve an even charge distribution between the odd data channel and the even data channel, so that the odd data channel and the even data channel can be evenly distributed.
  • the potential of the first reaches a common voltage, and then the odd-numbered data channels and the even-numbered data channels are respectively charged or discharged to the level of the corresponding polarity, thereby reducing the power consumption of the driving chip.
  • the power consumption reduction of the conventional charge sharing scheme is limited, and when the charge sharing technology is adopted, the timing control chip (TCON) is required to provide assistance, and the driver chip cannot directly judge and adopt the charge sharing. technology.
  • TCON timing control chip
  • the present disclosure provides a display processing method, a display processing device, and a display panel, which can solve the problem that the charge sharing solution in the related art has limited power consumption reduction capability and needs to rely on the assistance of a timing control chip.
  • an embodiment of the present disclosure provides a display processing method, including:
  • the charge sharing mode includes global charge sharing and same-polarity charge sharing .
  • charge sharing is performed among the data channels corresponding to each sub-pixel in the next row of pixels.
  • the step of determining the charge sharing mode between the data channels corresponding to each sub-pixel in the next row of pixels according to the data signals of the current row of pixels and the next row of pixels includes:
  • the charge sharing mode between the data channels corresponding to each sub-pixel in the next row of pixels is determined.
  • the steps of determining the charge sharing mode between the data channels corresponding to each sub-pixel in the next row of pixels include:
  • the first logic result and the second logic result determine whether charge sharing needs to be performed between the data channels corresponding to each sub-pixel in the next row of pixels, and determine the charge to be used if charge sharing is required sharing method.
  • the steps to determine the charge-sharing method to be used in a given situation include:
  • the charge sharing mode is global charge sharing.
  • the step of performing charge sharing among data channels corresponding to each sub-pixel in the next row of pixels according to the determined charge sharing manner includes:
  • the data channels corresponding to the same polarity sub-pixels are connected to each other;
  • an embodiment of the present disclosure further provides a display processing device, including:
  • an acquisition module used to acquire the data signals of the current line of pixels and the next line of pixels of the current frame image
  • the determining module is configured to determine, according to the data signals of the pixels of the current row and the pixels of the next row, the charge sharing mode between the data channels corresponding to each sub-pixel in the pixels of the next row, wherein the charge sharing mode includes global charge sharing and Same-polarity charge sharing;
  • the processing module is configured to perform charge sharing among the data channels corresponding to each sub-pixel in the next row of pixels according to the determined charge sharing manner.
  • the determining module includes:
  • an extraction unit for extracting the most significant bits of the data signal corresponding to the two sub-pixels of each data channel in the current row of pixels and the next row of pixels;
  • a determination unit configured to determine, according to the most significant bits of the data signals of the two sub-pixels corresponding to the same data channel in the pixels of the current row and the pixels of the next row, whether charging needs to be performed between the data channels corresponding to the sub-pixels in the pixels of the next row share, and determine a charge sharing manner between data channels corresponding to each sub-pixel in the next row of pixels when charge sharing is required.
  • the determining unit includes:
  • the first operation subunit is used to perform XOR operation on the most significant bits of the data signals of the two subpixels corresponding to the same data channel in the current row of pixels and the next row of pixels to obtain the XOR operation result of each data channel;
  • the second operation subunit is used to perform AND operation and OR operation on the XOR operation results of every at least two consecutive data channels, respectively, to obtain several AND operation results and OR operation results;
  • the third operation subunit is used to perform AND operation on the several AND operation results to obtain a first logical result, and perform an AND operation on the several OR operation results to obtain a second logical result;
  • the determining subunit is used to determine, according to the first logic result and the second logic result, whether charge sharing needs to be performed between the data channels corresponding to each subpixel in the next row of pixels, and whether charge sharing needs to be performed Determine the charge sharing method used under the circumstances.
  • the determining subunit includes:
  • a first micro-unit configured to determine not to perform charge sharing between the data channels corresponding to each sub-pixel in the next row of pixels when the first logical result and the second logical result are both 0;
  • a second micro-unit configured to determine that the charge sharing mode is same-polarity charge sharing when the first logic result is 1 and the second logic result is 0;
  • the third micro-unit is configured to determine that the charge sharing mode is global charge sharing when both the first logic result and the second logic result are 1.
  • the processing module includes:
  • the first communication unit is used to connect the data channels corresponding to the sub-pixels of the same polarity with each other under the condition that the determined charge sharing mode is the same polarity charge sharing;
  • the second connection unit is configured to connect all data channels with each other when the determined sharing mode is global charge sharing.
  • an embodiment of the present disclosure provides a display panel, including the display processing apparatus described in the second aspect.
  • the display processing method of the embodiment of the present disclosure can determine the charge sharing method to be used in different modes without the assistance of a timing control chip, and can be simultaneously applied to display panels with different structures such as a single-gate pixel structure and a double-gate pixel structure.
  • the power consumption of the display panel can be effectively reduced, and most of the existing circuits can be reused, thereby reducing the chip area.
  • FIG. 1 is a schematic diagram of a single-gate RGB pixel structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a single-gate RGBW pixel structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a dual-gate RGB pixel structure provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a dual-gate RGBW pixel structure provided by an embodiment of the present disclosure
  • FIG. 5 is one of the output voltage waveforms of the single-gate RGB pixel structure
  • FIG. 6 is the second output voltage waveform of the single-gate RGB pixel structure
  • FIG. 7 is the third output voltage waveform of the single-gate RGB pixel structure
  • FIG. 8 is the fourth output voltage waveform of the single-gate RGB pixel structure
  • FIG. 9 is the fifth output voltage waveform of the single-gate RGB pixel structure
  • Figure 10 is the sixth output voltage waveform of the single-gate RGB pixel structure
  • FIG. 11 is a schematic flowchart of a display processing method provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a detection circuit provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the classification of the first logical result and the second logical result provided by an embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of a charge sharing circuit provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the temperature of the display driver chip before and after the display processing method according to an embodiment of the present disclosure
  • FIG. 16 is a schematic structural diagram of a display processing apparatus according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a single-gate RGB pixel structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a single-gate type RGBW pixel structure provided by an embodiment of the present disclosure
  • FIG. 3 is the present disclosure
  • FIG. 4 is a schematic diagram of a structure of a dual-gate RGB pixel provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a structure of a dual-gate RGBW pixel provided by an embodiment of the present disclosure.
  • the pixel arrangement structure in the display panel includes a single-gate RGB pixel arrangement, a single-gate RGBW pixel arrangement, a double-gate RGB pixel arrangement, and a double-gate RGBW pixel arrangement Pixel arrangement structure, etc.
  • the conventional charge sharing scheme is proposed for a display panel with a certain pixel arrangement structure, and can only be applied to a display panel with a corresponding single pixel arrangement structure, and cannot be directly used.
  • this undoubtedly increases the workload of driving circuit chip design, and is inconvenient for application and promotion.
  • the conventional charge sharing scheme requires the assistance of a timing control chip (TCON), which means that the difficulty of circuit/chip design is increased, the area of the chip is increased, and the power consumption is also increased accordingly. Therefore, how to select an appropriate charge sharing method by judging the displayed frame picture data without the additional assistance of the timing control chip, and at the same time make the charge sharing method applicable to the display of different pixel arrangement structures Panels, ultimately reducing the difficulty of chip design, reducing operating power consumption, and expanding application scenarios have become problems that need to be solved urgently.
  • TCON timing control chip
  • FIG. 5 is one of the output voltage waveforms of the single-gate RGB pixel structure
  • FIG. 6 is the second output voltage waveform of the single-gate RGB pixel structure
  • FIG. 7 is the single-gate RGB pixel structure.
  • Figure 8 is the fourth output voltage waveform of the single-gate RGB pixel structure
  • Figure 9 is the fifth output voltage waveform of the single-gate RGB pixel structure
  • Figure 10 is the output voltage of the single-gate RGB pixel structure.
  • Waveform six As shown in Figure 5-7, CH1 to CH6 in the figure correspond to the six data channels (that is, six columns of data lines) of the single-gate RGB pixel structure.
  • the polarities of the driving data signals in CH1 and CH4 in Figure 5 are opposite.
  • the polarity of the driving data signals in CH3 and CH6 in FIG. 6 is opposite, corresponding to the blue in the third and sixth columns.
  • FIG. 7 is opposite, corresponding to the polarity change mode of the data signal of the red sub-pixel in the first column and the fourth column, CH3 Contrary to the polarity of the driving data signal in CH6, the polarity of the data signal corresponding to the blue sub-pixels in the third and sixth columns is changed.
  • the data corresponding to the odd-column sub-pixels and the even-column sub-pixels The polarities of the driving data signals in the channels are opposite, corresponding to the polarities of the data signals of the odd-column sub-pixels and the even-column sub-pixels.
  • FIG. 9 shows the driving data signals in the data channels corresponding to the odd-column sub-pixels and the even-column sub-pixels.
  • the polarities are the same, corresponding to the polarity change mode of the data signals of the odd-column sub-pixels and the even-column sub-pixels.
  • the polarities of the driving data signals in the data channels corresponding to the odd-column sub-pixels and the even-column sub-pixels do not change.
  • charge sharing is not required. From this, it can be known that the voltage waveform output to the display panel can reflect the polarity change law of different sub-pixels, that is, it can reflect the polarity change law of the driving data signals in the data channels corresponding to different sub-pixels. According to the changing law of its polarity, an appropriate charge sharing method is selected, thereby saving the power consumption of the display panel.
  • FIG. 11 is a schematic flowchart of a display processing method provided by an embodiment of the present disclosure.
  • the display processing method in the embodiment of the present disclosure may specifically include:
  • Step 111 Acquire the data signals of the pixels of the current line and the pixels of the next line of the current frame image.
  • FIG. 12 is a schematic diagram of a detection circuit provided by an embodiment of the present disclosure.
  • the data signal output from the first latch is output to the second latch, and the data signal output from the second latch is converted to a polarity with a level shift circuit (L/S) and an amplifier. level signal and output to the corresponding data channel. Therefore, it can be considered that the data signal output from the second latch corresponds to the data signal of the current row of pixels, and the data signal output from the first latch corresponds to the data signal of the next row of pixels, so that the second The latch and the first latch acquire the data signals of the pixels of the current line and the pixels of the next line of the current frame image.
  • L/S level shift circuit
  • the combination of the first latch, the second latch, the level conversion circuit and the amplifier constitutes a conversion circuit, more specifically a digital-to-analog conversion circuit, from the first latch and the second latch
  • the data signal output by the device is a digital signal.
  • Step 112 According to the data signals of the pixels of the current row and the pixels of the next row, determine the charge sharing mode between the data channels corresponding to each sub-pixel in the pixels of the next row, wherein the charge sharing mode includes global charge sharing and homopolarity. Sexual charge sharing.
  • the voltage waveform output to the display panel can reflect the polarity change rule of different sub-pixels, that is, it can reflect the polarity of the driving data signals in the data channels corresponding to different sub-pixels. Therefore, it can be determined whether charge sharing is required according to its polarity change law, and an appropriate charge sharing method can be selected when charge sharing is required.
  • the charge sharing method in the embodiment of the present application Including global charge sharing (GCS) and the same polarity charge sharing (Polarity charge sharing PCS).
  • the step of determining, according to the data signals of the pixels in the current row and the pixels in the next row, determines the charge sharing mode between the data channels corresponding to the sub-pixels in the pixels in the next row includes:
  • the charge sharing mode between the data channels corresponding to each sub-pixel in the next row of pixels is determined.
  • the driving data signals in the data channels corresponding to different sub-pixels have a certain polarity change rule, and the polarity change rule of the driving data signal can be reflected by the most significant bit, only each data signal needs to be extracted in the embodiment of the present disclosure According to the most significant bit of the data signal, it is possible to determine whether charge sharing is required between the data channels corresponding to each sub-pixel in the next row of pixels, and select the appropriate charge when it is determined that charge sharing is required. sharing method.
  • each data channel corresponds to the data line of each column of sub-pixels. Since only the current row of pixels and the next row of pixels are seen in the embodiment of the present disclosure, only two sub-pixels are corresponding to one data channel, and the so-called most significant bit, Namely Most Significant Bit, referred to as MSB.
  • the steps of determining the charge sharing mode between the data channels corresponding to each sub-pixel in the next row of pixels when charge sharing is required include:
  • the first logic result and the second logic result determine whether charge sharing needs to be performed between the data channels corresponding to each sub-pixel in the next row of pixels, and determine the charge to be used if charge sharing is required sharing method.
  • the M XOR operation results can be the XOR operation results of each adjacent at least two consecutive channels as a group, and the XOR operation results in the group are respectively AND operation and OR operation, optional, As shown in FIG. 12 , in the embodiment of the present disclosure, the XOR operation results corresponding to each consecutive three data channels are used as a group to perform the AND operation and the OR operation.
  • the result of XOR operation is a group, which can be changed according to actual needs. This change should also be considered as the scope covered by the inventive concept in this case. From this, N AND operation results and N OR operation results (M) can be obtained.
  • the first logical result iCO and the second logical result iHP can determine whether charge sharing needs to be performed between the data channels corresponding to each sub-pixel in the next row of pixels, and if charge sharing is required, determine the The charge sharing method between the data channels corresponding to each sub-pixel in the next row of pixels. It can be seen that, in the detection circuit that performs detection processing on the most significant bit in the embodiment of the present disclosure, approximately seven additional logic gates are required for every three data channels to realize the above-mentioned logic operation and complete the detection. The degree has almost no effect, the cost is almost unchanged, and the circuit occupied area can also be saved and power consumption can be reduced.
  • the charge sharing mode is global charge sharing.
  • FIG. 13 is a schematic diagram of the classification of the first logical result and the second logical result provided by the embodiment of the present disclosure.
  • the corresponding screen display mode at this time is a non-toggle pattern (Non toggle pattern), that is, corresponding to white , black, etc. to stabilize the picture, in this case, it is not necessary to perform charge sharing between the data channels corresponding to each sub-pixel in the next row of pixels; when the first logic result iCO is 1, the second logic result iHP In the case of 0, the corresponding screen display mode at this time is the color pattern (Color pattern).
  • charge sharing needs to be performed, and it can be determined that the charge sharing method is the same polarity charge sharing; in the first logic When the result iCO is 1 and the second logical result iHP is 1, the corresponding screen display mode is the All channel toggle pattern. In this case, charge sharing needs to be performed, and it can be determined that The charge sharing method is global charge sharing.
  • Step 113 According to the determined charge sharing manner, perform charge sharing among the data channels corresponding to each sub-pixel in the next row of pixels.
  • the charge sharing can be performed between the data channels corresponding to each sub-pixel in the next row of pixels.
  • the step of performing charge sharing among data channels corresponding to each sub-pixel in the next row of pixels according to the determined charge sharing manner includes:
  • the data channels corresponding to the same polarity sub-pixels are connected to each other;
  • FIG. 14 is a schematic diagram of a charge sharing circuit provided by an embodiment of the present disclosure. As shown in Figure 14, the figure shows 12 data channels from O1 to O12. After the signal output by the amplifier is given polarity by the front-end circuit, it can be output to the corresponding data channel, and finally reaches the corresponding sub-pixel for processing. drive.
  • polarity selection switches including P1B, N1B, P2B, N2B, P3B, N3B, N4B, N1, N2, N3, N4, P1, P2, P3, P4, through
  • the polarity of the signal corresponding to the data channel can be controlled; and a number of charge sharing switches are arranged between each data channel, including a first switch ST1, a second switch ST2, a third switch
  • the switch ST3 and the fourth switch ST4 can realize the charge sharing among the data channels by controlling the on-off of the above-mentioned charge sharing switch.
  • the polarity of each data channel in a row of pixels is +, -, +, -, +, -, +, -, +, -, +, -, +, - Therefore, by controlling the first switch ST1 and the third switch ST3 to be turned on, and the second switch ST2 and the fourth switch ST4 to be turned off, the charge sharing between the data channels of the same polarity can be realized, thereby reducing the power consumption of the display panel
  • display panels with other pixel arrangement structures can also share the same polarity charge.
  • the charge sharing circuit shown in FIG. 14 can also be used for global charge sharing.
  • the first switch ST1, the second switch ST2, the third switch ST3, and the fourth switch ST4 are all connected, that is Can.
  • FIG. 15 is a schematic diagram of the temperature of the display driver chip before and after using the display processing method according to an embodiment of the present disclosure.
  • the display processing method is adopted.
  • the temperature of the display driver chip in the red and blue image display can be reduced by 6°C
  • the black screen can be reduced by 2.75°C
  • the white screen can be reduced by 3.5°C. It can be seen that the power consumption of the display driver chip is effectively reduced. .
  • the display processing method of the embodiment of the present disclosure can determine the charge sharing method to be used in different modes without the assistance of a timing control chip, and can be simultaneously applied to display panels with different structures such as a single-gate pixel structure and a double-gate pixel structure.
  • the power consumption of the display panel can be effectively reduced, and most of the existing circuits can be reused, thereby reducing the chip area.
  • FIG. 16 is a schematic structural diagram of a display processing apparatus according to an embodiment of the present disclosure.
  • another embodiment of the present disclosure further provides a display processing apparatus, and the display processing apparatus 160 may include:
  • the acquisition module 161 is used to acquire the data signals of the current row of pixels and the next row of pixels of the current frame image
  • the determining module 162 is configured to determine, according to the data signals of the pixels in the current row and the pixels in the next row, the charge sharing mode between the data channels corresponding to the sub-pixels in the next row of pixels, wherein the charge sharing mode includes a global Charge sharing and same polarity charge sharing;
  • the processing module 163 is configured to perform charge sharing among the data channels corresponding to each sub-pixel in the next row of pixels according to the determined charge sharing manner.
  • the display processing device can determine the charge sharing method to be used in different modes without the assistance of a timing control chip, and can be simultaneously applied to display panels with different structures such as a single-gate pixel structure and a double-gate pixel structure.
  • the power consumption of the display panel can be effectively reduced, and most of the existing circuits can be reused, thereby reducing the chip area.
  • the determining module 162 includes:
  • an extraction unit for extracting the most significant bits of the data signal corresponding to the two sub-pixels of each data channel in the current row of pixels and the next row of pixels;
  • a determination unit configured to determine, according to the most significant bits of the data signals of the two sub-pixels corresponding to the same data channel in the pixels of the current row and the pixels of the next row, whether charging needs to be performed between the data channels corresponding to the sub-pixels in the pixels of the next row share, and determine a charge sharing manner between data channels corresponding to each sub-pixel in the next row of pixels when charge sharing is required.
  • the determining unit includes:
  • the first operation subunit is used to perform XOR operation on the most significant bits of the data signals of the two subpixels corresponding to the same data channel in the current row of pixels and the next row of pixels to obtain the XOR operation result of each data channel;
  • the second operation subunit is used to perform AND operation and OR operation on the XOR operation results of every at least two consecutive data channels, respectively, to obtain several AND operation results and OR operation results;
  • the third operation subunit is used to perform AND operation on the several AND operation results to obtain a first logical result, and perform an AND operation on the several OR operation results to obtain a second logical result;
  • the determining subunit is used for determining whether charge sharing is required between the data channels corresponding to each subpixel in the next row of pixels according to the first logic result and the second logic result, and when charge sharing is required Determine the charge sharing method used under the circumstances.
  • the determining subunit includes:
  • a first micro-unit configured to determine not to perform charge sharing between the data channels corresponding to each sub-pixel in the next row of pixels when the first logical result and the second logical result are both 0;
  • a second micro-unit configured to determine that the charge sharing mode is same-polarity charge sharing when the first logic result is 1 and the second logic result is 0;
  • the third micro-unit is configured to determine that the charge sharing mode is global charge sharing when both the first logic result and the second logic result are 1.
  • the processing module includes:
  • the first communication unit is used to connect the data channels corresponding to the sub-pixels of the same polarity with each other under the condition that the determined charge sharing mode is the same polarity charge sharing;
  • the second connection unit is configured to connect all data channels with each other when the determined sharing mode is global charge sharing.
  • the display processing device in the embodiment of the present disclosure is a device corresponding to the above-mentioned display processing method embodiment, which can implement each step of the above-mentioned display processing method and achieve the same technical effect. To avoid repetition, details are not repeated here.
  • Yet another embodiment of the present disclosure further provides a display panel
  • the display panel includes the display processing apparatus described in the above embodiment, and since the above-mentioned display processing apparatus has the above-mentioned beneficial effects, the display panel in the embodiment of the present disclosure also Correspondence has the above beneficial effects, and in order to avoid repetition, details are not repeated here.

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Abstract

提供了一种显示处理方法、显示处理装置及显示面板，显示处理方法包括：获取当前帧图像的当前行像素和下一行像素的数据信号（111）；根据当前行像素和下一行像素的数据信号，确定下一行像素中各子像素对应的数据通道之间的电荷共享方式，其中，电荷共享方式包括全局电荷共享和同极性电荷共享；根据确定的电荷共享方式（112），对下一行像素中各子像素对应的数据通道之间进行电荷共享（113）。

Description

显示处理方法、显示处理装置及显示面板
相关申请的交叉引用
本申请主张在2020年12月14日在中国提交的中国专利申请号No.202011472225.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，具体涉及一种显示处理方法、显示处理装置及显示面板。
背景技术
目前，为了降低显示面板的驱动芯片的功耗，电荷共享(Charge sharing)技术逐渐应用在液晶显示面板。常规的电荷共享技术可在奇数数据通道与偶数数据通道之间设置开关，然后通过控制开关的通断实现奇数数据通道和偶数数据通道之间进行电荷平均分配，从而使奇数数据通道和偶数数据通道的电位先到达一个共同电压附近，然后再分别使奇数数据通道和偶数数据通道充电或放电至对应极性的电平，由此降低驱动芯片的功耗。
然而，随着显示技术的进一步发展，常规的电荷共享方案的功耗降低量有限，并且在采用电荷共享技术时，需要时序控制芯片(TCON)提供协助，无法直接由驱动芯片判断并采用电荷共享技术。
发明内容
有鉴于此，本公开提供一种显示处理方法、显示处理装置及显示面板，能够解决相关技术中的电荷共享方案的功耗降低能力有限、需要依赖于时序控制芯片的协助的问题。
为解决上述技术问题，本公开采用以下技术方案：
第一方面，本公开实施例提供了一种显示处理方法，包括：
获取当前帧图像的当前行像素和下一行像素的数据信号；
根据当前行像素和下一行像素的数据信号，确定所述下一行像素中各子 像素对应的数据通道之间的电荷共享方式，其中，所述电荷共享方式包括全局电荷共享和同极性电荷共享。
根据确定的电荷共享方式，对所述下一行像素中各子像素对应的数据通道之间进行电荷共享。
可选的，所述根据当前行像素和下一行像素的数据信号，确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式的步骤包括：
提取当前行像素和下一行像素中每一数据通道的两个子像素对应的数据信号的最高有效位；
根据当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式。
可选的，所述根据当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式的步骤包括：
将当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位进行异或运算，得到每一数据通道的异或运算结果；
将每至少两个连续的数据通道的异或运算结果分别进行与运算以及或运算，得到若干个与运算结果以及或运算结果；
将所述若干个与运算结果进行与运算，得到第一逻辑结果，将所述若干个或运算结果进行与运算，得到第二逻辑结果；
根据所述第一逻辑结果和所述第二逻辑结果，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在需要进行电荷共享的情况下确定采用的电荷共享方式。
可选的，所述根据所述第一逻辑结果和所述第二逻辑结果，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在需要进行电荷共享的情况下确定采用的电荷共享方式的步骤包括：
在所述第一逻辑结果和所述第二逻辑结果均为0的情况下，确定不对所 述下一行像素中各子像素对应的数据通道之间进行电荷共享；
在所述第一逻辑结果为1、所述第二逻辑结果为0的情况下，确定电荷共享方式为同极性电荷共享；
在所述第一逻辑结果和所述第二逻辑结果均为1的情况下，确定电荷共享方式为全局电荷共享。
可选的，所述根据确定的电荷共享方式，对所述下一行像素中各子像素对应的数据通道之间进行电荷共享的步骤包括：
在确定的电荷共享方式为同极性电荷共享的情况下，将相同极性子像素对应的数据通道之间互相连通；
在确定的共享方式为全局电荷共享的情况下，将所有数据通道之间互相连通。
第二方面，本公开实施例还提供了一种显示处理装置，包括：
获取模块，用于获取当前帧图像的当前行像素和下一行像素的数据信号；
确定模块，用于根据当前行像素和下一行像素的数据信号，确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式，其中，所述电荷共享方式包括全局电荷共享和同极性电荷共享；
处理模块，用于根据确定的电荷共享方式，对所述下一行像素中各子像素对应的数据通道之间进行电荷共享。
可选的，所述确定模块包括：
提取单元，用于提取当前行像素和下一行像素中每一数据通道的两个子像素对应的数据信号的最高有效位；
确定单元，用于根据当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式。
可选的，所述确定单元包括：
第一运算子单元，用于将当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位进行异或运算，得到每一数据通道的异或运算结果；
第二运算子单元，用于将每至少两个连续的数据通道的异或运算结果分别进行与运算以及或运算，得到若干个与运算结果以及或运算结果；
第三运算子单元，用于将所述若干个与运算结果进行与运算，得到第一逻辑结果，将所述若干个或运算结果进行与运算，得到第二逻辑结果；
确定子单元，用于根据所述第一逻辑结果和所述第二逻辑结果，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在需要进行电荷共享的情况下确定采用的电荷共享方式。
可选的，所述确定子单元包括：
第一微单元，用于在所述第一逻辑结果和所述第二逻辑结果均为0的情况下，确定不对所述下一行像素中各子像素对应的数据通道之间进行电荷共享；
第二微单元，用于在所述第一逻辑结果为1、所述第二逻辑结果为0的情况下，确定电荷共享方式为同极性电荷共享；
第三微单元，用于在所述第一逻辑结果和所述第二逻辑结果均为1的情况下，确定电荷共享方式为全局电荷共享。
可选的，所述处理模块包括：
第一连通单元，用于在确定的电荷共享方式为同极性电荷共享的情况下，将相同极性子像素对应的数据通道之间互相连通；
第二连通单元，用于在确定的共享方式为全局电荷共享的情况下，将所有数据通道之间互相连通。
第三方面，本公开实施例提供了一种显示面板，包括如第二方面所述的显示处理装置。
本公开上述技术方案的有益效果如下：
本公开实施例的显示处理方法，无需时序控制芯片的协助即可确定不同模式下所需采用的电荷共享方式，能够同时应用在单栅型像素结构、双栅型像素结构等不同结构的显示面板上，可有效降低显示面板的功耗，并且可以复用大部分已有的电路，减小了芯片面积。
附图说明
图1为本公开实施例提供的单栅型RGB像素结构的示意图；
图2为本公开实施例提供的单栅型RGBW像素结构的的示意图；
图3为本公开实施例提供的双栅型RGB像素结构的示意图；
图4为本公开实施例提供的双栅型RGBW像素结构的示意图；
图5为单栅型RGB像素结构的输出电压波形之一；
图6为单栅型RGB像素结构的输出电压波形之二；
图7为单栅型RGB像素结构的输出电压波形之三；
图8为单栅型RGB像素结构的输出电压波形之四；
图9为单栅型RGB像素结构的输出电压波形之五；
图10为单栅型RGB像素结构的输出电压波形之六；
图11为本公开实施例提供的显示处理方法的流程示意图；
图12为本公开实施例提供的检测电路的示意图；
图13为本公开实施例提供的第一逻辑结果和第二逻辑结果的分类示意图；
图14为本公开实施例提供的电荷共享电路的示意图；
图15为本公开实施例提供的采用显示处理方法前后显示驱动芯片的温度示意图；
图16为本公开实施例提供的一种显示处理装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
请参考图1-图4，图1为本公开实施例提供的单栅型RGB像素结构的示意图，图2为本公开实施例提供的单栅型RGBW像素结构的的示意图，图3为本公开实施例提供的双栅型RGB像素结构的示意图，图4为本公开实施例提供的双栅型RGBW像素结构的示意图。如图1-4所示，目前，显示面板中的像素排 布结构有单栅型RGB像素排布结构、单栅型RGBW像素排布结构、双栅型RGB像素排布结构、双栅型RGBW像素排布结构等等，相关技术中，常规的电荷共享方案是针对于某一像素排布结构的显示面板所提出的，只能运用于对应的单一像素排布结构的显示面板中，无法直接运用于其他像素排布结构的显示面板中，这无疑增加了驱动电路芯片设计的工作量，不便于应用推广。并且，常规的电荷共享方案都需要借助时序控制芯片(TCON)的协助，也就意味着增加了电路/芯片设计的难度，同时增加了芯片的面积，功耗也相应增加。因此，如何在不需要时序控制芯片的额外协助的情况下，通过对显示的帧画面数据进行判断，选择合适的电荷共享方式，同时使电荷共享的方法可以运用于不同的像素排布结构的显示面板，最终降低芯片设计难度、降低运行功耗以及扩大应用场景，成为目前亟待解决的问题。
请参考图5-图10，图5为单栅型RGB像素结构的输出电压波形之一，图6为单栅型RGB像素结构的输出电压波形之二，图7为单栅型RGB像素结构的输出电压波形之三，图8为单栅型RGB像素结构的输出电压波形之四，图9为单栅型RGB像素结构的输出电压波形之五，图10为单栅型RGB像素结构的输出电压波形之六。如图5-7所示，图中CH1～CH6对应于单栅型RGB像素结构的六个数据通道(即六列数据线)，图5中CH1和CH4中的驱动数据信号的极性相反，对应于第一列和第四列的红色子像素的数据信号的极性变化方式，图6中CH3和CH6中的驱动数据信号的极性相反，对应于第三列和第六列的蓝色子像素的数据信号的极性变化方式，图7中CH1和CH4中的驱动数据信号的极性相反，对应于第一列和第四列的红色子像素的数据信号的极性变化方式，CH3和CH6中的驱动数据信号的极性相反，对应于第三列和第六列的蓝色子像素的数据信号的极性变化方式，图8中则是奇数列子像素和偶数列子像素对应的数据通道中的驱动数据信号的极性相反，对应于奇数列子像素和偶数列子像素的数据信号的极性变化方式，图9中为奇数列子像素和偶数列子像素对应的数据通道中的驱动数据信号的极性相同，对应于奇数列子像素和偶数列子像素的数据信号的极性变化方式，图10中为奇数列子像素和偶数列子像素对应的数据通道中的驱动数据信号的极性均不发生变化，此时即不需要进行电荷共享。由此可以知道，输出至显示面板的电压波形可以反映出不同子像 素的极性变化规律，即可以反映出不同子像素各自对应的数据通道中的驱动数据信号的极性变化规律，由此可以根据其极性变化规律，选择合适的电荷共享方式，从而节省显示面板的电力损耗。
由此，请参考图11，为本公开实施例提供的显示处理方法的流程示意图。如图11所示，本公开实施例中的显示处理方法具体可以包括：
步骤111：获取当前帧图像的当前行像素和下一行像素的数据信号。
请参考图12，为本公开实施例提供的检测电路的示意图。如图12所示，第一锁存器输出的数据信号输出至第二锁存器，第二锁存器输出的数据信号经由电平转换电路(L/S)以及放大器之后转换为具有极性的电平信号，并输出至对应的数据通道。由此，可以认为第二锁存器输出的数据信号即对应于当前行像素的数据信号，而第一锁存器输出的数据信号即对应于下一行像素的数据信号，从而即可从第二锁存器和第一锁存器获取到当前帧图像的当前行像素和下一行像素的数据信号。本公开实施例中，第一锁存器、第二锁存器、电平转换电路和放大器组合构成转换电路，更具体的说为数模转换电路，从第一锁存器和第二锁存器输出的数据信号为数字信号。
步骤112：根据当前行像素和下一行像素的数据信号，确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式，其中，所述电荷共享方式包括全局电荷共享和同极性电荷共享。
本公开实施例中，根据前述内容可知，输出至显示面板的电压波形可以反映出不同子像素的极性变化规律，也即可以反映出不同子像素各自对应的数据通道中的驱动数据信号的极性变化规律，由此可以根据其极性变化规律，确定是否需要进行电荷共享，并在需要进行电荷共享的情况下选择合适的电荷共享方式；可选的，本申请实施例中的电荷共享方式包括全局电荷共享(Global charge sharing，GCS)和同极性电荷共享(Polarity charge sharing PCS)。
本公开实施例中，所述根据当前行像素和下一行像素的数据信号，确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式的步骤包括：
提取当前行像素和下一行像素中每一数据通道的两个子像素对应的数据信号的最高有效位；
根据当前行像素和下一行像素中对应同一数据通道的两个子像素的数据 信号的最高有效位，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式。
由于不同子像素对应的数据通道中的驱动数据信号具有一定的极性变化规律，而驱动数据信号的极性变化规律可以通过最高有效位体现，因此本公开实施例中仅需要提取每一个数据信号中的最高有效位，便可根据数据信号的最高有效位来确定下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在确定需要进行电荷共享的情况下选择合适的电荷共享方式。由此，在获取了当前帧图像的当前行像素和下一行像素的数据信号后，需要提取当前行像素和下一行像素中每一数据通道的两个子像素对应的数据信号的最高有效位，其中，每一数据通道即对应于每一列子像素的数据线，由于本公开实施例中仅看当前行像素和下一行像素，因此一个数据通道中即仅对应两个子像素，而所谓最高有效位，即Most Significant Bit，简称MSB。
本公开实施例中，所述根据当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式的步骤包括：
将当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位进行异或运算，得到每一数据通道的异或运算结果；
将每至少两个连续的数据通道的异或运算结果分别进行与运算以及或运算，得到若干个与运算结果以及或运算结果；
将所述若干个与运算结果进行与运算，得到第一逻辑结果，将所述若干个或运算结果进行与运算，得到第二逻辑结果；
根据所述第一逻辑结果和所述第二逻辑结果，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在需要进行电荷共享的情况下确定采用的电荷共享方式。
请继续参考图12，在提取出当前行像素和下一行像素中每一数据通道的两个子像素对应的数据信号的最高有效位之后，先将当前行像素和下一行像 素中对应同一数据通道的两个子像素的数据信号的最高有效位进行异或运算，得到每一数据通道的异或运算结果，由于每一行像素对应于M个数据通道(图中仅示出6个)，因此，经异或运算之后，将得到M个异或运算结果，其中M为正整数；本公开实施例中，进一步的，再将每至少两个连续的数据通道的异或运算结果分别进行与运算以及或运算，也就是说，M个异或运算结果可以以每相邻的至少两个连续通道的异或运算结果为一组，组内的异或运算结果分别进行与运算以及或运算，可选的，如图12所示，本公开实施例中以每连续的三个数据通道对应的异或运算结果为一组进行与运算以及或运算，当然，实际设计时，还可以采用2个数据通道对应的异或运算结果为一组，具体可以根据实际需求进行改变，这种改变也应当认为是本案中发明构思所涵盖的范围，由此，可以得到N个与运算结果和N个或运算结果(M＝3N)；最后，再将所述若干个与运算结果进行与运算，得到第一逻辑结果iCO，而将所述若干个或运算结果进行与运算，得到第二逻辑结果iHP，最终根据所述第一逻辑结果iCO和所述第二逻辑结果iHP，即可确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式。可以看到，本公开实施例中对最高有效位进行检测处理的检测电路中，每三个数据通道大致需要7个额外的逻辑闸即可实现上述的逻辑运算，完成检测，因此对电路的复杂程度几乎没有影响，成本几乎不变，还可以节省电路占用面积，降低功耗。
本公开实施例中，所述根据所述第一逻辑结果和所述第二逻辑结果，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在需要进行电荷共享的情况下确定采用的电荷共享方式的步骤包括：
在所述第一逻辑结果和所述第二逻辑结果均为0的情况下，确定不对所述下一行像素中各子像素对应的数据通道之间进行电荷共享；
在所述第一逻辑结果为1、所述第二逻辑结果为0的情况下，确定电荷共享方式为同极性电荷共享；
在所述第一逻辑结果和所述第二逻辑结果均为1的情况下，确定电荷共享方式为全局电荷共享。
请参考图13，为本公开实施例提供的第一逻辑结果和第二逻辑结果的分类示意图。如图13所示，在所述第一逻辑结果iCO和所述第二逻辑结果iHP均为0的情况下，此时对应的画面显示模式为非切换模式(Non toggle pattern)，即对应于白色、黑等稳定画面，在该情况下，即不需要对下一行像素中各子像素对应的数据通道之间进行电荷共享；在所述第一逻辑结果iCO为1、所述第二逻辑结果iHP为0的情况下，此时对应的画面显示模式为色彩模式(Color pattern)，在该情况下，需要进行电荷共享，并且可以确定电荷共享方式为同极性电荷共享；在所述第一逻辑结果iCO为1、所述第二逻辑结果iHP为1的情况下，此时对应的画面显示模式为全通道切换模式(All channel toggle pattern)，在该情况下，需要进行电荷共享，并且可以确定电荷共享方式为全局电荷共享。
步骤113：根据确定的电荷共享方式，对所述下一行像素中各子像素对应的数据通道之间进行电荷共享。
在确定需要进行电荷共享，并确定了对应的电荷共享方式后，即可对下一行像素中各子像素对应的数据通道之间进行电荷共享。
本公开实施例中，具体的，所述根据确定的电荷共享方式，对所述下一行像素中各子像素对应的数据通道之间进行电荷共享的步骤包括：
在确定的电荷共享方式为同极性电荷共享的情况下，将相同极性子像素对应的数据通道之间互相连通；
在确定的共享方式为全局电荷共享的情况下，将所有数据通道之间互相连通。
请参考图14，为本公开实施例提供的电荷共享电路的示意图。如图14所示，图中示出了O1～O12的12个数据通道，放大器输出的信号经前端电路赋予极性后，即可对应输出到相应的数据通道，最终到达相应的子像素中进行驱动。其中，在前端电路出来的路径上，配置了若干极性选择开关，包括P1B、N1B、P2B、N2B、P3B、N3B、N4B、N1、N2、N3、N4、P1、P2、P3、P4，通过控制上述极性选择开关的通断，即可控制对应数据通道的信号的极性；并且，在各数据通道之间配置了若干电荷共享开关，包括第一开关ST1、第二开关ST2、第三开关ST3、第四开关ST4，通过控制上述电荷共享 开关的通断，可以实现各数据通道之间的电荷共享。例如，在显示面板的像素结构类型为RGB排布的时候，一行像素中每一数据通道的极性为+、-、+、-、+、-、+、-、+、-、+、-，由此，可以通过控制第一开关ST1和第三开关ST3打开，而第二开关ST2和第四开关ST4关闭，实现同极性的数据通道之间的电荷共享，从而降低显示面板的功耗；以此类推，其他像素排布结构的显示面板也可以实现同极性电荷共享。可以知道，图14中所示的电荷共享电路同样也可以用于全局电荷共享，在进行全局电荷共享时，第一开关ST1、第二开关ST2、第三开关ST3、第四开关ST4均连通即可。
请参考图15，为本公开实施例提供的采用显示处理方法前后的显示驱动芯片的温度示意图。如图15所示，通过测量采用了本公开实施例中的显示处理方法的显示驱动芯片和未采用本公开实施例中的显示处理方法的显示驱动芯片的温度，可以看到，采用了显示处理方法后，显示驱动芯片在红和蓝的图像显示中，温度能够降低6℃，而黑画面能降低2.75℃，白画面则可以降低3.5℃，由此可知，显示驱动芯片的功耗得到有效降低。
本公开实施例的显示处理方法，无需时序控制芯片的协助即可确定不同模式下所需采用的电荷共享方式，能够同时应用在单栅型像素结构、双栅型像素结构等不同结构的显示面板上，可有效降低显示面板的功耗，并且可以复用大部分已有的电路，减小了芯片面积。
请参考图16，为本公开实施例提供的一种显示处理装置的结构示意图。如图16所示，本公开另一方面实施例还提供了一种显示处理装置，所述显示处理装置160可以包括：
获取模块161，用于获取当前帧图像的当前行像素和下一行像素的数据信号；
确定模块162，用于用于根据当前行像素和下一行像素的数据信号，确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式，其中，所述电荷共享方式包括全局电荷共享和同极性电荷共享；
处理模块163，用于根据确定的电荷共享方式，对所述下一行像素中各子像素对应的数据通道之间进行电荷共享。
本公开实施例的显示处理装置，无需时序控制芯片的协助即可确定不同 模式下所需采用的电荷共享方式，能够同时应用在单栅型像素结构、双栅型像素结构等不同结构的显示面板上，可有效降低显示面板的功耗，并且可以复用大部分已有的电路，减小了芯片面积。
可选的，所述确定模块162包括：
提取单元，用于提取当前行像素和下一行像素中每一数据通道的两个子像素对应的数据信号的最高有效位；
确定单元，用于根据当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式。
可选的，所述确定单元包括：
第一运算子单元，用于将当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位进行异或运算，得到每一数据通道的异或运算结果；
第二运算子单元，用于将每至少两个连续的数据通道的异或运算结果分别进行与运算以及或运算，得到若干个与运算结果以及或运算结果；
第三运算子单元，用于将所述若干个与运算结果进行与运算，得到第一逻辑结果，将所述若干个或运算结果进行与运算，得到第二逻辑结果；
确定子单元，用于根据所述第一逻辑结果和所述第二逻辑结果，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在需要进行电荷共享的情况下确定采用的电荷共享方式。
可选的，所述确定子单元包括：
第一微单元，用于在所述第一逻辑结果和所述第二逻辑结果均为0的情况下，确定不对所述下一行像素中各子像素对应的数据通道之间进行电荷共享；
第二微单元，用于在所述第一逻辑结果为1、所述第二逻辑结果为0的情况下，确定电荷共享方式为同极性电荷共享；
第三微单元，用于在所述第一逻辑结果和所述第二逻辑结果均为1的情况下，确定电荷共享方式为全局电荷共享。
可选的，所述处理模块包括：
第一连通单元，用于在确定的电荷共享方式为同极性电荷共享的情况下，将相同极性子像素对应的数据通道之间互相连通；
第二连通单元，用于在确定的共享方式为全局电荷共享的情况下，将所有数据通道之间互相连通。
本公开实施例中的显示处理装置为与上述显示处理方法实施例对应的装置，能够实现上述显示处理方法的各个步骤，且能达到相同的技术效果，为避免重复，在此不再赘述。
本公开再一方面实施例还提供了一种显示面板，所述显示面板包括上实施例所述的显示处理装置，由于上述的显示处理装置具有上述有益效果，本公开实施例中的显示面板也对应具有上述有益效果，为避免重复，在此不再赘述。
以上所述是本公开的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (11)

  1. 一种显示处理方法，包括：
    获取当前帧图像的当前行像素和下一行像素的数据信号；
    根据当前行像素和下一行像素的数据信号，确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式，其中，所述电荷共享方式包括全局电荷共享和同极性电荷共享；
    根据确定的电荷共享方式，对所述下一行像素中各子像素对应的数据通道之间进行电荷共享。
  2. 根据权利要求1所述的显示处理方法，其中，所述根据当前行像素和下一行像素的数据信号，确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式的步骤包括：
    提取当前行像素和下一行像素中每一数据通道的两个子像素对应的数据信号的最高有效位；
    根据当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式。
  3. 根据权利要求2所述的显示处理方法，其中，所述根据当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式的步骤包括：
    将当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位进行异或运算，得到每一数据通道的异或运算结果；
    将每至少两个连续的数据通道的异或运算结果分别进行与运算以及或运算，得到若干个与运算结果以及或运算结果；
    将所述若干个与运算结果进行与运算，得到第一逻辑结果，将所述若干个或运算结果进行与运算，得到第二逻辑结果；
    根据所述第一逻辑结果和所述第二逻辑结果，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在需要进行电荷共享的情况下确定采用的电荷共享方式。
  4. 根据权利要求3所述的显示处理方法，其中，所述根据所述第一逻辑结果和所述第二逻辑结果，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在需要进行电荷共享的情况下确定采用的电荷共享方式的步骤包括：
    在所述第一逻辑结果和所述第二逻辑结果均为0的情况下，确定不对所述下一行像素中各子像素对应的数据通道之间进行电荷共享；
    在所述第一逻辑结果为1、所述第二逻辑结果为0的情况下，确定电荷共享方式为同极性电荷共享；
    在所述第一逻辑结果和所述第二逻辑结果均为1的情况下，确定电荷共享方式为全局电荷共享。
  5. 根据权利要求1所述的显示处理方法，其中，所述根据确定的电荷共享方式，对所述下一行像素中各子像素对应的数据通道之间进行电荷共享的步骤包括：
    在确定的电荷共享方式为同极性电荷共享的情况下，将相同极性子像素对应的数据通道之间互相连通；
    在确定的共享方式为全局电荷共享的情况下，将所有数据通道之间互相连通。
  6. 一种显示处理装置，包括：
    获取模块，用于获取当前帧图像的当前行像素和下一行像素的数据信号；
    确定模块，用于根据当前行像素和下一行像素的数据信号，确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式，其中，所述电荷共享方式包括全局电荷共享和同极性电荷共享；
    处理模块，用于根据确定的电荷共享方式，对所述下一行像素中各子像素对应的数据通道之间进行电荷共享。
  7. 根据权利要求6所述的显示处理装置，其中，所述确定模块包括：
    提取单元，用于提取当前行像素和下一行像素中每一数据通道的两个子 像素对应的数据信号的最高有效位；
    确定单元，用于根据当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，并在需要进行电荷共享的情况下确定所述下一行像素中各子像素对应的数据通道之间的电荷共享方式。
  8. 根据权利要求7所述的显示处理装置，其中，所述确定单元包括：
    第一运算子单元，用于将当前行像素和下一行像素中对应同一数据通道的两个子像素的数据信号的最高有效位进行异或运算，得到每一数据通道的异或运算结果；
    第二运算子单元，用于将每至少两个连续的数据通道的异或运算结果分别进行与运算以及或运算，得到若干个与运算结果以及或运算结果；
    第三运算子单元，用于将所述若干个与运算结果进行与运算，得到第一逻辑结果，将所述若干个或运算结果进行与运算，得到第二逻辑结果；
    确定子单元，用于根据所述第一逻辑结果和所述第二逻辑结果，确定所述下一行像素中各子像素对应的数据通道之间是否需要进行电荷共享，以及在需要进行电荷共享的情况下确定采用的电荷共享方式。
  9. 根据权利要求8所述的显示处理装置，其中，所述确定子单元包括：
    第一微单元，用于在所述第一逻辑结果和所述第二逻辑结果均为0的情况下，确定不对所述下一行像素中各子像素对应的数据通道之间进行电荷共享；
    第二微单元，用于在所述第一逻辑结果为1、所述第二逻辑结果为0的情况下，确定电荷共享方式为同极性电荷共享；
    第三微单元，用于在所述第一逻辑结果和所述第二逻辑结果均为1的情况下，确定电荷共享方式为全局电荷共享。
  10. 根据权利要求6所述的显示处理装置，其中，所述处理模块包括：
    第一连通单元，用于在确定的电荷共享方式为同极性电荷共享的情况下，将相同极性子像素对应的数据通道之间互相连通；
    第二连通单元，用于在确定的共享方式为全局电荷共享的情况下，将所有数据通道之间互相连通。
  11. 一种显示面板，包括如权利要求6-10中任一项所述的显示处理装置。
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