WO2022123785A1 - Three-dimensional integrated circuit - Google Patents

Three-dimensional integrated circuit Download PDF

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Publication number
WO2022123785A1
WO2022123785A1 PCT/JP2020/046357 JP2020046357W WO2022123785A1 WO 2022123785 A1 WO2022123785 A1 WO 2022123785A1 JP 2020046357 W JP2020046357 W JP 2020046357W WO 2022123785 A1 WO2022123785 A1 WO 2022123785A1
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Prior art keywords
integrated circuit
terminal group
pseudo
wafer
group
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PCT/JP2020/046357
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French (fr)
Japanese (ja)
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真也 横溝
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三菱電機株式会社
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Priority to JP2021531302A priority Critical patent/JP6972438B1/en
Priority to PCT/JP2020/046357 priority patent/WO2022123785A1/en
Publication of WO2022123785A1 publication Critical patent/WO2022123785A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the disclosed technology relates to a three-dimensional mounted integrated circuit in which a plurality of integrated circuits are stacked.
  • a fan-out wafer level package (FOWLP: Fan Out Wafer Level Package) is known as an effective technique for high-density integration of electronic components.
  • FOWLP Fan Out Wafer Level Package
  • Patent Document 1 an electronic device that is densely integrated using a reconstructed wafer (hereinafter referred to as “pseudo-wafer”) manufactured by FOWLP technology is known.
  • Patent Document 1 an integrated circuit having a metal member for support and an integrated circuit not having a metal member for support are alternately arranged on the bottom surface, and FOWLP is applied to form a three-dimensional structure with one pseudo-wafer, thereby forming a high-density integrated circuit.
  • the implementation is realized.
  • Patent Document 1 enables high-density integration, but has a metal member for support on the bottom surface, and an RF terminal, a control terminal, and a power supply terminal can be formed on only one side. Was high density and it was difficult to mount it on the board.
  • the present disclosure technique is for solving the above-mentioned problems, and can reduce the terminal density by forming RF terminals, control terminals, and power supply terminals on both sides after integrating integrated circuits at high density. It is an object of the present invention to provide a three-dimensional mounted integrated circuit.
  • the three-dimensional mounted integrated circuit according to the present disclosure technique is a three-dimensional mounted integrated circuit including N pseudo-waels (N: 2 or more natural numbers), and the pseudo-wafer has a first terminal group on the top surface.
  • a connection wiring group having a second terminal group on the bottom surface and electrically connecting the integrated circuit to any of the terminals of the first terminal group and the second terminal group and the integrated circuit.
  • N (n: 2 or more and N or less) internally provided with a penetrating wiring group that electrically connects between the terminals of the first terminal group and the terminals of the second terminal group so as to penetrate from the top surface to the bottom surface.
  • the first terminal group of the pseudo-wafer (n-1) and the second terminal group of the pseudo-wafer (n-1) are electrically connected.
  • the three-dimensional mounted integrated circuit according to the present disclosure technology has the above configuration, it has the effect of reducing the terminal density by forming RF terminals, control terminals, and power supply terminals on both sides after integrating the integrated circuits at high density. ..
  • FIG. 1 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the first embodiment.
  • the three-dimensional mounting integrated circuit according to the first embodiment includes a first pseudo-wafer 10 and a second pseudo-wafer 20, and includes a first pseudo-wafer 10 and a second pseudo-wafer 20.
  • the second terminal group 5 of the first pseudo-wafer 10 and the first terminal group 11 of the second pseudo-wafer 20 are electrically connected.
  • Solder bumps, gold bumps, or the like may be used for the connection between the second terminal group 5 and the first terminal group 11.
  • the first pseudo-wafer 10 includes a first terminal group 1, a first through wiring group 2, a first connection wiring group 3, a first integrated circuit 4 having terminals on both sides, and a second.
  • the terminal group 5 and the first resin film 6 are provided. Further, the first terminal group 1 is electrically connected to the first through wiring group 2 or the first connection wiring group 3, and the first integrated circuit 4 is electrically connected to the first connection wiring group 3.
  • the second terminal group 5 is electrically connected to the first through wiring group 2 or the first integrated circuit 4.
  • the second pseudo-wafer 20 includes a first terminal group 11, a second through wiring group 12, a second connection wiring group 13, a second integrated circuit 14 having terminals on both sides, and a second.
  • the terminal group 15 and the second resin film 16 are provided. Further, the first terminal group 11 is electrically connected to the second through wiring group 12 or the second connection wiring group 13, and the second integrated circuit 14 is electrically connected to the second connection wiring group 13.
  • the second terminal group 15 is electrically connected to the second through wiring group 12 or the second integrated circuit 14.
  • the integrated circuit is densely integrated, and the RF terminal, the control terminal, and the power supply terminal are formed on both sides, and the terminal density is increased. Can be mitigated.
  • FIG. 1 shows a connection between the second terminal group 5 and the first terminal group 11, but the first terminal group 1 or the second terminal group 5 and the first terminal group 5 are connected. Either the terminal group 11 or the second terminal group 15 may be connected.
  • FIG. 8 is a detailed view of the three-dimensional mounted integrated circuit according to the first embodiment. As shown in FIG. 8, the first integrated circuit 4 may use integrated circuits having different configurations in the same pseudo-wafer, and the second integrated circuit 14 also uses different configurations in the same pseudo-wafer. You may. Further, as shown in FIG. 8, the first through wiring group 2, the first connection wiring group 3, the second through wiring group 12, and the second connection wiring group 13 may be plural. ..
  • Embodiment 2 The three-dimensional mounted integrated circuit according to the second embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment.
  • FIG. 2 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the second embodiment.
  • the components of the three-dimensional mounting integrated circuit according to the second embodiment are the same as those of the first embodiment.
  • the three-dimensional mounted integrated circuit according to the second embodiment is arranged so that a part or all of the first integrated circuit 4a and the second integrated circuit 14a overlap when viewed transparently from the top surface to the bottom surface. Has the characteristics of
  • the distance between the integrated circuits can be shortened, so that higher density integration can be realized.
  • the three-dimensional mounted integrated circuit according to the second embodiment since the three-dimensional mounted integrated circuit according to the second embodiment has the above configuration, it can be further integrated at a higher density while obtaining the same effect as that of the first embodiment.
  • Embodiment 3 The three-dimensional mounted integrated circuit according to the third embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment.
  • FIG. 3 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the third embodiment.
  • the three-dimensional mounted integrated circuit according to the third embodiment includes a first through wiring group 2b, a first connection wiring group 3b, a first integrated circuit 4b, a second through wiring group 12b, and a second connection wiring group.
  • the periodic structure 30 including the 13b and the second integrated circuit 14b is periodically arranged.
  • the wiring design of the periodic structure 30 can be duplicated to design the wiring of the entire pseudo wafer. Therefore, the three-dimensional mounting integrated circuit according to the third embodiment can simplify the wiring design of the pseudo wafer.
  • the three-dimensional mounted integrated circuit according to the third embodiment has the above configuration, the same effects as those of the first and second embodiments can be obtained, and the design can be simplified.
  • Embodiment 4 The three-dimensional mounted integrated circuit according to the fourth embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment.
  • FIG. 4 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the fourth embodiment.
  • the components of the three-dimensional mounting integrated circuit according to the fourth embodiment are the same as those of the first embodiment.
  • pseudo wafers having the same periodic structure are used for the first pseudo wafer 10c and the second pseudo wafer 20c, and these are vertically stacked.
  • Using a pseudo-wafer having the same periodic structure makes it possible to simultaneously manufacture a first pseudo-wafer 10c and a second pseudo-wafer 20c by manufacturing and dividing one pseudo-wafer.
  • the three-dimensional mounting integrated circuit according to the fourth embodiment has the above configuration, the same effects as those of the first to third embodiments can be obtained, and the manufacturing process of the pseudo wafer can be omitted.
  • Embodiment 5 The three-dimensional mounted integrated circuit according to the fifth embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment.
  • FIG. 5 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the fifth embodiment.
  • the first antenna element group 31, the first connecting member 32, and the first A terminal group 33 on a resin substrate and a first resin substrate 34 are provided in the three-dimensional mounted integrated circuit according to the fifth embodiment.
  • the first connecting member 32 may use solder bumps, gold bumps, or the like.
  • the first antenna element group 31 is electrically connected to the first terminal group 1d
  • the terminal group 33 on the first resin substrate is electrically connected to the first connecting member 32
  • the first connecting member 32 is connected. Is electrically connected to the second terminal group 15d.
  • the antenna element is electrically connected to either the second terminal group of the first pseudo-wafer or the first terminal group of the N-th pseudo-wafer.
  • the resin substrate is electrically connected to the other. Since the first antenna element group 31 is electrically connected to the first terminal group 1d, the three-dimensional mounted integrated circuit according to the fifth embodiment realizes an array antenna corresponding to a high frequency signal having a short wavelength. Can be done.
  • Embodiment 6 The three-dimensional mounted integrated circuit according to the sixth embodiment has the same components as those of the fifth embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first to fifth embodiments.
  • FIG. 6 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the sixth embodiment.
  • the terminal group 35 on the second resin substrate and the wiring group 36 in the first resin substrate are used.
  • a third resin substrate upper terminal group 37, a second connection member 38, and a second resin substrate 39 are provided.
  • the second connecting member 38 may use solder bumps, gold bumps, or the like.
  • the first antenna element group 31f is electrically connected to the second resin substrate upper terminal group 35, and the second resin substrate upper terminal group 35 is electrically connected to the first resin substrate wiring group 36.
  • the wiring group 36 in the first resin substrate is electrically connected to the terminal group 37 on the third resin substrate, and the terminal group 37 on the third resin substrate is electrically connected to the second connecting member 38.
  • the connecting member 38 of 2 is electrically connected to the first terminal group 1e.
  • the three-dimensional mounting integrated circuit according to the sixth embodiment is provided with an antenna element on either the second terminal group of the first pseudo-wafer or the first terminal group of the N-th pseudo-wafer.
  • the resin substrate is electrically connected, and the resin substrate is electrically connected to the other.
  • Embodiment 7 The three-dimensional mounted integrated circuit according to the seventh embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment and the like.
  • FIG. 7 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the seventh embodiment.
  • the first connecting member 32f, the first resin substrate terminal group 33f, and the first The resin substrate 34f, the second connecting member 38f, and the third integrated circuit 40 are provided. Solder bumps or gold bumps may be used for the first connecting member 32f and the second connecting member 38f.
  • the third integrated circuit 40 does not exist inside the first pseudo-wafer 10 or inside the second pseudo-wafer 20.
  • the third integrated circuit 40 is electrically connected to the second connecting member 38f, the second connecting member 38f is electrically connected to the first terminal group 1f, and the terminal group 33f on the first resin substrate is It is electrically connected to the first connecting member 32f, and the first connecting member 32f is electrically connected to the second terminal group 15f.
  • the three-dimensional mounted integrated circuit according to the seventh embodiment can obtain the same effects as those of the first to fourth embodiments, and the step of manufacturing the pseudo wafer of the third integrated circuit 40 is omitted. be able to.

Abstract

This three-dimensional integrated circuit comprises N pseudo wafers (where N is a natural number equal to or greater than 2), the pseudo wafer having a first terminal group on the top surface and a second terminal group on the bottom surface, the pseudo wafer internally having an integrated circuit, a connection wire group electrically connecting terminals of either the first terminal group or the second terminal group to the integrated circuit, and a through-wire group electrically connecting terminals of the first terminal group with terminals of the second terminal group so as to pass through from the top surface to the bottom surface. The first terminal group of an nth pseudo wafer (where n is a natural number of 2 or greater and N or less) is electrically connected to the second terminal group of an (n-1)th pseudo wafer.

Description

３次元実装集積回路3D mounting integrated circuit
　本開示技術は、複数の集積回路を積層した3次元実装集積回路に関する。 The disclosed technology relates to a three-dimensional mounted integrated circuit in which a plurality of integrated circuits are stacked.
　電子部品の高密度集積に有効な技術として、ファンアウトウェハレベルパッケージ（ＦＯＷＬＰ：Ｆａｎ　Ｏｕｔ　Ｗａｆｅｒ　Ｌｅｖｅｌ　Ｐａｃｋａｇｅ）が知られている。例えば、ＦＯＷＬＰ技術により作製した再構築ウェハ（以下「疑似ウェハ」という）を用いて高密度集積した電子装置（例えば、特許文献１）が知られている。 A fan-out wafer level package (FOWLP: Fan Out Wafer Level Package) is known as an effective technique for high-density integration of electronic components. For example, an electronic device (for example, Patent Document 1) that is densely integrated using a reconstructed wafer (hereinafter referred to as “pseudo-wafer”) manufactured by FOWLP technology is known.
　特許文献１では、底面に支持用の金属部材を有する集積回路と有しない集積回路を交互に配置し、ＦＯＷＬＰを施し、１枚の疑似ウェハで３次元構造とすることにより、高密度な集積回路実装を実現している。 In Patent Document 1, an integrated circuit having a metal member for support and an integrated circuit not having a metal member for support are alternately arranged on the bottom surface, and FOWLP is applied to form a three-dimensional structure with one pseudo-wafer, thereby forming a high-density integrated circuit. The implementation is realized.
特開２０１９－１０２６６０号公報Japanese Unexamined Patent Publication No. 2019-102660
　特許文献１に記載の装置は、高密度集積化を可能にするが、底面に支持用の金属部材を有しており、ＲＦ端子、制御端子、及び電源端子を片面にしか形成できないため、端子が高密度となり基板への実装が困難であった。 The device described in Patent Document 1 enables high-density integration, but has a metal member for support on the bottom surface, and an RF terminal, a control terminal, and a power supply terminal can be formed on only one side. Was high density and it was difficult to mount it on the board.
　本開示技術は、上記課題を解消するためのものであり、集積回路を高密度集積した上で、ＲＦ端子、制御端子、及び電源端子を両面に形成し、端子密度を軽減することができる３次元実装集積回路を提供することを目的とする。 The present disclosure technique is for solving the above-mentioned problems, and can reduce the terminal density by forming RF terminals, control terminals, and power supply terminals on both sides after integrating integrated circuits at high density. It is an object of the present invention to provide a three-dimensional mounted integrated circuit.
　本開示技術に係る３次元実装集積回路は、Ｎ枚（Ｎ：２以上の自然数）の疑似ウェハを備える３次元実装集積回路であって、前記疑似ウェハは天面に第１の端子群を有し、底面に第２の端子群を有し、集積回路と、前記第１の端子群及び前記第２の端子群のいずれかの端子と前記集積回路とを電気的に接続する接続配線群と、前記第１の端子群と前記第２の端子群の端子間を天面から底面に貫通するように電気的に接続する貫通配線群とを内部に有し、ｎ（ｎ：２以上Ｎ以下の自然数）枚目の前記疑似ウェハの前記第１の端子群と、（ｎ－１）枚目の前記疑似ウェハの前記第２の端子群とが電気的に接続されたことを特徴とする。 The three-dimensional mounted integrated circuit according to the present disclosure technique is a three-dimensional mounted integrated circuit including N pseudo-waels (N: 2 or more natural numbers), and the pseudo-wafer has a first terminal group on the top surface. A connection wiring group having a second terminal group on the bottom surface and electrically connecting the integrated circuit to any of the terminals of the first terminal group and the second terminal group and the integrated circuit. , N (n: 2 or more and N or less) internally provided with a penetrating wiring group that electrically connects between the terminals of the first terminal group and the terminals of the second terminal group so as to penetrate from the top surface to the bottom surface. The first terminal group of the pseudo-wafer (n-1) and the second terminal group of the pseudo-wafer (n-1) are electrically connected.
　本開示技術に係る３次元実装集積回路は上記構成を備えるため、集積回路を高密度集積した上で、ＲＦ端子、制御端子、及び電源端子を両面に形成し、端子密度を軽減する効果を奏する。 Since the three-dimensional mounted integrated circuit according to the present disclosure technology has the above configuration, it has the effect of reducing the terminal density by forming RF terminals, control terminals, and power supply terminals on both sides after integrating the integrated circuits at high density. ..
本発明の実施の形態１に係る３次元実装集積回路の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the 3D mounting integrated circuit which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る３次元実装集積回路の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the 3D mounting integrated circuit which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る３次元実装集積回路の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the 3D mounting integrated circuit which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る３次元実装集積回路の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the 3D mounting integrated circuit which concerns on Embodiment 4 of this invention. 本発明の実施の形態５に係る３次元実装集積回路の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the 3D mounting integrated circuit which concerns on Embodiment 5 of this invention. 本発明の実施の形態６に係る３次元実装集積回路の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the 3D mounting integrated circuit which concerns on Embodiment 6 of this invention. 本発明の実施の形態７に係る３次元実装集積回路の一構成例を示す断面図である。It is sectional drawing which shows one structural example of the 3D mounting integrated circuit which concerns on Embodiment 7 of this invention. 本発明の実施の形態１に係る３次元実装集積回路の詳細図である。It is a detailed figure of the 3D mounting integrated circuit which concerns on Embodiment 1 of this invention.
　本開示技術に係る３次元実装集積回路の内容は、以下の図にそった説明により明らかにされる。 The contents of the three-dimensional mounted integrated circuit according to the disclosed technology will be clarified by the explanation according to the following figure.
実施の形態１．
　図１は、実施の形態１に係る３次元実装集積回路の一構成例を示す断面図である。図１が示すとおり実施の形態１に係る３次元実装集積回路は、第１の疑似ウェハ１０と、第２の疑似ウェハ２０とを備え、第１の疑似ウェハ１０と第２の疑似ウェハ２０を縦積みして、第１の疑似ウェハ１０の第２の端子群５と第２の疑似ウェハ２０の第１の端子群１１とを電気的に接続されている。第２の端子群５と第１の端子群１１との接続は、はんだバンプ、金バンプ等を用いてよい。 Embodiment 1.
FIG. 1 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the first embodiment. As shown in FIG. 1, the three-dimensional mounting integrated circuit according to the first embodiment includes a first pseudo-wafer 10 and a second pseudo-wafer 20, and includes a first pseudo-wafer 10 and a second pseudo-wafer 20. By stacking vertically, the second terminal group 5 of the first pseudo-wafer 10 and the first terminal group 11 of the second pseudo-wafer 20 are electrically connected. Solder bumps, gold bumps, or the like may be used for the connection between the second terminal group 5 and the first terminal group 11.
　第１の疑似ウェハ１０は、第１の端子群１と、第１の貫通配線群２と、第１の接続配線群３と、両面に端子を備えた第１の集積回路４と、第２の端子群５と、第１の樹脂膜６とを備える。また、第１の端子群１は、第１の貫通配線群２または第１の接続配線群３と電気的に接続され、第１の集積回路４は、第１の接続配線群３と電気的に接続され、第２の端子群５は、第１の貫通配線群２または第１の集積回路４と電気的に接続される。 The first pseudo-wafer 10 includes a first terminal group 1, a first through wiring group 2, a first connection wiring group 3, a first integrated circuit 4 having terminals on both sides, and a second. The terminal group 5 and the first resin film 6 are provided. Further, the first terminal group 1 is electrically connected to the first through wiring group 2 or the first connection wiring group 3, and the first integrated circuit 4 is electrically connected to the first connection wiring group 3. The second terminal group 5 is electrically connected to the first through wiring group 2 or the first integrated circuit 4.
　第２の疑似ウェハ２０は、第１の端子群１１と、第２の貫通配線群１２と、第２の接続配線群１３と、両面に端子を備えた第２の集積回路１４と、第２の端子群１５と、第２の樹脂膜１６とを備える。また、第１の端子群１１は、第２の貫通配線群１２または第２の接続配線群１３と電気的に接続され、第２の集積回路１４は、第２の接続配線群１３と電気的に接続され、第２の端子群１５は、第２の貫通配線群１２または第２の集積回路１４と電気的に接続される。 The second pseudo-wafer 20 includes a first terminal group 11, a second through wiring group 12, a second connection wiring group 13, a second integrated circuit 14 having terminals on both sides, and a second. The terminal group 15 and the second resin film 16 are provided. Further, the first terminal group 11 is electrically connected to the second through wiring group 12 or the second connection wiring group 13, and the second integrated circuit 14 is electrically connected to the second connection wiring group 13. The second terminal group 15 is electrically connected to the second through wiring group 12 or the second integrated circuit 14.
　以上のように、実施の形態１に係る３次元実装集積回路は上記の構成を備えるため、集積回路が高密度集積され、ＲＦ端子、制御端子、及び電源端子が両面に形成され、端子密度を軽減することができる。 As described above, since the three-dimensional mounted integrated circuit according to the first embodiment has the above configuration, the integrated circuit is densely integrated, and the RF terminal, the control terminal, and the power supply terminal are formed on both sides, and the terminal density is increased. Can be mitigated.
　なお、ここでは、第１の疑似ウェハ１０と第２の疑似ウェハ２０の２枚を縦積みする例を示したが、３枚以上を縦積みすることも可能である。また、図１は、第２の端子群５と第１の端子群１１とを接続しているものを示しているが、第１の端子群１または第２の端子群５と、第１の端子群１１または第２の端子群１５のいずれかが接続されていればよい。また、図８は実施の形態１に係る３次元実装集積回路の詳細図である。図８に示すように第１の集積回路４は同一の疑似ウェハ内でそれぞれ異なる構成の集積回路を用いてもよく、第２の集積回路１４も同様に同一の疑似ウェハ内で異なる構成を用いてもよい。また、図８に示すように第１の貫通配線群２と、第１の接続配線群３と、第２の貫通配線群１２と、第２の接続配線群１３は、複数であってもよい。 Although two pieces of the first pseudo-wafer 10 and the second pseudo-wafer 20 are vertically stacked here, it is also possible to vertically stack three or more wafers. Further, FIG. 1 shows a connection between the second terminal group 5 and the first terminal group 11, but the first terminal group 1 or the second terminal group 5 and the first terminal group 5 are connected. Either the terminal group 11 or the second terminal group 15 may be connected. Further, FIG. 8 is a detailed view of the three-dimensional mounted integrated circuit according to the first embodiment. As shown in FIG. 8, the first integrated circuit 4 may use integrated circuits having different configurations in the same pseudo-wafer, and the second integrated circuit 14 also uses different configurations in the same pseudo-wafer. You may. Further, as shown in FIG. 8, the first through wiring group 2, the first connection wiring group 3, the second through wiring group 12, and the second connection wiring group 13 may be plural. ..
実施の形態２．
　実施の形態２に係る３次元実装集積回路は、実施の形態１のものと同じ構成要素を有する。よって、ここでの記載は、実施の形態１で説明した重複する項目について適宜省略する。 Embodiment 2.
The three-dimensional mounted integrated circuit according to the second embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment.
　図２は、実施の形態２に係る３次元実装集積回路の一構成例を示す断面図である。図２が示すとおり、実施の形態２に係る３次元実装集積回路の構成要素は実施の形態１のものと同様である。実施の形態２に係る３次元実装集積回路は、天面から底面へ透過的に見たときに第１の集積回路４ａと第２の集積回路１４ａの一部または全てが重なるように配置されている特徴を有する。 FIG. 2 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the second embodiment. As shown in FIG. 2, the components of the three-dimensional mounting integrated circuit according to the second embodiment are the same as those of the first embodiment. The three-dimensional mounted integrated circuit according to the second embodiment is arranged so that a part or all of the first integrated circuit 4a and the second integrated circuit 14a overlap when viewed transparently from the top surface to the bottom surface. Has the characteristics of
　第１の集積回路４ａと第２の集積回路１４ａの一部または全てが重なるように配置されていると、集積回路同士の距離を短くできるため、さらに高密度集積を実現できる。 If a part or all of the first integrated circuit 4a and the second integrated circuit 14a are arranged so as to overlap each other, the distance between the integrated circuits can be shortened, so that higher density integration can be realized.
　以上のとおり実施の形態２に係る３次元実装集積回路は上記の構成を備えるため、実施の形態１と同様の効果を得た上で、さらに高密度集積化できる。 As described above, since the three-dimensional mounted integrated circuit according to the second embodiment has the above configuration, it can be further integrated at a higher density while obtaining the same effect as that of the first embodiment.
実施の形態３．
　実施の形態３に係る３次元実装集積回路は、実施の形態１のものと同じ構成要素を有する。よって、ここでの記載は、実施の形態１で説明した重複する項目について適宜省略する。 Embodiment 3.
The three-dimensional mounted integrated circuit according to the third embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment.
　図３は、実施の形態３に係る３次元実装集積回路の一構成例を示す断面図である。図３が示すとおり、実施の形態３に係る３次元実装集積回路の構成要素は実施の形態１のものと同様である。実施の形態３に係る３次元実装集積回路は、第１の貫通配線群２ｂと第１の接続配線群３ｂと第１の集積回路４ｂと第２の貫通配線群１２ｂと第２の接続配線群１３ｂと第２の集積回路１４ｂから成る周期構造３０が周期的に配列される。 FIG. 3 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the third embodiment. As shown in FIG. 3, the components of the three-dimensional mounting integrated circuit according to the third embodiment are the same as those of the first embodiment. The three-dimensional mounted integrated circuit according to the third embodiment includes a first through wiring group 2b, a first connection wiring group 3b, a first integrated circuit 4b, a second through wiring group 12b, and a second connection wiring group. The periodic structure 30 including the 13b and the second integrated circuit 14b is periodically arranged.
　周期構造３０が周期的に配列されると、周期構造３０の配線設計を複製して疑似ウェハ全体の配線設計が可能となる。このため、実施の形態３に係る３次元実装集積回路は、疑似ウェハの配線設計を簡略化できる。 When the periodic structure 30 is periodically arranged, the wiring design of the periodic structure 30 can be duplicated to design the wiring of the entire pseudo wafer. Therefore, the three-dimensional mounting integrated circuit according to the third embodiment can simplify the wiring design of the pseudo wafer.
　以上のとおり実施の形態３に係る３次元実装集積回路は上記の構成を備えるため、実施の形態１、２と同様の効果が得られ、設計を簡略化できる。 As described above, since the three-dimensional mounted integrated circuit according to the third embodiment has the above configuration, the same effects as those of the first and second embodiments can be obtained, and the design can be simplified.
実施の形態４．
　実施の形態４に係る３次元実装集積回路は、実施の形態１のものと同じ構成要素を有する。よって、ここでの記載は、実施の形態１で説明した重複する項目について適宜省略する。 Embodiment 4.
The three-dimensional mounted integrated circuit according to the fourth embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment.
　図４は、実施の形態４に係る３次元実装集積回路の一構成例を示す断面図である。図４が示すとおり、実施の形態４に係る３次元実装集積回路の構成要素は実施の形態１のものと同様である。実施の形態４に係る３次元実装集積回路は、第１の疑似ウェハ１０ｃと第２の疑似ウェハ２０ｃに同じ周期構造を有する疑似ウェハが用いられており、これらが縦積みされている。 FIG. 4 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the fourth embodiment. As shown in FIG. 4, the components of the three-dimensional mounting integrated circuit according to the fourth embodiment are the same as those of the first embodiment. In the three-dimensional mounting integrated circuit according to the fourth embodiment, pseudo wafers having the same periodic structure are used for the first pseudo wafer 10c and the second pseudo wafer 20c, and these are vertically stacked.
　同じ周期構造を有する疑似ウェハを用いることは、１枚の疑似ウェハを製造し、分割することによって、第１の疑似ウェハ１０ｃと第２の疑似ウェハ２０ｃとを同時に製造することが可能となる。 Using a pseudo-wafer having the same periodic structure makes it possible to simultaneously manufacture a first pseudo-wafer 10c and a second pseudo-wafer 20c by manufacturing and dividing one pseudo-wafer.
　以上のとおり実施の形態４に係る３次元実装集積回路は上記の構成を備えるため、実施の形態１から３と同様の効果が得られ、疑似ウェハの製造工程を省略できる。 As described above, since the three-dimensional mounting integrated circuit according to the fourth embodiment has the above configuration, the same effects as those of the first to third embodiments can be obtained, and the manufacturing process of the pseudo wafer can be omitted.
実施の形態５．
　実施の形態５に係る３次元実装集積回路は、実施の形態１のものと同じ構成要素を有する。よって、ここでの記載は、実施の形態１で説明した重複する項目について適宜省略する。 Embodiment 5.
The three-dimensional mounted integrated circuit according to the fifth embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment.
　図５は、実施の形態５に係る３次元実装集積回路の一構成例を示す断面図である。図５が示すとおり、実施の形態５に係る３次元実装集積回路は、実施の形態１の構成要素に加えて、第１のアンテナ素子群３１と、第１の接続部材３２と、第１の樹脂基板上端子群３３と、第１の樹脂基板３４とを備える。第１の接続部材３２は、はんだバンプまたは金バンプ等を用いてよい。第１のアンテナ素子群３１は第１の端子群１ｄと電気的に接続され、第１の樹脂基板上端子群３３は第１の接続部材３２と電気的に接続され、第１の接続部材３２は第２の端子群１５ｄと電気的に接続されている。 FIG. 5 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the fifth embodiment. As shown in FIG. 5, in the three-dimensional mounted integrated circuit according to the fifth embodiment, in addition to the components of the first embodiment, the first antenna element group 31, the first connecting member 32, and the first A terminal group 33 on a resin substrate and a first resin substrate 34 are provided. The first connecting member 32 may use solder bumps, gold bumps, or the like. The first antenna element group 31 is electrically connected to the first terminal group 1d, the terminal group 33 on the first resin substrate is electrically connected to the first connecting member 32, and the first connecting member 32 is connected. Is electrically connected to the second terminal group 15d.
　すなわち、実施の形態５に係る３次元実装集積回路は、１枚目の疑似ウェハの第２の端子群またはＮ枚目の疑似ウェハの第１の端子群のどちらか一方にアンテナ素子が電気的に接続され、他方に樹脂基板が電気的に接続される。第１のアンテナ素子群３１は第１の端子群１ｄと電気的に接続されているため、実施の形態５に係る３次元実装集積回路は波長の短い高周波信号に対応したアレーアンテナを実現することができる。 That is, in the three-dimensional mounting integrated circuit according to the fifth embodiment, the antenna element is electrically connected to either the second terminal group of the first pseudo-wafer or the first terminal group of the N-th pseudo-wafer. The resin substrate is electrically connected to the other. Since the first antenna element group 31 is electrically connected to the first terminal group 1d, the three-dimensional mounted integrated circuit according to the fifth embodiment realizes an array antenna corresponding to a high frequency signal having a short wavelength. Can be done.
実施の形態６．
　実施の形態６に係る３次元実装集積回路は、実施の形態５のものと同じ構成要素を有する。よって、ここでの記載は、実施の形態１から５で説明した重複する項目について適宜省略する。 Embodiment 6.
The three-dimensional mounted integrated circuit according to the sixth embodiment has the same components as those of the fifth embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first to fifth embodiments.
　図６は、実施の形態６に係る３次元実装集積回路の一構成例を示す断面図である。図６が示すとおり、実施の形態６に係る３次元実装集積回路は、実施の形態５の構成要素に加えて、第２の樹脂基板上端子群３５と、第１の樹脂基板内配線群３６と、第３の樹脂基板上端子群３７と、第２の接続部材３８と、第２の樹脂基板３９とを備える。第２の接続部材３８は、はんだバンプまたは金バンプ等を用いてよい。第１のアンテナ素子群３１ｆは第２の樹脂基板上端子群３５と電気的に接続され、第２の樹脂基板上端子群３５は第１の樹脂基板内配線群３６と電気的に接続され、第１の樹脂基板内配線群３６は第３の樹脂基板上端子群３７と電気的に接続され、第３の樹脂基板上端子群３７は第２の接続部材３８と電気的に接続され、第２の接続部材３８は第１の端子群１ｅと電気的に接続される。 FIG. 6 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the sixth embodiment. As shown in FIG. 6, in the three-dimensional mounted integrated circuit according to the sixth embodiment, in addition to the components of the fifth embodiment, the terminal group 35 on the second resin substrate and the wiring group 36 in the first resin substrate are used. A third resin substrate upper terminal group 37, a second connection member 38, and a second resin substrate 39 are provided. The second connecting member 38 may use solder bumps, gold bumps, or the like. The first antenna element group 31f is electrically connected to the second resin substrate upper terminal group 35, and the second resin substrate upper terminal group 35 is electrically connected to the first resin substrate wiring group 36. The wiring group 36 in the first resin substrate is electrically connected to the terminal group 37 on the third resin substrate, and the terminal group 37 on the third resin substrate is electrically connected to the second connecting member 38. The connecting member 38 of 2 is electrically connected to the first terminal group 1e.
　すなわち、実施の形態６に係る３次元実装集積回路は、１枚目の疑似ウェハの第２の端子群またはＮ枚目の疑似ウェハの第１の端子群のどちらか一方にアンテナ素子を備えた樹脂基板が電気的に接続され、他方に樹脂基板が電気的に接続される。上記の構成を備えることにより実施の形態６に係る３次元実装集積回路は、実施の形態５と同様の効果を得た上で、第１の集積回路４ｅと第１のアンテナ素子群３１ｆとの距離を離すことができ、干渉を抑制することができる。また、第１の樹脂基板内配線群３６を備えたことにより、配線の自由度を高めることができる。 That is, the three-dimensional mounting integrated circuit according to the sixth embodiment is provided with an antenna element on either the second terminal group of the first pseudo-wafer or the first terminal group of the N-th pseudo-wafer. The resin substrate is electrically connected, and the resin substrate is electrically connected to the other. By providing the above configuration, the three-dimensional integrated circuit according to the sixth embodiment has the same effect as that of the fifth embodiment, and then includes the first integrated circuit 4e and the first antenna element group 31f. The distance can be increased and interference can be suppressed. Further, by providing the first resin substrate wiring group 36, the degree of freedom of wiring can be increased.
実施の形態７．
実施の形態７に係る３次元実装集積回路は、実施の形態１のものと同じ構成要素を有する。よって、ここでの記載は、実施の形態１などで説明した重複する項目について適宜省略する。 Embodiment 7.
The three-dimensional mounted integrated circuit according to the seventh embodiment has the same components as those of the first embodiment. Therefore, the description here will appropriately omit the overlapping items described in the first embodiment and the like.
　図７は、実施の形態７に係る３次元実装集積回路の一構成例を示す断面図である。図７が示すとおり実施の形態７に係る３次元実装集積回路は、実施の形態１の構成要素に加えて、第１の接続部材３２ｆと、第１の樹脂基板上端子群３３ｆと、第１の樹脂基板３４ｆと、第２の接続部材３８ｆと、第３の集積回路４０とを備える。第１の接続部材３２ｆと第２の接続部材３８ｆは、はんだバンプまたは金バンプを用いてよい。第３の集積回路４０は、第１の集積回路４及び第２の集積回路１４とは異なり、第１の疑似ウェハ１０の内部にも第２の疑似ウェハ２０の内部にも存在しない。第３の集積回路４０は第２の接続部材３８ｆと電気的に接続され、第２の接続部材３８ｆは第１の端子群１ｆと電気的に接続され、第１の樹脂基板上端子群３３ｆは第１の接続部材３２ｆと電気的に接続され、第１の接続部材３２ｆは第２の端子群１５ｆと電気的に接続される。 FIG. 7 is a cross-sectional view showing a configuration example of a three-dimensional mounted integrated circuit according to the seventh embodiment. As shown in FIG. 7, in the three-dimensional mounting integrated circuit according to the seventh embodiment, in addition to the components of the first embodiment, the first connecting member 32f, the first resin substrate terminal group 33f, and the first The resin substrate 34f, the second connecting member 38f, and the third integrated circuit 40 are provided. Solder bumps or gold bumps may be used for the first connecting member 32f and the second connecting member 38f. Unlike the first integrated circuit 4 and the second integrated circuit 14, the third integrated circuit 40 does not exist inside the first pseudo-wafer 10 or inside the second pseudo-wafer 20. The third integrated circuit 40 is electrically connected to the second connecting member 38f, the second connecting member 38f is electrically connected to the first terminal group 1f, and the terminal group 33f on the first resin substrate is It is electrically connected to the first connecting member 32f, and the first connecting member 32f is electrically connected to the second terminal group 15f.
　上記の構成を備えることにより実施の形態７に係る３次元実装集積回路は、実施の形態１から４と同様の効果を得られ、第３の集積回路４０の疑似ウェハを作製する工程を省略することができる。 By providing the above configuration, the three-dimensional mounted integrated circuit according to the seventh embodiment can obtain the same effects as those of the first to fourth embodiments, and the step of manufacturing the pseudo wafer of the third integrated circuit 40 is omitted. be able to.
　１（１ｄ、１ｅ、１ｆ）　第１の端子群、　２（２ｂ）　第１の貫通配線群、　３（３ｂ）　第１の接続配線群、　４（４ａ、４ｂ、４ｅ）　第１の集積回路、　５　第２の端子群、　６　第１の樹脂膜、　１０（１０ｃ）　第１の疑似ウェハ、　１１　第１の端子群、　１２（１２ｂ）　第２の貫通配線群、　１３（１３ｂ）　第２の接続配線群、　１４（１４ａ、１４ｂ）　第２の集積回路、　１５（１５ｄ、１５ｆ）第２の端子群、　１６　第２の樹脂膜、　２０（２０ｃ）　第２の疑似ウェハ、　３０　周期構造、　３１（３１ｆ）　第１のアンテナ素子群、　３２（３２ｆ）　第１の接続部材、　３３（３３ｆ）　第１の樹脂基板上端子群、　３４（３４ｆ）　第１の樹脂基板、　３５　第２の樹脂基板上端子群、　３６　第１の樹脂基板内配線群、　３７　第３の樹脂基板上端子群、　３８（３８ｆ）　第２の接続部材、　３９　第２の樹脂基板、　４０　第３の集積回路。 1 (1d, 1e, 1f) 1st terminal group, 2 (2b) 1st through wiring group, 3 (3b) 1st connection wiring group, 4 (4a, 4b, 4e) 1st integrated circuit, 5 2nd terminal group, 6 1st resin film, 10 (10c) 1st pseudo wafer, 11 1st terminal group, 12 (12b) 2nd through wiring group, 13 (13b) 2nd connection Wiring group, 14 (14a, 14b) second integrated circuit, 15 (15d, 15f) second terminal group, 16 second resin film, 20 (20c) second pseudo wafer, 30 periodic structure, 31 ( 31f) 1st antenna element group, 32 (32f) 1st connection member, 33 (33f) 1st resin substrate upper terminal group, 34 (34f) 1st resin substrate, 35 2nd resin substrate upper terminal Group, 36 1st resin substrate wiring group, 37 3rd resin substrate upper terminal group, 38 (38f) 2nd connection member, 39 2nd resin substrate, 40 3rd integrated circuit.

Claims (7)

  1. 　Ｎ枚（Ｎ：２以上の自然数）の疑似ウェハを備える３次元実装集積回路であって、
    前記疑似ウェハは
    　天面に第１の端子群を有し、底面に第２の端子群を有し、
    　集積回路と、
    　前記第１の端子群及び前記第２の端子群のいずれかの端子と前記集積回路とを電気的に接続する接続配線群と、
    　前記第１の端子群と前記第２の端子群の端子間を天面から底面に貫通するように電気的に接続する貫通配線群とを内部に有し、
    　ｎ（ｎ：２以上Ｎ以下の自然数）枚目の前記疑似ウェハの前記第１の端子群と、（ｎ－１）枚目の前記疑似ウェハの前記第２の端子群とが電気的に接続されたことを特徴とする３次元実装集積回路。     A three-dimensional mounted integrated circuit equipped with N pseudo-wafers (N: 2 or more natural numbers).
    The pseudo-wafer has a first terminal group on the top surface and a second terminal group on the bottom surface.
    With integrated circuits
    A connection wiring group that electrically connects any of the terminals of the first terminal group and the second terminal group to the integrated circuit, and
    It has a through wiring group that electrically connects between the terminals of the first terminal group and the terminals of the second terminal group so as to penetrate from the top surface to the bottom surface.
    The first terminal group of the n (n: natural number of 2 or more and N or less) sheet of the pseudo wafer and the second terminal group of the pseudo wafer of the (n-1) th sheet are electrically connected. A three-dimensional mounted integrated circuit characterized by being made.
  2. 　天面から底面へ透過的に見たときに異なる前記疑似ウェハが有する前記集積回路同士の一部または全てが重なるように前記集積回路を配置した請求項１に記載の３次元実装集積回路。 The three-dimensional mounted integrated circuit according to claim 1, wherein the integrated circuits are arranged so that some or all of the integrated circuits of the pseudo wafers that are different when viewed transparently from the top surface to the bottom surface overlap each other.
  3. 　前記集積回路、前記接続配線群、前記貫通配線群、前記第１の端子群、及び前記第２の端子群による周期構造を備えた請求項１または２に記載の３次元実装集積回路。 The three-dimensional mounted integrated circuit according to claim 1 or 2, further comprising a periodic structure consisting of the integrated circuit, the connection wiring group, the through wiring group, the first terminal group, and the second terminal group.
  4. 　前記集積回路、前記接続配線群、前記貫通配線群、前記第１の端子群，及び前記第２の端子群による同一の前記周期構造を備えた前記疑似ウェハを接続したことを特徴とする請求項３に記載の３次元実装集積回路。 The claim is characterized in that the pseudo wafer having the same periodic structure by the integrated circuit, the connection wiring group, the through wiring group, the first terminal group, and the second terminal group is connected. 3. The three-dimensional mounted integrated circuit according to 3.
  5. 　１枚目の前記疑似ウェハの前記第２の端子群またはＮ枚目の前記疑似ウェハの前記第１の端子群のどちらか一方にアンテナ素子が電気的に接続され、他方に樹脂基板が電気的に接続されたことを特徴とする請求項１から請求項４のいずれか１項に記載の３次元実装集積回路。 The antenna element is electrically connected to either the second terminal group of the first pseudo-wafer or the first terminal group of the N-th pseudo-wafer, and the resin substrate is electrically connected to the other. The three-dimensional mounted integrated circuit according to any one of claims 1 to 4, characterized in that it is connected to.
  6. 　１枚目の前記疑似ウェハの前記第２の端子群またはＮ枚目の前記疑似ウェハの前記第１の端子群のどちらか一方にアンテナ素子を備えた樹脂基板が電気的に接続され、他方に樹脂基板が電気的に接続されたことを特徴とする請求項１から請求項４のいずれか１項に記載の３次元実装集積回路。 A resin substrate provided with an antenna element is electrically connected to either one of the second terminal group of the first pseudo-wafer or the first terminal group of the N-th pseudo-wafer, and to the other. The three-dimensional mounting integrated circuit according to any one of claims 1 to 4, wherein the resin substrate is electrically connected.
  7. 　１枚目の前記疑似ウェハの前記第２の端子群またはＮ枚目の前記疑似ウェハの前記第１の端子群のどちらか一方に第３の集積回路が電気的に接続され、他方に樹脂基板が電気的に接続されたことを特徴とする請求項１から請求項４のいずれか１項に記載の３次元実装集積回路。 A third integrated circuit is electrically connected to either one of the second terminal group of the first pseudo-wafer or the first terminal group of the N-th pseudo-wafer, and a resin substrate is connected to the other. The three-dimensional mounted integrated circuit according to any one of claims 1 to 4, wherein the wafers are electrically connected.
PCT/JP2020/046357 2020-12-11 2020-12-11 Three-dimensional integrated circuit WO2022123785A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002344146A (en) * 2001-05-15 2002-11-29 Tdk Corp High frequency module and its manufacturing method
JP2005217225A (en) * 2004-01-30 2005-08-11 Shinko Electric Ind Co Ltd Semiconductor device and method for manufacturing the same
JP2009016786A (en) * 2007-07-02 2009-01-22 Nepes Corp Ultrathin semiconductor package and its manufacturing method
WO2017187559A1 (en) * 2016-04-27 2017-11-02 三菱電機株式会社 High frequency circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002344146A (en) * 2001-05-15 2002-11-29 Tdk Corp High frequency module and its manufacturing method
JP2005217225A (en) * 2004-01-30 2005-08-11 Shinko Electric Ind Co Ltd Semiconductor device and method for manufacturing the same
JP2009016786A (en) * 2007-07-02 2009-01-22 Nepes Corp Ultrathin semiconductor package and its manufacturing method
WO2017187559A1 (en) * 2016-04-27 2017-11-02 三菱電機株式会社 High frequency circuit

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