JP2000252381A - Mounting structure of lsi chip on multilayer substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate the high speed performance and reduce the size of an LSI chip and increase the number of terminals by removing the influence by the through hole capacitance to prevent noise. SOLUTION: This is a mounting structure of an LSI chip for mounting an LSI chip 1 on a multilayer substrate 5 made by stacking a plurality of signal layer 5a-5h through insulators 6. This mounting structure comprises the LSI chip 1 having a step-formed terminal face 2 and terminals 3 formed on each of steps 2a-2e, the mutilayer substrate 5 having an LSI chip mounting section which is step-formed from the mounting face side in conformity with the terminal face 2 of the LSI chip 1, and connections 9 which are formed on exposed parts 8a-8e of each signal layer exposed when the substrate 5 is step-formed to be connected to the terminals 3 of the LSI chip 1. When mounting the LSI chip 1, the LSI chip 1 is inserted into the LSI chip mounting section of the substrate 5 and then the connections 9 and the terminals 3 of the LSI chip 1 are connected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an LSI chip mounting structure for mounting an LSI chip having a large number of terminals on a laminated substrate.

[0002]

2. Description of the Related Art In recent years, as the integration and capacity of semiconductors have increased, there has been a demand for a laminated substrate on which LSI chips are mounted to reduce noise and increase the density of connection terminals. To solve such a problem, for example, Japanese Patent Application Laid-Open
No. 181445 discloses an invention in which a bump substrate is connected to a laminated substrate having a built-in capacitor portion of an LSI chip. According to the present invention, since the capacitor section incorporated in the laminated substrate filters noise, switching noise is greatly reduced, and malfunction can be prevented.

As described in JP-A-8-181445, when an LSI chip has a large number of terminals on a terminal surface, it is difficult to extract a signal when the LSI chip is mounted on a laminated board having a small number of signal layers. Therefore, an LSI chip is generally mounted on a laminated substrate having a large number of signal layers. FIG. 6 is a schematic view of a laminated substrate and an LSI chip illustrating a conventional example of a mounting structure of an LSI chip, and FIG. 7 is a plan view of a mounting surface of the laminated substrate of FIG. 6 on which the LSI chip is mounted. FIG.
As shown in Fig. 6, the laminated substrate 5 'is formed of a plurality of signal layers (eight layers 5a' to 5h 'in the example shown in Fig. 6).

[0004] A connection pad 9 'is arranged on the surface of the laminated substrate 5' (the surface on which the LSI chip 1 'is mounted) in correspondence with the terminal 3', and a predetermined signal layer 5a is provided near the connection pad 9 '. Through holes 9a 'reaching' 5h 'are formed, and the signal layers 5a'-5' are formed through the through holes 9a '.
The wiring 9b 'of h' is connected to the connection pad 9 '.
For power supply to the LSI chip, an arbitrary signal layer (for example, 5e ') of the laminated substrate 5' is used as a signal layer dedicated to power supply.
The communication is performed from the signal layer 5e 'through the through hole 9a'.

However, when the signal passes through the through hole 9a 'as described above, the higher the frequency,
Alternatively, there is a problem that the longer the through hole 9a ', the greater the influence of the through hole capacitance, which increases the noise and the tendency to hinder high speed operation. The power supply is also made through hole 9a '.
However, there is a problem that noise and voltage drop occur. FIG. 8 is a graph showing a transmission waveform of the LSI chip 1 ′. As shown in FIG. 8, noise N occurs in the middle of the transmission wave.

Also, a through hole 9 is provided between the connection pads 9 '.
Since a 'is formed, a certain distance between terminals is required, and there is a problem that it is difficult to reduce the size of the LSI chip 1' and increase the number of terminals. Such a problem cannot be solved by the invention described in the above-mentioned JP-A-8-181445. That is, Japanese Patent Application Laid-Open No. Hei.
The mounting structure described in No. 45 is also LS
Since the I chip and the wiring board are connected, the influence of through-hole capacitance occurs.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has been made in consideration of the above problems. LS capable of providing a structure and supplying power to an LSI chip without generating a voltage drop or noise
It is an object of the present invention to provide an I-chip mounting structure, and to provide an LSI chip mounting structure that makes it easy to reduce the size of the LSI chip and increase the number of terminals.

[0008]

According to an aspect of the present invention, there is provided an LSI chip mounting structure for mounting an LSI chip on a laminated substrate having a plurality of signal layers, comprising: An LSI chip in which a surface is formed in a step-like manner, and a terminal is provided for each step; a laminated substrate in which an LSI chip mounting portion is formed in a step-like manner from the mounting surface side in accordance with the terminal surface of the LSI chip; The LSI is formed on the exposed surface of each signal layer exposed by
A connection portion connected to a terminal of the chip;
The configuration is such that the LSI chip is inserted into a chip mounting portion, and the connection portion and a terminal of the LSI chip are connected and mounted. With this configuration, it is possible to connect the terminals of the LSI chip and the wiring of the predetermined signal layer without passing through the through-holes.
It is possible to increase the speed of the I chip. When the number of terminals is the same, the distance between the terminals can be reduced to reduce the size of the LSI chip. When the size of the LSI chip is the same, the number of terminals that can be provided on the terminal surface is reduced. You can do more.

According to a second aspect of the present invention, the plurality of signal layers are stacked via an insulator having the same thickness. According to this configuration, each ball-shaped terminal contacts each corresponding pad in an equal state. Therefore, the connection state of each terminal with each pad after the melting of each terminal becomes uniform, and a contact failure or the like is eliminated.

According to a third aspect of the present invention, the terminal surface of the LSI chip is formed stepwise from the entire periphery surrounding the terminal surface toward the center. According to this configuration, the present invention can be applied to an LSI chip having a large number of terminals.

According to a fourth aspect of the present invention, the terminal surface of the LSI chip is formed stepwise from one or both of two opposing sides. According to this configuration, the present invention can be applied to an LSI chip having a large number of terminals, and the direction of extracting signals from the LSI chip is limited to the left and right directions of the LSI chip. Wiring can be easily formed.

According to a fifth aspect of the present invention, the laminated substrate includes a dedicated signal layer for supplying power to the LSI chip. According to this configuration, power can be supplied without passing through the through-hole, so that noise generation and voltage drop due to the through-hole capacitance can be prevented.

According to a sixth aspect of the present invention, a terminal of the LSI chip or a connection portion of the laminated substrate is formed of a ball-shaped electrode. According to this configuration, the connection between the terminal of the LSI chip and the connection portion of the wiring board can be ensured,
Generation of noise can be further reduced.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION In the following, L is applied to a laminated substrate of the present invention.
The mounting structure of the SI chip will be described in detail with reference to the drawings. FIG. 1 is a schematic side view illustrating a mounting structure of an LSI chip on a laminated substrate according to an embodiment of the present invention, FIG. 2 is a plan view of the laminated substrate illustrating an arrangement of connection portions, and FIG. 7 is a graph illustrating a transmission waveform of an LSI chip in the explanatory diagram of the operation of FIG.

The terminal surface 2 of the LSI chip 1 is formed stepwise from four sides surrounding the terminal surface 2 toward the center. In this embodiment, the LSI chip 1 has 10 columns 1
It has a total of 100 terminals 3 in 0 rows. In this embodiment, the terminals 3 are formed of a ball-shaped solder. The steps on the terminal surface 2 are formed in five steps, and each step 2a, 2b, 2
The terminals 3 are arranged at substantially equal intervals for each of c, 2d, and 2e.

The laminated substrate 5 on which the LSI chip 1 is mounted is formed by laminating eight signal layers 5a to 5h. Wiring not shown is formed in each of the signal layers 5a to 5h, and an insulator 6 having the same thickness is interposed between the signal layers. The third and fifth signal layers 5c and 5e from the surface (mounting surface) of the multilayer substrate 5 are power-only layers for supplying power to the LSI chip 1.

The mounting portion of the laminated substrate 5 on which the LSI chip 1 is mounted is arranged such that the square is gradually reduced in accordance with the shape of the terminal surface 2 of the LSI chip 1 so that the insulator 6 and the signal layer 5a are formed from the front side. To 5e are sequentially cut out to form a step shape. Five steps of the laminated substrate 5 are formed in the same manner as the steps of the LSI chip 1, and the exposed portions 8 of the signal layers 5b to 5f are formed.
In a to 8e, connection pads 9 as connection portions are formed at substantially equal intervals according to the arrangement of the terminals 3 of the LSI chip 1. Each connection pad 9 is connected to a wiring on each of the signal layers 5b to 5f.

The LSI chip 1 is inserted into the mounting portion of the laminated substrate 5 formed in a step shape (the insertion direction is indicated by an arrow in FIG. 1), and the terminal 3 of each of the step portions 2a to 2e is connected to each signal. Connected to connection pads 9 of layers 5b to 5f. Insulator 6,
Since the thicknesses of..., 6 are the same, each ball-shaped terminal 3 contacts each corresponding pad 9 in an equal state. Therefore, the connection state of each terminal 3 with each pad 9 after melting is uniform, and a contact failure or the like is eliminated.

According to the mounting structure of the LSI chip configured as described above, each terminal 3 of the LSI chip can be connected to the wiring of the predetermined signal layer 5b to 5f without passing through a through hole. The effect of Hall capacitance can be completely eliminated, noise generation and voltage drop can be prevented, and high speed operation is not hindered. FIG. 3 is a view showing an L chip in the mounting structure of the LSI chip of this embodiment.
4 is a graph showing a transmission waveform of an SI chip. As shown in FIG. 3, it can be seen that the transmission waveform of the LSI chip is flat and no noise occurs.

Further, according to the mounting structure of the LSI chip of this embodiment, the terminals 3 of the steps 2a to 2e and the signal layers 5b to 5b of the LSI chip 1 are not inserted through the through holes.
f, the connection pads 9 can be connected to each other, so that when the number of terminals is the same, the distance between the terminals can be reduced to reduce the size of the LSI chip. Can increase the number of terminals that can be provided on the terminal surface.

Next, another embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a schematic side view illustrating a mounting structure of an LSI chip on a laminated substrate according to another embodiment of the present invention, and FIG. 5 is a plan view of the laminated substrate illustrating an arrangement of connection portions.

The terminal surface 12 of the LSI chip 11 is formed stepwise from each of two parallel sides of the terminal surface 12 toward the center. In this embodiment, the LSI chip 11 has 6
It has a total of 60 terminals 13 in 10 columns. The steps of the terminal surface 12 are formed in three steps, and each step 12a, 12b,
Ten terminals 13 are arranged at equal intervals for each 12c.

The laminated substrate 15 on which the LSI chip 11 is mounted has six signal layers 15a to 15a as in the previous embodiment.
15f. Wirings (not shown) are formed in 15a to 15f, and an insulator 16 is formed between signal layers. The third signal layer 15c from the surface of the laminated substrate 15 is
A power supply dedicated layer for supplying power to the LSI chip 11. The mounting portion of the laminated substrate 15 on which the LSI chip 11 is mounted has an insulator 16 and signal layers 15a, 15b,
15c are sequentially cut in parallel to form a step shape.

The steps of the laminated substrate 15 correspond to the LSI chip 11
And three signal layers 15b and 15
The exposed portions 18a, 18b, 18c of c, 15d have L
A connection pad 19 is formed in accordance with the terminal 13 for each of the steps 12a, 12b, and 12c of the SI chip 11. Each connection pad 19 is connected to a wiring on each signal layer 15b, 15c, 15d.

In this embodiment, as in the previous embodiment, the formation of through holes is not required, so that generation of noise and voltage drop can be prevented, and speeding up is not hindered. That is, a flat transmission waveform similar to that shown in FIG. 3 can be obtained. When the number of terminals is the same, the distance between the terminals can be reduced to reduce the size of the LSI chip. When the size of the LSI chip is the same, the number of terminals that can be provided on the terminal surface is reduced. You can do more. Further, according to the mounting structure of this embodiment, the direction of extracting signals from the LSI chip 11 is limited to the left and right directions of the LSI chip 11, so that formation of wiring for extracting signals is more difficult than in the previous embodiment. Also has the advantage of being easier.

Although the preferred embodiment of the present invention has been described, the present invention is not limited to the above embodiment. For example, in the above embodiment, the LSI chip 1 having 100 terminals and the LSI chip 1 having 60 terminals
1 has been described as an example, but the present invention is also applicable to an LSI chip having less than 60 or more than 100 terminals 3 and 13. In this case, according to the number of terminals, the LSI
The number of steps formed on the end face of the chip may be increased or decreased. Further, the shape of the stairs formed on the terminal surface and the laminated substrate is symmetric in the above embodiment, but may be asymmetric in the left and right.

[0027]

According to the LSI chip mounting structure of the present invention, the following effects can be obtained. Since each terminal of the LSI chip can be connected to a wiring of a predetermined signal layer of the laminated substrate without passing through the through-hole, the influence of the through-hole capacitance can be eliminated to prevent the generation of noise and increase the speed of the LSI chip. Can be achieved.

Also, since no through hole is required,
Even if the number of terminals increases, the LSI chip can be easily mounted on the laminated substrate. Furthermore, when the number of terminals is the same, the distance between the terminals can be reduced to reduce the size of the LSI chip. When the size of the LSI chip is the same, the number of terminals that can be provided on the terminal surface is reduced. You can do more. In addition, power can be supplied without passing through the through-hole, so that inconveniences such as voltage drop and noise can be avoided.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention in which L is applied to a laminated substrate.
FIG. 2 is a schematic side view illustrating a mounting structure of an SI chip.

FIG. 2 is a plan view of a laminated substrate for explaining an arrangement of connection portions.

FIG. 3 is an explanatory diagram of the operation of this embodiment, and is a graph showing a transmission waveform of an LSI chip.

FIG. 4 is a schematic side view illustrating a mounting structure of an LSI chip on a laminated substrate according to another embodiment of the present invention.

FIG. 5 is a plan view of a laminated substrate illustrating an arrangement of connection portions according to another embodiment of the present invention.

FIG. 6 is a schematic view of a laminated substrate and an LSI chip for explaining a conventional example of a mounting structure of the LSI chip.

FIG. 7 is a plan view of a mounting surface of an LSI chip of the laminated substrate of FIG. 6;

FIG. 8 shows an LSI in a conventional LSI chip mounting structure.
4 is a graph showing a transmission waveform of a chip.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 LSI chip 2 Terminal surface 2a-2e Step part 3 Terminal 5 Laminated substrate 6 Insulator 8a-8e Exposed part 9 Connection pad 11 LSI chip 12 Terminal surface 12a-12c Step 13 Terminal 15 Laminated substrate 16 Insulator 18a-18c Exposed Part 19 Connection pad N Noise

Claims (6)

[Claims] An LSI is mounted on a laminated substrate having a plurality of signal layers.
An LSI chip mounting structure for mounting a chip, wherein an LSI chip in which a terminal surface is formed in a stepped shape and a terminal is provided for each stage, and an LSI chip mounting portion is mounted according to the terminal surface of the LSI chip A laminated substrate formed stepwise from the surface side, and a connection portion formed on an exposed surface of each signal layer exposed by being formed stepwise and connected to a terminal of the LSI chip; Inserting the LSI chip into the LSI chip mounting portion,
The connection structure and a terminal of the LSI chip are connected and mounted, the mounting structure of the LSI chip. 2. The plurality of signal layers, in which terminals of the LSI chip are brought into direct contact with the connection portions to connect the terminals and the connection portions, are laminated via an insulator having the same thickness. The mounting structure of an LSI chip on a laminated substrate according to claim 1, wherein: 3. The laminated substrate according to claim 1, wherein the terminal surface of the LSI chip is formed in a step shape from the entire periphery surrounding the terminal surface toward the center. LSI chip mounting structure. 4. The laminated substrate according to claim 1, wherein the terminal surface of the LSI chip is formed in a step shape from one or both of two opposing sides. LSI chip mounting structure. 5. The laminated substrate according to claim 1, wherein the laminated substrate includes a dedicated signal layer for supplying power to the LSI chip. LSI chip mounting structure. 6. The laminated substrate according to claim 1, wherein the terminal of the LSI chip or the connection portion of the laminated substrate is formed of a ball-shaped electrode. LSI chip mounting structure.