JP2003347502A - Semiconductor chip and stacked type semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a reliability and reduce a manufacturing cost by reducing damages due to an external bonding force and preventing the falling-off of through electrodes and the interfacial separation when stacking a plurality of semiconductor chips. <P>SOLUTION: The semiconductor chip comprises a main body 11 of the chip formed with a desired circuit, the through electrodes 16 embedded in a plurality of through holes 12 extended through the main body 11 of the chip, and external electrodes 17 and 18 formed on both end parts of each through electrode 16. In such a semiconductor chip, the plurality of through holes 12 are formed at a constant pitch α along the periphery of the main body 11 of the chip, with ends of each through hole 12 being shifted by an integer times (N≥1) as large as the pitch α on the front and rear faces of the main body 11 of the chip. In a stacked type semiconductor module wherein a plurality of such semiconductor chips 10 are stacked, part of the through electrodes 16 of one semiconductor chip are electrically connected to part of those of the adjacent semiconductor chips which are shifted by one pitch. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip having a through electrode penetrating the front and back surfaces of a chip body.
Further, the present invention relates to a three-dimensional stacked semiconductor module configured by stacking a plurality of the semiconductor chips.

[0002]

2. Description of the Related Art Conventionally, a semiconductor chip used for a stacked three-dimensional stacked semiconductor module is shown in a plan view in FIG. 5A and an AA 'view in FIG. It is configured as shown in a sectional view. Through holes 12 are provided on the four sides of the peripheral portion of the chip body 11 so as to be perpendicular to the main plane so as to connect the main planes on the front and back surfaces with the shortest distance, and through electrodes 16 are embedded in the respective through holes 12. Is formed. The external electrodes 17,
18 are provided. An insulating film 13 is formed on the inner surface of the through hole 12, and insulating films 14 and 15 are formed on the front and back surfaces of the chip body 11.

When a plurality of semiconductor chips 10 are stacked, as shown in FIG. 6A, the corresponding through electrodes of each chip are electrically connected to each other.
An electrode can be commonly used for the interposer substrate 30.

However, this type of device has the following problems. As shown in FIG. 7, when a plurality of chips 10 are vertically mounted using the bonding tool 50, damage is caused at an interface (wall surface) where the through electrode 16 and the chip body 11 are in contact with each other due to a bonding external force applied perpendicularly to the through electrode 16. In this case, the through electrode 16 itself may fall off or the interface may peel off.

On the other hand, when a plurality of the same chips are stacked in a memory module or the like, it is necessary to independently and electrically access pads of the individual chips from outside.

In the case of a conventional package device, for example, a Tape Carrier Package (T)
CP) When stacking multiple devices to make a module,
A proposal has been made to stack the same package device by means as shown in FIG. FIG. 8A is a perspective view, and FIG.
(B) is a sectional view.

As shown in FIG. 8B, TCP devices are stacked to form a module. At this time, a terminal 801 (for example, a select terminal, etc.) which needs to access each chip independently, a terminal 802 (for example, power supply, ground, address terminal, etc.) commonly accessed for each chip, Terminal 801
Are connected to the terminal 802 and 812 is connected to the terminal 802. 802a denotes a terminal of the substrate on which the module is mounted and corresponds to the terminal 802 that is commonly accessed for each chip, and 801c corresponds to the top chip of the terminal 801 that independently accesses each chip.
The one corresponding to the second chip from the top is denoted by 801b, and the one corresponding to the third chip from the top is denoted by 801a.

Terminal 8 for independently accessing each chip
01 on the tape carrier to be connected to the
a to 801c... have redundant connection parts,
Devices are common to all chips that make stacked modules. At the time of mounting, the redundant portion of 811 is cut away while leaving necessary parts, so that it is mounted as shown in FIG. As described above, TCP
When making a laminated module using a device, the device itself is common, and it is made separately at the time of mounting. By using a common device, the cost of producing a stacked module was kept low.

However, since the stacked module of the TCP device has wirings (811, 812) for forming a package, a signal delay occurs at this portion, and a crosstalk noise between the wirings occurs at this portion. This is a factor that causes problems in electrical characteristics. This situation is becoming increasingly apparent as devices operate at higher speeds.

[0010] Attempts have been made to make a stacked module by stacking in a chip state without packaging.
When making a laminated module by laminating in chip state,
It is not possible to use a technique that was created by implementation. FIG.
In the case where the one corresponding to 801a to 801c in (a) is realized by the chip wiring, it is necessary to previously form the wiring as shown in FIGS. 6 (b) to (d) on the chip.

Reference numerals 601d, 612d, and 623d denote terminals of each chip which need to be individually accessed. 601a
Is a through electrode for accessing the lowermost chip 601d. Reference numeral 602a denotes a through electrode provided on the lowermost chip for accessing 612d of the second chip from the bottom. Reference numeral 603a is a through electrode provided on the lowest chip for accessing the third chip 623d from the bottom. A through electrode 612a accesses the second chip 612d from the bottom. 613a is a through electrode provided on the second chip from the bottom to access 623d of the third chip from the bottom. 623a is a through electrode provided on the third chip from the bottom to access 623d of the third chip from the bottom.

Since these wirings and through-electrode arrangements cannot be shared by individual chips, it is necessary to create them separately for each chip, and it is necessary to create and stack each chip as a separate device. This greatly increases the cost of producing a laminated module, and when laminating and mounting,
This is a significant disadvantage because it forces the chips fabricated as separate devices to be stacked in the correct order.

One solution to this problem is USP6
In the case of 141245, as shown in FIG. 9, a chip is shifted and stacked. By stacking in this manner, individual chips can be independently accessed at the portions shifted by shifting, and a means for sharing the chips can be obtained. However, when the method as shown in FIG. 9 is used, the chips are stacked diagonally, which is not only difficult in the manufacturing process, but also vulnerable to an external impact, and chipping or cracking occurs at the end chip. The possibilities were great. Further, since the shifting direction is limited in this method, in the case of the peripheral arrangement as shown in FIG.
There is also a problem that only the side pad row can be applied.

[0014]

As described above, conventionally, when a stacked semiconductor module is formed by stacking a plurality of semiconductor chips each having a through electrode penetrating the front and back of the chip, a through-hole is formed by a bonding external force applied perpendicularly to the through electrode. There has been a problem that the interface between the electrode and the semiconductor chip is damaged, the through electrode itself falls off, or the interface peels off.

Further, in a stacked semiconductor module in which a plurality of the same chips are stacked, it is difficult to electrically independently access the pads of each chip from outside.
That is, to provide a chip-specific rewiring layer for each layer,
Significant demerits are given to the design or manufacture, resulting in an increase in the cost of the entire module, and further, an increase in the wiring length causes a signal delay. In addition, when the chips of each layer are stacked by being shifted by a multiple of the pad pitch, the mechanical strength is weak, and there is a problem that the chip at the end may be chipped or cracked by an external impact, and in the case of a peripheral arrangement 2
There is also a problem that only the side pad row can be applied.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to reduce damage due to an external bonding force when a plurality of layers are stacked, and to prevent the penetration electrode from falling off or the interface. An object of the present invention is to provide a semiconductor chip which can prevent peeling of the semiconductor chip and can improve reliability and reduce manufacturing cost.

Another object of the present invention is to provide a semiconductor device having a plurality of the above-described semiconductor chips stacked and arranged without providing a chip-specific rewiring layer in each layer or disposing the chips in a shifted manner. It is an object of the present invention to provide a stacked semiconductor module that enables electrical access to pads of individual chips independently, thereby improving reliability as a module and reducing manufacturing costs.

[0018]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, the present invention relates to a semiconductor chip having a chip body on which a desired circuit is formed, and through electrodes respectively embedded in a plurality of through holes penetrating the chip body. The hole is formed so as to be inclined with respect to a direction perpendicular to the main plane of the chip body.

Here, preferred embodiments of the present invention include the following.

(1) The through holes are provided at a constant pitch along the periphery of the chip body. (2) The through hole is formed at a position where the opening on the front side and the opening on the back side do not overlap with respect to projection in a direction perpendicular to the main plane of the chip body. (3) A plurality of through-holes are provided at a constant pitch α, and have a deviation of an integral multiple of the pitch α (N ≧ 1) on the front and back of the chip body.

(4) External electrodes electrically connected to the respective ends of the through electrodes are provided on the front and back surfaces of the chip body. (5) The through electrode must be electrically insulated from the chip body.

The present invention also provides a stacked semiconductor module comprising a plurality of stacked semiconductor chips having the above structure,
At least a part of the through-electrode is characterized in that adjacent semiconductor chips are electrically connected with their corresponding terminals shifted by an integral multiple of the pitch α (N ≧ 1).

Here, preferred embodiments of the present invention include the following.

(1) The through holes are formed on two sides along the X direction of the peripheral portion of the chip body and two sides along the Y direction orthogonal to the X direction, and all the through holes are inclined in the X direction. Formed,
On two sides along the X direction, the through electrodes are electrically connected to adjacent semiconductor chips with corresponding terminals shifted.

(1-1) For each semiconductor chip, the expected number of stacked layers × the through electrodes formed on two sides along the X direction
Electrodes for connection with internal circuits are provided with a pitch of N. (1-2) The through electrodes formed on two sides along the Y direction are used for exchanging signals only between the stacked chips. (1-3) The through electrodes formed on the two sides along the Y direction are connected to the bumps at the same position by rewiring on the chip surface or the chip back surface. (1-4) Signals to be individually applied to each chip are input to the through electrodes formed on two sides along the X direction. (1-5) The through electrodes formed on the two sides along the Y direction are to receive signals to be commonly applied to all chips. (1-6) The gap between the through electrodes in adjacent semiconductor chips is one pitch.

(2) The through holes are formed on two sides along the X direction of the peripheral portion of the chip body and two sides along the Y direction orthogonal to the X direction, and on two sides along the X direction in the X direction. The two sides along the Y direction are formed so as to be inclined in the Y direction, and in each side, the through electrodes are electrically connected to adjacent semiconductor chips with corresponding terminals being shifted from each other. .

(2-1) For each semiconductor chip, the expected number of laminations ×
Electrodes for connection with internal circuits are provided with a pitch of N. (2-2) At least one set of the through electrodes is to be supplied with a signal to be individually applied to each chip. (2-3) The gap between the through electrodes in adjacent semiconductor chips is one pitch.

(Function) According to the present invention, the through electrodes provided on the chip body are arranged at an angle to the chip surface. Increases resistance. Specifically, in a manufacturing process or a finished product, a vertical external force applied from the outside is directly prevented from being applied to a wall surface of a through electrode of each semiconductor chip, mechanical damage is significantly reduced by stress dispersion, and Connection reliability can be improved.

Further, since pads at the same position on the front and back of the semiconductor chip are not directly connected vertically but are electrically connected to each other with a pitch of one pitch between adjacent semiconductor chips, even if a plurality of the same chips are stacked, the semiconductor The individual terminals of the chip can be electrically accessed independently from the outside. In this case, it is not necessary to provide a chip-specific rewiring layer for each layer or to displace the chips in a displaced manner. This makes it possible to improve reliability and reduce manufacturing costs.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
(A) is a plan view, (b) is a cross-sectional view taken along the line AA 'of (a), and (c) is a view of (a) in FIG. The sectional view taken along the line BB 'is shown.

In the figure, reference numeral 11 denotes a chip body, and through holes 12 penetrating the front and back surfaces of the chip are provided at equal pitches on four sides of the periphery of the chip body 11. Here, two sides along the X direction are referred to as sides 1 and 3, and two sides along the Y direction are referred to as sides 2 and 4.

The through holes 12 are provided in the X direction with respect to the direction perpendicular to the main surface of the chip body 11, and are shifted in the X direction on the front and back sides of the chip body 11 by an amount corresponding to one pitch of the electrode arrangement. ing. That is, the opening on the front surface side and the opening on the rear surface side of the through hole 12 are shifted from the chip body 11 in the X direction by an amount corresponding to one pitch of the electrode arrangement. An insulating film 13 is formed inside the through hole 12, and insulating films 14 and 15 are also formed on the front and back surfaces of the chip body 11.
A metal electrode (through electrode) 16 is buried in the through hole 12 via an insulating film 13. These through electrodes 16 are electrically insulated from the chip body 11. The external electrodes 1 are provided at both ends of the through electrode 16.
7, 18 are formed respectively.

Next, a method of manufacturing a semiconductor chip according to the present embodiment will be described with reference to the cross-sectional views in FIGS.

First, as shown in FIG. 2A, Si is formed on the semiconductor wafer 19 after the formation of the circuit including the semiconductor chip.
An insulating film 14 of O ₂ or the like is formed, and the insulating film 14 is patterned by well-known lithography to form openings having a constant period.

Next, as shown in FIG. 2B, the oblique inclination angle from one side of the semiconductor wafer 19 with respect to the main plane by a wet or dry etching method using anisotropic etching or a processing method such as a laser method. A "hole penetrating vertically" or a "hole not penetrating at this stage" (finally becoming a penetrating electrode) 12 is formed. For example, by RIE having parallel plate electrodes, the wafer is arranged at an angle to the direction of application of the electric field, and the wafer
Is selectively etched to form an oblique hole 12.

Next, as shown in FIG.
A process of forming an insulating film 13 on the side wall of the substrate, a process of embedding a conductive material by a plating method or the like, and a metal wiring process by an etching method / sputtering method are performed. An electrode 16 is formed. Specifically, the inner surface of the hole 12 is formed by plasma CVD using S
After forming the insulating film 13 made of iO ₂ , T
A barrier layer (not shown) such as aN is formed. Further, a Cu layer serving as a seed layer is formed on the surface of the barrier layer by a plasma CVD method.
A film (not shown) is formed. Subsequently, a Cu film is buried in the hole 12 by performing electrolytic plating,
As a result, a through electrode 16 is formed.

Next, as shown in FIG. 2D, an external electrode 17 on the front side electrically connected to the through electrode 16 is formed using Cu, Al or the like. Subsequently, a reinforcing member 20 such as quartz glass for reinforcing the mechanical strength of the semiconductor wafer 19 is attached to the surface of the semiconductor wafer 19.

Next, as shown in FIG. 2E, a mechanical grinding method or a wet or dry etching method is used.
Grinding (or etching) the semiconductor wafer 19 from the back side
Then, the through electrodes 16 are exposed on the back surface.

Then, as shown in FIG. 2F, the semiconductor wafer 19 is subjected to a step of forming the insulating film 15 on the back side and a step of forming the external electrodes 18 on the back side by an etching method / sputtering method. The structure having the through electrode 16 connecting the external electrodes 17 and 18 is completed. Thereafter, as shown in FIG. 2G, the wafer is divided into individual chips 10 through a dicing process.

In this manufacturing process, the through electrode 1
The hole 12 for forming the hole 6 is formed by making the semiconductor wafer 19 thinner from the back surface, but it is needless to say that the hole 12 can be formed at the stage of FIG. FIG. 1A shows a case where pads are arranged in a row in the periphery. However, the present invention can be applied to a case where a plurality of rows of pads are present by adjusting the inclination angle of each through electrode. Needless to say.

As described above, in the present embodiment, the chip body 1
A through electrode 16 for electrically connecting the external electrodes 17 and 18 on the front and back surfaces of the chip body 1 is provided so as to penetrate obliquely with respect to the main plane (circuit surface) of the chip body 11. That is,
A pair of front and back external electrodes 17 and 18 connected to the through electrode 16
Are formed so that the “position on the main plane of the semiconductor chip” (coordinates) differs between the front and back sides. Therefore, a vertical external force applied from the outside during assembly is prevented from being directly applied to the interface between the through electrode 16 of each chip body 11 and the insulating film 13, and mechanical damage is greatly reduced due to stress distribution. Connection reliability can be improved.

The penetrating electrodes 11 do not necessarily need to be shifted by one pitch of the electrode arrangement in the X direction.
What is necessary is just to form so that the displacement of 1) may arise. The external electrodes on the side 1 and the external electrodes on the side 3 in FIG. 1 are connected by being shifted by N for each stage when stacked and mounted in the vertical direction by oblique through electrodes. This makes it possible to provide individual signals to the stacked chips as described later.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
1A is a plan view, and FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 1A. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, a plurality of semiconductor chips 10 of the first embodiment are stacked. On the interposer substrate 30, for example, four semiconductor chips 10 of FIG. 1 (chips A to D) are stacked. On sides 1 and 3 of each semiconductor chip 10 along the X direction, as shown in FIG. 3B, through electrodes are connected between adjacent chips with a shift of one pitch in the X direction. This makes it possible to provide individual signals to the stacked chips.

FIG. 3B illustrates a method of individually applying signals to the stacked chips. However, here, the case of N = 1 is shown. The leftmost electrodes of the four chips A, B, C, and D are referred to as a1, b1, c1, and d1, respectively. These electrodes a1, b1, c1, and d1 are electrodes located at the same position as a chip. Since the penetrating electrodes 16 are formed obliquely and connected to positions shifted by one pitch in one step, a
The signal from the interposer 20 can be given to one terminal, the signal from the interposer 20 can be given to the b1 terminal of the chip B, and so on, and the signals can be individually given to the four electrodes a1 to d1.

Here, in each chip 10, the external electrodes 17 on the sides 1 and 3 in the X direction are connected to the internal circuit every fourth, and the other electrodes are not connected to the internal circuit, Functions as wiring. This makes it possible for the four chips 10 having exactly the same configuration to independently access each electrode 17 connected to the internal circuit and corresponding to the same position.

The electrodes on the side 2 and the electrodes on the side 4 are electrodes that do not conduct up and down as they are. These electrodes can be used as terminals to be connected only between the stacked chips, but they are stacked by wiring so that electrodes at the same position are electrically connected by rewiring on the front surface or the back surface of the chip. It can be used as a signal terminal commonly applied to chips. Commonly applied signals include, for example, power, ground, and bus signals.

As described above, according to the present embodiment, FIG.
By stacking a plurality of semiconductor chips 10 as shown in FIG. 1, adjacent semiconductor chips can be electrically connected to each other by shifting the through electrodes 16 by one pitch in the X direction. For this reason, it is possible to independently and electrically access the individual terminals of the stacked semiconductor chips 10 from the outside. In this case, it is not necessary to provide a chip-specific rewiring layer for each layer or to displace the chips in a displaced manner. This makes it possible to improve reliability and reduce manufacturing costs.

In a conventional through electrode having a structure extending perpendicularly to the main plane, since the coordinates of the external electrodes in the main plane in space are the same on the front and back, such independent access is separately required.
This would not be possible without other measures such as providing wiring. This feature of the present embodiment is very important for electrically operating each chip in a module in which the same chips are stacked.

(Third Embodiment) FIG. 4 shows a third embodiment of the present invention.
1A is a plan view, and FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 1A. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor chip 40 used in this embodiment is
Similar to the semiconductor chip 10 shown in FIG. 1, through holes 12 are provided on four peripheral sides on the chip main surface, but the inclination direction of the through holes 12 is different from that of the semiconductor chip 10. That is, the through holes 12 of the semiconductor chip 40 used in the present embodiment are not all inclined in the X direction, but two sides along the X direction are provided inclined in the X direction, and the through holes 12 along the Y direction are provided. The two sides are provided to be inclined in the Y direction.

With such a configuration, as shown in FIG. 4 (b), the through electrodes 16 can be connected by shifting one pitch between adjacent chips in the Y direction as well as in the X direction. Therefore, the same effect as the second embodiment can be obtained.

The present invention is not limited to the above embodiments. The through holes (through electrodes) provided in the chip body are not necessarily provided in a single row along the periphery of the chip body, and may be provided in a plurality of rows.
Furthermore, it is not necessarily limited to only the peripheral part, but it is also possible to provide the part other than the peripheral part. Further, the through holes do not need to be shifted by the same amount as the electrode pitch, and may have a shift of an integral multiple of the electrode pitch α (N ≧ 1) on the front and back of the chip body.

Further, in the embodiment, the example of the four-layer lamination has been described, but it is needless to say that the present invention can be applied to the lamination of two, three, or five or more layers. Further, in the embodiment, wirings for connecting the external electrodes and the internal circuit are provided every four layers for laminating four layers. However, every two layers are provided for every three layers, and every three layers are provided for every three layers. , A connection wiring may be provided. That is,
In each of the semiconductor chips, wiring for connecting to the internal circuit may be provided at a pitch of the expected number of laminations × N for through electrodes arranged in parallel to the direction in which the through holes are inclined.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0058]

As described above in detail, according to the present invention, it is possible to reduce the damage due to the external bonding force when a plurality of layers are stacked, to prevent the penetration electrodes from dropping off and the interface to be separated. The reliability can be improved and the manufacturing cost can be reduced. Furthermore, by stacking a plurality of these semiconductor chips, the individual terminals of the semiconductor chips can be electrically accessed from the outside independently without providing a chip-specific rewiring layer in each layer or displacing the chips. It is possible to do.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view illustrating a schematic configuration of a semiconductor chip according to a first embodiment.

FIG. 2 is a sectional view showing a manufacturing step of the semiconductor chip of the first embodiment.

FIGS. 3A and 3B are a plan view and a cross-sectional view illustrating a schematic configuration of a stacked semiconductor module according to a second embodiment.

FIG. 4 is a plan view and a cross-sectional view illustrating a schematic configuration of a stacked semiconductor module according to a third embodiment.

FIG. 5 is a plan view and a cross-sectional view illustrating a schematic configuration of a conventional stacked semiconductor module.

FIG. 6 is a cross-sectional view and a perspective view showing a module configuration in which conventional semiconductor chips are stacked.

FIG. 7 is a cross-sectional view for explaining a problem when a plurality of chips are vertically mounted using a joining tool.

FIG. 8 is a perspective view and a cross-sectional view showing a module configuration in which TCPs are stacked.

9A and 9B are a plan view and a cross-sectional view illustrating a module configuration in which semiconductor chips are stacked while being shifted;

[Explanation of symbols]

10, 40 ... semiconductor chip 11 ... Chip body 12 ... Through-hole 13, 14, 15 ... insulating film 16 ... Through electrode 17, 18 ... external electrodes 19 ... Semiconductor wafer 20 ... Reinforcing member 30 ... interposer substrate 50 ... joining tool

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Tomomi Sato             22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka Prefecture             In the company

Claims (15)

[Claims] 1. A semiconductor chip comprising: a chip body on which a desired circuit is formed; and a plurality of through-electrodes embedded in a plurality of through-holes penetrating the chip body. A semiconductor chip formed to be inclined with respect to a direction perpendicular to a main plane of the chip body. 2. The semiconductor chip according to claim 1, wherein said through holes are provided at a constant pitch along a peripheral portion of said chip body. 3. The through hole according to claim 1, wherein the opening on the front side and the opening on the back side do not overlap with respect to projection in a direction perpendicular to the main plane of the chip body. Item 3. A semiconductor chip according to item 1 or 2. 4. The semiconductor device according to claim 3, wherein a plurality of the through holes are provided at a constant pitch α, and the front and back surfaces of the chip body have a shift of an integral multiple of the pitch α (N ≧ 1).
The semiconductor chip according to the above. 5. The semiconductor chip according to claim 1, wherein external electrodes electrically connected to respective ends of the through electrodes are provided on the front and back surfaces of the chip body. 6. A stacked semiconductor module comprising a plurality of stacked semiconductor chips according to claim 4 or 5, wherein at least a part of said through electrode is an integral multiple of a pitch α between adjacent semiconductor chips. A stacked semiconductor module, wherein the corresponding terminals are electrically connected by being shifted by N ≧ 1). 7. The through holes are formed on two sides along the X direction of the peripheral portion of the chip body and two sides along the Y direction orthogonal to the X direction, and all the through holes are inclined in the X direction. 7. The stacked semiconductor module according to claim 6, wherein the through electrodes are electrically connected on two sides along the X direction, with corresponding terminals shifted between adjacent semiconductor chips. . 8. A semiconductor device according to claim 2, wherein each of said semiconductor chips has
With respect to the through electrodes formed on the sides, the assumed number of lamination steps × N
8. The stacked semiconductor module according to claim 7, wherein electrodes for connection to an internal circuit are provided at a pitch of: 9. The stacked semiconductor module according to claim 7, wherein the through electrodes formed on two sides along the Y direction are used for exchanging signals only between the stacked chips. 10. A through electrode formed on two sides along the Y direction is formed by rewiring on the front surface or the rear surface of the chip.
The stacked semiconductor module according to claim 7, wherein the stacked semiconductor modules are connected to bumps at the same position. 11. The stacked semiconductor module according to claim 7, wherein the through electrodes formed on two sides along the X direction receive signals to be individually applied to each chip. . 12. The stacked semiconductor module according to claim 7, wherein the through electrodes formed on two sides along the Y direction receive signals to be commonly applied to all chips. . 13. The through hole is formed on two sides along the X direction around the periphery of the chip body and two sides along the Y direction orthogonal to the X direction, and on two sides along the X direction in the X direction. The two sides along the Y direction are formed so as to be inclined in the Y direction, and in each side, the through electrodes are electrically connected to adjacent semiconductor chips with corresponding terminals being shifted from each other. The stacked semiconductor module according to claim 6, wherein: 14. An electrode for connection to an internal circuit is provided for each of the semiconductor chips at a pitch of the expected number of laminations × N with respect to through electrodes arranged in parallel to the direction in which the through holes are inclined. 14. The stacked semiconductor module according to claim 13, wherein: 15. At least one set of the through electrodes includes:
14. The stacked semiconductor module according to claim 13, wherein a signal to be individually applied to each chip is input.