CN116686085A

CN116686085A - Chip packaging structure, manufacturing method thereof and electronic equipment

Info

Publication number: CN116686085A
Application number: CN202180088527.2A
Authority: CN
Inventors: 王士伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-24
Filing date: 2021-05-24
Publication date: 2023-09-01
Also published as: WO2022246603A1

Abstract

The application provides a chip packaging structure, a manufacturing method thereof and electronic equipment, wherein the chip packaging structure comprises: a substrate, a first die and a second die located over the substrate, and at least one interconnect bridge. The active faces of the first die and the second die face the substrate, and an interconnect bridge is bridged between the first die and the second die. The first bare chip is provided with a first silicon through hole, the second bare chip is provided with a second silicon through hole, the interconnection bridge is communicated with the wiring layer on the active surface of the first bare chip through the first silicon through hole, and the interconnection bridge is communicated with the wiring layer on the active surface of the second bare chip through the second silicon through hole. By arranging the first through silicon vias and the second through silicon vias, signals can be led to the passive surfaces of the first bare chip and the second bare chip and are interconnected by the interconnection bridge, and the interconnection bridge does not occupy the vertical channel resource of power supply, so that circuits in the overlapping area of the first bare chip and the second bare chip and the interconnection bridge can be vertically supplied, and the power supply reliability of the first bare chip and the second bare chip is improved.

Description

Chip packaging structure, manufacturing method thereof and electronic equipment

Technical Field

The present application relates to the field of chip technologies, and in particular, to a chip packaging structure, a manufacturing method thereof, and an electronic device.

Background

With the development of information technology, the generation of data presents an exponential growth, which is more demanding on data processing capabilities. In the big data age of the high-speed development of information technology, the high performance requirement of chips is increasing, how to increase the bandwidth density of chips is one of the research directions in the industry. The bandwidth density of a chip is understood to mean the amount of data transmitted per unit length and per unit time of the chip.

A multi-chip module (MCM) is a packaging technology that integrates a plurality of dies (die) on the same substrate. Compared with the traditional packaging technology, the multi-chip module technology can increase the packaging density of chips, and further, the bandwidth density of the chips can be increased. In the related art, the multi-chip module may perform chip interconnection in the following manner: (1) the die are interconnected by traces in the substrate; (2) the die are interconnected by an interposer; (3) The die are interconnected by fan-out packaging (FOP) technology; (4) High density traces are fabricated in an interconnection bridge (bridge) through which the dies are interconnected.

Fig. 1 is a schematic cross-sectional view of a chip package structure for interconnecting chips using an interconnection bridge, and as shown in fig. 1, two dies 11 are disposed on a substrate 10, and an active surface S1 of the die 11 faces the substrate 10. By fabricating high density traces in the interconnect bridge 12, high density interconnection of die may be achieved through the interconnect bridge 12. However, in order to electrically connect the interconnection bridge 12 to the die 11, the interconnection bridge 12 needs to be provided on the active surface S1 side of the die 11. Because of the shielding of the interconnection bridge 12, it is difficult for the circuit in the overlapping area (for example, the area indicated by the dashed box W in fig. 1) of the die 11 and the interconnection bridge 12 to obtain power supply directly from the substrate 10 through a vertical path, if the circuit in the overlapping area W needs to be powered, the power needs to be supplied by adopting a wire winding manner, and the voltage drop generated by the longer the power supply trace is larger, so that the power supply effect is worse. That is, due to the shielding of the interconnect bridge 12, the circuit power supply in the area W where the die 11 overlaps the interconnect bridge 12 is defective, and particularly for high power dies, there is a power supply reliability risk.

Disclosure of Invention

The application provides a chip packaging structure, a manufacturing method thereof and electronic equipment, which are used for improving the power supply reliability of a bare chip.

In a first aspect, the present application provides a chip package structure, including: a substrate, a first die and a second die located over the substrate, and at least one interconnect bridge. The active faces of the first die and the second die face the substrate, and an interconnect bridge is bridged between the first die and the second die. The first bare chip is provided with a first silicon through hole, the second bare chip is provided with a second silicon through hole, the interconnection bridge is communicated with the wiring layer on the active surface of the first bare chip through the first silicon through hole, and the interconnection bridge is communicated with the wiring layer on the active surface of the second bare chip through the second silicon through hole.

In the chip packaging structure provided by the embodiment of the application, the interconnection bridge is bridged between the first bare chip and the second bare chip, the first silicon through hole is arranged in the first bare chip, the second silicon through hole is arranged in the second bare chip, the interconnection bridge is communicated with the wiring layer on the active surface of the first bare chip through the first silicon through hole, and the interconnection bridge is communicated with the wiring layer on the active surface of the second bare chip through the second silicon through hole. In this way, the interconnect bridge achieves a high density interconnect between the first die and the second die by electrically connecting the first through-silicon via and the second through-silicon via. And the first through silicon vias and the second through silicon vias can lead signals to the passive surfaces of the first bare chip and the second bare chip, and the interconnection bridge is used for signal interconnection, the interconnection bridge does not shield the active surfaces of the first bare chip and the second bare chip, namely, the interconnection bridge does not occupy the vertical channel resource of power supply, so that the circuits in the overlapping area of the first bare chip and the second bare chip and the interconnection bridge can perform vertical power supply, and the power supply reliability of the first bare chip and the second bare chip is improved.

In the embodiment of the application, the active surfaces of the first bare chip and the second bare chip are arranged to face the substrate, so that the first bare chip and the second bare chip can be electrically connected with the signal wires in the substrate. A plurality of first solder balls may be disposed on active sides of the first and second die, and the first and second die may be electrically connected to the substrate through the first solder balls. Alternatively, a plurality of second solder balls may be disposed on a side of the substrate facing away from the first die, such that the chip package structure may be electrically connected to other components through the second solder balls, e.g., the chip package structure may be electrically connected to the printed circuit board through the second solder balls.

In one possible implementation manner, the interconnecting bridge may include: the interconnection bridge comprises a semiconductor substrate and a wiring layer, wherein the wiring layer in the interconnection bridge is positioned on one side of the semiconductor substrate close to the base plate. The wiring layer in the interconnection bridge is electrically connected with the first through silicon via and the second through silicon via. In this way, signal interconnection of the first die and the second die is achieved.

In one possible implementation manner, the wiring layer in the first die may include at least one first signal line, the wiring layer in the second die may include at least one second signal line, and the wiring layer in the interconnection bridge may include at least one connection line, one end of which is electrically connected to the first signal line, and the other end of which is electrically connected to the second signal line. In this way, signal interconnection between the two first dies and the second die is realized, and in practical application, the first dies can transmit corresponding signals to the second dies through connection lines in the interconnection bridge, and different connection lines can transmit different signals.

In a specific implementation, the wiring layer in the interconnection bridge may include at least two metal conductive layers that are stacked, and each metal conductive layer may be provided with a connection line, so that more connection lines may be provided in the interconnection bridge, and signals transmitted by different connection lines may be different, so that more signal interconnections between the first die and the second die may be implemented.

In one possible implementation, at least two first through-silicon vias are provided in the first die, and a pitch between two adjacent first through-silicon vias is in a range of 5 μm to 100 μm, for example, a pitch between two adjacent first through-silicon vias may be about 10 μm. At least two second through silicon vias are arranged in the second bare chip, and the distance between every two adjacent second through silicon vias is in the range of 5 μm to 100 μm, for example, the distance between every two adjacent second through silicon vias can be about 10 μm. I.e., the pitch between the through silicon vias is smaller, the density of the connecting lines connecting the first die (or the second die) can be made larger, and high-density interconnection between the first die and the second die can be realized. In particular, in order to facilitate electrical connection with the connection lines in the interconnection bridge, the first through-silicon vias in the first die may be arranged in a row, and the second through-silicon vias in the second die may be arranged in a row, which is not limited herein.

In one possible implementation, the first through-silicon-via is located at an edge of the first die, the second through-silicon-via is located at an edge of the second die, the first die is disposed adjacent to the second die, and the edge of the first die having the first through-silicon-via is disposed opposite to the edge of the second die having the second through-silicon-via, the interconnection bridge is bridged between the die and the second die, and the interconnection bridge is electrically connected with the first through-silicon-via and the second through-silicon-via. Thus, the area of the interconnecting bridge is smaller, the interconnecting bridge occupies smaller space of the first die and the second die, and the interconnecting bridge is prevented from affecting the functions of the first die and the second die.

In alternative embodiments, the overall chip package structure is reduced in size. Recesses may be provided in the semiconductor substrate of two adjacent first and second dies on opposite sides. And the recess in the first die and the recess in the adjacent second die constitute a recess, such that the interconnect bridge can be embedded in the recess. The recess in the semiconductor substrate creates an open opening in the passive side of the first die (or second die) such that the resultant recess has an outward opening to facilitate creation or placement of the interconnection bridge.

In other alternative embodiments, the recess in the semiconductor substrate may have only an opening toward the side of the semiconductor substrate, so that the recess is enclosed by the semiconductor substrate with the top, side and bottom surfaces of the recess being in close contact.

In one possible implementation, the recess has an opening on a side facing away from the substrate, and the surface of the interconnect bridge on the side facing away from the substrate is flush with the surfaces of the first die and the second die on the side facing away from the substrate. In this way, the interconnect bridge does not affect the overall thickness of the chip package structure, and the surface of the passive side of the first die and the second die can be made relatively flat.

In a possible implementation manner, the chip packaging structure provided by the embodiment of the present application may further include: and the plastic sealing layer is positioned on the substrate and wraps the first bare chip, the second bare chip and the interconnecting bridge. The plastic layer can protect and encapsulate the first bare chip, the second bare chip and the interconnection bridge, and prevent the first bare chip, the second bare chip and the interconnection bridge from being damaged.

In a second aspect, the present application also provides an electronic device, which may include: any one of the above chip package structures.

In a third aspect, the present application further provides a method for manufacturing the chip packaging structure, where the method may include:

providing a first die and a second die;

forming a first through silicon via in the first die and a second through silicon via in the second die;

binding the first die and the second die on the same substrate, and enabling the active surfaces of the first die and the second die to face the substrate;

the interconnection bridge is bridged between the first die and the second die, and is communicated with the wiring layer on the active surface of the first die through the first silicon through hole, and is communicated with the wiring layer on the active surface of the second die through the second silicon through hole.

In the method for manufacturing the chip packaging structure provided by the embodiment of the application, the first through-hole electrically connected with the wiring layer is formed in the first bare chip, the second through-hole electrically connected with the wiring layer is formed in the second bare chip, and after the first bare chip and the second bare chip are bound on the same substrate, the interconnection bridge can be lapped between the first bare chip and the second bare chip, so that the interconnection bridge is communicated with the wiring layer on the active surface of the first bare chip through the first through-hole, the interconnection bridge is communicated with the wiring layer on the active surface of the second bare chip through the second through-hole, high-density interconnection between the first bare chip and the second bare chip is realized, the interconnection bridge does not shield the active surfaces of the first bare chip and the second bare chip, namely the interconnection bridge does not occupy the vertical channel resource of power supply, and therefore, the circuits in the overlapping area of the first bare chip and the second bare chip and the interconnection bridge can be powered vertically, and the power supply reliability of the first bare chip and the second bare chip is improved.

In one possible implementation, the following method may be used to form the first through-silicon vias in the first die: etching the active surface of the first die, forming a blind hole or a through hole in the first die, filling a conductive material, such as a metal material, in the formed blind hole or through hole, and electrically connecting the filled conductive material with the first signal line in the wiring layer to form a first through silicon via electrically connected with the wiring layer, the first through silicon via penetrating at least part of the first die in the thickness direction. Then, the first die is turned over, the passive side of the first die is made to face upwards, the passive side of the first die is etched to form a recess at the edge of the first die, and the first through silicon via is exposed at the bottom of the recess. So that signals are directed to the passive side of the first die so that subsequent first through silicon vias can be electrically connected to the interconnect bridge and the interconnect bridge can be embedded within the first die by forming recesses at the edges of the first die to form spaces capable of receiving the interconnect bridge. The second die may be processed in a similar manner to form second through silicon vias and recesses in the second die.

In one possible implementation manner, the binding the first die and the second die to the same substrate may include: the first die and the second die are positioned adjacent to each other with the recess in the first die disposed opposite the recess in the second die to form a recess for receiving the interconnect bridge for subsequent placement of the interconnect bridge within the recess.

In one possible implementation, the interconnecting bridge may be fabricated as follows: a wiring layer, which may be a passive wafer, of a plurality of interconnect bridges is formed over a semiconductor substrate, which may include a metal conductive layer and an insulating layer. The semiconductor substrate is then diced to obtain a plurality of discrete interconnect bridges. Thus, a plurality of interconnection bridges can be manufactured through the same semiconductor substrate, and the manufacturing efficiency is high.

Drawings

FIG. 1 is a schematic cross-sectional view of a chip package structure employing an interconnect bridge for chip interconnection;

fig. 2 is a schematic cross-sectional structure of a chip package structure according to an embodiment of the present application;

fig. 3 is a schematic view of a partial planar structure of a chip package structure according to an embodiment of the present application;

FIG. 4a is a partially simplified schematic illustration of the structure of FIG. 2;

FIG. 4b is a simplified schematic diagram of a chip package structure according to an embodiment of the present application;

fig. 5 is a schematic cross-sectional view of a chip package structure according to an embodiment of the present application;

FIG. 6 is a flowchart of a method for fabricating a chip package structure according to an embodiment of the present application;

fig. 7 to 12 are schematic structural diagrams corresponding to each step in the manufacturing method according to the embodiment of the present application.

Reference numerals:

10-a substrate; 11 a-a first die; 11 b-a second die; 111-a semiconductor substrate of a first die or a second die; 112-a routing layer of the first die or the second die; 12-interconnecting bridges; 121-a semiconductor substrate of an interconnection bridge; 122-wiring layers of interconnect bridges; 131-a first through silicon via; 132-second through silicon vias; 14-first solder balls; 15-second solder balls; 16-plastic sealing layer; l1-a first signal line; l2-a second signal line; l3-connecting lines; u-shaped recess; t-groove.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings.

It should be noted that the same reference numerals in the drawings of the present application denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations of relative positional relationships and are not intended to represent true proportions.

The chip packaging structure provided by the embodiment of the application can be applied to various electronic devices, such as smart phones, smart televisions, smart television set-top boxes, personal computers (personal computer, PCs), wearable devices, smart broadband and other electronic devices. It should be noted that the chip package structure proposed by the embodiments of the present application is intended to include, but not be limited to, application in these and any other suitable types of electronic devices. The chip packaging structure, the manufacturing method and the electronic equipment provided by the application are described in detail below with reference to the accompanying drawings.

Fig. 2 is a schematic cross-sectional structure of a chip package structure according to an embodiment of the present application, where, as shown in fig. 2, the chip package structure according to an embodiment of the present application may include: a substrate 10, a first die 11a and a second die 11b located above the substrate 10, and at least one interconnect bridge 12. The active surfaces S1 of the first die 11a and the second die 11b face the substrate 10, and the interconnection bridge 12 is interposed between the first die 11a and the second die 11 b. The first die 11a is provided with a first through-silicon via 131, the second die 11b is provided with a second through-silicon via 132, the interconnection bridge 12 communicates with the wiring layer 112 on the active surface S1 of the first die 11a through the first through-silicon via 131, and the interconnection bridge 12 communicates with the wiring layer 112 on the active surface S1 of the second die 11b through the second through-silicon via 132.

The die (die), such as the first die 11a or the second die 11b in fig. 2, may be a die or a wafer, and is fabricated from a semiconductor material into an unpackaged integrated circuit body in which the intended functions of the integrated circuit are implemented. Alternatively, the die may include: the semiconductor device comprises a semiconductor substrate and a wiring layer positioned on one side of the semiconductor substrate, wherein semiconductor devices such as transistors are formed in the semiconductor substrate, various functional circuits can be arranged in the wiring layer, and the functional circuits in the wiring layer and the semiconductor devices in the semiconductor substrate can form a complete chip circuit structure. The side of the die (e.g., the first die 11a or the second die 11 b) having the wiring layer 112 is referred to as an active surface S1, and the side of the die having the semiconductor substrate 111 is referred to as a passive surface S2.

In the embodiment of the present application, the chip package structure may include a first die and a second die, and in the drawings of the present application, for more clearly illustrating a specific structure of the chip package structure, a first die and a second die are taken as examples for illustration, and not limited to the specific number of the first die and the second die, and in the specific implementation, the number of the first die and the second die in the chip package structure may be set according to actual needs. In addition, in the embodiment of the present application, the first die and the second die refer to two dies electrically connected to the interconnection bridge, and of course, the chip package structure may also include independently arranged dies, which may be arranged according to actual needs, and the application is not limited herein.

As shown in fig. 2, in the embodiment of the present application, the active surfaces S1 of the first die 11a and the second die 11b are disposed toward the substrate 10, so that the first die 11a and the second die 11b are electrically connected with the signal lines in the substrate 10. A plurality of first solder balls 14 may be disposed on the active surface S1 side of the first die 11a and the second die 11b, and the first die 11a and the second die 11b may be electrically connected to the substrate 10 through the first solder balls 14. Alternatively, a plurality of second solder balls 15 may be disposed on a side of the substrate 10 facing away from the first die 11a, so that the chip package structure may be electrically connected to other components through the second solder balls 15, for example, the chip package structure may be electrically connected to the printed circuit board through the second solder balls 15.

In an embodiment of the present application, the interconnection bridge 12 may be bridged between the adjacent first die 11a and the second die 11b to form a signal path between the two adjacent dies.

In other alternative embodiments, the interconnection bridge 12 may be implemented by other means, for example, the interconnection bridge 12 may be a rewiring layer (Redistribution Layer, RDL) that is lapped over the passive surfaces S2 of the adjacent first die 11a and second die 11 b. In terms of process implementation, after the adjacent first die 11a and second die 11b are molded into a molded body, a redistribution layer is formed on the back surface of the molded body, that is, on the side where the passive surfaces of the first die 11a and the second die 11b are located, and the first through silicon vias 131 (or the second through silicon vias 132) can be led out to the redistribution layer through connecting wires, so that the two adjacent dies are directly connected through the redistribution layer.

In alternative embodiments, the interconnect bridge 12 may be a die. As shown in fig. 2, the interconnecting bridge 12 may include: a semiconductor substrate 121 and a wiring layer 122, the wiring layer 122 in the interconnect bridge 12 being located on a side of the semiconductor substrate 121 close to the substrate 10. The wiring layer 122 in the interconnection bridge 12 is electrically connected to the first through-silicon via 131 and the second through-silicon via 132, and thus, signal interconnection of the first die 11a and the second die 11b is realized. Alternatively, the interconnect bridge 12 may be a passive device, i.e. only connecting lines are included in the interconnect bridge 12. In addition, the interconnection bridge 12 may be an active device, and since the interconnection bridge 12 has a semiconductor substrate, various semiconductor devices may be formed on the interconnection bridge 12 for satisfying various demands of signal interconnection. For example, field effect transistors may be included in the interconnect bridge 12 so that whether signals are transmitted or not may be controlled.

Fig. 3 is a schematic view of a partial planar structure of a chip package structure according to an embodiment of the present application, as shown in fig. 3, a dashed box in the drawing indicates a position of an interconnection bridge, a wiring layer in the first die 11a may include at least one first signal line L1, a wiring layer in the second die 11b may include at least one second signal line L2, the wiring layer in the interconnection bridge may include at least one connection line L3, one end of the connection line L3 is electrically connected to the first signal line L1, the other end is electrically connected to the second signal line L2, and one end of the connection line L3 is electrically connected to the first signal line L1 through a first through-silicon via 131 and the other end is electrically connected to the second signal line L2 through a second through-silicon via 132. In this way, signal interconnection between the first die 11a and the second die 11b is achieved, and in practical application, the first die 11a may transmit corresponding signals to the second die 11b through the connection lines L3 in the interconnection bridge, and different connection lines L3 may transmit different signals.

It should be noted that, in fig. 3, the chip package structure is illustrated by taking three first signal lines L1, three second signal lines L2, and three connecting lines L3 as examples, and the first signal lines L1, the second signal lines L2, and the connecting lines L3 are illustrated by taking straight lines as examples, and in a specific implementation, the number and shape of the first signal lines L1, the second signal lines L2, and the connecting lines L3 may be set according to actual needs, which is not limited herein. Since the first signal line L1 and the connection line L3 are located on different layers and the second signal line L2 and the connection line L3 are located on different layers, when the chip package structure is viewed in the direction of the first die toward the substrate, the patterns of the first signal line L1 and the second signal line L2 cannot be viewed, and thus the first signal line L1 and the second signal line L2 are indicated by broken lines in fig. 3.

With continued reference to fig. 3, in a specific implementation, the wiring layers in the interconnection bridge may include at least two metal conductive layers that are stacked, and each metal conductive layer may be provided with a connection line L3, so that more connection lines L3 may be provided in the interconnection bridge, and signals transmitted by different connection lines L3 may be different, so that more signal interconnections between the first die 11a and the second die 11b may be implemented.

In the embodiment of the present application, as shown in fig. 2 and 3, at least two first through-silicon vias 131 are disposed in the first die 11a, and a pitch between two adjacent first through-silicon vias 131 is in a range of 5 μm to 100 μm, for example, a pitch between two adjacent first through-silicon vias 131 may be about 10 μm. At least two second through-silicon vias 132 are provided in the second die 11b, and a pitch between two adjacent second through-silicon vias 132 is in a range of 5 μm to 100 μm, for example, a pitch between two adjacent second through-silicon vias 132 may be about 10 μm. In particular, in order to facilitate electrical connection with the connection line L3 in the interconnection bridge 12, the first through-silicon vias 131 in the first die 11a may be arranged in a row, and the second through-silicon vias 132 in the second die 11b may be arranged in a row, however, the first through-silicon vias 131 and the second through-silicon vias 132 may be arranged in other manners, which are not limited herein.

In the manufacturing process, the connecting line L3 in the interconnecting bridge 12 may be manufactured by a semiconductor manufacturing process, and the line width of the connecting line L3 is smaller, and generally the line width of the connecting line L3 is smaller than the apertures of the first through silicon via 131 and the second through silicon via 132. The first through-silicon vias 131, the second through-silicon vias 132 are electrically connected with the connection lines L3 in the interconnection bridge 12, and therefore, the interconnection density between the first die 11a and the second die 11b depends on the densities of the first through-silicon vias 131 and the second through-silicon vias 132, that is, the smaller the aperture of the first through-silicon vias 131 and the second through-silicon vias 132, the higher the density, the greater the number of connection lines L3 that the first die 11a and the second die 11b can connect, and the greater the interconnection density between the first die 11a and the second die 11 b. In the embodiment of the present application, the pitch between two adjacent first through-silicon vias 131 (or second through-silicon vias 132) is in the range of 5 μm to 100 μm, that is, the pitch between the first through-silicon vias 131 (or second through-silicon vias 132) is smaller, so that the density of the connection lines L3 is larger, and high-density interconnection between the first die 11a and the second die 11b can be realized.

In some embodiments of the present application, as shown in fig. 2, a first through-silicon via 131 is located at an edge of a first die 11a, a second through-silicon via 132 is located at an edge of a second die 11b, the first die 11a is disposed adjacent to the second die 11b, and the edge of the first die 11a having the first through-silicon via 131 is disposed opposite to the edge of the second die 11b having the second through-silicon via 132, an interconnection bridge 12 is bridged between the adjacent first die 11a and second die 11b, and the interconnection bridge 12 is electrically connected to the first through-silicon via 131 and the second through-silicon via 132. Thus, the area of the interconnection bridge 12 is small, the space occupied by the interconnection bridge 12 by the first die 11a and the second die 11b is small, and the interconnection bridge 12 is prevented from affecting the functions of the first die 11a and the second die 11 b.

In alternative embodiments, the overall chip package structure is reduced in size. As shown in fig. 2 and 4a, recesses U may be provided at opposite sides of the semiconductor substrate 111 of two adjacent first and second dies 11a and 11 b. And the recess U in the first die 11a and the recess U in the adjacent second die 11b constitute a recess T, so that the interconnect bridge 12 can be embedded in said recess T. In fig. 2 and 4a, the recess U in the semiconductor substrate 111 described above creates an open opening on the passive side S2 of the first die 11a (or the second die 11 b) such that the resultant recess T has an outward opening for the creation or placement of the interconnect bridge 12.

In other alternative embodiments, as shown in fig. 4b, the recess U in the semiconductor substrate 111 may also have only an opening towards the side of the semiconductor substrate 111, so that the recess T is surrounded by the semiconductor substrate on top, on the sides and on the bottom.

The first die 11a is further provided with a first through-silicon via 131, and the second die 11b is further provided with a second through-silicon via 132. The first through-silicon via 131 (or the second through-silicon via 132) penetrates the semiconductor substrate 111, communicating the recess T and the wiring layer 112. The first through silicon vias 131 and the second through silicon vias 132 have signal lines therein, so that when the interconnection bridge 12 is accommodated in the groove T, the signal lines on the interconnection bridge 12 can be electrically connected to the wiring layers 112 of the first die 11a and the second die 11b through the first through silicon vias 131 and the second through silicon vias 132, respectively. For example, when the interconnect bridge 12 is a die, the semiconductor layer 122 of the interconnect bridge 12 is in contact with the bottom surface of the recess T, thereby communicating with the wiring layer 112 through the first through-silicon via 131 and the second through-silicon via 132.

Optionally, with continued reference to fig. 2 and 4a, the recess T has an opening on the side facing away from the substrate 10, and the surface of the side of the interconnection bridge 12 facing away from the substrate 10 is flush with the surfaces of the first die 11a and the second die 11b facing away from the substrate 10. In this way, the interconnection bridge 12 does not affect the total thickness of the chip package structure, and the surface of the first die 11a and the second die 11b on the passive surface S2 side can be made flat. It should be noted that the surface of the interconnection bridge 12 on the side facing away from the substrate 10 is flush with the surfaces of the first die 11a and the second die 11b on the side facing away from the substrate 10, which means that: the interconnect bridge 12 is spaced apart from the surface of the first die 11a and the second die 11b facing away from the substrate 10 by a distance that is within a certain range, i.e. approximately level with the two planes within a certain tolerance.

Fig. 5 is a schematic diagram of another cross-sectional structure of a chip package structure according to an embodiment of the present application, where, as shown in fig. 5, the chip package structure according to an embodiment of the present application may further include: a Molding layer (Molding) 16 located above the substrate 10, where the Molding layer 16 encapsulates the first die 11a, the second die 11b, and the interconnection bridge 12, and the Molding layer 16 can protect and encapsulate the first die 11a, the second die 11b, and the interconnection bridge 12, so as to prevent the first die 11a, the second die 11b, and the interconnection bridge 12 from being damaged. Alternatively, the plastic layer 16 may be made of a material such as a resin, however, the plastic layer 16 may be made of other materials, which is not limited herein.

Based on the same technical concept, the embodiment of the application also provides electronic equipment, which can comprise: any one of the above chip package structures. In the embodiment of the application, the interconnection density between the bare chips in the chip packaging structure is higher, and the interconnection bridge does not occupy the vertical channel resource of power supply, so that the circuit in the overlapping area of the bare chips and the interconnection bridge can perform vertical power supply, the power supply reliability of the bare chips is higher, and the performance of the electronic equipment is better.

Based on the same technical concept, the embodiment of the present application further provides a method for manufacturing the chip package structure, and fig. 6 is a flowchart of a method for manufacturing the chip package structure provided by the embodiment of the present application, as shown in fig. 6, where the method may include:

s201, providing a first bare chip and a second bare chip;

s202, forming a first through silicon via in a first bare chip and forming a second through silicon via in a second bare chip;

s203, binding the first bare chip and the second bare chip on the same substrate, and enabling the active surfaces of the first bare chip and the second bare chip to face the substrate;

s204, the interconnection bridge is bridged between the first die and the second die, and is communicated with the wiring layer on the active surface of the first die through the first silicon through hole, and is communicated with the wiring layer on the active surface of the second die through the second silicon through hole.

In the above step S201, in order to improve the manufacturing efficiency, wiring layers in the first die and the second die, which may include a metal conductive layer and an insulating layer, may be formed over the same semiconductor substrate. The semiconductor substrate is then diced to obtain a first die and a second die, and the resulting first die or second die may have a structure as shown in fig. 7, and specifically, the first die 11a (or the second die 11 b) may include: a semiconductor substrate 111, and a wiring layer 112 located on one side of the semiconductor substrate 111, the wiring layer 112 being located on one side of the active surface S1 of the first die 11a (or the second die 11 b).

Fig. 8 is a schematic illustration of forming a first through silicon via in a first die, and fig. 9 is a schematic illustration of forming a recess at an edge of the first die. In the above step S202, the first through-silicon-via may be formed in the first die by the following method: referring to fig. 8, the active surface S1 of the first die 11a is etched, a blind via or a through hole is formed in the first die 11a, a conductive material, such as a metal material, is filled in the formed blind via or through hole, and the filled conductive material is electrically connected with the first signal line in the wiring layer 112 to form a first through silicon via 131 electrically connected with the wiring layer 112, the first through silicon via 131 penetrating at least part of the first die 11a in the thickness direction. Then, referring to fig. 9, the first die 11a is flipped over, the inactive face S2 of the first die 11a is turned up, the inactive face S2 of the first die 11a is etched to form a recess U at the edge of the first die 11a, and the first through-silicon via 131 is exposed at the bottom of the recess U, so that a signal is led to the inactive face S2 side of the first die 11a so that the subsequent first through-silicon via 131 can be electrically connected with the interconnection bridge, and the interconnection bridge can be embedded into the first die 11a by forming the recess U at the edge of the first die 11a to form a space capable of accommodating the interconnection bridge.

Fig. 10 is a schematic view of a structure in which a recess is formed at an edge of the second die, and referring to fig. 10, the second die 11b is processed by a similar process method to form a second through silicon via 132 and a recess U in the second die 11 b. In actual processing, the dies need to be processed according to the signal interconnection requirements between the dies, as well as the locations of the signal lines in the dies. For example, the first die 11a shown in fig. 9 needs to be electrically connected to the interconnect bridge on the right side, so that the first through-silicon via 131 and the recess U need to be formed on the right side edge of the first die 11a. The second die 11b shown in fig. 10 needs to be electrically connected to the interconnect bridge on the left side, so the second through-silicon via 132 and the recess U need to be formed on the left side edge of the second die 11 b.

After the above step S202, a plurality of first solder balls may be formed on the active surface side of the first die and the second die so as to be subsequently bonded on the substrate. Fig. 11 is a schematic diagram of binding the first die and the second die on the same substrate, and as shown in fig. 11, the step S203 may include: the first die 11a and the second die 11b are placed adjacent to each other with the recess U in the first die 11a being disposed opposite to the recess U in the second die 11b to form a recess T for accommodating the interconnection bridge so that the interconnection bridge is subsequently disposed within the recess. Alternatively, the first die 11a and the second die 11b to be connected with the interconnection bridge may have a certain pitch therebetween, as long as the groove T is formed to be able to accommodate the interconnection bridge.

In the process, the semiconductor substrate may be used to make the interconnection bridge, fig. 12 is a schematic diagram of making the interconnection bridge, and as shown in fig. 12, the interconnection bridge may be made according to the following method: a plurality of interconnection bridge wiring layers 122 are formed over a semiconductor substrate 121, which may be a passive wafer, and the wiring layers 122 may include a metal conductive layer and an insulating layer. The semiconductor substrate 121 is then diced, for example, as may be done in accordance with the dashed lines in fig. 12, resulting in a plurality of discrete interconnect bridges 12. Thus, a plurality of interconnection bridges 12 can be formed on the same semiconductor substrate, and the manufacturing efficiency is high.

In the above step S204, referring to fig. 2, the interconnection bridge 12 is mounted between the first die 11a and the second die 11b with the wiring layer 122 in the interconnection bridge 12 facing the substrate 10, one end of the connection line in the wiring layer 112 is electrically connected to the first through-silicon via 131 in the first die 11a, the other end is electrically connected to the second through-silicon via 132 in the second die 11b, and the interconnection bridge 12 is embedded in the groove T formed by the adjacent first die 11a and second die 11 b. Optionally, in the actual process, a solder paste may be coated on the surfaces of the first through-silicon vias 131 and the second through-silicon vias 132, or a solder paste may be coated on the surface of the wiring layer 122 of the interconnection bridge 12, and the interconnection bridge 12 is placed in the groove T formed by the adjacent first die 11a and second die 11b, so that the wiring layer 122 is electrically connected with the first through-silicon vias 131 and the second through-silicon vias 132 through the solder paste, and then the wiring layer 122 is bonded with the first through-silicon vias 131 and the second through-silicon vias 132 respectively by heating.

Referring to fig. 5, after step S204, a molding layer 16 may be formed on the substrate 10, such that the molding layer 16 wraps the first die 11a, the second die 11b and the interconnection bridge 12, and the molding layer 16 may protect and encapsulate the first die 11a, the second die 11b and the interconnection bridge 12, so as to prevent the first die 11a, the second die 11b and the interconnection bridge 12 from being damaged. Alternatively, the plastic layer 16 may be made of a material such as a resin, however, the plastic layer 16 may be made of other materials, which is not limited herein.

Further, with continued reference to fig. 5, after step S204, a plurality of second solder balls 15 may also be formed on a side of the substrate 10 facing away from the first die 11a. In this way, the chip package structure may be electrically connected to other components through the second solder balls 15, for example, the chip package structure may be electrically connected to the printed circuit board through the second solder balls 15.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit or scope of the embodiments of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is also intended to include such modifications and variations.

Claims

A chip package structure, comprising: a substrate, a first die and a second die located over the substrate, and at least one interconnect bridge;

the active faces of the first die and the second die face the substrate;

the interconnect bridge is bridged between the first die and the second die,

a first through silicon via is arranged in the first bare chip, and a second through silicon via is arranged in the second bare chip;

the interconnect bridge communicates with a routing layer on the active side of the first die through the first through-silicon via, and the interconnect bridge communicates with a routing layer on the active side of the second die through the second through-silicon via.
The chip package structure of claim 1, wherein the first through silicon via is located at an edge of the first die and the second through silicon via is located at an edge of the second die;

the first die is arranged adjacent to the second die, and the edge of the first die with the first through silicon vias is arranged opposite to the edge of the second die with the second through silicon vias;

the interconnect bridge is bridged between the adjacent first die and the second die.
The chip package structure of claim 2, wherein the semiconductor substrates of the adjacent first die and second die are each provided with recesses on opposite sides, and the recesses in the first die and the recesses in the adjacent second die form grooves;

the interconnection bridge is embedded in the groove.
The chip package structure of claim 3, wherein the recess has an opening on a side facing away from the substrate, and a surface of the interconnect bridge on the side facing away from the substrate is flush with surfaces of the first die and the second die on the side facing away from the substrate.
The chip packaging structure according to claim 1, wherein at least two first through silicon vias are arranged in the first bare chip, and a distance between two adjacent first through silicon vias is in a range of 5 μm to 100 μm;

at least two second through silicon vias are arranged in the second bare chip, and the distance between every two adjacent second through silicon vias is in the range of 5-100 mu m.
The chip package structure of any one of claims 1 to 5, wherein the interconnection bridge comprises: a semiconductor substrate and a wiring layer;

the wiring layer in the interconnection bridge is located on one side of the semiconductor substrate of the interconnection bridge, which is close to the base plate, and the wiring layer in the interconnection bridge is electrically connected with the first through silicon vias and the second through silicon vias.
The chip package structure of claim 6, wherein the routing layer in the first die comprises at least one first signal line, the routing layer in the second die comprises at least one second signal line, and the routing layer in the interconnect bridge comprises at least one connection line;

one end of the connecting wire is electrically connected with the first signal wire, and the other end of the connecting wire is electrically connected with the second signal wire.
The chip package structure according to any one of claims 1 to 7, further comprising: a plastic sealing layer over the substrate;

the plastic layer encapsulates the first die, the second die, and the interconnect bridge.
An electronic device, comprising: the chip package structure according to any one of claims 1 to 8.
A method of manufacturing the chip package structure according to any one of claims 1 to 8, comprising:

providing a first die and a second die;

forming a first through silicon via in the first die and a second through silicon via in the second die;

binding the first die and the second die on the same substrate with active faces of the first die and the second die facing the substrate;

and bridging an interconnection bridge between the first die and the second die, and enabling the interconnection bridge to be communicated with a wiring layer on the active surface of the first die through the first through silicon holes, and enabling the interconnection bridge to be communicated with a wiring layer on the active surface of the second die through the second through silicon holes.
The method of manufacturing of claim 10, wherein the forming a first through silicon via in the first die comprises:

etching the active surface of the first bare chip to form a first through silicon via electrically connected with the wiring layer of the first bare chip; the first through silicon via penetrates at least part of the first bare chip in the thickness direction;

etching the passive surface of the first bare chip to form a recess at the edge of the first bare chip and exposing the first through silicon via at the bottom of the recess;

the forming a second through silicon via in the second die, comprising:

etching the active surface of the second bare chip to form a second through silicon via electrically connected with the wiring layer of the second bare chip; the second through silicon vias penetrate through at least part of the second bare chip in the thickness direction;

and etching the passive surface of the second bare chip to form a recess at the edge of the second bare chip and expose the second through silicon via at the bottom of the recess.
The method of manufacturing of claim 11, wherein the bonding the first die and the second die to the same substrate comprises:

the first die and the second die are placed in adjacent positions with the recess in the first die disposed opposite the recess in the second die to form a recess for receiving the interconnect bridge.
A method of manufacturing as claimed in any one of claims 10 to 12, wherein the interconnect bridge is manufactured as follows:

forming a wiring layer of a plurality of the interconnection bridges over a semiconductor substrate;

and cutting the semiconductor substrate to obtain a plurality of discrete interconnection bridges.