KR100842922B1 - Semiconductor package - Google Patents

Abstract

A semiconductor package is provided to improve integration degree of data and data processing speed by connecting pads with bonding pads. A substrate includes first and second chip regions(FR,SR). A first connective pads(120) are arranged in the first chip region. A second connective pads(130) are arranged in the second chip region. One or more circuit patterns(140) are formed to connect the first connective pads to the second connective pads. A plurality of ball pads(150) are arranged on the bottom surface of the substrate to be connected to the ball lands. A semiconductor chip module(200) includes a first semiconductor chip(210) having first bonding pads(212,214,216,218) and a second semiconductor chip having second bonding pads(232,234,236,238,239). A conductive wire is formed to connect the first bonding pads to the first connective pads and to connect the second bonding pads to the second connective pads.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor package.

Recently, semiconductor packages including semiconductor devices for storing massive data and processing data stored in a short time have been developed.

In general, a semiconductor package is a semiconductor chip manufacturing process for forming a semiconductor chip by integrating devices such as transistors, resistors, capacitors, and the like on a wafer, and a semiconductor chip having a weak electrical connection and brittleness with an external circuit board by individualizing the semiconductor chip from the wafer. It is manufactured by a package process that protects it from externally applied shocks and / or vibrations.

In particular, recently, wafer level packages having only about 100% to about 105% of the size of semiconductor chips have been developed.

Recently, while the size of the semiconductor package is gradually decreasing, the semiconductor package is required to store more data and process more data.

In particular, recently developed semiconductor packages require a large number of input / output terminals to store more data and / or process more data, but as the size of the semiconductor package decreases, It is difficult to secure an area for forming output terminals.

In addition, as the size of the semiconductor chip has been reduced with the recent development of the semiconductor chip manufacturing process, the semiconductor chip and the semiconductor chip having a semiconductor chip smaller than the specifications of the semiconductor package prescribed by the Joint Electron Device Engineering Council (JEDEC), etc. Although a package is being developed, when the size of the semiconductor chip and the semiconductor package is smaller than the size prescribed by JEDEC, it is difficult to apply the semiconductor package to electronic devices.

The present invention provides a semiconductor package suitable for satisfying a package specification size by securing a sufficient area to form the input / output terminals required by individualizing at least two semiconductor chips and forming a redistribution pattern on the individualized semiconductor chips. .

A semiconductor package according to the present invention includes a substrate body having a first chip region and a second chip region, first connection pads disposed in the first chip region, second connection pads disposed in the second chip region, and Circuit patterns formed on a substrate body and electrically connecting the first connection pads and the respective second connection pads corresponding to the first connection pads, and disposed on a bottom surface of the substrate body, A substrate including electrically connected ball lands, a first semiconductor chip disposed in the first chip region and having first bonding pads, and a second semiconductor chip disposed in the second chip region and having second bonding pads. And a semiconductor chip module, and conductive wires electrically connecting the first bonding pads to the first connection pads, the second bonding pads, and the second connection pads.

The semiconductor package has a shape in which the first connection pads and the second connection pads are symmetrical with respect to the boundary of the first and second chip regions.

The circuit patterns of the semiconductor package may include a first circuit pattern electrically connected to the first and second connection pads, a second circuit pattern formed on a different layer from the first circuit pattern, and electrically connected to the respective ball lands; And a third circuit pattern formed on a layer different from the first and second circuit patterns and electrically connecting the first and second circuit patterns.

The ball lands of the semiconductor package are regularly arranged.

The first and second semiconductor chips of the semiconductor package are integrally formed.

The first and second semiconductor chips of the semiconductor package are separated.

The first and second bonding pads of the semiconductor package are disposed at the edges of the first and second semiconductor chips.

A semiconductor package according to the present invention includes a substrate body including a first chip region, a second chip region, and an opening for opening the first and second chip regions, and a first substrate disposed around the opening corresponding to the first chip region. First connection pads, second connection pads disposed around the opening corresponding to the second chip region, each of the first connection pads and the respective first connection pads formed in the substrate body. Circuit patterns electrically connecting two connection pads, a substrate including ball lands disposed on a bottom surface of the substrate body and electrically connected to the respective circuit patterns, and disposed in the first chip area and exposed by the openings. A semiconductor chip module including a first semiconductor chip having first bonding pads and a second semiconductor chip disposed in the second chip region and having second bonding pads; The first bonding pads and the respective first connection pad and a conductive wire for electrically connecting the respective second connection pad and each of the second bonding pads.

The first connection pads and the second connection pads of the semiconductor package may have symmetrical shapes with respect to the boundary of the first and second chip regions.

The circuit patterns of the semiconductor package may include a first circuit pattern electrically connected to the first and second connection pads, a second circuit pattern formed on a different layer from the first circuit pattern, and electrically connected to the respective ball lands; And a third circuit pattern formed on a layer different from the first and second circuit patterns and electrically connecting the first and second circuit patterns.

The ball lands of the semiconductor package are regularly arranged.

The first and second semiconductor chips of the semiconductor package are integrally formed.

The first and second semiconductor chips of the semiconductor package are separated.

The first and second bonding pads of the semiconductor package are disposed at the centers of the first and second semiconductor chips.

For example, the pitch of the ball land defined by the JEDEC, at least two semiconductor chips having a size smaller than the size sufficient to arrange the ball land integrally formed or adjacent to the semiconductor chip module suitable for the JEDEC standard The pads are formed and the pads and the bonding pads of the semiconductor chip are connected using conductive wires to improve data integration and data processing speed of the semiconductor chip as well as satisfy the JEDEC standard.

Hereinafter, a semiconductor package according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate The present invention may be embodied in various other forms without departing from the spirit of the invention.

1 is a plan view showing a semiconductor package according to a first embodiment of the present invention.

Referring to FIG. 1, the semiconductor package 400 includes a substrate 100, a semiconductor chip module 200, and a conductive wire 300.

FIG. 2 is a plan view illustrating a rear surface of a substrate of the semiconductor package illustrated in FIG. 1.

1 and 2, the substrate 100 may include a substrate body 110, first connection pads 120, second connection pads 130, circuit patterns 140, and ball lands 150. Include them.

The substrate body 110 has a plate shape, for example. The substrate body 110 having a plate shape may be, for example, a multilayer printed circuit board.

The substrate body 110 having a plate shape has a first chip region FR and a second chip region SR. In the present embodiment, the first chip region FR and the second chip region SR are disposed adjacent to each other.

The first connection pads 120 are disposed at both sides of the first chip region FR of the substrate body 110. The plurality of first connection pads 120 are disposed along the Y axis direction of the substrate body 110, for example.

For example, eight first connection pads 120 are formed. Four first connection pads 120 are disposed on both sides of the first chip region FR. Alternatively, the first connection pads 120 may be disposed on one side of the first chip region FR.

Hereinafter, each of the first connection pads 120 disposed on both sides of the first chip region FR may include a first sub connection pad 122, a second sub connection pad 124, and a third sub connection pad 126. And the fourth sub connection pad 128. The first to fourth sub connection pads 122, 124, 126, and 128 are sequentially disposed along the Y axis direction of FIG. 1. Although it is shown and described that only eight first connection pads 120 are formed in this embodiment, the first connection pads 120 may be configured to have at least nine or more.

The second connection pads 130 are disposed on both sides of the second chip region SR of the substrate body 110. The plurality of second connection pads 130 may be disposed along the Y axis direction of the substrate body 110, for example.

For example, eight second connection pads 130 may be provided. Four second connection pads 130 are disposed on both sides of the second chip region SR. Alternatively, the first connection pads 120 may be disposed on one side of the second chip region SR.

Hereinafter, each of the second connection pads 130 disposed on both sides of the second chip region SR may include the fifth sub connection pad 132, the sixth sub connection pad 134, and the seventh sub connection pad 136. And the eighth sub connection pad 138. The fifth to eighth sub connection pads 132, 134, 136, and 138 are sequentially disposed along the Y axis direction of FIG. 1. Although it is shown and described that only eight second connection pads 130 are included in the present embodiment, the second connection pads 130 may be configured to have at least nine.

In the present exemplary embodiment, the first connection pads 120 and the second connection pads 130 are formed in a symmetrical shape with respect to the boundary of the first chip region FR and the second chip region SR.

The circuit patterns 140 are formed on the substrate body 110, and the circuit patterns 140 electrically connect the first connection pads 120 and the second connection pads 130 corresponding to the first connection pads 120. Connect.

For example, the circuit pattern 140 electrically connects the first sub connection pad 122 of the first connection pad 120 and the fifth sub connection pad 132 of the second connection pad 130.

In addition, the circuit pattern 140 electrically connects the second sub connection pad 124 of the first connection pad 120 and the sixth sub connection pad 134 of the second connection pad 130.

In addition, the circuit pattern 140 electrically connects the third sub-connection pad 126 of the first connection pad 120 and the seventh sub-connection pad 136 of the second connection pad 130.

In addition, the circuit pattern 140 electrically connects the fourth sub connection pad 128 of the first connection pad 120 and the eighth sub connection pad 138 of the second connection pad 130.

As such, to electrically connect the first to fourth sub connection pads 122, 124, 126 and 128 of the first connection pad 120 and the fifth to eighth sub connection pads 132, 134, 136 and 138 of the second connection pad 130. The circuit patterns 140 may be formed in one layer. Alternatively, the circuit patterns 140 may be formed on two insulating layers, respectively. Alternatively, the circuit patterns 140 may be formed on three insulating layers, respectively.

In this embodiment, the circuit patterns 140 are each formed in three insulating layers, for example. In the present embodiment, the circuit patterns 140 include the first circuit pattern 142, the second circuit pattern 144, and the third circuit pattern 146 disposed on different insulating layers.

The first circuit patterns 142 are connected to the first to eighth sub connection pads 122, 124, 126, 128, 132, 134, 136, and 138, respectively.

The third circuit patterns 146 are electrically connected to each ball land 150 to be described later.

The second circuit patterns 144 electrically connect each first circuit pattern 142 and each second circuit pattern 144. The second circuit patterns 144 are particularly disposed at portions where the first circuit patterns 142 cross each other. The first circuit pattern 142 and the second circuit pattern 144 are electrically connected through, for example, conductive vias 148.

The ball lands 150 are disposed on the surface of the substrate body 110, and the ball lands 150 are regularly arranged. For example, the ball lands 150 have a layout suitable for the rules of the Joint Electron Device Engineering Council (JEDEC).

Ball lands 150 having an arrangement suitable for JEDEC regulations are electrically connected to each circuit pattern 140.

Conductive balls such as solder balls may be disposed on the ball lands 150.

3 is a plan view illustrating the semiconductor chip module illustrated in FIG. 1. 4 is a cross-sectional view taken along the line II ′ of FIG. 1. FIG. 5 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

3 to 5, the semiconductor chip module 200 may include, for example, a plurality of m × n matrices (wherein m is one or more, n is two or more, and m and n are natural numbers). Semiconductor chips. In this embodiment, the semiconductor chips of the semiconductor chip module 200 are arranged in a 1 × 2 matrix form. Alternatively, the semiconductor chips of the semiconductor chip module 200 may be arranged in various forms such as a 1 × 2 matrix and a 2 × 2 matrix.

The semiconductor chip module 200 is disposed on the substrate body 110 by an adhesive member 205.

Hereinafter, the semiconductor chips will be defined as the first semiconductor chip 210 and the second semiconductor chip 230. In the present embodiment, the first semiconductor chip 210 and the second semiconductor chip 230 may be integrally formed. Alternatively, the first semiconductor chip 210 and the second semiconductor chip 230 may be separated from each other. When the first semiconductor chip 210 and the second semiconductor chip 230 are separated from each other, the first semiconductor chip 210 and the second semiconductor chip 230 may be different types.

The first semiconductor chip 210 may include a plurality of first bonding pads 212, 214, 216, 218 and 219. The first bonding pads 212, 214, 216, 218 are disposed at both edges of the first semiconductor chip 210, for example. The first bonding pads 212, 214, 216, and 218 are disposed in the Y axis direction of FIG. 1. The first bonding pads 212, 214, 216, and 218 are disposed adjacent to the first connection pads 120.

The second semiconductor chip 230 includes a plurality of second bonding pads 232, 234, 236, 238 and 239.

The second bonding pads 232, 234, 236, 238 are disposed at both edges of the second semiconductor chip 230, for example. The second bonding pads 232, 234, 236 and 238 are disposed in the Y axis direction of FIG. 1. The second bonding pads 232, 234, 236, and 238 are disposed adjacent to the second connection pads 130.

The first and second semiconductor chips 210 and 230 may be integrally formed. Alternatively, the first and second semiconductor chips 210 and 230 may be separated. The separated first and second semiconductor chips 210 and 230 may be, for example, different types.

The conductive wire 300 electrically connects each first bonding pad 209 and each first connection member 120 of the first semiconductor chip 210. In addition, the conductive wire 300 electrically connects each second bonding pad 230 and each second connection member 130 of the second semiconductor chip 230.

6 is a plan view illustrating a rear surface of a semiconductor package according to a second exemplary embodiment of the present invention.

Referring to FIG. 6, the semiconductor package 800 includes a substrate 500, a semiconductor chip module 600, and a conductive wire 700.

The substrate 500 includes a substrate body 510, first connection pads 520, second connection pads 530, circuit patterns 540, and ball lands 550.

The substrate body 510 having a plate shape may be, for example, a multilayer printed circuit board.

The substrate body 510 having a plate shape has a first chip region FR and a second chip region SR. In the present embodiment, the first chip region FR and the second chip region SR are disposed adjacent to each other. Alternatively, the first chip region FR and the second chip region SR may be spaced apart from each other by a predetermined interval.

An opening 501 having a slit shape toward the Y axis direction shown in FIG. 6 is disposed at the center of the substrate body 510.

The first connection pads 520 are disposed adjacent to the opening 501 corresponding to the first chip region FR of the substrate body 510. The first connection pads 520 are disposed at both sides of the opening 501.

For example, eight first connection pads 520 are formed. Four first connection pads 520 are disposed at each side of the opening 501. Alternatively, the first connection pads 520 may be disposed at one side of the opening 501.

Hereinafter, each of the first connection pads 520 disposed on both sides of the opening 501 may include a first sub connection pad 522, a second sub connection pad 524, a third sub connection pad 526, and a fourth sub pad. It is defined as the sub connection pad 528. The first to fourth sub connection pads 522, 524, 526, and 528 are sequentially disposed along the Y-axis direction of FIG. 6.

Although it is shown and described that only eight first connection pads 520 are included in the present embodiment, the first connection pads 520 may be configured to have at least nine or more.

The second connection pads 530 are disposed at both sides of the opening 501 corresponding to the second chip region SR of the substrate body 110. The plurality of second connection pads 530 is disposed along the Y axis direction of the substrate body 510, for example.

For example, eight second connection pads 530 are formed. Four second connection pads 530 are disposed at both sides of the opening 501. Alternatively, the second connection pads 530 may be disposed at one side of the opening 501.

Hereinafter, each of the second connection pads 530 disposed at both sides of the opening 501 corresponding to the second chip region SR may include the fifth sub connection pad 532, the sixth sub connection pad 534, and the fifth connection pad 534. It is defined as a seventh sub-connection pad 536 and an eighth sub-connection pad 538. The fifth to eighth sub connection pads 532, 534, 536, and 538 are sequentially disposed along the Y axis direction of FIG. 6.

Although it is illustrated and described that only eight second connection pads 530 are formed in the present embodiment, the second connection pads 530 may be configured to have at least nine or more.

In the present exemplary embodiment, the first connection pads 520 and the second connection pads 530 are formed in a symmetrical shape with respect to the boundary of the first chip region FR and the second chip region SR.

The circuit patterns 540 are formed in the substrate body 510, and the circuit patterns 540 electrically connect the first connection pads 520 and the second connection pads 530 corresponding to the first connection pads 520. Connect.

For example, the circuit pattern 540 electrically connects the first sub connection pad 522 of the first connection pad 520 and the fifth sub connection pad 532 of the second connection pad 530.

In addition, the circuit pattern 540 electrically connects the second sub connection pad 524 of the first connection pad 520 and the sixth sub connection pad 534 of the second connection pad 530.

In addition, the circuit pattern 540 electrically connects the third sub connection pad 526 of the first connection pad 520 and the seventh sub connection pad 536 of the second connection pad 530.

In addition, the circuit pattern 540 electrically connects the fourth sub connection pad 528 of the first connection pad 520 and the eighth sub connection pad 538 of the second connection pad 530.

As such, to electrically connect the first to fourth sub connection pads 522, 524, 526 and 528 of the first connection pad 520 and the fifth to eighth sub connection pads 532, 534, 536 and 538 of the second connection pad 530. The circuit patterns 540 may be disposed on one insulating layer. Alternatively, the circuit patterns 540 may be formed on the two insulating layers, respectively. Alternatively, the circuit patterns 540 may be formed on the three insulating layers, respectively.

In this embodiment, the circuit patterns 540 disposed on the different insulating layers include the first circuit pattern 542, the second circuit pattern 544, and the third circuit pattern 546.

The first circuit patterns 542 are connected to the first to eighth sub connection pads 522, 524, 526, 528, 532, 534, 536 and 538, respectively.

The third circuit patterns 546 are electrically connected to each ball land 550 to be described later.

The second circuit patterns 544 electrically connect each first circuit pattern 542 and each second circuit pattern 544. The second circuit patterns 544 are particularly disposed at portions where the first circuit patterns 542 cross each other. The first circuit pattern 542 and the second circuit pattern 544 are electrically connected through, for example, conductive vias 548.

The ball lands 550 are disposed on the surface of the substrate body 510, and the ball lands 550 are regularly arranged. For example, the ball lands 550 have a layout that conforms to JEDEC regulations.

Ball lands 550 having an arrangement suitable for JEDEC regulations are electrically connected to each circuit pattern 540.

Conductive balls such as solder balls may be disposed in the ball lands 550.

FIG. 7 is a plan view illustrating the semiconductor chip module illustrated in FIG. 6. FIG. 8 is a cross-sectional view taken along the line III-III ′ of FIG. 6.

7 to 8, the semiconductor chip module 600 may include, for example, a plurality of m × n matrices (wherein m is one or more, n is two or more, and m and n are natural numbers). Semiconductor chips. In this embodiment, the semiconductor chip module 600 is arranged in the form of a 1 × 2 matrix, for example. Alternatively, the semiconductor chips of the semiconductor chip module 200 may be arranged in a 1 × 2 matrix form and in a 2 × 2 matrix form.

 The semiconductor chip module 600 is disposed on the substrate body 610 by an adhesive member 605.

Hereinafter, the semiconductor chips will be defined as a first semiconductor chip 610 and a second semiconductor chip 630. In the present embodiment, the first semiconductor chip 610 and the second semiconductor chip 630 may be integrally formed. Alternatively, the first semiconductor chip 610 and the second semiconductor chip 630 may be separated from each other. When the first semiconductor chip 610 and the second semiconductor chip 630 are separated from each other, the first semiconductor chip 610 and the second semiconductor chip 630 may be different types.

The first semiconductor chip 610 includes a plurality of first bonding pads 612, 614, 616, 618 and 619. The first bonding pads 612, 614, 616, 618 are disposed at, for example, a central portion of the first semiconductor chip 610. The first bonding pads 612, 614, 616, and 618 disposed at the center portion of the first semiconductor chip 610 are exposed by the opening 501 of the substrate body 510.

The first bonding pads 612, 614, 616, 618 are disposed in the Y axis direction of FIG. 7. The first bonding pads 612, 614, 616, 618 are disposed adjacent to the first connection pads 520.

The second semiconductor chip 630 includes a plurality of second bonding pads 632, 634, 636, 638; 639.

The second bonding pads 632, 634, 636, 638 are disposed at, for example, a central portion of the second semiconductor chip 630. The second bonding pads 632, 634, 636 and 638 disposed at the center of the second semiconductor chip 630 are exposed by the opening 501 of the substrate body 510. The second bonding pads 632, 634, 636, 638 are disposed in the Y axis direction of FIG. 7. The second bonding pads 632, 634, 636, 638 are disposed adjacent to the second connection pads 530.

The first and second semiconductor chips 610 and 630 may be integrally formed. Alternatively, the first and second semiconductor chips 610 and 630 may be in a separated state. The separated first and second semiconductor chips 610 and 630 may be, for example, different types.

The conductive wire 700 electrically connects each of the first bonding pads 609 and each of the first connection members 520 of the first semiconductor chip 610 through the opening 501 formed in the substrate body 510. In addition, the conductive wire 700 electrically connects each second bonding pad 630 and each second connection member 530 of the second semiconductor chip 630 through an opening 501 formed in the substrate body 510. do.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

1 is a plan view showing a semiconductor package according to a first embodiment of the present invention.

FIG. 2 is a plan view illustrating a rear surface of a substrate of the semiconductor package illustrated in FIG. 1.

3 is a plan view illustrating the semiconductor chip module illustrated in FIG. 1.

4 is a cross-sectional view taken along the line II ′ of FIG. 1.

FIG. 5 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

6 is a plan view illustrating a rear surface of a semiconductor package according to a second exemplary embodiment of the present invention.

FIG. 7 is a plan view illustrating the semiconductor chip module illustrated in FIG. 6.

FIG. 8 is a cross-sectional view taken along the line III-III ′ of FIG. 6.

Claims (14)

A substrate body having a first chip region and a second chip region, first connection pads disposed in the first chip region, second connection pads disposed in the second chip region, and formed in the substrate body At least one circuit pattern electrically connecting a first connection pad and each of the second connection pads corresponding to the first connection pads, and ball lands disposed on a bottom surface of the substrate body and electrically connected to the circuit patterns. A substrate comprising; A semiconductor chip module including a first semiconductor chip disposed in the first chip region and having first bonding pads and a second semiconductor chip disposed in the second chip region and having second bonding pads; And And a conductive wire electrically connecting the first bonding pads to the first connection pads, the second bonding pads, and the second connection pads. The method of claim 1, And the circuit pattern is disposed on one insulating layer. The method of claim 1, The circuit pattern may include a first circuit pattern electrically connected to the first and second connection pads, a second circuit pattern disposed on an insulating layer different from the first circuit pattern, and electrically connected to each ball land. And a third circuit pattern disposed on an insulating layer different from the first and second circuit patterns and electrically connecting the first and second circuit patterns. The method of claim 1, And the ball lands are regularly arranged. The method of claim 1, And the first and second semiconductor chips are integrally formed. The method of claim 1, And the first and second semiconductor chips are separated. The method of claim 1, And the first and second bonding pads are disposed at edges of the first and second semiconductor chips. A substrate body including a first chip region, a second chip region, and an opening opening the first and second chip regions, first connection pads disposed around the opening corresponding to the first chip region, the first Second connection pads disposed around the opening corresponding to the two chip regions, and electrically connected to each of the first connection pads and the second connection pads corresponding to the first connection pads, respectively formed on the substrate body. A substrate including ball lands disposed on a bottom surface of the substrate body and electrically connected to the circuit patterns; A semiconductor chip module disposed in the first chip region and including a first semiconductor chip having first bonding pads exposed by the opening and a second semiconductor chip disposed in the second chip region and having second bonding pads; And And a conductive wire electrically connecting the first bonding pads to the first connection pads, the second bonding pads, and the second connection pads through the openings. The method of claim 8, And the circuit pattern is disposed on one insulating layer. The method of claim 8, The circuit pattern may include a first circuit pattern electrically connected to the first and second connection pads, a second circuit pattern disposed on an insulating layer different from the first circuit pattern, and electrically connected to each ball land. And a third circuit pattern disposed on an insulating layer different from the first and second circuit patterns and electrically connecting the first and second circuit patterns. The method of claim 8, And the ball lands are regularly arranged. The method of claim 8, And the first and second semiconductor chips are integrally formed. The method of claim 8, And the first and second semiconductor chips are separated. The method of claim 8, And the first and second bonding pads are disposed in the center of the first and second semiconductor chips.

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