JP2005285295A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a chip select terminal and is laminated to connect the same kinds of terminals with each other, and a stacked semiconductor device using the same. <P>SOLUTION: With regard to a semiconductor device mounting a semiconductor chip comprising a selector circuit for selecting only one of a chip select and a plurality of signals and a circuit for generating a logical state for individually identifying a plurality of semiconductor devices, the semiconductor device comprises a connecting terminal including a plurality of chip select terminals provided through upper and lower surfaces of a package, and the plurality of chip select terminals and the selector circuit are connected. Only one of the plurality of chip select signals is validated according to the state of a chip select signal inputted to the selector circuit, the chip select signal is connected to the circuit for generating the logical state for individually identifying the plurality of semiconductor devices, and the select signal is outputted after changing its logical state into state for selecting different semiconductor devices. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device on which a semiconductor chip having a chip select terminal is mounted, and a stacked semiconductor device formed by stacking the semiconductor devices.

  In recent years, miniaturization and weight reduction of various electronic devices have been desired, and therefore miniaturization of individual electronic components constituting the electronic device is also progressing.

  However, most of the electronic components using semiconductor chips are the well-known dual in-line package (DIP) type in which the periphery of one semiconductor chip is molded with resin or ceramic and external terminals are provided, or the flat package type for surface mounting, BGA type.

  When such DIP type electronic components are used, for example, when configuring a memory circuit using a plurality of semiconductor memories, DIP type semiconductor memories are arranged side by side on a circuit board, and individual semiconductor memories are arranged as necessary. The semiconductor memory to be used is selected according to the memory address by inputting a select signal associated with the memory address signal to the chip select terminal.

  For this reason, as the memory capacity to be used increases, the mounting area of electronic components increases, which hinders downsizing of electronic devices. In order to prevent an increase in the mounting area, a stacked semiconductor device is also disclosed in which a plurality of semiconductor chips are arranged three-dimensionally to reduce the mounting area.

  Hereinafter, a conventional semiconductor device will be briefly described with reference to FIGS. FIG. 4 is a schematic plan view of a conventional semiconductor device, and FIG. 5 is a schematic cross-sectional view when the semiconductor devices of FIG. 4 are stacked.

  4A to 4D are perspective plan views showing circuit patterns of the respective packages. The stacked semiconductor device 100 shown in FIG. 5 is configured by stacking four packages 130, 131, 132, 133 on a mother board 134. As shown in FIG. 4, each semiconductor device is formed in a rectangular shape in plan view, and 16 connection terminals 1 to 16 are arranged along each long side. 4 shows the upper surface of each semiconductor device. The connection terminals 1 to 8 are arranged at a constant arrangement pitch along the upper long side in FIG. 4, and the connection terminals along the lower long side in FIG. 9 to 16 are arranged at a constant arrangement pitch.

  Similarly, 16 connection terminals are arranged on the lower surface of each semiconductor device. Each connection terminal on the lower surface is arranged at a position directly below each connection terminal on the upper surface, and each of the connection terminals 1 to 16 on the upper surface and directly below each connection terminal. The connection terminal is electrically connected through a through hole.

  As illustrated in FIG. 5, the stacked semiconductor device 100 is configured by stacking such packages 130, 131, 132, and 133 on a mother board 134 in a state where the positions of the connection terminals coincide with each other. In each package, for example, a semiconductor chip 140 which is a memory chip is mounted, and its chip select terminal is connected to a different connection terminal for each package, so that the semiconductor chip 140 of each package can be individually selected. .

  Therefore, in the lowermost package 130, as shown in FIG. 4A, a circuit pattern 160 for connecting the chip select terminal 150 and the connection terminal 9 of the semiconductor chip 140 is formed in the package. In the second-stage package 131 from the bottom, as shown in FIG. 4B, a circuit pattern 161 for connecting the chip select terminal 150 of the semiconductor chip 140 and the connection terminal 10 is formed in the package. In the third stack carrier 132 from the bottom, as shown in FIG. 4C, a circuit pattern 162 that connects the chip select terminal 150 of the semiconductor chip 140 and the connection terminal 11 is formed in the package. ing. In the uppermost package 133, as shown in FIG. 4D, a circuit pattern 163 that connects the chip select terminal 150 and the connection terminal 12 of the semiconductor chip 140 is formed in the package.

  As a result, as shown in FIG. 5, the chip select terminal 150 of the semiconductor chip 140 mounted on the uppermost package 133 is connected to the circuit on the mother board 134 by the connection terminal 9 on the lower surface, so that the second-stage semiconductor The chip select terminal 150 of the chip 132 is connected to the motherboard 134 by a path 171 indicated by a dotted line, and the chip select terminals 150 of the third and uppermost semiconductor chips 140 are connected to the motherboard 134 by a path 172 and a path 173, respectively. .

  Japanese Patent Laid-Open No. 2003-163326 discloses another technique. Briefly described below. As shown in FIG. 6, the chip select terminal 250 on the upper surface of the semiconductor chip 230 and the connection terminals 9 to 12 are connected by the wiring 270 on the upper surface of the chip, and the wiring 270 on the upper surface of the chip is cut at the dotted line portion shown in FIG. A semiconductor chip in which only the chip select terminal 250 and the connection terminal 9 are connected can be obtained. Similarly, by changing the cutting position of the wiring 270, a semiconductor chip in which only one of the chip select signal 250 and the connection terminals 10 to 12 is connected is obtained.

JP 2003-163326 A

  The problem to be solved is that, when the packages of the semiconductor devices to be stacked are made into individual patterns, it is necessary to design the patterns individually for each package and to create and manufacture different masks, which increases the initial cost. Is a point. In addition, since each semiconductor device is a different part, it must be managed individually, which increases the management cost. In addition, in the case of individually cutting a pattern in which a plurality of chip select signals are connected on each stacked semiconductor device, the manufacturing process becomes complicated and the manufacturing cost increases.

  The present invention inputs all of a plurality of chip select signals into a semiconductor chip, and makes only one of the plurality of chip select signals corresponding to the state of a signal capable of individually identifying each stacked semiconductor device. By making effective, it is possible to make the semiconductor chip and the package of each semiconductor device to be laminated the same, and to eliminate an increase in cost.

  The semiconductor device of the present invention has an advantage that a plurality of connection terminals formed in the same position on the same chip and the same package having chip select terminals can be connected and stacked.

  A plurality of the semiconductor devices of the present invention can be stacked by connecting the connection terminals formed at the same position. At this time, a plurality of chip select signals are input to a selector circuit provided in each semiconductor chip. Further, one of the plurality of chip select signals is selected according to the state of the chip select selection signal. Further, the chip select selection signal is also input to the increment circuit, and is changed to an incremented state and output. The signal output from the increment circuit is input as the chip select selection signal for the next-stage semiconductor chip. As a result, it is possible to stack semiconductor chips corresponding to the number of the chip select terminals at the maximum by making the chip select signal of each semiconductor chip valid only by one different chip select signal.

  1 is a diagram showing the connection relationship of the semiconductor device of the present invention device, FIG. 2 is a perspective plan view of the package 30 as viewed from the upper surface side, and FIG. 3 is a side view of the package 30 shown in FIG. FIG.

  In each figure, 1 to 20 are connection terminals on the package, 30 is a package, 31 is a motherboard, 40 is a semiconductor chip, 50 to 53 are chip select input terminals of the semiconductor chip 40, and 54 and 55 are chip select selections of the semiconductor chip. Signal input terminals 56 and 57 are chip select selection signal output terminals of the semiconductor chip, and 60 to 67 are wirings for connecting the input terminals of the semiconductor chip and the connection terminals on the package.

  As shown in FIG. 3, in the stacked semiconductor device of this embodiment, as in the conventional case, the connection terminals 1 to 20 are arranged in a line at intervals on the upper and lower surfaces of the package, and the connection terminals on the lower surface correspond to each other. It is arranged almost directly below the connecting terminal on the upper surface.

  In the embodiment of the present invention, the connection terminals 11 to 14 on the upper and lower surfaces of the package are chip select connection terminals. As shown in FIG. 3A, the upper connection terminal 11 is connected to the lower connection terminal by a through hole. 11 is electrically connected. The chip select terminal 50 of the semiconductor chip 40 is also electrically connected by wire bonding and wiring 60. Similarly, the connection terminals 12 to 14 and the chip select terminals 51 to 53 of the semiconductor chip 40 are also electrically connected.

  The connection terminals 19 and 20 are chip select selection signals. As shown in FIGS. 3B and 3C, the connection terminals 19 and 20 on the upper surface of the package are electrically insulated from the connection terminals 19 and 20 on the lower surface of the package. ing. The connection terminals 19 and 20 on the lower surface of the package are electrically connected to the chip select selection signal input terminals 54 and 55 of the semiconductor chip 40 by wire bonding and wirings 64 and 65, respectively. The connection terminals 19 and 20 on the upper surface of the package are electrically connected to the chip select selection signal input terminals 56 and 57 of the semiconductor chip 40 by wire bonding and wirings 66 and 67, respectively.

  In this embodiment, as shown in FIG. 1, four packages 30 are stacked to constitute a stacked semiconductor device. The connection terminals on the lower surface of the package and the mother board 34 and the connection terminals at the same position of the package 30 are connected using, for example, solder balls made of solder.

  In the semiconductor chip 40 stacked at the lowermost stage shown in FIG. 1, chip select 0 to 3 are input from the mother board to the chip select terminals 50 to 53 through solder balls, through holes and wirings, and further a selector circuit in the semiconductor chip. Connected to.

  The chip select selection signal signal is input from the GND (0V) of the motherboard to the chip select selection signal input terminals 54 and 55 through solder balls, through holes, and wirings, and is further connected to a selector circuit in the semiconductor chip. At this time, since the signals input to the chip select selection signal input terminals 54 and 55 are 0 V, the logical values are “0” and “0”, respectively. The selector circuit is designed to select only chip select 0 when the logical values are “0” and “0”. As a result, the memory circuit of the lowermost semiconductor chip 40 is set to the operating state or the non-operating state by the chip select 0.

  The chip select selection signal is also input to the increment circuit, and the logical values “0” and “0” are incremented to become “1” and “0”, and are output from the chip select selection signal output terminals 56 and 57. It is sent to the second-stage semiconductor chip.

  Chip select 0 to 3 input to the lowermost semiconductor chip in the second-stage semiconductor chip 40 from the motherboard are input to the chip select terminals 50 to 53 through the package of the lowermost semiconductor device, and further to the semiconductor. Connected to the selector circuit in the chip.

  The logic values “1” and “0” from the chip select selection signal output terminals 56 and 57 of the lowermost semiconductor chip 40 are applied to the chip select selection signal input terminals 54 and 55 of the second stage semiconductor chip 40 from the motherboard. Signal is input. The selector circuit is designed to select the chip select 1 when the logical values are “1” and “0”. As a result, the memory circuit of the second-stage semiconductor chip 40 from the mother board is set to the operating state or the non-operating state by the chip select 1.

  Further, the chip select selection signal is also input to an increment circuit, and logical values “1” and “0” are incremented to become “0” and “1”, and three stages from the select signal output terminals 56 and 57 are obtained. Sent to the semiconductor chip of the eye.

  The chip select signals 0 to 3 are connected to the third and fourth semiconductor chips 40 from the mother board in the same manner as the second semiconductor chip 40 from the mother board. The logic values “0” and “0” of the chip select selection signal output terminals 56 and 57 of the second-stage semiconductor chip 40 from the motherboard are connected to the chip select selection signal input terminals 54 and 55 of the third-stage semiconductor chip 40 from the motherboard. 1 "signal is input. The logic values “0” and “1” of the chip select selection signal input of the third-stage semiconductor chip 40 from the motherboard are incremented to the chip select selection signal input terminals 54 and 55 of the fourth-stage semiconductor chip 40 from the motherboard. Signals with logical values “1” and “1” are input. The selector circuit is designed to select the chip select 2 when the logical values are “0” and “1”, and to select the chip select 3 when the logical values are “1” and “1”. As a result, the memory circuit of the semiconductor chip 40 in the third stage from the motherboard is set to the operating state or non-operating state by the chip select 2, and the memory circuit of the semiconductor chip 40 in the fourth stage from the motherboard is operated by the chip select 3. State or non-operational state is set. In this way, it is possible to obtain a stacked semiconductor device in which only one chip select signal different from each other in the chip select signal of each semiconductor chip is valid.

  In this embodiment, a stacked semiconductor device in which four semiconductor devices are stacked has been described. However, the number of stacked semiconductor devices is not limited to four. It is also possible to stack up to four semiconductor devices. It is also possible to stack four or more semiconductor devices by increasing the number of chip select signals and chip select selection signals.

  In this embodiment, the increment circuit has been described as an example, but it can also be realized by a decrement circuit. Further, the circuit is not limited to the increment / decrement circuit as long as it is a circuit that generates a logic state for individually identifying a plurality of semiconductor devices.

  In this embodiment, the semiconductor chip is mounted in a 20-pin package and connected to the package by wire bonding. The semiconductor chip is mounted on the upper and lower surfaces of the package. Semiconductor chip Other than wire bonding, for example, the form of connection to the package by solder balls or the like can be easily inferred, and the number of pins of the semiconductor device, the mounting position of the semiconductor chip, the connection method with the package, and the connection method between the packages are limited is not.

It is a figure which shows the connection relation of a semiconductor device. (Example 1) It is the see-through plan view which looked at the semiconductor device from the upper surface side. (Example 1) It is a perspective sectional view from the side of a semiconductor device. (Example 1) It is the see-through plan view which looked at the semiconductor device from the upper surface side. (Background technology) It is a schematic sectional drawing of the laminated | stacked semiconductor device. (Background technology) It is the see-through plan view which looked at the semiconductor device from the upper surface side. (Background technology)

Explanation of symbols

1 to 20 Connection terminal on package 30 Semiconductor device 31 Motherboard 40 Package 50 to 53 Chip select input terminal 54 and 55 Chip select selection signal input terminal 56 and 57 Chip select selection signal output terminal 60 to 67 Wiring in package 100 Multilayer semiconductor Device 131 to 133 Semiconductor device 134 Motherboard 140 Semiconductor chip 150 Chip select input terminal 160 to 163 Wiring in package 171 to 174 Signal propagation path 230 Semiconductor chip 250 Chip select input terminal 270 Wiring on semiconductor chip

Claims (4)

  Semiconductor chip comprising a chip select for setting an internal circuit in an operating state or a non-operating state, a selector circuit for selecting only one of a plurality of signals, and a circuit for generating a logic state for individually identifying the plurality of semiconductor devices Is a semiconductor device mounted on the upper surface, lower surface or inside of the package (circuit board), and includes a plurality of connection terminals including a plurality of chip select terminals, each penetratingly provided on the upper and lower surfaces of the package. The plurality of chip select terminals and the selector circuit are connected, and only one of the plurality of chip select signals is made effective according to the state of the chip select selection signal input to the selector circuit, and the chip select selection signal To a circuit for generating a logic state for individually identifying the plurality of semiconductor devices, and a chip select selection signal Semiconductor device and outputs the physical state by changing the state of selecting the different semiconductor device.   The semiconductor device according to claim 1, wherein an internal circuit of the semiconductor chip is a memory circuit.   2. The stacked semiconductor device according to claim 1, wherein connection terminals at the same position including the chip select terminal of the semiconductor device of claim 1 are connected and stacked, and different chip select signals can be selected. 3. A stacked semiconductor device according to claim 2, wherein the connection terminals at the same position including the chip select terminal of the semiconductor device of claim 2 are connected and stacked, and different chip select signals can be selected.

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