WO2022121389A1 - 高分辨率脉冲宽度调制信号产生电路 - Google Patents

高分辨率脉冲宽度调制信号产生电路 Download PDF

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Publication number
WO2022121389A1
WO2022121389A1 PCT/CN2021/116216 CN2021116216W WO2022121389A1 WO 2022121389 A1 WO2022121389 A1 WO 2022121389A1 CN 2021116216 W CN2021116216 W CN 2021116216W WO 2022121389 A1 WO2022121389 A1 WO 2022121389A1
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delay
signal
module
pwm
unit
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PCT/CN2021/116216
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English (en)
French (fr)
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陈帅
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华大半导体有限公司
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Publication of WO2022121389A1 publication Critical patent/WO2022121389A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

Definitions

  • the invention relates to the field of integrated circuit design, in particular to a high-resolution pulse width modulation signal generating circuit.
  • n log 2 (fck/fswpwm) .
  • the clock frequency fck cannot be arbitrarily increased due to the limitation of the process.
  • the count clock of the digital PWM needs to reach a frequency of more than 8GHz, and the resolution is 122ps. It is difficult to realize under the integrated circuit technology. Therefore, the limitation of the process capability on the clock frequency of the counter contradicts the high resolution requirement of PWM.
  • the purpose of the present invention is to provide a high-resolution pulse width modulation signal generating circuit for solving the problem that the accuracy of the PWM signal in the prior art is limited by the clock frequency.
  • the present invention provides a high-resolution pulse width modulation signal generating circuit, the high-resolution pulse width modulation signal generating circuit at least includes:
  • Control module PWM counting module, delay module, output selection module and calibration module
  • the control module receives a control signal, and is used for generating a rising edge delay amount, a falling edge delay amount, an output selection signal and a calibration control signal;
  • the PWM counting module receives a counting clock, and generates a PWM signal based on the counting clock;
  • the delay module is connected to the output end of the control module and the PWM counting module, and delays the PWM signal based on the rising edge delay amount and the falling edge delay amount;
  • the output selection module is connected to the output terminals of the control module, the PWM counting module and the delay module, and outputs the output signal of the PWM counting module or the delay module based on the output selection signal;
  • the calibration module is connected to the output end of the control module, and receives the count clock, counts the frequency-divided signal of the ring oscillation signal of the delay module based on the count clock, and compares the ring oscillation signal with the clock based on the count clock.
  • the multiple relationship of the counting clock realizes the calibration of the delay amount, wherein the high level width of the ring oscillation signal is the rising edge delay amount in the delay module, and the low level width is a preset width.
  • control module includes a delay amount selection register, and outputs the rising edge delay amount and the falling edge delay amount based on the delay amount selection register.
  • the PWM counting module includes a counting unit and a comparison unit; the counting unit receives the counting clock, counts the counting clock and outputs a count value; the comparison unit is connected to the output end of the counting unit , compare the count value with a preset value, and flip the level when the count value reaches the preset value to obtain the PWM signal.
  • the PWM counting module also receives a phase adjustment control signal, the phase adjustment control signal is connected to the comparison unit, and the phase adjustment of the PWM signal is realized by changing the preset value, thereby realizing the pulse frequency. modulation function.
  • the delay module includes a rising edge delay unit and a falling edge delay unit;
  • the rising edge delay unit is connected to the output terminals of the PWM counting module and the control module, and performs a rising edge delay on the PWM signal based on the rising edge delay amount;
  • the falling edge delay unit is connected to the rising edge delay The output end of the unit and the control module performs a falling edge delay on the PWM signal after the rising edge delay based on the falling edge delay amount;
  • the falling edge delay unit is connected to the output terminals of the PWM counting module and the control module, and performs a falling edge delay on the PWM signal based on the falling edge delay amount;
  • the rising edge delay unit is connected to the falling edge The edge delay unit and the output end of the control module perform a rising edge delay on the PWM signal after the falling edge delay based on the rising edge delay amount.
  • both the rising edge delay unit and the falling edge delay unit include a delay decoder, a delay chain composed of m sequentially cascaded delay blocks, and an AND-OR logic unit;
  • the delay decoder decodes the delay amount to obtain a delay amount selection signal and a delay block valid signal
  • the delay chain receives the PWM signal, each delay block in the delay chain receives the delay amount selection signal and the delay block valid signal, and based on the delay amount selection signal and the delay block valid signal, the PWM signal is delayed;
  • the input end of the AND-OR logic unit is connected to the output end of the delay chain and the PWM signal, and an AND-OR operation is performed on the output signal of the delay chain and the PWM signal to obtain the delay signal of the PWM signal;
  • the delay block includes first to n+1th data selectors that are cascaded in sequence, the first input end of the latter-stage data selector is connected to the output end of the former-stage data selector, and the first to n+1th data selectors of each data selector are connected.
  • Two input terminals are connected to the PWM signal, the first input terminal and the second input terminal of the first data selector are connected to the PWM signal, and the control terminal of the first data selector to the nth data selector
  • the corresponding delay quantity selection signals are respectively connected, and the control end of the n+1th data selector is connected to the corresponding delay block effective signal, wherein n is a natural number greater than or equal to 1.
  • the data selector is a two-to-one selector.
  • the ring vibration signal generating unit includes a delay selection subunit, a preset delay subunit, an edge detection subunit and an RS flip-flop;
  • the delay selection subunit is connected to the output end of the RS flip-flop, and the delay selection subunit has the same structure as the rising edge delay unit, and selects different delays based on the calibration control signal for the RS flip-flop.
  • the output signal is delayed;
  • the preset delay subunit is connected to the output end of the RS flip-flop, and delays the output signal of the RS flip-flop based on a preset delay amount;
  • the edge detection subunit is connected to the output end of the preset delay unit, and performs edge detection on the output signal of the preset delay subunit;
  • the reset terminal of the RS flip-flop is connected to the output terminal of the delay selection subunit, and the set terminal is connected to the output terminal of the edge detection subunit to generate the ring oscillation signal.
  • the high-resolution pulse width modulation signal generating circuit of the present invention has the following beneficial effects:
  • the high-resolution pulse width modulation signal generating circuit of the present invention improves the resolution of the pulse width modulation signal without changing the count clock, and can be used to adjust the period and duty ratio of the PWM signal.
  • the high-resolution pulse width modulation signal generation circuit of the present invention measures the multiple relationship between the counting clock and the delay chain through the calibration circuit, and the delay module can be conveniently regarded as the subordinate extension of the PWM counting module, which is convenient for software control and improves. Accuracy of high-resolution PWM.
  • the high-resolution pulse width modulation signal generation circuit of the present invention uses the basic unit device MUX as the minimum delay unit of the delay chain, and is also used as the delay selection logic, which reduces the inherent delay from the input of the delay module to the output of the delay module, and has It is beneficial to reduce the error of the delay chain.
  • FIG. 1 is a schematic structural diagram of a high-resolution pulse width modulation signal generating circuit of the present invention.
  • FIG. 2 is a schematic structural diagram of the PWM counting module of the present invention.
  • FIG. 3 is a schematic diagram showing the structure of the rising edge delay unit of the present invention.
  • the present invention provides a high-resolution pulse width modulation signal generating circuit 1, and the high-resolution pulse width modulation signal generating circuit 1 includes:
  • a control module 11 a PWM counting module 12 , a delay module 13 , an output selection module 14 and a calibration module 15 .
  • the control module 11 receives control signals for generating a rising edge delay amount up[7:0], a falling edge delay amount down[7:0], an output selection signal ctl1 and a calibration control signal ctl2.
  • control module 11 includes, but is not limited to, a delay selection register, an output control unit, and a calibration control unit (not shown in the figure), which are arbitrarily used to control each module in the high-resolution PWM signal generating circuit 1
  • the working control signals can be generated by the control module 11 .
  • the selection of the rising edge delay amount up[7:0] and the falling edge delay amount down[7:0] is realized by changing the delay amount selection register. Based on the characteristics of the register, the selection occurs on the edge of the PWM signal. When changing, the output value of the delay amount selection register will not change immediately, so that the output competition of the high-resolution PWM signal can be avoided.
  • control module 11 also receives the count clock ck as the working clock, and in actual use, the source of the working clock of the control module 11 can be set as required, which is not limited to this embodiment.
  • the rising edge delay amount up[7:0] and the falling edge delay amount down[7:0] are 8-bit bus signals.
  • the number of bits of the rising edge delay amount and the falling edge delay amount may be set as required, which is not limited to this embodiment.
  • the PWM counting module 12 receives the counting clock ck, and generates a PWM signal based on the counting clock ck.
  • the PWM counting module 12 includes a counting unit 121 and a comparing unit 122 .
  • the counting unit 121 receives the counting clock ck, counts the counting clock ck, and outputs a count value.
  • the comparison unit 122 is connected to the output terminal of the counting unit 121, compares the count value with a preset value (comparison threshold), and flips the level when the count value reaches the preset value to obtain the PWM signal.
  • circuit structure capable of generating a PWM waveform is applicable to the present invention, and is not limited to this embodiment.
  • the PWM counting module 11 also receives a phase adjustment control signal ctl3.
  • the phase adjustment control signal ctl3 is provided by the control module 11; the phase adjustment control signal ctl3 is connected to The comparison unit 122 realizes the adjustment of the phase of the PWM signal by changing the preset value, thereby realizing the pulse frequency modulation (Pulse Frequency Modulation, PFM) function.
  • PFM Pulse Frequency Modulation
  • the delay module 13 is connected to the output terminals of the control module 11 and the PWM counting module 12, based on the rising edge delay amount up[7:0] and the falling edge delay amount down[ 7:0] perform a delay operation on the PWM signal.
  • the delay module 13 includes a rising edge delay unit 13a and a falling edge delay unit 13b.
  • the rising edge delay unit 13a is connected to the output terminals of the PWM counting module 12 and the control module 11, and the PWM signal is raised based on the rising edge delay amount up[7:0] edge delay;
  • the falling edge delay unit 13b is connected to the rising edge delay unit 13a and the output end of the control module 11, and based on the falling edge delay amount down[7:0], the PWM signal after the rising edge delay is processed Falling edge delay.
  • the rising edge delay unit 13a and the falling edge delay unit 13b have the same structure, and both include a delay decoder 131, a delay chain formed by m sequentially cascaded delay blocks 132, and an AND-OR logic unit 133.
  • the rising edge delay unit 13a is taken as an example, the difference between the falling edge delay unit 13b and the rising edge delay unit 13a is only that they receive different delay amounts (the rising edge delay unit receives the rising edge delay The edge delay unit receives the falling edge delay amount), and the objects of delay are different (the rising edge delay unit delays the rising edge, and the falling edge delay unit delays the falling edge), which will not be repeated here.
  • the delay decoder 131 decodes the rising edge delay amount up[7:0] to obtain the rising edge delay amount selection signal sel[255:0] and the delay block valid signal nohit[7:0].
  • the delay decoder 131 is a decoder with 8 inputs and 256 outputs, and decodes the 8-bit rising edge delay amount into a 256-bit rising edge delay amount selection signal, and only one bit of the rising edge delay is delayed at the same time.
  • the quantity selection signal is valid, and the delay decoder 131 also outputs an 8-bit delay block valid signal.
  • the delay chain includes m successively cascaded delay blocks 132, m is a natural number greater than or equal to 1, and m is set to 8 in this embodiment; the delay chain receives The PWM signal delays the rising edge of the PWM signal based on the rising edge delay amount selection signal sel[255:0] and the delay block valid signal nohit[7:0].
  • the input end of the first stage delay block is connected to the PWM signal
  • the input end of the second stage delay block is connected to the output end of the first stage delay block
  • the input end of the third stage delay block is connected to the output end of the second stage delay block...
  • the input terminal of the eighth stage delay block is connected to the output terminal of the seventh stage delay block; the first stage delay block receives the last eight bits (sel[255:224]) of the rising edge delay amount selection signal and all The last bit (nohit[7]) of the valid signal of the delay block, the second to eighth stage delay blocks respectively receive the delayed eight bits in the rising edge delay amount selection signal and the delay in the valid signal of the delay block , to obtain the corresponding rising edge delay. Further, taking the eighth stage delay block as an example, as shown in FIG.
  • the delay block 132 includes the first to n+1th data selectors 1321 cascaded in sequence, wherein n is a natural number greater than or equal to 1;
  • the first input end of the rear-stage data selector is connected to the output end of the previous-stage data selector, the second input end of each data selector is connected to the PWM signal, and the first input end and the second input end of the first data selector are connected to the PWM signal.
  • the input terminal is connected to the PWM signal, the control terminals from the first data selector to the nth data selector are respectively connected to the corresponding one-bit signal in the delay selection signal, and the n+1th data selector
  • the control terminal of is connected to the corresponding one-bit signal in the effective signal of the delay block; as an example, n is set to 32, and the data selector adopts a two-to-one selector (MUX).
  • the corresponding delay block is selected to add the delay, and when the delay block valid signal (nohit[0]) in the delay block 132 is at a high level
  • the PWM signal is directly output through the last-stage two-to-one selector; when the delay amount selects the signal (sel[0], sel[1]...sel[30] or sel[31])
  • the corresponding two-choice selector is selected to add delay, and when the delay selection signal (sel[0], sel[1]...sel[30] or sel[31]) is high level, it corresponds to two-choice A selector is not selected to output the PWM signal directly.
  • the delay block 132 further includes a buffer stage 1322 connected to the input end of the first data selector, and the PWM signal is input to each data selector after passing through the buffer stage 1322, wherein , the buffer stage 1322 and the n+1 th data selector (the last stage) are inherently delayed, that is, no matter what the amount of delay is, as long as the PWM signal passes through the delay chain, there will be these delays.
  • the input terminal of the AND-OR logic unit 133 is connected to the output terminal of the delay chain and the PWM signal, and performs AND-OR on the output signal of the delay chain and the PWM signal. operation to obtain the delayed signal of the PWM signal.
  • the AND-OR logic unit 133 includes an AND gate and a NOT gate connected to the output end of the AND gate. In actual use, any circuit structure that can realize AND-OR logic is applicable to the present invention. This embodiment is limited.
  • the rising edge delay unit 13a further includes a buffer 134 connected to the input end of the first-stage delay block, and the PWM signal is output to the delay block via the buffer 134 132 and the AND-OR logic unit 133.
  • the buffer 134 and the AND-OR logic unit 133 are inherently delayed.
  • the lengths of the metal lines at the input ends of each data selector in the present invention are equal (or approximately equal, allowing process errors), and the lengths of the metal lines at the output ends are equal (or approximately equal, process error is allowed).
  • the basic unit two-to-one selector used for delay in the present invention has the functions of delay amount and delay amount selection control at the same time. Compared with the prior art, the circuit scale is small, and the inherent delay brought by the selection circuit is short, which is beneficial to PWM Fine control of the signal.
  • the PWM signal may be delayed on the falling edge first, and then delayed on the rising edge.
  • the falling edge delay unit is connected to the output end of the PWM counting module and the control module, and the falling edge delay is performed on the PWM signal based on the falling edge delay amount;
  • the rising edge delay unit is connected to the falling edge
  • the delay unit and the output end of the control module perform a rising edge delay on the PWM signal after the falling edge delay based on the rising edge delay amount; this embodiment is not limited.
  • the output selection module 14 is connected to the output terminals of the control module 11 , the PWM counting module 12 and the delay module 13 , and outputs the PWM counting module 11 or the delay module 13 based on the output selection signal ctl1
  • the output signal of the delay module 12 is used to obtain the output signal PWM' of the high-resolution pulse width modulation signal generating circuit 1 .
  • the output selection module 14 when the rising edge and/or falling edge of the PWM signal needs to be delayed, the output selection module 14 outputs the output signal of the delay module 12; when it is not necessary to delay the rising edge and/or falling edge of the PWM signal /or when the falling edge is delayed, the output selection module 14 outputs the output signal of the PWM counting module 11 .
  • the calibration module 15 is connected to the output end of the control module 11, and receives the count clock ck, and based on the count clock ck, the frequency division signal of the ring oscillation signal calclk of the delay module 13 Carry out counting, and realize the calibration of the delay amount based on the multiple relationship between the ring vibration signal calclk and the counting clock ck, wherein the high level width of the ring vibration signal calclk is the rising edge delay amount in the delay module , the low level width is the preset width.
  • the calibration module 15 includes a ring vibration signal generation unit 151 and a calibration operation unit 152; the ring vibration signal generation unit 151 generates at least two ring vibration signals of different frequencies, each ring vibration signal The high-level widths of the delay modules 13 are selected respectively for different delay amounts, and the low-level width of each ring vibration signal is a preset value; the calibration arithmetic unit 152 divides the ring vibration signal calclk, and based on The counting clock ck counts the frequency-divided signal of the ring oscillation signal calclk and calculates by hardware to obtain the multiple relationship Fcal of the ring oscillation signal calclk and the counting clock ck, that is, the calibration amount, and outputs a calibration completion mark comp, adjust the rising edge delay amount or the falling edge delay amount based on the calibration amount Fcal to achieve high resolution output.
  • the ring vibration signal generating unit 151 includes a delay selection subunit 1511 , a preset delay subunit 1512 , an edge detection subunit 1513 and an RS flip-flop 1514 .
  • the delay selection subunit 1511 is connected to the output end of the RS flip-flop 1514.
  • the delay selection subunit 1511 has the same structure as the rising edge delay unit 13a, and selects different delay pairs based on the calibration control signal ctl2
  • the output signal of the RS flip-flop 1514 is delayed.
  • the delay amount of the delay selection subunit 1511 is set to 256 segments and 128 segments respectively, that is, all or half of the MUXs in the rising edge delay unit 13a are selected to be added to the delay chain, respectively.
  • the delay amount of the delay selection sub-unit 1511 can be set as required, and is not limited to the 256-segment and 128-segment segments in this embodiment.
  • the preset delay subunit 1512 is connected to the output end of the RS flip-flop 1514, and delays the output signal of the RS flip-flop 1514 based on a preset delay amount.
  • the preset delay amount is set based on process conditions, and details are not repeated here.
  • the edge detection subunit 1513 is connected to the output end of the preset delay subunit 1512 , and performs edge detection on the output signal of the preset delay subunit 1512 .
  • the reset terminal RST of the RS flip-flop 1514 is connected to the output terminal of the delay selection subunit 1511, and the set terminal SET is connected to the output terminal of the edge detection subunit 1513, thereby generating the ring oscillation signal calclk.
  • the calibration and calculation of the present invention are all realized by hardware, and the CPU does not need to be used for conversion, thereby reducing the load of the CPU.
  • the high-level width of the ring oscillation signal calclk is determined by the delay selected by the delay selection subunit 1511, and the low-level width is determined by the delay of the preset delay subunit 1512. .
  • 256 segments of delay are selected first, and the 512 frequency division of the ring vibration signal calclk measured by the calibration arithmetic unit 152 (the frequency division value can be set as required, not limited to this embodiment) can be divided into 256 CNTs.
  • the counting clock ck is selected; then 128 delays are selected, and the 512 frequency division of the ring oscillation signal calclk measured by the calibration arithmetic unit 152 can be divided into CNT128 the counting clock ck.
  • Tck is the period of the counting clock ck, and from these two formulas, it can be calculated how many Xs each ck is equal to, and the calibration value Fcal can be obtained:
  • the present invention provides a high-resolution pulse width modulation signal generating circuit, including a control module, a PWM counting module, a delay module, an output selection module and a calibration module;
  • the control module receives a control signal and is used to generate a rising edge delay amount, falling edge delay amount, output selection signal and calibration control signal;
  • the PWM counting module receives a counting clock, and generates a PWM signal based on the counting clock;
  • the delay module is connected to the control module and the PWM counting module The output terminal of the PWM signal is delayed based on the rising edge delay amount and the falling edge delay amount;
  • the output selection module is connected to the output of the control module, the PWM counting module and the delay module terminal, output the output signal of the PWM counting module or the delay module based on the output selection signal;
  • the calibration module is connected to the output terminal of the control module, and receives the counting clock, based on the counting clock The frequency division signal of the ring oscillation signal of the delay module is counted, and the
  • the high-resolution pulse width modulation signal generating circuit of the present invention improves the resolution of the pulse width modulation signal without changing the counting clock, and can be used to adjust the period and duty ratio of the PWM signal.
  • the high-resolution pulse width modulation signal generating circuit of the present invention measures the multiple relationship between the counting clock and the delay chain through the calibration circuit, so that the delay module can be conveniently regarded as the subordinate extension of the PWM counting module, which is convenient for software control and improves the high resolution. rate PWM accuracy.
  • the high-resolution pulse width modulation signal generating circuit of the present invention uses the basic unit device MUX as the minimum delay unit of the delay chain, and is also used as the delay selection logic, which reduces the inherent delay from the input of the delay module to the output of the delay module, which is beneficial to reducing Delay chain error. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

本发明提供一种高分辨率脉冲宽度调制信号产生电路，包括：控制模块，产生上升、下降沿延迟量；PWM计数模块，产生PWM信号；延迟模块，基于上升、下降沿延迟量对PWM信号进行延迟操作；输出选择模块，基于输出选择信号输出PWM计数模块或延迟模块的输出信号；校准模块，基于计数时钟对所述延迟模块的环振信号的分频信号进行计数，并根据环振信号与计数时钟的关系实现延迟量的校准。本发明在不改变计数时钟的情况下提高PWM信号的分辨率；通过计数时钟和迟延链的倍数关系，将延迟模块当作PWM计数模块的下位扩展，方便控制，提高了PWM信号的精度；使用MUX当作迟延链的最小迟延单位和迟延选择逻辑，减小了固有迟延，有利于降低迟延链的误差。

Description

高分辨率脉冲宽度调制信号产生电路 技术领域
本发明涉及集成电路设计领域，特别是涉及一种高分辨率脉冲宽度调制信号产生电路。
背景技术
在开关电源、照明、太阳能逆变器、无线充电器和马达控制中，数字化PWM被用来控制开关功率元件以调节目标电压。随着SiC和GaN半导体技术的发展，开关功率器件的开关频率越来越高，这就对控制系统提出了产生高分辨率PWM信号的要求。
一般来说，对于给定开关频率fswpwm的脉冲宽度调制(Pulse Width Modulation，PWM)信号，其分辨率位数n由计数器的时钟频率fck决定，其计算公式为n＝log 2(fck/fswpwm)。假设，计数时钟频率为100MHz、开关频率为1MHz的PWM信号，它的分辨率为log 2(100/1)＝6.6，也就是说这个PWM信号具有6.6位的分辨率。在很多应用场合，PWM信号的分辨率需要达到10位以上，这时时钟频率fck需要达到fswpwm*2 10＝1024MHz。而时钟频率fck受到工艺制程的限制不能随意提高，比如在1MHz载波频率下实现13位的PWM精度情况下，数字化PWM的计数时钟需要达到8GHz以上的频率，分辨率为122ps，这个指标在一般的集成电路工艺下很难实现，因此，工艺制程能力对计数器时钟频率的限制与PWM的高分辨率需求形成了矛盾。
如何进一步提高PWM信号的精度、减小误差，已成为本领域技术人员亟待解决的问题之一。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种高分辨率脉冲宽度调制信号产生电路，用于解决现有技术中PWM信号的精度受限于时钟频率的问题。
为实现上述目的及其他相关目的，本发明提供一种高分辨率脉冲宽度调制信号产生电路，所述高分辨率脉冲宽度调制信号产生电路至少包括：
控制模块、PWM计数模块、延迟模块、输出选择模块及校准模块；
所述控制模块接收控制信号，用于产生上升沿延迟量、下降沿延迟量、输出选择信号及校准控制信号；
所述PWM计数模块接收计数时钟，基于所述计数时钟产生PWM信号；
所述延迟模块连接所述控制模块及所述PWM计数模块的输出端，基于所述上升沿延迟 量和所述下降沿延迟量对所述PWM信号进行延迟操作；
所述输出选择模块连接所述控制模块、所述PWM计数模块及所述延迟模块的输出端，基于所述输出选择信号输出所述PWM计数模块或所述延迟模块的输出信号；
所述校准模块连接所述控制模块的输出端，并接收所述计数时钟，基于所述计数时钟对所述延迟模块的环振信号的分频信号进行计数，并基于所述环振信号与所述计数时钟的倍数关系实现延迟量的校准，其中，所述环振信号的高电平宽度为所述延迟模块中的上升沿延迟量，低电平宽度为预设宽度。
可选地，所述控制模块包括延迟量选择寄存器，基于所述延迟量选择寄存器输出所述上升沿延迟量及所述下降沿延迟量。
可选地，所述PWM计数模块包括计数单元及比较单元；所述计数单元接收所述计数时钟，对所述计数时钟进行计数并输出计数值；所述比较单元连接所述计数单元的输出端，将所述计数值与预设值进行比较，当所述计数值到达所述预设值时翻转电平以得到所述PWM信号。
更可选地，所述PWM计数模块还接收相位调整控制信号，所述相位调整控制信号连接所述比较单元，通过改变所述预设值实现对所述PWM信号相位的调整，进而实现脉冲频率调制功能。
可选地，所述延迟模块包括上升沿延迟单元及下降沿延迟单元；
所述上升沿延迟单元连接所述PWM计数模块及所述控制模块的输出端，基于所述上升沿延迟量对所述PWM信号进行上升沿延迟；所述下降沿延迟单元连接所述上升沿延迟单元及所述控制模块的输出端，基于所述下降沿延迟量对上升沿延迟后的PWM信号进行下降沿延迟；
或者，所述下降沿延迟单元连接所述PWM计数模块及所述控制模块的输出端，基于所述下降沿延迟量对所述PWM信号进行下降沿延迟；所述上升沿延迟单元连接所述下降沿延迟单元及所述控制模块的输出端，基于所述上升沿延迟量对下降沿延迟后的PWM信号进行上升沿延迟。
更可选地，所述上升沿延迟单元及所述下降沿延迟单元均包括延迟译码器、m个依次级联的延迟块构成的延迟链及与或逻辑单元；
所述延迟译码器将延迟量译码得到延迟量选择信号及延迟块有效信号；
所述延迟链接收所述PWM信号，所述延迟链中各延迟块接收所述延迟量选择信号及所述延迟块有效信号，基于所述延迟量选择信号及所述延迟块有效信号对所述PWM信号进行 延迟；
所述与或逻辑单元的输入端连接所述延迟链的输出端及所述PWM信号，对所述延迟链的输出信号及所述PWM信号进行与或运算，得到所述PWM信号的延迟信号；
其中，m为大于等于1的自然数。
可选地，所述延迟块包括依次级联的第一至第n+1数据选择器，后级数据选择器的第一输入端连接前级数据选择器的输出端，各数据选择器的第二输入端连接所述PWM信号，所述第一数据选择器的第一输入端及第二输入端连接所述PWM信号，所述第一数据选择器至所述第n数据选择器的控制端分别连接对应的延迟量选择信号，所述第n+1数据选择器的控制端连接对应的延迟块有效信号，其中，n为大于等于1的自然数。
更可选地，所述数据选择器为二选一选择器。
更可选地，所述校准模块包括环振信号产生单元及校准运算单元，所述环振信号产生单元产生至少两个不同频率的环振信号，各环振信号的高电平宽度分别选择所述延迟模块的不同延迟量，各环振信号的低电平宽度为预设宽度；所述校准运算单元对所述环振信号进行分频，并基于所述计数时钟对所述环振信号的分频信号进行计数，得到所述环振信号与所述计数时钟的倍数关系。
可选地，所述环振信号产生单元包括延迟选择子单元、预设延迟子单元、边沿检测子单元及RS触发器；
所述延迟选择子单元连接所述RS触发器的输出端，所述延迟选择子单元与所述上升沿延迟单元的结构相同，基于所述校准控制信号选择不同的延迟量对所述RS触发器的输出信号进行延迟；
所述预设延迟子单元连接所述RS触发器的输出端，基于预设延迟量对所述RS触发器的输出信号进行延迟；
所述边沿检测子单元连接所述预设延迟单元的输出端，对所述预设延迟子单元的输出信号进行边沿检测；
所述RS触发器的复位端连接所述延迟选择子单元的输出端，置位端连接所述边沿检测子单元的输出端，产生所述环振信号。
如上所述，本发明的高分辨率脉冲宽度调制信号产生电路，具有以下有益效果：
1.本发明的高分辨率脉冲宽度调制信号产生电路在不改变计数时钟的情况下，提高脉冲宽度调制信号的分辨率，可以用于调整PWM信号的周期和占空比。
2.本发明的高分辨率脉冲宽度调制信号产生电路通过校准电路测量出计数时钟和迟延链 的倍数关系，可以比较方便得将延迟模块当作PWM计数模块的下位扩展，方便软件控制，提高了高分辨率PWM的精度。
3.本发明的高分辨率脉冲宽度调制信号产生电路使用基本单元器件MUX当作迟延链的最小迟延单位，兼用作迟延选择逻辑，减小了从延迟模块输入到延迟模块输出的固有迟延，有利于降低迟延链的误差。
附图说明
图1显示为本发明的高分辨率脉冲宽度调制信号产生电路的结构示意图。
图2显示为本发明的PWM计数模块的结构示意图。
图3显示为本发明的上升沿延迟单元的结构示意图。
图4显示为本发明的延迟块的结构示意图。
图5显示为本发明的校准模块的结构示意图。
元件标号说明
1                      高分辨率脉冲宽度调制信号产生电路
11                     控制模块
12                     PWM计数模块
121                    计数单元
122                    比较单元
13                     延迟模块
13a                    上升沿延迟单元
13b                    下降沿延迟单元
131                    延迟译码器
132                    延迟块
1321                   数据选择器
1322                   缓冲级
133                    与或逻辑单元
134                    缓冲器
14                     输出选择模块
15                     校准模块
151                    环振信号产生单元
1511                   延迟选择子单元
1512                   预设延迟子单元
1513                   边沿检测子单元
1514                   RS触发器
152                    校准运算单元
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1～图5。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1所示，本发明提供一种高分辨率脉冲宽度调制信号产生电路1，所述高分辨率脉冲宽度调制信号产生电路1包括：
控制模块11、PWM计数模块12、延迟模块13、输出选择模块14及校准模块15。
如图1所示，所述控制模块11接收控制信号，用于产生上升沿延迟量up[7:0]、下降沿延迟量down[7:0]、输出选择信号ctl1及校准控制信号ctl2。
具体地，所述控制模块11包括但不限于延迟量选择寄存器、输出控制单元及校准控制单元(图中未显示)，任意用于控制所述高分辨率脉冲宽度调制信号产生电路1中各模块工作的控制信号均可通过所述控制模块11产生。其中，所述上升沿延迟量up[7:0]及所述下降沿延迟量down[7:0]的选择通过改变所述延迟量选择寄存器实现，基于寄存器的特性，在PWM信号的边沿发生变化时，所述延迟量选择寄存器的输出值不会马上发生改变，从而可免除高分辨率的PWM信号的输出产生竞争。
具体地，在本实施例中，所述控制模块11还接收计数时钟ck作为工作时钟，在实际使用中可根据需要设置所述控制模块11的工作时钟的来源，不以本实施例为限。
需要说明的是，作为示例，所述上升沿延迟量up[7:0]及所述下降沿延迟量down[7:0]为8 位总线信号。在实际使用中可根据需要设置所述上升沿延迟量及所述下降沿延迟量的位数，不以本实施例为限。
如图1所示，所述PWM计数模块12接收所述计数时钟ck，基于所述计数时钟ck产生PWM信号。
具体地，如图2所示，在本实施例中，所述PWM计数模块12包括计数单元121及比较单元122。所述计数单元121接收所述计数时钟ck，对所述计数时钟ck进行计数并输出计数值。所述比较单元122连接所述计数单元121的输出端，将所述计数值与预设值(比较阈值)进行比较，当所述计数值到达所述预设值时翻转电平以得到所述PWM信号。
需要说明的是，任意可产生PWM波形的电路结构均适用于本发明，不以本实施例为限。
作为本发明的另一种实现方式，所述PWM计数模块11还接收相位调整控制信号ctl3，作为示例，所述相位调整控制信号ctl3由所述控制模块11提供；所述相位调整控制信号ctl3连接所述比较单元122，通过改变所述预设值实现对所述PWM信号相位的调整，进而实现脉冲频率调制(Pulse Frequency Modulation，PFM)功能。
如图1所示，所述延迟模块13连接所述控制模块11及所述PWM计数模块12的输出端，基于所述上升沿延迟量up[7:0]和所述下降沿延迟量down[7:0]对所述PWM信号进行延迟操作。
具体地，如图1所示，所述延迟模块13包括上升沿延迟单元13a及下降沿延迟单元13b。在本实施例中，所述上升沿延迟单元13a连接所述PWM计数模块12及所述控制模块11的输出端，基于所述上升沿延迟量up[7:0]对所述PWM信号进行上升沿延迟；所述下降沿延迟单元13b连接所述上升沿延迟单元13a及所述控制模块11的输出端，基于所述下降沿延迟量down[7:0]对上升沿延迟后的PWM信号进行下降沿延迟。在本实施例中，所述上升沿延迟单元13a及所述下降沿延迟单元13b的结构相同，均包括延迟译码器131、m个依次级联的延迟块132构成的延迟链及与或逻辑单元133。本实施中以所述上升沿延迟单元13a为例，所述下降沿延迟单元13b与所述上升沿延迟单元13a的差别仅在于接收不同的延迟量(上升沿延迟单元接收上升沿延迟量，下降沿延迟单元接收下降沿延迟量)，且延迟的对象不同(上升沿延迟单元对上升沿进行延迟，下降沿延迟单元对下降沿进行延迟)，在此不一一赘述。
更具体地，如图3所示，所述延迟译码器131将所述上升沿延迟量up[7:0]译码得到上升沿延迟量选择信号sel[255:0]及延迟块有效信号nohit[7:0]。在本实施例中，所述延迟译码器131为8输入256输出的译码器，将8位上升沿延迟量译码为256位上升沿延迟量选择信号，同一时刻仅一位上升沿延迟量选择信号有效，所述延迟译码器131还输出8位延迟块有效信 号。
更具体地，如图3所示，所述延迟链包括m个依次级联的延迟块132，m为大于等于1的自然数，在本实施例中m设定为8个；所述延迟链接收所述PWM信号，基于所述上升沿延迟量选择信号sel[255:0]及所述延迟块有效信号nohit[7:0]对所述PWM信号的上升沿进行延迟。第一级延迟块的输入端连接所述PWM信号，第二级延迟块的输入端连接第一级延迟块的输出端，第三级延迟块的输入端连接第二级延迟块的输出端……依次类推，第八级延迟块的输入端连接第七级延迟块的输出端；第一级延迟块接收所述上升沿延迟量选择信号的最后八位(sel[255:224])及所述延迟块有效信号的最后一位(nohit[7])，第二级至第八级延迟块分别接收所述上升沿延迟量选择信号中顺延的八位及所述延迟块有效信号中的顺延的一位，以此获取对应的上升沿延迟。进一步地，以第八级延迟块为例，如图4所示，所述延迟块132包括依次级联的第一至第n+1数据选择器1321，其中，n为大于等于1的自然数；后级数据选择器的第一输入端连接前级数据选择器的输出端，各数据选择器的第二输入端连接所述PWM信号，所述第一数据选择器的第一输入端及第二输入端连接所述PWM信号，所述第一数据选择器至所述第n数据选择器的控制端分别连接所述延迟量选择信号中对应的一位信号，所述第n+1数据选择器的控制端连接所述延迟块有效信号中对应的一位信号；作为示例，n设定为32个，所述数据选择器采用二选一选择器(MUX)。当所述延迟块132中延迟块有效信号(nohit[0])为低电平时对应延迟块被选中加入延迟，当所述延迟块132中延迟块有效信号(nohit[0])为高电平时对应延迟块未被选中所述PWM信号直接通过最后一级二选一选择器输出；当所述延迟量选择信号(sel[0]、sel[1]…sel[30]或sel[31])为低电平时对应二选一选择器被选中加入延迟，当所述延迟量选择信号(sel[0]、sel[1]…sel[30]或sel[31])为高电平时对应二选一选择器未被选中直接输出所述PWM信号。作为本发明的另一种实现方式，所述延迟块132还包括连接于所述第一数据选择器输入端的缓冲级1322，所述PWM信号经过所述缓冲级1322后输入各数据选择器，其中，所述缓冲级1322及第n+1数据选择器(最后一级)为固有延迟，即无论延迟量为多少，只要所述PWM信号经过所述延迟链就会存在这些延迟。
更具体地，如图3所示，所述与或逻辑单元133的输入端连接所述延迟链的输出端及所述PWM信号，对所述延迟链的输出信号及所述PWM信号进行与或运算，得到所述PWM信号的延迟信号。在本实施例中，所述与或逻辑单元133包括与门及连接于所述与门输出端的非门，在实际使用中，任意可实现与或逻辑的电路结构均适用于本发明，不以本实施例为限。
作为本发明的另一种实现方式，所述上升沿延迟单元13a还包括连接于所述第一级延迟 块输入端的缓冲器134，所述PWM信号经由所述缓冲器134输出到所述延迟块132及所述与或逻辑单元133。所述缓冲器134及所述与或逻辑单元133为固有延迟。
需要说明的是，为了减小每段迟延之间的误差，本发明中各数据选择器输入端的金属线长度相等(或近似相等，允许工艺误差)、输出端的金属线长度相等(或近似相等，允许工艺误差)。本发明中用于延迟的基本单元二选一选择器同时具有迟延量和迟延量选择控制的作用，相比于现有技术，电路规模小，由选择电路带来的固有迟延短，有利于PWM信号的精细控制。
需要说明的是，在实际使用中可先对所述PWM信号进行下降沿延迟，而后再进行上升沿延迟。则所述下降沿延迟单元连接所述PWM计数模块及所述控制模块的输出端，基于所述下降沿延迟量对所述PWM信号进行下降沿延迟；所述上升沿延迟单元连接所述下降沿延迟单元及所述控制模块的输出端，基于所述上升沿延迟量对下降沿延迟后的PWM信号进行上升沿延迟；不以本实施例为限。
如图1所示，所述输出选择模块14连接所述控制模块11、所述PWM计数模块12及所述延迟模块13的输出端，基于所述输出选择信号ctl1输出所述PWM计数模块11或所述延迟模块12的输出信号，以得到所述高分辨率脉冲宽度调制信号产生电路1的输出信号PWM’。
具体地，当需要对所述PWM信号的上升沿和/或下降沿进行延迟时，所述输出选择模块14输出所述延迟模块12的输出信号；当不需要对所述PWM信号的上升沿和/或下降沿进行延迟时，所述输出选择模块14输出所述PWM计数模块11的输出信号。
如图1所示，所述校准模块15连接所述控制模块11的输出端，并接收所述计数时钟ck，基于所述计数时钟ck对所述延迟模块13的环振信号calclk的分频信号进行计数，并基于所述环振信号calclk与所述计数时钟ck的倍数关系实现延迟量的校准，其中，所述环振信号calclk的高电平宽度为所述延迟模块中的上升沿延迟量，低电平宽度为预设宽度。
具体地，在本实施例中，所述校准模块15包括环振信号产生单元151及校准运算单元152；所述环振信号产生单元151产生至少两个不同频率的环振信号，各环振信号的高电平宽度分别选择所述延迟模块13的不同延迟量，各环振信号的低电平宽度为预设值；所述校准运算单元152对所述环振信号calclk进行分频，并基于所述计数时钟ck对所述环振信号calclk的分频信号进行计数并通过硬件计算，得到所述环振信号calclk与所述计数时钟ck的倍数关系Fcal，即校准量，并输出校准完成标志comp，基于所述校准量Fcal调整所述上升沿延迟量或所述下降沿延迟量以实现高分辨率输出。
更具体地，所述环振信号产生单元151包括延迟选择子单元1511、预设延迟子单元1512、 边沿检测子单元1513及RS触发器1514。所述延迟选择子单元1511连接所述RS触发器1514的输出端，所述延迟选择子单元1511与所述上升沿延迟单元13a的结构相同，基于所述校准控制信号ctl2选择不同的延迟量对所述RS触发器1514的输出信号进行延迟。作为示例，在本实施例中，将所述延迟选择子单元1511的延迟量分别设置为256段和128段，即分别选择所述上升沿延迟单元13a中全部MUX或一半MUX加入延迟链，在实际使用中可根据需要设置所述延迟选择子单元1511的延迟量，不以本实施例的256段和128段为限。所述预设延迟子单元1512连接所述RS触发器1514的输出端，基于预设延迟量对所述RS触发器1514的输出信号进行延迟。所述预设延迟量基于工艺条件进行设置，在此不一一赘述。所述边沿检测子单元1513连接所述预设延迟子单元1512的输出端，对所述预设延迟子单元1512的输出信号进行边沿检测。所述RS触发器1514的复位端RST连接所述延迟选择子单元1511的输出端，置位端SET连接所述边沿检测子单元1513的输出端，进而产生所述环振信号calclk。
更具体地，所述校准模块15使用所述计数时钟ck对所述环振信号calclk进行校准，以计数时钟ck为基准，测量出所述计数时钟ck与所述环振信号calclk的倍数关系(fck＝Fcal*X，其中X为1段的迟延量，Fcal为校准量)，进而基于所述计数时钟ck与所述环振信号calclk的关系对所述高分辨率脉冲宽度调制信号产生电路1的输出信号进行补偿，产生高分辨率的PWM信号。本发明的校准及运算全部通过硬件实现，不需要使用CPU进行换算，降低CPU的负荷。在所述校准模块15中，所述环振信号calclk的高电平宽度由所述延迟选择子单元1511选择的迟延量确定，低电平宽度由所述预设延迟子单元1512的迟延量确定。作为示例，首先选择256段迟延，通过所述校准运算单元152测得所述环振信号calclk的512分频(分频数值可根据需要设置，不以本实施例为限)可以分成CNT256个所述计数时钟ck；再选择128段迟延，通过所述校准运算单元152测得所述环振信号calclk的512分频可以分成CNT128个所述计数时钟ck。
设每段迟延为X，固有迟延为DLY，那么得到以下式子：
(256X+DLY)*512＝Tck*CNT256  (1)
(128X+DLY)*512＝Tck*CNT128  (2)
其中，Tck为所述计数时钟ck的周期，由这两个式子可以计算出每个ck等于多少个X，得到校准量Fcal满足：
Fcal＝Tck/x＝512*128/(CNT256-CNT128)。
综上所述，本发明提供一种高分辨率脉冲宽度调制信号产生电路，包括控制模块、PWM计数模块、延迟模块、输出选择模块及校准模块；所述控制模块接收控制信号，用于产生上升沿延迟量、下降沿延迟量、输出选择信号及校准控制信号；所述PWM计数模块接收计数 时钟，基于所述计数时钟产生PWM信号；所述延迟模块连接所述控制模块及所述PWM计数模块的输出端，基于所述上升沿延迟量和所述下降沿延迟量对所述PWM信号进行延迟操作；所述输出选择模块连接所述控制模块、所述PWM计数模块及所述延迟模块的输出端，基于所述输出选择信号输出所述PWM计数模块或所述延迟模块的输出信号；所述校准模块连接所述控制模块的输出端，并接收所述计数时钟，基于所述计数时钟对所述延迟模块的环振信号的分频信号进行计数，并基于所述环振信号与所述计数时钟的倍数关系实现延迟量的校准，其中，所述环振信号的高电平宽度为所述延迟模块中的上升沿延迟量，低电平宽度为预设宽度。本发明的高分辨率脉冲宽度调制信号产生电路在不改变计数时钟的情况下，提高脉冲宽度调制信号的分辨率，可以用于调整PWM信号的周期和占空比。本发明的高分辨率脉冲宽度调制信号产生电路通过校准电路测量出计数时钟和迟延链的倍数关系，可以比较方便得将延迟模块当作PWM计数模块的下位扩展，方便软件控制，提高了高分辨率PWM的精度。本发明的高分辨率脉冲宽度调制信号产生电路使用基本单元器件MUX当作迟延链的最小迟延单位，兼用作迟延选择逻辑，减小了从延迟模块输入到延迟模块输出的固有迟延，有利于降低迟延链的误差。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种高分辨率脉冲宽度调制信号产生电路，其特征在于，所述高分辨率脉冲宽度调制信号产生电路至少包括：
    控制模块、PWM计数模块、延迟模块、输出选择模块及校准模块；
    所述控制模块接收控制信号，用于产生上升沿延迟量、下降沿延迟量、输出选择信号及校准控制信号；
    所述PWM计数模块接收计数时钟，基于所述计数时钟产生PWM信号；
    所述延迟模块连接所述控制模块及所述PWM计数模块的输出端，基于所述上升沿延迟量和所述下降沿延迟量对所述PWM信号进行延迟操作；
    所述输出选择模块连接所述控制模块、所述PWM计数模块及所述延迟模块的输出端，基于所述输出选择信号输出所述PWM计数模块或所述延迟模块的输出信号；
    所述校准模块连接所述控制模块的输出端，并接收所述计数时钟，基于所述计数时钟对所述延迟模块的环振信号的分频信号进行计数，并基于所述环振信号与所述计数时钟的倍数关系实现延迟量的校准，其中，所述环振信号的高电平宽度为所述延迟模块中的上升沿延迟量，低电平宽度为预设宽度。
  2. 根据权利要求1所述的高分辨率脉冲宽度调制信号产生电路，其特征在于：所述控制模块包括延迟量选择寄存器，基于所述延迟量选择寄存器输出所述上升沿延迟量及所述下降沿延迟量。
  3. 根据权利要求1所述的高分辨率脉冲宽度调制信号产生电路，其特征在于：所述PWM计数模块包括计数单元及比较单元；所述计数单元接收所述计数时钟，对所述计数时钟进行计数并输出计数值；所述比较单元连接所述计数单元的输出端，将所述计数值与预设值进行比较，当所述计数值到达所述预设值时翻转电平以得到所述PWM信号。
  4. 根据权利要求3所述的高分辨率脉冲宽度调制信号产生电路，其特征在于：所述PWM计数模块还接收相位调整控制信号，所述相位调整控制信号连接所述比较单元，通过改变所述预设值实现对所述PWM信号相位的调整，进而实现脉冲频率调制功能。
  5. 根据权利要求1所述的高分辨率脉冲宽度调制信号产生电路，其特征在于：所述延迟模块包括上升沿延迟单元及下降沿延迟单元；
    所述上升沿延迟单元连接所述PWM计数模块及所述控制模块的输出端，基于所述上 升沿延迟量对所述PWM信号进行上升沿延迟；所述下降沿延迟单元连接所述上升沿延迟单元及所述控制模块的输出端，基于所述下降沿延迟量对上升沿延迟后的PWM信号进行下降沿延迟；
    或者，所述下降沿延迟单元连接所述PWM计数模块及所述控制模块的输出端，基于所述下降沿延迟量对所述PWM信号进行下降沿延迟；所述上升沿延迟单元连接所述下降沿延迟单元及所述控制模块的输出端，基于所述上升沿延迟量对下降沿延迟后的PWM信号进行上升沿延迟。
  6. 根据权利要求5所述的高分辨率脉冲宽度调制信号产生电路，其特征在于：所述上升沿延迟单元及所述下降沿延迟单元均包括延迟译码器、m个依次级联的延迟块构成的延迟链及与或逻辑单元；
    所述延迟译码器将延迟量译码得到延迟量选择信号及延迟块有效信号；
    所述延迟链接收所述PWM信号，所述延迟链中各延迟块接收所述延迟量选择信号及所述延迟块有效信号，基于所述延迟量选择信号及所述延迟块有效信号对所述PWM信号进行延迟；
    所述与或逻辑单元的输入端连接所述延迟链的输出端及所述PWM信号，对所述延迟链的输出信号及所述PWM信号进行与或运算，得到所述PWM信号的延迟信号；
    其中，m为大于等于1的自然数。
  7. 根据权利要求6所述的高分辨率脉冲宽度调制信号产生电路，其特征在于：所述延迟块包括依次级联的第一至第n+1数据选择器，后级数据选择器的第一输入端连接前级数据选择器的输出端，各数据选择器的第二输入端连接所述PWM信号，所述第一数据选择器的第一输入端及第二输入端连接所述PWM信号，所述第一数据选择器至所述第n数据选择器的控制端分别连接对应的延迟量选择信号，所述第n+1数据选择器的控制端连接对应的延迟块有效信号，其中，n为大于等于1的自然数。
  8. 根据权利要求7所述的高分辨率脉冲宽度调制信号产生电路，其特征在于：所述数据选择器为二选一选择器。
  9. 根据权利要求5～8任意一项所述的高分辨率脉冲宽度调制信号产生电路，其特征在于：所述校准模块包括环振信号产生单元及校准运算单元，所述环振信号产生单元产生至少两个 不同频率的环振信号，各环振信号的高电平宽度分别选择所述延迟模块的不同延迟量，各环振信号的低电平宽度为预设宽度；所述校准运算单元对所述环振信号进行分频，并基于所述计数时钟对所述环振信号的分频信号进行计数，得到所述环振信号与所述计数时钟的倍数关系。
  10. 根据权利要求9所述的高分辨率脉冲宽度调制信号产生电路，其特征在于：所述环振信号产生单元包括延迟选择子单元、预设延迟子单元、边沿检测子单元及RS触发器；
    所述延迟选择子单元连接所述RS触发器的输出端，所述延迟选择子单元与所述上升沿延迟单元的结构相同，基于所述校准控制信号选择不同的延迟量对所述RS触发器的输出信号进行延迟；
    所述预设延迟子单元连接所述RS触发器的输出端，基于预设延迟量对所述RS触发器的输出信号进行延迟；
    所述边沿检测子单元连接所述预设延迟单元的输出端，对所述预设延迟子单元的输出信号进行边沿检测；
    所述RS触发器的复位端连接所述延迟选择子单元的输出端，置位端连接所述边沿检测子单元的输出端，产生所述环振信号。
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