WO2022120940A1 - 单调计数器及其计数方法 - Google Patents

单调计数器及其计数方法 Download PDF

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Publication number
WO2022120940A1
WO2022120940A1 PCT/CN2020/138227 CN2020138227W WO2022120940A1 WO 2022120940 A1 WO2022120940 A1 WO 2022120940A1 CN 2020138227 W CN2020138227 W CN 2020138227W WO 2022120940 A1 WO2022120940 A1 WO 2022120940A1
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Prior art keywords
storage block
data
bit
current
current storage
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PCT/CN2020/138227
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English (en)
French (fr)
Inventor
卢中舟
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武汉新芯集成电路制造有限公司
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Publication of WO2022120940A1 publication Critical patent/WO2022120940A1/zh
Priority to US18/328,741 priority Critical patent/US20230315318A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
    • H03K21/403—Arrangements for storing the counting state in case of power supply interruption

Definitions

  • the invention relates to the technical field of communication, in particular to a monotone counter and a counting method thereof.
  • the Replay Protection Monotonic Counter refers to a counter with a monotonic counting function. After the data recorded in the Replay Protection Monotonic Counter is responded, the Replay Protection Monotonic Counter will only increase monotonically with the change of the count value.
  • the response protection monotonic counter is combined with FLASH (flash memory) to ensure the confidentiality and integrity of read and write data during data storage.
  • FLASH flash memory
  • the response protection monotonic counter is combined with FLASH to determine the number of times of memory storage.
  • a count value is added to the monotonic counter, thus providing a complete data record for FLASH to read and write data times.
  • the data is counted monotonically to ensure the non-repetition of the data, which in turn can improve the confidentiality of the data transmission.
  • the present invention provides a monotonic counter and a counting method thereof, which effectively prevent the problem of errors in the counting operation of the monotonic counter when an abnormal situation occurs.
  • the present invention provides a monotonic counter, the monotonic counter includes a controller and a plurality of storage blocks, the storage blocks include count base bits, identification bits, check bits, and data bits for storing count data , there is one current storage block in the plurality of storage blocks, wherein the controller includes:
  • an interrupt recording module used to record the interrupt that occurs in the monotonic counter
  • the logic judgment module is used for judging whether the data bits of the current storage block are full after the interrupt occurs in the monotonic counter and the power-on reset occurs, and when the data bits are not full, in the Write data again into the data bit of the last stored count data of the current storage block.
  • the rewriting of data includes supplementary writing or rewriting in the data bits.
  • the logic judging module is also used to judge whether to switch another storage block to the current storage block when the data bits are full, and when the switching has been carried out, to the current storage before the switching. Blocks are erased.
  • the logic judgment module is also used for rewriting data in the data bit of the last stored count data of the current storage block or after erasing the current storage block before the switching, Write data into the first data bit in the current storage block that does not store count data for counting.
  • the logic judging module is also used to judge whether the current storage block before the switching has been erased before the current storage block before the switching is erased, and when the erasing is not performed. During the process, the parity bit of the current storage block before the switching is destroyed, so that the parity bit is inconsistent with the parity bit of the current storage block after the switching.
  • the destruction includes rewriting the parity bit of the current storage block before the switching.
  • the logic judging module is further configured to switch the other storage block to the current storage block when the switching is not performed.
  • the logic judgment module is also used to write the current count value into the count base bit of the current memory block after the switch before the destruction and/or after the switch, and in the The check bit and the identification bit are written in the switched current storage block.
  • the current count value is the sum of the data bits of the current storage block and the data recorded by the count base bits.
  • the interruption includes the occurrence of power down or reset.
  • the present invention also provides a counting method for a monotonic counter, wherein the monotonic counter includes a plurality of storage blocks, and the storage blocks include a count base bit, an identification bit, a check bit, and a count bit for storing count data. data bits, there is one current storage block in the plurality of storage blocks, and the counting method includes:
  • the first judgment step is to judge whether the data bits of the current storage block are full
  • the rewriting of data includes supplementary writing or rewriting in the data bits.
  • the first judging step it also includes:
  • the current storage block before the switching is erased.
  • the erasing step or the rewriting step it also includes:
  • the erasing step it also includes:
  • the third judgment step is to judge whether the current memory block before the switching has been erased
  • Destruction step when the result of the third judgment step indicates that the current storage block before the switch has not been erased, destroy the check bit of the current storage block before the switch, so that the check bit is the same as that of the current storage block before the switch.
  • the check bits of the switched current memory block are inconsistent.
  • the destruction includes rewriting the parity bit of the current storage block before the switching.
  • the second judging step it also includes:
  • the destroying step is performed to destroy the check bit of the current storage block before the switch, so that the check bit is inconsistent with the check bit of the current storage block after the switch.
  • the destruction step and/or after the switching step it also includes:
  • the current count value is written into the count base bit of the switched current storage block, and the check bit and the identification bit are written into the switched current storage block.
  • the current count value is the sum of the data bits of the current storage block and the data recorded by the count base bits.
  • the interruption includes the occurrence of power down or reset.
  • the present invention provides a monotonic counter, comprising a controller and a plurality of storage blocks, the storage block includes a count base bit, an identification bit, a check bit, and a data bit for storing count data, and the plurality of storage blocks have a current A storage block, wherein the controller includes: an interrupt recording module for recording the interruption of the monotonic counter, and for judging whether the data bits of the current storage block are full after the monotonic counter is interrupted and power-on reset, and when When the data bits are not full, the logic judgment module that rewrites the data in the last data bit of the current storage block that has stored count data, so that when an abnormal situation occurs in the monotonic counter, the count data recorded by the monotonic counter can be guaranteed. It is completely written, which can effectively prevent the monotonic counter from causing errors in its counting operation due to abnormal conditions.
  • FIG. 1 is a schematic structural diagram of a monotonic counter provided by an embodiment of the present invention.
  • FIG. 2 is a schematic flowchart of a counting method for a monotonic counter provided by an embodiment of the present invention.
  • FIG. 3 is a further schematic flowchart of the counting method of the monotonic counter provided by the embodiment of the present invention.
  • the present invention aims at the problem of the response protection monotonic counter in the prior art, when an abnormal situation occurs, the counting operation of the response protection monotonic counter is wrong, and the embodiment according to the invention is used to solve the problem.
  • the response protection monotonic counter is interrupted due to an abnormal condition, after it is powered on and reset, some measures need to be taken to prevent the response protection monotonic counter from being read abnormally in the future.
  • the internal memory block for counting operation will have four possible working states, namely: 1. The current memory block that is counting is not full; 2. The counting is in progress The current memory block is full, but the new memory block has not been switched to continue counting; 3. The new memory block has been switched to continue counting, but the full memory block has not yet been erased; 4. The new memory block has been switched The memory block continues to be counted, and the operation of erasing the full memory block is in progress.
  • the present invention proposes the following measures.
  • FIG. 1 is a schematic structural diagram of a monotonic counter 100 according to an embodiment of the present invention. From FIG. 1, it can be known that each component of the embodiment according to the present invention and the relative position of each component are relation.
  • the monotonic counter 100 includes a controller 110 and a plurality of storage blocks 120 , and each storage block 120 includes a count base bit 121 , an identification bit 122 , a check bit 123 and a plurality of storage blocks for storing count data. data bits 124, and there is one current storage block in the plurality of storage blocks 120, wherein the controller 110 may specifically include:
  • Interrupt recording module 111 the interrupt recording module 111 is used to record the interruption that occurs in the monotonic counter 100;
  • the logic judgment module 112 is used for judging whether the data bit 124 of the current storage block is full after the monotonic counter 100 is interrupted and power-on reset, and when the data bit 124 is not full, in the current storage Data is written again in data bit 124 of the last stored count data of the block.
  • the monotonic counter 100 is used to ensure the confidentiality and integrity of its corresponding memory read and write data, and the count data in the monotonic counter 100 can be monotonically incremented.
  • the data bits 124 can record a limited number of values. Therefore, when the count value in a memory block 120 in the monotonic counter 100 reaches the upper limit, it will switch to a storage that has not been counted, or that has been counted but the count data has been erased. Block 120 continues counting.
  • the count data of the memory block 120 before the switch must be saved in the memory block 120 after the switch, as the basis for the counting of the memory block 120 after the switch, and the memory block 120 after the switch will be in the Continue to count on the basis of this count, and the count base bit 121 is used to record the count data counted when the previous current storage block is full and switched;
  • the data recorded in the identification bit 122 is used to represent whether the memory block 120 needs to be erased and programmed. Specifically, the identification bit 122 has only two data states, and one data state indicates that the memory block 120 needs to be erased and programmed. (such as 00), a data state indicating that the memory block 120 has been erased and programmed, and does not need to be erased and programmed again (such as FF);
  • the validity of the check bit 123 is used to represent whether the data in the count base bit 121 and the identification bit 122 of the storage block 120 are valid. Specifically, the counting base bit 121 and the identification bit 122 are subjected to some check operation (such as addition operation, parity operation, XOR operation or cyclic redundancy check (cyclic redundancy check).
  • some check operation such as addition operation, parity operation, XOR operation or cyclic redundancy check (cyclic redundancy check).
  • redundancy check operation
  • the check digit 123 is valid, that is, the storage block corresponding to the check digit 123
  • the data in 120 is valid, no abnormality occurs, and it also indicates that the storage block is the current storage block; and if the two values are not equal, it means that the check digit 123 is invalid, that is, the storage block 120 corresponding to the check digit 123 is invalid.
  • the data in is invalid, or an exception occurs, which also indicates that the storage block is not the current storage block;
  • the data bit 124 is a unit for storing count data.
  • each storage block 120 includes a plurality of data bits 124 .
  • the data bit 124 can use n zeros to represent the count value of the monotonic counter 100 plus 1.
  • the logic judgment module 112 determines that the data bit 124 is not full, it will count the last stored value of the current storage block.
  • the data is rewritten in the data bit 124 of the data, and the way of rewriting the data may include supplementary writing or rewriting in the data bit 124, with n being 8, and before the monotonic counter 100 is interrupted, the last stored count
  • the data bit 124 of the data has been written with 3 0s as an example: A.
  • the logic judgment module 112 will write data in the first data bit 124 that does not store count data in the current storage block. count.
  • the logic judging module 112 can ensure that when the monotonic counter 100 is interrupted, if the storage block 120 in the monotonic counter 100 is in the aforementioned "1" (1, the current storage block that is being counted is not full ) state, after the monotonic counter 100 is powered on, the read and write operations of the monotonic counter 100 will not be abnormal.
  • the storage block 120 in the monotonic counter 100 is in the aforementioned "2" (2.
  • the current storage block that is being counted is full, but the new storage block has not been switched to continue counting)
  • the embodiment according to the present invention has the following solutions:
  • the logical determination module 112 determines whether to switch another storage block 120 to the current storage block (wherein the other storage block 120 stores the moving data, and the moving data is the data stored in the current storage block that has been filled), and when the switch is not performed, the logic judgment module 112 will switch another storage block 120 to the current storage block, and then write the current count value to The count base bit 121 of the current storage block after the switch is entered, and the check bit 123 and the identification bit 122 are written in the current storage block after the switch.
  • the above-mentioned current count value is the sum of the data recorded by the data bit 124 of the current storage block and the count base bit 121, and the sum of the recorded data refers to the value of the data bit 124 of the previous storage block and all data bits. Sum the values in 124.
  • the monotonic counter 100 is often used together with the flash memory. Each time the flash memory reads and writes data, 1 is written to the data bit in the current storage block of the monotonic counter 100, so all the data bits in a storage block 120 are 124 Adding the value of the count base bit 121 equals the current count value.
  • the data bit 124 can use n zeros to represent the count value of the monotonic counter 100 plus 1 (n is an integer greater than or equal to 1).
  • n is an integer greater than or equal to 1).
  • the count base bit of the monotonic counter 100 is 1000 and n is 8, the data bit 124 When there are 3 bytes of 0, at the current moment, the current count value of the monotonic counter 100 is 1003.
  • the logic The judging module 112 will destroy the check digit 123 of the current storage block before the switch, so that the check digit 123 is inconsistent with the check digit 123 of the current storage block after the switch, so as to better match the current storage block before the switch with the after switch. the current memory block.
  • the destruction operation of the logic judgment module 112 is to rewrite the data in the check bit 123 of the current storage block before the switch to any value different from the current value, so that even if the switch has not been performed In the erasing operation of the previous current storage block, the value calculated by the count base bit 121 and the identification bit 122 of the current storage block before the switch is also not equal to the value of the check bit 123, that is, it indicates the current storage block before the switch. It is not the storage block that continues to count next, which ensures the correctness of the count.
  • the logic judgment module 112 will determine the switch.
  • the previous current storage block is erased, and after that, data is written into the first data bit 124 that does not store count data in the switched current storage block for counting.
  • the embodiment according to the present invention has the following solutions:
  • the logic judging module 112 judges the current Whether the memory block has been erased, when the erasure is not in progress, the logic judgment module 112 will first complete the writing of the count base bit 121, the identification bit 122 and the check bit 123 of the current memory block after switching, and then, The logic judgment module 112 will destroy the check digit 123 of the current storage block before the switch, so that the check digit 123 is inconsistent with the check digit 123 of the current storage block after the switch, so as to better match the current storage block before the switch with the switch. After the current memory block is distinguished.
  • the destruction operation of the logic judgment module 112 is to rewrite the data in the check bit 123 of the current storage block before the switch to any value different from the current value, so that even if the switch has not been performed In the erasing operation of the previous current storage block, the value calculated by the count base bit 121 and the identification bit 122 of the current storage block before the switch is also not equal to the value of the check bit 123, that is, it indicates the current storage block before the switch. Not the chunk of memory that continues to count next.
  • the logic judgment module 112 will determine the switch.
  • the previous current storage block is erased, and after that, data is written into the first data bit 124 that does not store count data in the switched current storage block for counting.
  • the storage block 120 in the monotonic counter 100 is in the aforementioned "4" (4.
  • the new storage block has been switched and continues to count, and the operation of erasing the full storage block is in progress. ) state, in order to ensure that after the monotonic counter 100 is powered on, the read and write operations of the monotonic counter 100 will not be abnormal, the embodiment according to the present invention has the following solutions:
  • the logic judging module 112 will perform an erasing operation on the current storage block before switching again to ensure that the data in the current storage block before switching is completely erased. After that, data is written into the first data bit 124 that does not store count data in the switched current storage block for counting.
  • the interruption caused by the abnormality of the monotonic counter 100 specifically includes the interruption caused by the occurrence of power failure, reset, voltage instability and other abnormal conditions.
  • the present invention provides a monotonic counter 100, including a controller 110 and a plurality of storage blocks 120.
  • the storage blocks 120 include a count base bit 121, an identification bit 122, a check bit 123, and a counter for storing the count.
  • the data bit 124 of the data there is one current storage block among the plurality of storage blocks 120, wherein the controller 110 includes: an interrupt recording module 111 for recording an interruption that occurs in the monotonic counter 100, and an interruption recording module 111 for recording an interruption in the monotonic counter 100
  • the controller 110 includes: an interrupt recording module 111 for recording an interruption that occurs in the monotonic counter 100, and an interruption recording module 111 for recording an interruption in the monotonic counter 100
  • the controller 110 includes: an interrupt recording module 111 for recording an interruption that occurs in the monotonic counter 100, and an interruption recording module 111 for recording an interruption in the monotonic counter 100
  • the controller 110 includes: an interrupt recording module 111 for recording an interruption that occurs in the monotonic counter 100, and an interruption recording module 111 for recording an interruption in the monotonic counter 100
  • the controller 110 includes: an interrupt recording module 111 for recording an interruption that occurs in the monotonic counter 100, and an interruption recording module 111 for recording an interruption in the monotonic counter 100
  • the controller 110 includes: an interrupt recording module 111 for recording an
  • FIG. 2 is a schematic flowchart of a counting method of the monotonic counter 100 provided by an embodiment of the present invention.
  • the counting method is applied to the monotonic counter 100, and the monotonic counter 100 includes a plurality of storage blocks, each Each of the storage blocks includes count base bits, identification bits, check bits, and data bits for storing count data, and there is one current storage block among the plurality of storage blocks.
  • the monotonic counter 100 is used to ensure the confidentiality and integrity of its corresponding memory read and write data, the count data in the monotonic counter 100 can be monotonically increased, and since the data of each storage block in the monotonic counter 100 The number of bits that can be recorded is limited. Therefore, when the count value in a memory block in the monotonic counter 100 reaches the upper limit, it will switch to a memory block that has not been counted, or that has been counted but the count data has been erased to continue. count. When switching memory blocks for counting, the count data of the memory block before switching must be saved in the memory block after switching, as the basis for the counting of memory blocks after switching, and the memory block after switching will continue on the basis of this counting. Count, the count base bit is used to record the count data counted when the last current storage block is full and switched;
  • the data recorded in the identification bit is used to indicate whether the memory block needs to be erased and programmed.
  • the identification bit has only two data states. One data state indicates that the memory block needs to be erased and programmed (such as 00). , a data state that indicates that the memory block has been erased and programmed, and does not need to be erased and programmed again (such as FF);
  • the validity of the check bit is used to characterize whether the data in the count base bit and the identification bit of the storage block are valid. Specifically, the counting base bit and the identification bit will pass some kind of check operation (such as addition operation, parity operation, XOR operation or cyclic redundancy check (cyclic redundancy check). redundancy check) operation) to generate a value, and then compare the value with the value in the check digit. If the two values are equal, it means that the check digit is valid, that is, the data in the storage block corresponding to the check digit.
  • some kind of check operation such as addition operation, parity operation, XOR operation or cyclic redundancy check (cyclic redundancy check). redundancy check) operation
  • the data bit is a unit for storing count data.
  • each storage block 120 will include multiple data bits.
  • Detection step S101 It is detected that the monotonic counter 100 is interrupted.
  • the monotonic counter 100 may be interrupted due to the occurrence of power failure, reset, unstable voltage and other abnormal conditions.
  • the first judgment step S102 Judging whether the data bits of the current storage block are full.
  • Rewriting step S103 when the result of the first judging step S102 indicates that the data bits are not full, write data again in the last data bit of the current storage block that has stored count data.
  • the data bits may use n zeros to represent the count value of the monotonic counter 100 plus 1, and in the rewriting step S103, the method of rewriting the data may include supplementary writing in the data bits. Or rewrite, take n as 8, and before the interruption of the monotonic counter 100, the last data bit of the stored count data has been written with 3 0s as an example: A. Write 5 0s on the data bit; or, B, "rewrite in the data bit", that is, rewrite the 8 0s in the data bit, where the 8 0s include the written 3 0.
  • the rewriting step S103 can ensure that when the monotonic counter 100 is interrupted, if the storage block in the monotonic counter 100 is in the aforementioned "1" state (1. The current storage block that is being counted is not written to) full), after the monotonic counter 100 is powered on, the read and write operations of the monotonic counter 100 will not be abnormal.
  • FIG. 3 is a further schematic flowchart of the counting method of the monotonic counter 100 provided by the embodiment of the present invention, as shown in FIG. 3, because the judgment result of the first judgment step S102 also includes In the case of "the data bits of the current storage block are full", therefore, after the first judgment step S102, it can also include:
  • the second judging step S104 when the result of the first judging step S102 indicates that the data bits are full, judging whether to switch another storage block to the current storage block;
  • Erasing step S105 when the result of the second judging step S104 indicates that another storage block has been switched to the current storage block, the current storage block before the switching is erased.
  • another storage block stores moving data
  • the moving data is the data stored in the current storage block that has been fully written.
  • the erasing step S105 or the rewriting step S103 it also includes:
  • Counting step S106 Write data into the first data bit in the current storage block that does not store count data for counting.
  • the erasing step S105 it also includes:
  • the third judgment step S107 judging whether the current storage block before the switching has been erased
  • Destruction step S108 when the result of the third judgment step S107 indicates that the current storage block before the switch has not been erased, destroy the check digit of the current storage block before the switch, so that the check digit and the current storage block after the switch are checked. Inconsistent verification.
  • the destruction step S108 is to better distinguish the current storage block before the switch from the current storage block after the switch. Specifically, in the destruction step S108, the calibration of the current storage block before the switch is performed. The data in the verification bit is rewritten to any value different from the current value. In this way, even if the erase operation of the current storage block before the switch has not been performed, the count base bit and the identification bit of the current storage block before the switch are calculated. The obtained value is also not equal to the value of the check digit, that is, it indicates that the current storage block before the switch is not the storage block that continues to be counted next, which ensures the correctness of the count.
  • the erasing step S105 will be directly executed, that is, the current storage block before the switching is performed again.
  • the block erase operation ensures that the data in the current storage block before the switch is completely erased.
  • the judgment result of the second judgment step S104 also includes the situation that "another storage block has not been switched to the current storage block", after the second judgment step S104, it may also include:
  • Switching step S109 when the result of the second judging step S104 indicates that another storage block is not switched to the current storage block, another storage block is switched to the current storage block;
  • the destroying step S108 is performed to destroy the check digit of the current storage block before the switch, so that the check digit is inconsistent with the check digit of the current storage block after the switch.
  • Writing step S110 write the current count value into the count base bit of the switched current storage block, and write the check bit and the identification bit in the switched current storage block.
  • the above current count value is the sum of the data bits of the current storage block and the data recorded by the count base bit, and the recorded data sum refers to the value of the data bits of the previous storage block and the value of all data bits. beg for peace.
  • the monotonic counter 100 is often used together with the flash memory. Every time the flash memory reads and writes data, 1 is written to the data bit in the current storage block of the monotonic counter 100, so all data bits in a storage block plus The value of the count base bit is equal to the current count value.
  • the data bits can use n 0s to represent the count value of the monotonic counter 100 plus 1 (n is an integer greater than or equal to 1).
  • n is an integer greater than or equal to 1
  • the count base bit of the monotonic counter 100 is 1000
  • n is 8
  • the data bits have 3
  • the current count value of the monotonic counter 100 is 1003.
  • the above erasing step S105 and destroying step S108 can ensure that when the monotonic counter 100 is interrupted, if the memory block in the monotonic counter 100 is in the aforementioned "2" (2, the current memory block that is being counted) Full, but the new memory block has not been switched to continue counting), "3" (3, the new memory block has been switched and the counting continues, but the full memory block has not yet started to be erased), and "4" (4.
  • the new memory block has been switched to continue counting, and the operation of erasing the full memory block is in progress) after the monotonic counter 100 is powered on, the read and write operations of the monotonic counter 100 will not be abnormal. Therefore, it is possible to effectively prevent the occurrence of the problem that the monotonic counter 100 has an error in its counting operation due to an interruption.
  • the present invention provides a counting method of the monotonic counter 100, the counting method is applied to the monotonic counter 100, and the monotonic counter 100 includes a plurality of storage blocks, each storage block includes a counting base bit, an identification bit , a check bit, and a data bit for storing count data, and there is a current storage block in the plurality of storage blocks, the counting method includes: detecting that the monotonic counter 100 is interrupted, and then judging the data bit of the current storage block Whether it is full, if not, write data again in the last data bit of the current storage block that has stored count data, so that when an abnormal situation occurs in the monotonic counter 100, it can be guaranteed that the count data recorded by the monotonic counter 100 is Complete writing can effectively prevent the monotonic counter 100 from having an error in its counting operation due to the occurrence of abnormal conditions.

Abstract

一种单调计数器（100），包括多个存储块（120），存储块（120）包括多个数据位（124），且具有一个当前存储块（120）；以及控制器（110）包括用于记录中断的中断记录模块（111），以及用于在单调计数器（100）发生中断并上电复位后，判断当前存储块（120）的数据位（124）是否写满，且当数据位（124）未写满时，在当前存储块（120）的最后一个已存储计数数据的数据位（124）中再次写入数据的逻辑判断模块（112）。

Description

单调计数器及其计数方法 技术领域
本发明涉及通讯技术领域，尤其涉及一种单调计数器及其计数方法。
 背景技术
应答保护单调计数器（Replay Protection Monotonic Counter，RPMC）是指具有单调计数功能的计数器，在应答保护单调计数器中计入的数据后，应答保护单调计数器只会随着计数值的变化单调递增。通常应答保护单调计数器是与FLASH（快闪存储器）相结合，用于在数据存储过程中来保证读写数据的机密性和完整性。例如，应答保护单调计数器与FLASH结合用于确定存储器存储次数，当FLASH每进行一次数据的读写，就在单调计数器中增加一个计数值，因此为FLASH提供读写数据次数提供一个完整的数据记录；又如，在数据发送过程中，数据单调计数，保证数据的不重复性，进而可以提升数据发送的机密性。
但是，现有技术下的应答保护单调计数器，当有异常情况发生时（比如异常掉电、复位以及电压不稳定等），单调计数器的计数操作往往会出现错误。
 技术问题
本发明提供了一种单调计数器及其计数方法，有效地防止了当异常情况发生时，单调计数器的计数操作出现错误的问题。
 技术解决方案
一方面，本发明提供了一种单调计数器，所述单调计数器包括控制器以及多个存储块，所述存储块包括计数基位、标识位、校验位、以及用于存储计数数据的数据位，所述多个存储块中具有一个当前存储块，其中，所述控制器包括：
中断记录模块，用于记录所述单调计数器发生的中断；
逻辑判断模块，用于在所述单调计数器发生了所述中断并上电复位后，判断所述当前存储块的所述数据位是否写满，且当所述数据位未写满时，在所述当前存储块的最后一个已存储计数数据的所述数据位中再次写入数据。
进一步优选的，所述再次写入数据包括在所述数据位中进行补写或重写。
进一步优选的，所述逻辑判断模块还用于当所述数据位已写满时，判断是否将另一存储块切换为当前存储块，且当所述切换已进行时，对切换前的当前存储块进行擦除。
进一步优选的，所述逻辑判断模块还用于在所述当前存储块的最后一个已存储计数数据的所述数据位中再次写入数据或对所述切换前的当前存储块进行擦除之后，在所述当前存储块中第一个未存储计数数据的所述数据位中写入数据进行计数。
进一步优选的，所述逻辑判断模块还用于在对所述切换前的当前存储块进行擦除之前，判断所述切换前的当前存储块是否已在进行擦除，且当所述擦除未进行时，破坏所述切换前的当前存储块的所述校验位，使所述校验位与切换后的当前存储块的所述校验位不一致。
进一步优选的，所述破坏包括对所述切换前的当前存储块的所述校验位进行改写。
进一步优选的，所述逻辑判断模块还用于当所述切换未进行时，将所述另一存储块切换为当前存储块。
进一步优选的，所述逻辑判断模块还用于在进行所述破坏之前及/或进行所述切换之后，将当前计数值写入所述切换后的当前存储块的所述计数基位，并在所述切换后的当前存储块中写入所述校验位以及所述标识位。
进一步优选的，所述当前计数值为所述当前存储块的数据位以及计数基位记录的数据之和。
进一步优选的，所述中断包括发生掉电或复位。
另一方面，本发明还提供了一种单调计数器的计数方法，所述单调计数器包括多个存储块，所述存储块包括计数基位、标识位、校验位、以及用于存储计数数据的数据位，所述多个存储块中具有一个当前存储块，所述计数方法包括：
检测步骤，检测到所述单调计数器发生了中断；
第一判断步骤，判断所述当前存储块的所述数据位是否写满；
重写步骤，当所述第一判断步骤的结果指示所述数据位未写满时，在所述当前存储块的最后一个已存储计数数据的所述数据位中再次写入数据。
进一步优选的，所述再次写入数据包括在所述数据位中进行补写或重写。
进一步优选的，在所述第一判断步骤之后，还包括：
第二判断步骤，当所述第一判断步骤的结果指示所述数据位已写满时，判断是否将另一存储块切换为当前存储块；
擦除步骤，当所述第二判断步骤的结果指示已将所述另一存储块切换为当前存储块时，对切换前的当前存储块进行擦除。
进一步优选的，在所述擦除步骤或所述重写步骤之后，还包括：
计数步骤，在所述当前存储块中第一个未存储计数数据的所述数据位中写入数据进行计数。
进一步优选的，在所述擦除步骤之前，还包括：
第三判断步骤，判断所述切换前的当前存储块是否已在进行擦除；
破坏步骤，当所述第三判断步骤的结果指示所述切换前的当前存储块尚未进行擦除时，破坏所述切换前的当前存储块的所述校验位，使所述校验位与切换后的当前存储块的所述校验位不一致。
进一步优选的，所述破坏包括对所述切换前的当前存储块的所述校验位进行改写。
进一步优选的，在所述第二判断步骤之后，还包括：
切换步骤，当所述第二判断步骤的结果指示未将所述另一存储块切换为当前存储块时，将所述另一存储块切换为当前存储块；
之后，执行所述破坏步骤，破坏所述切换前的当前存储块的所述校验位，使所述校验位与切换后的当前存储块的所述校验位不一致。
进一步优选的，在所述破坏步骤之前及/或所述切换步骤之后，还包括：
写入步骤，将当前计数值写入所述切换后的当前存储块的所述计数基位，并在所述切换后的当前存储块中写入所述校验位以及所述标识位。
进一步优选的，所述当前计数值为所述当前存储块的数据位以及计数基位记录的数据之和。
进一步优选的，所述中断包括发生掉电或复位。
 有益效果
本发明提供了一种单调计数器，包括控制器以及多个存储块，存储块包括计数基位、标识位、校验位、以及用于存储计数数据的数据位，多个存储块中具有一个当前存储块，其中，控制器包括：用于记录单调计数器发生的中断的中断记录模块，以及用于在单调计数器发生了中断并上电复位后，判断当前存储块的数据位是否写满，且当数据位未写满时，在当前存储块的最后一个已存储计数数据的数据位中再次写入数据的逻辑判断模块，从而当单调计数器有异常情况发生时，可以保证单调计数器所记录的计数数据被完整写入，从而可以有效地防止单调计数器因异常情况的出现而使其计数操作发生错误的问题出现。
 附图说明
为了更清楚地说明本发明的技术方案，下面将对根据本发明而成的各实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本发明而成的实施例所提供的单调计数器的结构示意图。
图2是根据本发明而成的实施例所提供的单调计数器的计数方法的流程示意图。
图3是根据本发明而成的实施例所提供的单调计数器的计数方法的进一步流程示意图。
 本发明的实施方式
下面将结合本发明而成的实施例中的附图，对本发明而成的实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明针对现有技术下的应答保护单调计数器，当异常情况发生时，应答保护单调计数器的计数操作出现错误的问题，根据本发明而成的实施例用以解决该问题。
容易理解的是，当应答保护单调计数器发生异常情况而导致其产生中断时，在其上电复位后，需要采取一些措施防止应答保护单调计数器在后续出现读取异常的情况。而在应答保护单调计数器有中断发生时，其内部进行计数操作的存储块会有四种可能出现的工作状态，分别是：1、正在进行计数的当前存储块未写满；2、正在进行计数的当前存储块已写满，但还未切换新的存储块继续进行计数；3、已切换新的存储块继续进行计数，但还未开始擦除已写满的存储块；4、已切换新的存储块继续进行计数，且正在进行擦除已写满的存储块的操作。
针对上述四种可能出现的情况，本发明提出了如下的措施。
请参阅图1，图1是根据本发明而成的实施例所提供的单调计数器100的结构示意图，从图1可知根据本发明而成的实施例的各组成部分，以及各组成部分的相对位置关系。
如图1所示，该单调计数器100包括控制器110以及多个存储块120，且每个存储块120包括计数基位121、标识位122、校验位123以及多个用于存储计数数据的数据位124，且多个存储块120中具有一个当前存储块，其中，控制器110具体可以包括：
中断记录模块111，该中断记录模块111用于记录单调计数器100发生的中断；
逻辑判断模块112，该逻辑判断模块112用于在单调计数器100发生了中断并上电复位后，判断当前存储块的数据位124是否写满，且当数据位124未写满时，在当前存储块的最后一个已存储计数数据的数据位124中再次写入数据。
需要说明的是，单调计数器100用以保证其对应的存储器读写数据的机密性和完整性，单调计数器100中的计数数据可以单调性地递增，而由于单调计数器100中每个存储块120的数据位124所能记录的数值有限，因此，当单调计数器100中的一个存储块120中的计数值达到上限后，会切换一个没有进行计数、或者进行过计数但计数数据已经被擦除的存储块120继续进行计数。在切换存储块120进行计数时，必须将切换前的存储块120的计数数据保存到切换后的存储块120中，以作为切换后的存储块120计数的基础，切换后的存储块120会在这个计数基础上继续进行计数，计数基位121就是用于记录上一个当前存储块写满切换时所计入的计数数据；
标识位122中记录的数据用于表征存储块120是否需要进行擦除及编程操作，具体地，标识位122只具有两种数据状态，一种数据状态表征存储块120需要进行擦除及编程操作（如00），一种数据状态表征存储块120已经进行擦除及编程、不需要再进行擦除及编程操作（如FF）；
校验位123的有效性用于表征存储块120的计数基位121以及标识位122中的数据是否有效。具体地，计数基位121与标识位122会通过某种校验运算（譬如加法运算、奇偶运算、异或运算或循环冗余校验（cyclic redundancy check）运算）生成一数值，之后，将该数值与校验位123中的数值进行比较，若二值相等，则表征校验位123有效，也即，该校验位123对应的存储块120中的数据有效、未出现异常、也指示了该存储块是当前存储块；而若这二值不等，则表征校验位123无效，也即，该校验位123对应的存储块120中的数据无效、或发生了异常、也指示了该存储块不是当前存储块；
数据位124则是用于存储计数数据的单元，一般，为了增加存储块120的存储量、减少擦除次数，每个存储块120中会包括多个数据位124。
需要说明的是，数据位124可以用n个0代表该单调计数器100的计数值加1，当逻辑判断模块112判断出数据位124未写满后，会在当前存储块的最后一个已存储计数数据的数据位124中再次写入数据，再次写入数据的方式可以包括在数据位124中进行补写或重写，以n为8，且在单调计数器100发生中断前，最后一个已存储计数数据的数据位124已写入3个0为例：A、“在数据位124中进行补写”即，在该数据位124上补写5个0；或者，B、“在数据位124中进行重写”即，将该数据位124中的8个0重新写入，此处的8个0包含已写入的3个0。
容易理解的是，在逻辑判断模块112完成对数据位124的再次写入数据的操作之后，逻辑判断模块112会在当前存储块中第一个未存储计数数据的数据位124中写入数据进行计数。
容易理解的是，该逻辑判断模块112可以保证当单调计数器100产生中断时，若单调计数器100中的存储块120处于前文所述的“1”（1、正在进行计数的当前存储块未写满）的状态，在单调计数器100上电后，单调计数器100的读写操作不会出现异常。
进一步的，针对中断发生时，单调计数器100中的存储块120处于前文所述的“2”（2、正在进行计数的当前存储块已写满，但还未切换新的存储块继续进行计数）的状态，为保证单调计数器100上电后，单调计数器100的读写操作不会出现异常，根据本发明而成的实施例有如下解决方法：
当逻辑判断模块112判断出当前存储块的数据位124已写满时，逻辑判断模块112会判断是否将另一存储块120切换为当前存储块（其中，另一存储块120存储有搬移数据，且搬移数据为已写满的当前存储块中所存储的数据），且当该切换未进行时，逻辑判断模块112会将另一存储块120切换为当前存储块，之后，将当前计数值写入切换后的当前存储块的计数基位121，并在切换后的当前存储块中写入校验位123以及标识位122。
需要说明的是，上述当前计数值为当前存储块的数据位124以及计数基位121记录的数据之和，该记录的数据之和是指将前存储块的数据位124的值和所有数据位124中的值求和。在实际应用中，单调计数器100常和闪存一同使用，闪存每进行一次数据的读写，就在单调计数器100的当前存储块中的数据位写1，所以一个存储块120中所有的数据位124加上计数基位121的值等于当前计数值。举例来说，数据位124可以用n个0代表该单调计数器100的计数值加1（n为大于等于1的整数），当单调计数器100的计数基位是1000，n是8，数据位124有3个byte的0时，则当前时刻，该单调计数器100的当前计数值是1003。
进一步的，在上述“将当前计数值写入切换后的当前存储块的计数基位121，并在切换后的当前存储块中写入校验位123以及标识位122”的操作完成之后，逻辑判断模块112会破坏切换前的当前存储块的校验位123，使校验位123与切换后的当前存储块的校验位123不一致，以更好地将切换前的当前存储块与切换后的当前存储块区分开来。
需要说明的是，逻辑判断模块112的破坏操作，是将切换前的当前存储块的校验位123中的数据改写为与当前值不一样的任何一个值，如此一来，即便还没有进行切换前的当前存储块的擦除操作，切换前的当前存储块的计数基位121与标识位122计算得到的数值也与校验位123的值不等，即指示了该切换前的当前存储块不是接下来继续进行计数的存储块，保证了计数的正确性。
进一步的，在上述“破坏切换前的当前存储块的校验位123，使校验位123与切换后的当前存储块的校验位123不一致”的操作完成之后，逻辑判断模块112会对切换前的当前存储块进行擦除，之后，在切换后的当前存储块中第一个未存储计数数据的数据位124中写入数据进行计数。
进一步的，针对中断发生时，单调计数器100中的存储块120处于前文所述的“3”（3、已切换新的存储块继续进行计数，但还未开始擦除已写满的存储块）的状态，为保证单调计数器100上电后，单调计数器100的读写操作不会出现异常，根据本发明而成的实施例有如下解决方法：
当逻辑判断模块112判断出当前存储块的数据位124已写满，且逻辑判断模块112进一步判断出已将另一存储块120切换为当前存储块时，逻辑判断模块112会判断切换前的当前存储块是否已在进行擦除，当擦除未进行时，逻辑判断模块112会先完成对切换后的当前存储块的计数基位121、标识位122以及校验位123的写入，之后，逻辑判断模块112会破坏切换前的当前存储块的校验位123，使校验位123与切换后的当前存储块的校验位123不一致，以更好地将切换前的当前存储块与切换后的当前存储块区分开来。
需要说明的是，逻辑判断模块112的破坏操作，是将切换前的当前存储块的校验位123中的数据改写为与当前值不一样的任何一个值，如此一来，即便还没有进行切换前的当前存储块的擦除操作，切换前的当前存储块的计数基位121与标识位122计算得到的数值也与校验位123的值不等，即指示了该切换前的当前存储块不是接下来继续进行计数的存储块。
进一步的，在上述“破坏切换前的当前存储块的校验位123，使校验位123与切换后的当前存储块的校验位123不一致”的操作完成之后，逻辑判断模块112会对切换前的当前存储块进行擦除，之后，在切换后的当前存储块中第一个未存储计数数据的数据位124中写入数据进行计数。
进一步的，针对中断发生时，单调计数器100中的存储块120处于前文所述的“4”（4、已切换新的存储块继续进行计数，且正在进行擦除已写满的存储块的操作）的状态，为保证单调计数器100上电后，单调计数器100的读写操作不会出现异常，根据本发明而成的实施例有如下解决方法：
当逻辑判断模块112判断出当前存储块的数据位124已写满，且逻辑判断模块112进一步判断出已将另一存储块120切换为当前存储块，且判断出对切换前的当前存储块的擦除操作已在进行中时，逻辑判断模块112会再进行一次对切换前的当前存储块的擦除操作，以保证切换前的当前存储块中的数据被完全擦除。之后，在切换后的当前存储块中第一个未存储计数数据的数据位124中写入数据进行计数。
具体地，单调计数器100发生异常而出现的中断具体包括发生掉电、复位、电压不稳定以及其他异常情况而导致的中断。
区别于现有技术，本发明提供了一种单调计数器100，包括控制器110以及多个存储块120，存储块120包括计数基位121、标识位122、校验位123、以及用于存储计数数据的数据位124，多个存储块120中具有一个当前存储块，其中，控制器110包括：用于记录单调计数器100发生的中断的中断记录模块111，以及用于在单调计数器100发生了中断并上电复位后，判断当前存储块的数据位124是否写满，且当数据位124未写满时，在当前存储块的最后一个已存储计数数据的数据位124中再次写入数据的逻辑判断模块112，从而当单调计数器100有异常情况发生时，可以保证单调计数器100所记录的计数数据被完整写入，从而可以有效地防止单调计数器100因异常情况的出现而使其计数操作发生错误的问题出现。
请参阅图2，图2是根据本发明而成的实施例所提供的单调计数器100的计数方法的流程示意图，该计数方法应用于单调计数器100，且该单调计数器100包括多个存储块，每个存储块包括计数基位、标识位、校验位、以及用于存储计数数据的数据位，且多个存储块中具有一个当前存储块。
需要说明的是，单调计数器100用以保证其对应的存储器读写数据的机密性和完整性，单调计数器100中的计数数据可以单调性地递增，而由于单调计数器100中每个存储块的数据位所能记录的数值有限，因此，当单调计数器100中的一个存储块中的计数值达到上限后，会切换一个没有进行计数、或者进行过计数但计数数据已经被擦除的存储块继续进行计数。在切换存储块进行计数时，必须将切换前的存储块的计数数据保存到切换后的存储块中，以作为切换后的存储块计数的基础，切换后的存储块会在这个计数基础上继续进行计数，计数基位就是用于记录上一个当前存储块写满切换时所计入的计数数据；
标识位中记录的数据用于表征存储块是否需要进行擦除及编程操作，具体地，标识位只具有两种数据状态，一种数据状态表征存储块需要进行擦除及编程操作（如00），一种数据状态表征存储块已经进行擦除及编程、不需要再进行擦除及编程操作（如FF）；
校验位的有效性用于表征存储块的计数基位以及标识位中的数据是否有效。具体地，计数基位与标识位会通过某种校验运算（譬如加法运算、奇偶运算、异或运算或循环冗余校验（cyclic redundancy check）运算）生成一数值，之后，将该数值与校验位中的数值进行比较，若二值相等，则表征校验位有效，也即，该校验位对应的存储块中的数据有效、未出现异常、也指示了该存储块是当前存储块；而若这二值不等，则表征校验位无效，也即，该校验位对应的存储块中的数据无效、或发生了异常、也指示了该存储块不是当前存储块；
数据位则是用于存储计数数据的单元，一般，为了增加存储块的存储量、减少擦除次数，每个存储块120中会包括多个数据位。
下面根据图2，对应用于单调计数器100的该计数方法的具体流程进行说明：
检测步骤S101：检测到单调计数器100发生了中断。
具体地，单调计数器100会因为其发生掉电、复位、电压不稳定以及其他异常情况而导致单调计数器100产生中断。
第一判断步骤S102：判断当前存储块的数据位是否写满。
重写步骤S103：当第一判断步骤S102的结果指示数据位未写满时，在当前存储块的最后一个已存储计数数据的数据位中再次写入数据。
需要说明的是，需要说明的是，数据位可以用n个0代表该单调计数器100的计数值加1，在重写步骤S103中，再次写入数据的方式可以包括在数据位中进行补写或重写，以n为8，且在单调计数器100发生中断前，最后一个已存储计数数据的数据位已写入3个0为例：A、“在数据位中进行补写”即，在该数据位上补写5个0；或者，B、“在数据位中进行重写”即，将该数据位中的8个0重新写入，此处的8个0包含已写入的3个0。
容易理解的是，该重写步骤S103可以保证当单调计数器100产生中断时，若单调计数器100中的存储块处于前文所述的“1”的状态（1、正在进行计数的当前存储块未写满），在单调计数器100上电后，单调计数器100的读写操作不会出现异常。
进一步的，请参阅图3，图3是根据本发明而成的实施例所提供的单调计数器100的计数方法的进一步流程示意图，如图3所示，因为第一判断步骤S102的判断结果还包括“当前存储块的数据位已写满”的情况，所以，在第一判断步骤S102之后，还可以包括：
第二判断步骤S104：当第一判断步骤S102的结果指示数据位已写满时，判断是否将另一存储块切换为当前存储块；
擦除步骤S105：当第二判断步骤S104的结果指示已将另一存储块切换为当前存储块时，对切换前的当前存储块进行擦除。
其中，另一存储块存储有搬移数据，且搬移数据为已写满的当前存储块中所存储的数据。
进一步的，在擦除步骤S105或重写步骤S103之后，还包括：
计数步骤S106：在当前存储块中第一个未存储计数数据的数据位中写入数据进行计数。
进一步的，在擦除步骤S105之前，还包括：
第三判断步骤S107：判断切换前的当前存储块是否已在进行擦除；
破坏步骤S108：当第三判断步骤S107的结果指示切换前的当前存储块尚未进行擦除时，破坏切换前的当前存储块的校验位，使校验位与切换后的当前存储块的校验位不一致。
需要说明的是，破坏步骤S108是为了更好地将切换前的当前存储块与切换后的当前存储块区分开来，具体地，在破坏步骤S108中，是将切换前的当前存储块的校验位中的数据改写为与当前值不一样的任何一个值，如此一来，即便还没有进行切换前的当前存储块的擦除操作，切换前的当前存储块的计数基位与标识位计算得到的数值也与校验位的值不等，即指示了该切换前的当前存储块不是接下来继续进行计数的存储块，保证了计数的正确性。
进一步的，若在第三判断步骤S107后，判断结果指示切换前的当前存储块的擦除操作已在进行中时，会直接执行擦除步骤S105，即，再进行一次对切换前的当前存储块的擦除操作，以保证切换前的当前存储块中的数据被完全擦除。
进一步的，因为第二判断步骤S104的判断结果还包括“尚未将另一存储块切换为当前存储块”的情况，所以，在第二判断步骤S104之后，还可以包括：
切换步骤S109：当第二判断步骤S104的结果指示未将另一存储块切换为当前存储块时，将另一存储块切换为当前存储块；
之后，执行破坏步骤S108，破坏切换前的当前存储块的校验位，使校验位与切换后的当前存储块的校验位不一致。
需要说明的是，因为在破坏步骤S108之前及/或切换步骤S109之后，需要完成对单调计数器100的计数基位、校验位以及标识位的写入，所以，在破坏步骤S108之前或切换步骤S109之后，还包括：
写入步骤S110：将当前计数值写入切换后的当前存储块的计数基位，并在切换后的当前存储块中写入校验位以及标识位。
需要说明的是，上述当前计数值为当前存储块的数据位以及计数基位记录的数据之和，该记录的数据之和是指将前存储块的数据位的值和所有数据位中的值求和。在实际应用中，单调计数器100常和闪存一同使用，闪存每进行一次数据的读写，就在单调计数器100的当前存储块中的数据位写1，所以一个存储块中所有的数据位加上计数基位的值等于当前计数值。举例来说，数据位可以用n个0代表该单调计数器100的计数值加1（n为大于等于1的整数），当单调计数器100的计数基位是1000，n是8，数据位有3个byte的0时，则当前时刻，该单调计数器100的当前计数值是1003。
容易理解的是，上述擦除步骤S105以及破坏步骤S108可以保证当单调计数器100产生中断时，若单调计数器100中的存储块处于前文所述的“2”（2、正在进行计数的当前存储块已写满，但还未切换新的存储块继续进行计数）、“3”（3、已切换新的存储块继续进行计数，但还未开始擦除已写满的存储块）以及“4”（4、已切换新的存储块继续进行计数，且正在进行擦除已写满的存储块的操作）的状态，在单调计数器100上电后，单调计数器100的读写操作不会出现异常，从而可以有效地防止单调计数器100因为发生了中断而使其计数操作出现错误的问题发生。
区别于现有技术，本发明提供了一种单调计数器100的计数方法，该计数方法应用于单调计数器100，且该单调计数器100包括多个存储块，每个存储块包括计数基位、标识位、校验位、以及用于存储计数数据的数据位，且多个存储块中具有一个当前存储块，该计数方法包括：检测到单调计数器100发生了中断，之后，判断当前存储块的数据位是否写满，若否，则在当前存储块的最后一个已存储计数数据的数据位中再次写入数据，从而当单调计数器100有异常情况发生时，可以保证单调计数器100所记录的计数数据被完整写入，从而可以有效地防止单调计数器100因异常情况的出现而使其计数操作发生错误的问题出现。
除上述实施例外，本发明还可以有其他实施方式。凡采用等同替换或等效替换形成的技术方案，均落在本发明要求的保护范围。
综上所述，虽然本发明已将优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种单调计数器，其中，所述单调计数器包括控制器以及多个存储块，所述存储块包括计数基位、标识位、校验位、以及用于存储计数数据的数据位，所述多个存储块中具有一个当前存储块，其中，所述控制器包括：
    中断记录模块，用于记录所述单调计数器发生的中断；
    逻辑判断模块，用于在所述单调计数器发生了所述中断并上电复位后，判断所述当前存储块的所述数据位是否写满，且当所述数据位未写满时，在所述当前存储块的最后一个已存储计数数据的所述数据位中再次写入数据。
  2. 根据权利要求1所述的单调计数器，其中，所述再次写入数据包括在所述数据位中进行补写或重写。
  3. 根据权利要求1所述的单调计数器，其中，所述逻辑判断模块还用于当所述数据位已写满时，判断是否将另一存储块切换为当前存储块，且当所述切换已进行时，对切换前的当前存储块进行擦除。
  4. 根据权利要求3所述的单调计数器，其中，所述逻辑判断模块还用于在所述当前存储块的最后一个已存储计数数据的所述数据位中再次写入数据或对所述切换前的当前存储块进行擦除之后，在所述当前存储块中第一个未存储计数数据的所述数据位中写入数据进行计数。
  5. 根据权利要求3所述的单调计数器，其中，所述逻辑判断模块还用于在对所述切换前的当前存储块进行擦除之前，判断所述切换前的当前存储块是否已在进行擦除，且当所述擦除未进行时，破坏所述切换前的当前存储块的所述校验位，使所述校验位与切换后的当前存储块的所述校验位不一致。
  6. 根据权利要求5所述的单调计数器，其中，所述破坏包括对所述切换前的当前存储块的所述校验位进行改写。
  7. 根据权利要求5所述的单调计数器，其中，所述逻辑判断模块还用于当所述切换未进行时，将所述另一存储块切换为当前存储块。
  8. 根据权利要求5所述的单调计数器，其中，所述逻辑判断模块还用于在进行所述破坏之前及/或进行所述切换之后，将当前计数值写入所述切换后的当前存储块的所述计数基位，并在所述切换后的当前存储块中写入所述校验位以及所述标识位。
  9. 根据权利要求8所述的单调计数器，其中，所述当前计数值为所述当前存储块的数据位以及计数基位记录的数据之和。
  10. 根据权利要求1所述的单调计数器，其中，所述中断包括发生掉电或复位。
  11. 一种单调计数器的计数方法，所述单调计数器包括多个存储块，所述存储块包括计数基位、标识位、校验位、以及用于存储计数数据的数据位，所述多个存储块中具有一个当前存储块，其中，所述计数方法包括：
    检测步骤，检测到所述单调计数器发生了中断；
    第一判断步骤，判断所述当前存储块的所述数据位是否写满；
    重写步骤，当所述第一判断步骤的结果指示所述数据位未写满时，在所述当前存储块的最后一个已存储计数数据的所述数据位中再次写入数据。
  12. 根据权利要求11所述的计数方法，其中，所述再次写入数据包括在所述数据位中进行补写或重写。
  13. 根据权利要求11所述的计数方法，其中，在所述第一判断步骤之后，还包括：
    第二判断步骤，当所述第一判断步骤的结果指示所述数据位已写满时，判断是否将另一存储块切换为当前存储块；
    擦除步骤，当所述第二判断步骤的结果指示已将所述另一存储块切换为当前存储块时，对切换前的当前存储块进行擦除。
  14. 根据权利要求13所述的计数方法，其中，在所述擦除步骤或所述重写步骤之后，还包括：
    计数步骤，在所述当前存储块中第一个未存储计数数据的所述数据位中写入数据进行计数。
  15. 根据权利要求13所述的计数方法，其中，在所述擦除步骤之前，还包括：
    第三判断步骤，判断所述切换前的当前存储块是否已在进行擦除；
    破坏步骤，当所述第三判断步骤的结果指示所述切换前的当前存储块尚未进行擦除时，破坏所述切换前的当前存储块的所述校验位，使所述校验位与切换后的当前存储块的所述校验位不一致。
  16. 根据权利要求15所述的计数方法，其中，所述破坏包括对所述切换前的当前存储块的所述校验位进行改写。
  17. 根据权利要求15所述的计数方法，其中，在所述第二判断步骤之后，还包括：
    切换步骤，当所述第二判断步骤的结果指示未将所述另一存储块切换为当前存储块时，将所述另一存储块切换为当前存储块；
    之后，执行所述破坏步骤，破坏所述切换前的当前存储块的所述校验位，使所述校验位与切换后的当前存储块的所述校验位不一致。
  18. 根据权利要求17所述的计数方法，其中，在所述破坏步骤之前及/或所述切换步骤之后，还包括：
    写入步骤，将当前计数值写入所述切换后的当前存储块的所述计数基位，并在所述切换后的当前存储块中写入所述校验位以及所述标识位。
  19. 根据权利要求18所述的计数方法，其中，所述当前计数值为所述当前存储块的数据位以及计数基位记录的数据之和。
  20. 根据权利要求11所述的计数方法，其中，所述中断包括发生掉电或复位。
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