WO2022116321A1 - 子像素结构、像素区块以及显示面板 - Google Patents

子像素结构、像素区块以及显示面板 Download PDF

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Publication number
WO2022116321A1
WO2022116321A1 PCT/CN2020/139487 CN2020139487W WO2022116321A1 WO 2022116321 A1 WO2022116321 A1 WO 2022116321A1 CN 2020139487 W CN2020139487 W CN 2020139487W WO 2022116321 A1 WO2022116321 A1 WO 2022116321A1
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Prior art keywords
pixel
block
sub
adjacent
pixel blocks
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PCT/CN2020/139487
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English (en)
French (fr)
Inventor
刘毅
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Tcl华星光电技术有限公司
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Publication of WO2022116321A1 publication Critical patent/WO2022116321A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present application relates to the technical field of sub-pixel structures, and in particular, to a sub-pixel structure, a pixel block and a display panel.
  • the red, blue, and green three-color sub-pixels are all rectangular designs.
  • indicators such as liquid crystal efficiency and viewing angle under this design are gradually approaching the design bottleneck, and it is difficult to make a major breakthrough.
  • the pixel electrode area is a regular rectangle, and the internal traces are composed of a cross-shaped trunk electrode, an M-shaped branch electrode symmetrical about the trunk electrode, and a regional edge sealing.
  • the dark lines of liquid crystal are distributed along the vertical and horizontal main roads, so that better liquid crystal efficiency can be obtained.
  • the design structure of such a rectangular liquid crystal pixel is very unstable, and is prone to abnormal dark lines.
  • the closer the shape of the pixel block is to a square the higher the liquid crystal efficiency and the higher the transmittance.
  • the liquid crystal pixels tend to be rectangular, the dark area of the liquid crystal increases, and the efficiency of the liquid crystal decreases.
  • the square pixel block has the advantage of stable dark pattern. When the aspect ratio of the rectangle is too large, dark pattern anomaly is prone to occur, while the square pixel block has no dark pattern abnormality.
  • the existing pixel is usually composed of three rectangular sub-pixels of the same size, wherein the dark pattern of the rectangular sub-pixels is unstable, and since the shape of the sub-pixels is fixed as a rectangle, the arrangement of the sub-pixels is relatively simple in the combination of pixels. , the shape is relatively simple, and the existing sub-pixel structure has the technical problems of single structure and abnormal dark lines.
  • the embodiments of the present application provide a sub-pixel structure, which alleviates the technical problems of single structure and abnormal dark lines in the existing sub-pixel structure.
  • An embodiment of the present application provides a sub-pixel structure, including more than two pixel blocks, the pixel blocks are arranged along a first direction and/or a second direction to form a sub-pixel, wherein the adjacent pixel blocks are Parts are connected and formed with an isolation area, and the isolation area is used to separate the adjacent pixel blocks, so that the adjacent pixel blocks are arranged independently of each other, and the dark lines of the adjacent pixel blocks are independent of each other.
  • the pixel block includes a quadrilateral area for display, and the quadrilateral area includes trunk electrodes arranged in a cross shape, and the Aspect ratios range from 1:1 to 1:2.5.
  • the pixel block further includes a branch electrode, the trunk electrode is connected to the branch electrode, the adjacent pixel blocks are connected through the trunk electrode, and the pixel signal can pass through the pixel main electrode. Branches are transferred to adjacent pixel blocks.
  • the distance between the block interface and the two sides of the edge of the quadrilateral region is the same, and adjacent block interfaces are in contact with each other and are arranged correspondingly.
  • At least one side of the quadrilateral area protrudes outward to form a block interface, adjacent to the block interface is disposed opposite, and the adjacent pixel blocks pass through the block interface connection.
  • a recess is formed on the side of the quadrilateral area on which the block interface is provided, and when adjacent pixel blocks are connected through the block interface, the recess is formed on the side of the quadrilateral area.
  • the isolation regions are formed between adjacent pixel blocks.
  • the shapes and sizes of the plurality of the quadrilateral regions are the same, and the shapes and sizes of the plurality of the block interfaces are the same.
  • the cross-sectional shape of the block interface is an isosceles trapezoid, and the inclination angle of any hypotenuse of the trapezoid is 45 degrees.
  • the width of the recess is at least 10 microns, and the height of the pixel block is at least 5 microns.
  • the pixel electrodes of the pixel blocks include trunk electrodes and branch electrodes, the trunk electrodes of adjacent pixel blocks are electrically connected through block interfaces, and the branch electrodes are related to the phase
  • the connected trunk electrodes are arranged asymmetrically.
  • the pixel blocks are arranged along the first direction and the second direction, and the shape of the sub-pixel structure is any one of an L-shape, a cross-shape, and an earth-shape.
  • the sub-pixel structure includes at least three of the pixel blocks.
  • This embodiment provides a pixel block, including a quadrilateral area and at least one block interface, the quadrilateral area and the block interface are provided with pixel electrodes, the four sides of the quadrilateral area have the same length, and the block interface are arranged on four sides of the quadrilateral area, wherein when a plurality of the pixel blocks are arranged adjacently, the block interface is used to separate the adjacent quadrilateral areas.
  • the pixel block includes the quadrilateral area and one of the block interfaces.
  • the pixel block includes the quadrilateral area and two of the block interfaces, and the block interfaces are respectively disposed on any two sides of the quadrilateral area.
  • any two adjacent sides of the quadrilateral area are respectively provided with a block interface.
  • any two opposite sides of the quadrilateral area are respectively provided with a block interface.
  • the pixel block includes the quadrilateral area and three of the block interfaces, and the block interfaces are respectively disposed on any three sides of the quadrilateral area.
  • the pixel block includes the quadrilateral area and four of the block interfaces, and the block interfaces are respectively disposed on four sides of the quadrilateral area.
  • the cross-sectional shape of the block interface may be any one of a trapezoid, a parallelogram, a rectangle, and a square.
  • the present embodiment provides a display panel including a plurality of pixel units, the pixel units include at least three of the sub-pixel structures, the sub-pixel structures include more than two pixel blocks, and the pixel blocks are located along the The first direction and/or the second direction are arranged to form a sub-pixel, wherein the adjacent pixel blocks are partially connected and an isolation area is formed, and the isolation area is used to separate the adjacent pixel blocks, so that the The adjacent pixel blocks are arranged independently of each other, and the dark lines of the adjacent pixel blocks are independent of each other.
  • the sub-pixel structure provided by the embodiments of the present application includes two or more pixel blocks arranged along the first direction and/or the second direction, adjacent pixel blocks are partially connected and an isolation region is formed, and the phase is separated by the isolation region.
  • the adjacent pixel blocks are arranged independently of each other; by making the adjacent pixel blocks independently arranged, the dark lines of the pixel blocks are independent of each other, which alleviates the technical problems of single structure and abnormal dark lines in the existing sub-pixel structure.
  • FIG. 1 is a first schematic top view of a sub-pixel structure provided by an embodiment of the present application
  • FIG. 2 is a first schematic top view of a pixel block provided by an embodiment of the present application
  • FIG. 3 is a second schematic top view of a pixel block provided by an embodiment of the present application.
  • FIG. 4 is a third schematic top view of a pixel block provided by an embodiment of the present application.
  • FIG. 5 is a fourth schematic top view of a pixel block provided by an embodiment of the present application.
  • FIG. 6 is a fifth schematic top view of a pixel block provided by an embodiment of the present application.
  • FIG. 7 is a comparison diagram of transmittance between the splicing design of the sub-pixel structure provided by the embodiment of the present application and the general design;
  • FIG. 8 is a comparison diagram of dark pattern simulation of a splicing design of a sub-pixel structure provided by an embodiment of the present application and a general design;
  • FIG. 9 is a schematic structural diagram of a pixel design provided by an embodiment of the present application.
  • FIG. 10 is a dark pattern simulation diagram of a sub-pixel structure provided by an embodiment of the present application.
  • FIG. 11 is a second schematic top view of a sub-pixel structure provided by an embodiment of the present application.
  • FIG. 12 is a third schematic top view of a sub-pixel structure provided by an embodiment of the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the sub-pixel structure 2 provided by the embodiment of the present application has more than two pixel blocks 1, and the pixel blocks 1 are arranged along the first direction and/or the second direction to form a sub-pixel, wherein, The adjacent pixel blocks 1 are partially connected and an isolation area 40 is formed, and the isolation area 40 is used to separate the adjacent pixel blocks 1, so that the adjacent pixel blocks 1 are arranged independently of each other, adjacent to each other.
  • the dark patterns of the pixel block 1 are independent of each other.
  • the sub-pixel structure 2 includes more than two pixel blocks 1, and the pixel blocks 1 are arranged along the first direction and/or the second direction to form a sub-pixel, wherein the adjacent pixels are
  • the block 1 is partially connected and an isolation area 40 is formed, and the isolation area 40 is used to separate the adjacent pixel blocks 1, so that the adjacent pixel blocks 1 are arranged independently of each other, and the adjacent pixel blocks
  • the dark lines of 1 are independent of each other; a plurality of the pixel blocks 1 can be combined into sub-pixel structures of various forms, and the dark lines of the quadrilateral area 10 of a single pixel block 1 are relatively stable, which alleviates the existence of existing pixel structures.
  • the technical problem of single sub-pixel structure and abnormal dark pattern is arranged along the first direction and/or the second direction to form a sub-pixel, wherein the adjacent pixels are
  • the block 1 is partially connected and an isolation area 40 is formed, and the isolation area 40 is used to separate the adjacent pixel blocks 1, so that the adjacent pixel blocks 1 are
  • the pixel blocks 1 arranged independently of each other refer to the fact that the dark patterns of the pixel blocks 1 are independent of each other, and a plurality of the pixel blocks 1 can be arbitrarily combined and arranged to form sub-pixel structures 2 of different shapes.
  • the pixel block 1 includes a trunk electrode 301 and a branch electrode 302 , adjacent pixel blocks 1 are connected through the trunk electrode 301 , and pixel signals can be transmitted to the adjacent pixel block 1 through the pixel trunk 301 .
  • the two or more pixel blocks 1 arranged independently of each other include two pixel blocks 1 arranged independently of each other.
  • each pixel block 1 is formed by independently setting adjacent pixel blocks 1, and then the sub-pixel structure 2 is formed by arranging two or more pixel blocks 1 in a one-dimensional or two-dimensional direction.
  • the sub-pixel structures 2 are diverse, and the pixel blocks 1 can be arbitrarily combined and arranged to form the sub-pixel structures 2 .
  • the aspect ratio of the quadrilateral area 10 of the pixel block 1 is 1:1.
  • the dark pattern is most convergent.
  • the pixel block 1 includes a quadrilateral area 10 for display, the quadrilateral area 10 includes trunk electrodes 301 arranged in a cross shape, and the Aspect ratios range from 1:1 to 1:2.5.
  • At least one side of the quadrilateral area 10 protrudes outward to form a block interface 20, adjacent to the block interface 20 is disposed opposite, and the adjacent pixel blocks 1 pass through the block interface 20 connections.
  • a recess is formed on the side of the quadrilateral area 10 where the block interface 20 is disposed oppositely.
  • the recess is formed in the phase.
  • the isolation regions 40 are formed between adjacent pixel blocks.
  • the shapes and sizes of the plurality of the quadrilateral regions 10 are the same, and the shapes and sizes of the plurality of the block interfaces are the same.
  • the cross-sectional shape of the block interface 20 is an isosceles trapezoid, and the inclination angle of any hypotenuse of the trapezoid is 45 degrees.
  • the width of the recess is at least 10 microns, and the height of the pixel block 1 is at least 5 microns.
  • the pixel electrodes of the pixel block 1 include a trunk electrode 301 and a branch electrode 302 , and the trunk electrodes 301 adjacent to the pixel block 1 are electrically connected through the block interface 20 , and the branch electrodes 302
  • the trunk electrodes 301 are arranged asymmetrically with respect to the connected ones.
  • the pixel blocks 1 are arranged along the first direction and the second direction, and the sub-pixel structure 2 is any one of an L-shape, a cross-shape, and an earth-shape.
  • the sub-pixel structure 2 includes at least three of the pixel blocks 1 .
  • the closer the shape of the pixel block 1 is to a square the higher the liquid crystal efficiency and the higher the transmittance; and if the pixel block 1 is closer to a rectangle, the liquid crystal dark area will increase, the liquid crystal efficiency will decrease, and the transmittance will be higher. will also decrease, and when the aspect ratio of the rectangle is larger, the dark pattern anomaly is more likely to occur, while the square graphic unit does not have dark pattern abnormality, and the square graphic unit has the advantage of stable dark pattern.
  • the pixel electrode 30 includes a trunk electrode 301 and a branch electrode 302 connected to the trunk electrode 301 .
  • the trunk electrode 301 includes a horizontal trunk electrode 301 and a vertical trunk electrode 301 .
  • the length and width of the quadrilateral area 10 in the pixel block 1 is 1:1, when increasing the width of a single trunk electrode 301 of the pixel electrode 30 or simultaneously increasing the width of the horizontal trunk electrode 301 and the vertical trunk electrode 301 When the width is wide, the dark streaks are not disordered.
  • the width of the quadrilateral area 10 when the width of the quadrilateral area 10 is 1:1, the dark lines of the pixel block 1 and the sub-pixel structure 2 are stable, and when the width of the main electrode 301 is changed, the stability of the dark lines is not affected. Effect.
  • the sub-pixel structure 2 is L-shaped.
  • the L-shape may be composed of four pixel blocks 1 .
  • the four pixel blocks 1 may be two pixel blocks 1 including one of the block interfaces 20 and two pixel blocks 1 including two of the block interfaces 20 .
  • the distance between the block interface 20 and the two sides of the edge of the quadrilateral area 10 is the same, and the adjacent block interfaces 20 are in contact with each other and are arranged correspondingly.
  • one quadrilateral area 10 includes a first block interface 20 and a second block interface 20, and another quadrilateral area 10 also includes a third block interface 20 and a fourth block interface 20,
  • the first block interface 20 and the second block interface 20 have different shapes and sizes, wherein the cross-sectional area of the first block interface 20 is larger than the cross-sectional area of the second block interface 20 .
  • the third block interface 20 and the fourth block interface 20 have different shapes and sizes, wherein the cross-sectional area of the third block interface 20 is larger than the cross-sectional area of the fourth block interface 20 .
  • first block interface 20 and the third block interface 20 can be arranged in contact with each other.
  • the second block interface 20 and the fourth block interface 20 can be arranged in contact with each other.
  • the shape and size of the first block interface 20 and the third block interface 20 may be the same.
  • the second block interface 20 may be the same in shape and size as the fourth block interface 20 .
  • the pixel block 1 provided by the embodiment of the present application includes a quadrilateral area 10 and at least one block interface 20 .
  • the quadrilateral area 10 and the block interface 20 are provided with pixel electrodes 30 .
  • the lengths of the four sides of the quadrilateral area 10 are the same, and the block interface 20 is arranged on the four sides of the quadrilateral area 10 . to separate the adjacent quadrilateral regions 10 .
  • the pixel block 1 includes a quadrilateral area 10 and at least one block interface 20 .
  • the quadrilateral area 10 and the block interface 20 are provided with pixel electrodes 30
  • the four sides of the quadrilateral area 10 are provided with pixel electrodes 30 .
  • the block interface 20 is arranged on the four sides of the quadrilateral area 10, wherein, when a plurality of the pixel blocks 1 are arranged adjacently, the block interface 20 is used to separate the adjacent all The quadrilateral area 10; a plurality of the pixel blocks 1 can be combined into sub-pixel structures 2 of various forms, while a single pixel block 1 is square, and its dark pattern is relatively stable, which alleviates the existence of sub-pixels in the existing pixel structure.
  • the quadrilateral area 10 and the pixel electrodes 30 of the block interface 20 are integrally arranged.
  • the dark pattern of the quadrilateral area 10 is stable, a plurality of pixel blocks 1 are combined together, and the block interface 20 is used to separate adjacent quadrilateral areas 10 .
  • the pixel electrode 30 includes a trunk electrode 301 and a branch electrode 302 .
  • any side of the quadrilateral area 10 is provided with only one of the block interfaces 20 at most.
  • any side of the quadrilateral area 10 may be provided with a plurality of the block interfaces 20 .
  • the pixel block 1 includes at least two of the block interfaces 20 , and a plurality of the block interfaces 20 have the same shape and size.
  • the quadrilateral area 10 and the block interface 20 are included, and the block interface 20 is disposed on any side of the quadrilateral area 10 .
  • the distance between the block interface 20 and the two sides of the edge of the quadrilateral region 10 is the same.
  • the quadrilateral area 10 and two block interfaces 20 are included, and the block interfaces 20 are respectively disposed on two adjacent sides of the quadrilateral area 10 . .
  • the quadrilateral area 10 and two block interfaces 20 are included, and the block interfaces 20 are respectively disposed on two opposite sides of the quadrilateral area 10 .
  • the quadrilateral area 10 and three block interfaces 20 are included, and the block interfaces 20 are respectively disposed on three sides of the quadrilateral area 10 .
  • the quadrilateral area 10 and four block interfaces 20 are included, and the block interfaces 20 are respectively disposed on four sides of the quadrilateral area 10 .
  • the cross-sectional shape of the block interface 20 is a trapezoid
  • the trapezoid includes two oblique sides, a bottom side, and a top side, wherein the bottom side and one of the quadrilateral regions 10 The sides are coincident, the width of the depression is at least 10 microns, the inclination angle of any one of the hypotenuses is 45 degrees, and the height of the trapezoid is at least 5 microns.
  • the width of the recesses is at least 10 microns, so that the space of the isolation region 40 is larger and the adjacent square sides are isolated.
  • the heights of the trapezoids are in the range of at least 5 microns, so that the height of the block interface 20 is larger, isolating adjacent square sides.
  • the cross-sectional shape of the block interface 20 may be any of a trapezoid, a parallelogram, a rectangle, a square, and the like.
  • the pixel electrode 30 includes a main electrode 301 and a branch electrode 302 , and the main electrode 301 and the branch electrode 302 are integrally provided with the quadrilateral area 10 and the block interface 20 .
  • the dark pattern is very stable and will not be affected by the backbone of the pixel electrode 30 in the pixel area 1 Influence of electrode 301 width.
  • the transmittance of the splicing design is higher than that of the general design.
  • the actual utilization area is lower than that of the general design, and the penetration rate of the splicing design is significantly higher than that of the general design, and its higher liquid crystal efficiency makes up for the loss of penetration rate caused by this area defect.
  • the splicing design of the sub-pixel structure 2 has a higher transmittance.
  • the present application further provides a pixel structure including at least three of the sub-pixel structures.
  • the pixel structure includes a first sub-pixel 201 , a second sub-pixel 202 and a third sub-pixel 203 .
  • the first sub-pixel 201 , the second sub-pixel 202 , and the third sub-pixel 203 are formed by combining a plurality of pixel blocks 11 , and the shapes may be the same or different.
  • the pixels include, but are not limited to, the three pixel shape combination schemes shown.
  • the pixel electrode 30 includes a main electrode 301 and a branch electrode 302, and the branch electrode 302 includes a first branch electrode 302 arranged along a first direction and a second branch electrode 302 arranged along a second direction .
  • first branch electrodes 302 and the second branch electrodes 302 are staggered.
  • one of the first branch electrodes 302 and one of the second branch electrodes 302 are periodically staggered.
  • one of the first branch electrodes 302 and a plurality of the second branch electrodes 302 are arranged in a staggered manner.
  • a plurality of the first branch electrodes 302 and one of the second branch electrodes 302 are staggered periodically.
  • a plurality of the first branch electrodes 302 and a plurality of the second branch electrodes 302 are arranged in a staggered period.
  • FIG. 10 a dark pattern simulation diagram of the sub-pixel structure provided by the embodiment shown in FIG. 1 of the present application, wherein the sub-pixel structure includes four pixel blocks arranged in a two-dimensional direction, and adjacent pixel areas are formed.
  • the blocks are electrically connected by trunk electrodes, and the dark lines between adjacent pixel blocks are independent of each other. Under different voltages, the dark lines of the sub-pixel structure and the dark lines of each pixel block are relatively stable.
  • the pixel blocks 1 are arranged along a first direction and a second direction, and the sub-pixel structure 2 is in the shape of a cross, so The sub-pixel structure 2 includes at least three of the pixel blocks 1 .
  • the sub-pixel structure 2 includes at least five pixel blocks 1 .
  • the sub-pixel structure 2 includes one pixel block 1 as shown in FIG. 6 , and at least four pixel blocks 1 as shown in FIG. 2 .
  • the pixel blocks 1 are arranged along the first direction and the second direction, and the shape of the sub-pixel structure 2 is an earth-shaped shape.
  • the sub-pixel structure 2 includes at least three of the pixel blocks 1 .
  • the sub-pixel structure 2 includes at least four pixel blocks 1 .
  • the sub-pixel structure 2 includes one pixel block 1 as shown in FIG. 5 , and at least three pixel blocks 1 as shown in FIG. 2 .
  • the present application further provides a display panel, the display panel includes a plurality of pixel units, the pixel units include at least three of the sub-pixel structures 2, and the sub-pixel structures 2 include more than two pixel blocks 1,
  • the pixel blocks 1 are arranged along the first direction and/or the second direction to form a sub-pixel, wherein the adjacent pixel blocks 1 are partially connected and an isolation region 40 is formed, and the isolation region 40 is used for isolation
  • the adjacent pixel blocks 1 are opened, so that the adjacent pixel blocks 1 are arranged independently of each other, and the dark lines of the adjacent pixel blocks 1 are independent of each other.
  • the display panel includes the sub-pixel structure 2 and the pixel block 1 as shown in FIG. 1 to FIG. 12 .
  • Embodiments of the present application provide a sub-pixel structure, a pixel block, and a pixel structure.
  • the sub-pixel structure includes more than two pixel blocks, and the pixel blocks are arranged along a first direction and/or a second direction to form a Sub-pixels, wherein the adjacent pixel blocks are partially connected and an isolation area is formed, and the isolation area is used to separate the adjacent pixel blocks, so that the adjacent pixel blocks are arranged independently of each other, adjacent to each other.
  • the dark lines of the pixel blocks are independent of each other; a plurality of the pixel blocks can be combined into sub-pixel structures of various forms, and the aspect ratio of the quadrilateral area of a single pixel block is 1:1, and its dark lines It is relatively stable, and alleviates the technical problems of single sub-pixel structure and abnormal dark lines in the existing pixel structure.

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Abstract

本申请实施例提供的子像素结构包括两个以上的沿第一方向和/或第二方向排列的像素区块，相邻像素区块部分连接且形成有隔离区，通过隔离区使相邻像素区块互相独立设置；通过相邻像素区块相互独立设置，使像素区块的暗纹互相独立，缓解了现有子像素结构存在结构单一且暗纹异常的技术问题。

Description

子像素结构、像素区块以及显示面板 技术领域
本申请涉及子像素结构技术领域，尤其涉及一种子像素结构、一种像素区块和一种显示面板。
 背景技术
目前普遍采用的液晶像素的设计，其红色、蓝色、绿色三色子像素都为长方型设计。随着液晶面板的发展，在该种设计下的液晶效率，视野角等指标逐渐接近设计瓶颈，难以有较大突破。
在液晶显示屏的设计中，像素电极区域为规则的矩形，其内部的走线为呈十字形排布的主干电极、米字型关于主干电极对称的分支电极、以及区域封边组成，对于一般长方形液晶像素的设计，液晶暗纹沿着纵横主干道分布，可以获得比较好的液晶效率。但是对于复杂形状的液晶像素的设计，这种长方形液晶像素的设计构造则很不稳定，容易产生异常的暗纹。
同时通过模拟，我们发现像素区块形状越接近于正方形，其液晶效率越高，穿透率越高。而如果液晶像素趋于长方形，液晶暗区增多，液晶效率会下降。我们发现正方形的像素区块具有暗纹稳定的的优势，矩形长宽比过大时，容易产生暗纹异常，而正方形的像素区块则无暗纹异常发生。
 技术问题
因此，现有像素通常由三个大小相同的矩形子像素组成，其中矩形子像素的暗纹不稳定，同时由于子像素的形状固定为矩形，在像素的组合上，子像素的排布较为单一，形状也较为单一，现有子像素结构存在结构单一且暗纹异常的技术问题。
 技术解决方案
本申请实施例提供一种子像素结构，缓解现有子像素结构存在结构单一且暗纹异常的技术问题。
本申请实施例提供一种子像素结构，包括两个以上的像素区块，所述像素区块沿着第一方向和/或第二方向排列形成一子像素，其中，相邻所述像素区块部分连接且形成有隔离区，所述隔离区用于隔开相邻所述像素区块，使相邻所述像素区块相互独立设置，相邻所述像素区块的暗纹相互独立。
在本申请实施例提供的子像素结构中，所述像素区块包括用于显示的四边形区，所述四边形区包括呈十字形排布的主干电极、所述呈十字形排布的主干电极的长宽比范围为1:1至1:2.5。
在本申请实施例提供的子像素结构中，所述像素区块还包括分支电极，所述主干电极与所述分支电极相连，相邻像素区块通过主干电极相连接，像素信号可通过像素主枝传输给相邻像素区块。
在本申请实施例提供的子像素结构中，所述区块接口距离所述四边形区边缘两侧的间距相同，相邻区块接口互相触接且对应设置。
在本申请实施例提供的子像素结构中，所述四边形区的至少一边向外突出形成区块接口，相邻所述区块接口对向设置，相邻所述像素区块通过所述区块接口连接。
在本申请实施例提供的子像素结构中，所述四边形区上设置所述区块接口的一侧相对形成有凹陷，当相邻像素区块通过区块接口连接时，所述凹陷在所述相邻像素区块间形成所述隔离区。
在本申请实施例提供的子像素结构中，多个所述四边形区的形状、大小相同，多个所述区块接口的形状、大小相同。
在本申请实施例提供的子像素结构中，所述区块接口的截面形状为等腰梯形，所述梯形的任一条斜边的倾斜角度为45度。
在本申请实施例提供的子像素结构中，所述凹陷的宽度范围为至少10微米，所述像素区块高的范围为至少5微米。
在本申请实施例提供的子像素结构中，所述像素区块的像素电极包括主干电极和分支电极，相邻所述像素区块的主干电极通过区块接口电连接，所述分支电极关于相连接的所述主干电极非对称设置。
在本申请实施例提供的子像素结构中，所述像素区块沿着第一方向和第二方向排列设置，所述子像素结构的形状为L形、十字形、土字形中的任一种，所述子像素结构包括至少三个所述像素区块。
本实施例提供一种像素区块，包括四边形区和至少一个区块接口，所述四边形区和所述区块接口设置有像素电极，所述四边形区的四条边长度相同，所述区块接口设置在所述四边形区的四条边，其中，在多个所述像素区块相邻排列时，所述区块接口用于隔开相邻的所述四边形区。
在本申请实施例提供的像素区块中，所述像素区块包括所述四边形区和一个所述区块接口。
在本申请实施例提供的像素区块中，所述像素区块包括所述四边形区和两个所述区块接口，所述区块接口分别设置在所述四边形区的任意两条边上。
在本申请实施例提供的像素区块中，所述四边形区的任意两相邻边分别设置有一个区块接口。
在本申请实施例提供的像素区块中，所述四边形区的任意两相对边分别设置有一个区块接口。
在本申请实施例提供的像素区块中，所述像素区块包括所述四边形区和三个所述区块接口，所述区块接口分别设置在所述四边形区的任意三条边上。
在本申请实施例提供的像素区块中，所述像素区块包括所述四边形区和四个所述区块接口，所述区块接口分别设置在所述四边形区的四条边上。
在本申请实施例提供的像素区块中，所述区块接口的截面形状可以为梯形、平行四边形、矩形、正方形中的任一种。
本实施例提供一种显示面板，包括多个像素单元，所述像素单元包括至少三个所述子像素结构，所述子像素结构包括两个以上的像素区块，所述像素区块沿着第一方向和/或第二方向排列形成一子像素，其中，相邻所述像素区块部分连接且形成有隔离区，所述隔离区用于隔开相邻所述像素区块，使相邻所述像素区块相互独立设置，相邻所述像素区块的暗纹相互独立。
 有益效果
本申请实施例提供的子像素结构包括两个以上的沿第一方向和/或第二方向排列的像素区块，相邻所述像素区块部分连接且形成有隔离区，通过隔离区使相邻所述像素区块互相独立设置；通过使相邻像素区块独立设置，使像素区块的暗纹互相独立，缓解了现有子像素结构存在结构单一且暗纹异常的技术问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的子像素结构的第一种俯视示意图；
图2为本申请实施例提供的像素区块的第一种俯视示意图；
图3为本申请实施例提供的像素区块的第二种俯视示意图；
图4为本申请实施例提供的像素区块的第三种俯视示意图；
图5为本申请实施例提供的像素区块的第四种俯视示意图；
图6为本申请实施例提供的像素区块的第五种俯视示意图；
图7为本申请实施例提供的子像素结构的拼接设计和一般设计的穿透率对比图；
图8为本申请实施例提供的子像素结构的拼接设计和一般设计的暗纹仿真对比图；
图9为本申请实施例提供的像素设计的结构示意图；
图10为本申请实施例提供的子像素结构的暗纹仿真图；
图11为本申请实施例提供的子像素结构的第二种俯视示意图；
图12为本申请实施例提供的子像素结构的第三种俯视示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
如图1所示，本申请实施例提供的子像素结构2两个以上的像素区块1，所述像素区块1沿着第一方向和/或第二方向排列形成一子像素，其中，相邻所述像素区块1部分连接且形成有隔离区40，所述隔离区40用于隔开相邻所述像素区块1，使相邻所述像素区块1相互独立设置，相邻所述像素区块1的暗纹相互独立。
在本实施例中，子像素结构2包括两个以上的像素区块1，所述像素区块1沿着第一方向和/或第二方向排列形成一子像素，其中，相邻所述像素区块1部分连接且形成有隔离区40，所述隔离区40用于隔开相邻所述像素区块1，使相邻所述像素区块1相互独立设置，相邻所述像素区块1的暗纹相互独立；通过多个所述像素区块1可以组合成多种形态的子像素结构，同时单个像素区块1的四边形区10的暗纹较稳定，缓解了现有像素结构存在子像素结构单一且暗纹异常的技术问题。
其中，相互独立设置的像素区块1指的是各所述像素区块1的暗纹相互独立，且多个所述像素区块1可随意组合排列形成不同形状的子像素结构2。
其中，所述像素区块1包括主干电极301和分支电极302，相邻像素区块1通过主干电极301相连接，像素信号可通过像素主枝301传输给相邻像素区块1。
其中，两个以上的相互独立设置的像素区块1包括两个相互独立设置的像素区块1。
在本实施例中，通过相邻像素区块1独立设置形成各像素区块1独立的暗纹，再通过两个以上像素区块1以一维或二维方向排列形成子像素结构2，所述子像素结构2具有多样性，所述像素区块1可以任意组合、排列形成子像素结构2。
在一种实施例中，所述像素区块1的四边形区10的长宽比为1:1。
其中，所述像素区块1的四边形区10的长宽比范围为1:1时，即四边形区10为方形区域时，暗纹最收敛。
在一种实施例中，所述像素区块1包括用于显示的四边形区10，所述四边形区10包括呈十字形排布的主干电极301、所述呈十字形排布的主干电极301的长宽比范围为1:1至1:2.5。
在一种实施例中，所述四边形区10的至少一边向外突出形成区块接口20，相邻所述区块接口20对向设置，相邻所述像素区块1通过所述区块接口20连接。
在一种实施例中，所述四边形区10上设置所述区块接口20的一侧相对形成有凹陷，当相邻像素区块1通过区块接口20连接时，所述凹陷在所述相邻像素区块间形成所述隔离区40。
在一种实施例中，多个所述四边形区10的形状、大小相同，多个所述区块接口的形状、大小相同。
在一种实施例中，所述区块接口20的截面形状为等腰梯形，所述梯形的任一条斜边的倾斜角度为45度。
在一种实施例中，所述凹陷的宽度范围为至少10微米，所述像素区块1高的范围为至少5微米。
在一种实施例中，所述像素区块1的像素电极包括主干电极301和分支电极302，相邻所述像素区块1的主干电极301通过区块接口20电连接，所述分支电极302关于相连接的所述主干电极301非对称设置。
在一种实施例中，所述像素区块1沿着第一方向和第二方向排列设置，所述子像素结构2的形状为L形、十字形、土字形中的任一种，所述子像素结构2包括至少三个所述像素区块1。
通过模拟可知像素区块1形状越接近于正方形，其液晶效率越高，穿透率越高；而如果像素区块1越接近于矩形，则液晶暗区增多，液晶效率会下降，穿透率也会降低，且所述矩形的长宽比越大时，越容易产生暗纹异常，而正方形图形单元则无暗纹异常发生，正方形的图形单元具有暗纹稳定的的优势。
在一种实施例中，所述像素电极30包括主干电极301、以及与所述主干电极301连接的分支电极302，所述主干电极301包括横向主干电极301和纵向主干电极301。
其中，所述像素区块1中的所述四边形区10长宽为1:1时，在增加单条所述像素电极30主干电极301的宽度时或同时增加横向主干电极301和纵向主干电极301的宽度时，暗纹均未发生紊乱。
在本实施例中，当所述四边形区10的宽度为1:1时，像素区块1以及子像素结构2的暗纹稳定，当改变主干电极301的宽度时，也不影响暗纹的稳定效果。
在一种实施例中，如图1所示，所述子像素结构2为L形。
其中，所述L形可以为四个像素区块1组成。
其中，所述四个像素区块1可以为两个包括一所述区块接口20的像素区块1、以及包含两个所述区块接口20的两个像素区块1。
其中，一个可以为相邻边分别设置有一个区块接口20的像素区块1，另一个可以为相对边分别设置有一个区块接口20的像素区块1。
其中，所述区块接口20距离所述四边形区10边缘两侧的间距相同，相邻区块接口20互相触接且对应设置。
在一种实施例中，所述子像素结构2中，相邻四边形区10之间的区块接口20可以为四个。
其中，一个四边形区10包括第一区块接口20和第二区块接口20，另一个四边形区10也包括第三区块接口20和第四区块接口20，
其中，所述第一区块接口20和所述第二区块接口20的形状、大小不同，其中第一区块接口20的截面面积大小大于所述第二区块接口20的截面面积大小。
其中，所述第三区块接口20和所述第四区块接口20的形状、大小不同，其中第三区块接口20的截面面积大小大于所述第四区块接口20的截面面积大小。
其中，所述第一区块接口20可以与所述第三区块接口20互相触接设置。
其中，所述第二区块接口20可以与所述第四区块接口20互相触接设置。
其中，所述第一区块接口20可以与所述第三区块接口20的形状、大小相同。
其中，所述第二区块接口20可以与所述第四区块接口20的形状、大小相同。
如图2至图6所示，本申请实施例提供的像素区块1包括四边形区10和至少一个区块接口20，所述四边形区10和所述区块接口20设置有像素电极30，所述四边形区10的四条边长度相同，所述区块接口20设置在所述四边形区10的四条边，其中，在多个所述像素区块1相邻排列时，所述区块接口20用于隔开相邻的所述四边形区10。
在本实施例中，所述像素区块1包括四边形区10和至少一个区块接口20，所述四边形区10和所述区块接口20设置有像素电极30，所述四边形区10的四条边长度相同，所述区块接口20设置在所述四边形区10的四条边，其中，在多个所述像素区块1相邻排列时，所述区块接口20用于隔开相邻的所述四边形区10；通过多个所述像素区块1可以组合成多种形态的子像素结构2，同时单个像素区块1为方形，其暗纹较稳定，缓解了现有像素结构存在子像素结构2单一且暗纹异常的技术问题。
其中，所述四边形区10和所述区块接口20的像素电极30一体设置。
其中，所述四边形区10的暗纹稳定，多个像素区块1组合在一起，所述区块接口20用于隔开相邻的四边形区10。
其中像素电极30包括主干电极301和分支电极302。
在一种实施例中，所述四边形区10的任一边最多只设置有一所述区块接口20。
在一种实施例中，所述四边形区10的任一边可以设置有多个所述区块接口20。
在一种实施例中，所述像素区块1包括至少两个所述区块接口20，多个所述区块接口20的形状、大小均相同。
在一种实施例中，如图2所示，包括一所述四边形区10和一所述区块接口20，所述区块接口20设置在所述四边形区10的任一条边。
其中，所述区块接口20距离所述四边形区10边缘两侧的间距相同。
在一种实施例中，如图3所示，包括一所述四边形区10和两个所述区块接口20，所述区块接口20分别设置在所述四边形区10相邻的两条边。
在一种实施例中，如图4所示，包括一所述四边形区10和两个所述区块接口20，所述区块接口20分别设置在所述四边形区10相对的两条边。
在一种实施例中，如图5所示，包括一所述四边形区10和三个所述区块接口20，所述区块接口20分别设置在所述四边形区10的三条边。
在一种实施例中，如图6所示，包括一所述四边形区10和四个所述区块接口20，所述区块接口20分别设置在所述四边形区10的四条边。
在一种实施例中，所述区块接口20的截面形状为梯形，所述梯形包括两条斜边、一底边、一顶边，其中，所述底边与所述四边形区10的一条边重合，所述凹陷的宽度范围为至少10微米，任一所述斜边的倾斜角度为45度，所述梯形的高度范围为至少5微米。
在一种实施例中，所述所述凹陷的宽度范围为至少10微米，使得隔离区40的空间较大，隔离相邻的方形边。
在一种实施例中，梯形的高度范围为至少5微米，使得区块接口20的高度较大，隔离相邻的方形边。
在一种实施例中，所述区块接口20的截面形状可以为梯形、平行四边形、矩形、正方形等形状中的任一种。
在一种实施例中，所述像素电极30包括主干电极301和分支电极302，所述主干电极301和所述分支电极302一体设置与所述四边形区10和所述区块接口20。
在本实施例中，所述四边形区10的长宽比接近于1：1时，即为方形时，其暗纹非常稳定，不会受到所述像素区块1中的所述像素电极30主干电极301宽度的影响。
如图7、图8所示，为所述子像素结构2的拼接设计和一般设计在不同电压下的穿透率数据，拼接设计的穿透率高于一般设计的穿透率，由于接头的存在其实际利用面积比一般设计的实际利用面积要低，同时拼接设计的穿透率明显高于一般设计，其较高的液晶效率弥补了这一面积缺损带来的穿透率损失。
其中，对比穿透率数据可以在图8中直观的看到，在电压相同的情况下，拼接设计的穿透率高于一般设计的穿透率。
其中，所述子像素结构2的拼接设计的穿透率更高。
如图9所示，本申请还提供一种像素结构，包括至少三个所述子像素结构。
其中，像素结构包括第一子像素201、第二子像素202、第三子像素203。
在一种实施例中，所述第一子像素201、所述第二子像素202、所述第三子像素203均有多个像素区块11组合而成，形状可以相同，也可以不同。
在一种实施例中，如图8所示，所述像素包括但不限于所示的三种像素形状组合方案。
在一种实施例中，所述像素电极30包括主干电极301和分支电极302，所述分支电极302包括沿第一方向设置的第一分支电极302和沿第二方向设置的第二分支电极302。
在一种实施例中，所述第一分支电极302和所述第二分支电极302交错排列。
其中，一所述第一分支电极302和一所述第二分支电极302为周期交错排列。
其中，一所述第一分支电极302和多个所述第二分支电极302为周期交错排列。
其中，多个所述第一分支电极302和一所述第二分支电极302为周期交错排列。
其中，多个所述第一分支电极302和多个所述第二分支电极302为周期交错排列。
如图10所示，为本申请图1所示实施例提供的子像素结构的暗纹仿真图，其中，所述子像素结构包括四个像素区块沿二维方向排列形成，相邻像素区块之间通过主干电极电连接，相邻像素区块之间暗纹相互独立，在不同的电压下，子像素结构的暗纹和各像素区块的暗纹均较稳定。
如图11所示，为本申请实施例提供的一种子像素结构2，所述像素区块1沿着第一方向和第二方向排列设置，所述子像素结构2的形状为十字形，所述子像素结构2包括至少三个所述像素区块1。
其中，所述子像素结构2至少包括五个像素区块1。
在本实施例中，所述子像素结构2包括一个如图6所示的像素区块1、以及至少4个如图2所示的像素区块1。
如图12所示，为本申请实施例提供的一种子像素结构2，所述像素区块1沿着第一方向和第二方向排列设置，所述子像素结构2的形状为土字形，所述子像素结构2包括至少三个所述像素区块1。
其中，所述子像素结构2至少包括四个像素区块1。
在本实施例中，所述子像素结构2包括一个如图5所示的像素区块1、以及至少3个如图2所示的像素区块1。
本申请还提供一种显示面板，所述显示面板包括多个像素单元，所述像素单元包括至少三个所述子像素结构2，所述子像素结构2包括两个以上的像素区块1，所述像素区块1沿着第一方向和/或第二方向排列形成一子像素，其中，相邻所述像素区块1部分连接且形成有隔离区40，所述隔离区40用于隔开相邻所述像素区块1，使相邻所述像素区块1相互独立设置，相邻所述像素区块1的暗纹相互独立。
其中，所述显示面板包括如图1至图12的所述子像素结构2和所述像素区块1。
本申请实施例提供了一种子像素结构、像素区块、以及像素结构，子像素结构包括两个以上的像素区块，所述像素区块沿着第一方向和/或第二方向排列形成一子像素，其中，相邻所述像素区块部分连接且形成有隔离区，所述隔离区用于隔开相邻所述像素区块，使相邻所述像素区块相互独立设置，相邻所述像素区块的暗纹相互独立；通过多个所述像素区块可以组合成多种形态的子像素结构，同时单个像素区块的四边形区的长宽比为1:1，其暗纹较稳定，缓解了现有像素结构存在子像素结构单一且暗纹异常的技术问题。
以上对本申请实施例所提供的一种进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种子像素结构，其包括两个以上的像素区块，所述像素区块沿着第一方向和/或第二方向排列形成一子像素，其中，相邻所述像素区块部分连接且形成有隔离区，所述隔离区用于隔开相邻所述像素区块，使相邻所述像素区块相互独立设置，相邻所述像素区块的暗纹相互独立。
  2. 如权利要求1所述的子像素结构，其中，所述像素区块包括用于显示的四边形区，所述四边形区包括呈十字形排布的主干电极、所述呈十字形排布的主干电极的长宽比范围为1:1至1:2.5。
  3. 如权利要求2所述的子像素结构，其中，所述像素区块还包括分支电极，所述主干电极与所述分支电极相连，相邻像素区块通过主干电极相连接，像素信号可通过像素主枝传输给相邻像素区块。
  4. 如权利要求3所述的像素区块，其中，所述区块接口距离所述四边形区边缘两侧的间距相同，相邻区块接口互相触接且对应设置。
  5. 如权利要求2所述的子像素结构，其中，所述四边形区的至少一边向外突出形成区块接口，相邻所述区块接口对向设置，相邻所述像素区块通过所述区块接口连接。
  6. 如权利要求5所述的子像素结构，其中，所述四边形区上设置所述区块接口的一侧相对形成有凹陷，当相邻像素区块通过区块接口连接时，所述凹陷在所述相邻像素区块间形成所述隔离区。
  7. 如权利要求1所述的子像素结构，其中，多个所述四边形区的形状、大小相同，多个所述区块接口的形状、大小相同。
  8. 如权利要求7所述的子像素结构，其中，所述区块接口的截面形状为等腰梯形，所述梯形的任一条斜边的倾斜角度为45度。
  9. 如权利要求8所述的子像素结构，其中，所述凹陷的宽度范围为至少10微米，所述像素区块高的范围为至少5微米。
  10. 如权利要求7所述的子像素结构，其中，所述像素区块的像素电极包括主干电极和分支电极，相邻所述像素区块的主干电极通过区块接口电连接，所述分支电极关于相连接的所述主干电极非对称设置。
  11. 如权利要求5所述的子像素结构，其中，所述像素区块沿着第一方向和第二方向排列设置，所述子像素结构的形状为L形、十字形、土字形中的任一种，所述子像素结构包括至少三个所述像素区块。
  12. 一种像素区块，其包括四边形区和至少一个区块接口，所述四边形区和所述区块接口设置有像素电极，所述四边形区的四条边长度相同，所述区块接口设置在所述四边形区的四条边，其中，在多个所述像素区块相邻排列时，所述区块接口用于隔开相邻的所述四边形区。
  13. 如权利要求12所述的像素区块，其中，所述像素区块包括所述四边形区和一个所述区块接口。
  14. 如权利要求12所述的像素区块，其中，所述像素区块包括所述四边形区和两个所述区块接口，所述区块接口分别设置在所述四边形区的任意两条边上。
  15. 如权利要求14所述的像素区块，其中，所述四边形区的任意两相邻边分别设置有一个区块接口。
  16. 如权利要求14所述的像素区块，其中，所述四边形区的任意两相对边分别设置有一个区块接口。
  17. 如权利要求12所述的像素区块，其中，所述像素区块包括所述四边形区和三个所述区块接口，所述区块接口分别设置在所述四边形区的任意三条边上。
  18. 如权利要求12所述的像素区块，其中，所述像素区块包括所述四边形区和四个所述区块接口，所述区块接口分别设置在所述四边形区的四条边上。
  19. 如权利要求12所述的像素区块，其中，所述区块接口的截面形状可以为梯形、平行四边形、矩形、正方形中的任一种。
  20. 一种显示面板，其包括多个像素单元，所述像素单元包括至少三个所述子像素结构，所述子像素结构包括两个以上的像素区块，所述像素区块沿着第一方向和/或第二方向排列形成一子像素，其中，相邻所述像素区块部分连接且形成有隔离区，所述隔离区用于隔开相邻所述像素区块，使相邻所述像素区块相互独立设置，相邻所述像素区块的暗纹相互独立。
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