WO2022116257A1 - 阻变存储器及其制备方法 - Google Patents

阻变存储器及其制备方法 Download PDF

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WO2022116257A1
WO2022116257A1 PCT/CN2020/136003 CN2020136003W WO2022116257A1 WO 2022116257 A1 WO2022116257 A1 WO 2022116257A1 CN 2020136003 W CN2020136003 W CN 2020136003W WO 2022116257 A1 WO2022116257 A1 WO 2022116257A1
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layer
resistive
resistive switching
sccm
upper electrode
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PCT/CN2020/136003
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English (en)
French (fr)
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许晓欣
李晓燕
董大年
余杰
吕杭炳
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中国科学院微电子研究所
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Priority to US18/254,981 priority Critical patent/US20240023469A1/en
Publication of WO2022116257A1 publication Critical patent/WO2022116257A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/023—Formation of switching materials, e.g. deposition of layers by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes

Definitions

  • the present disclosure relates to the technical field of memory, and in particular, to a resistive memory and a preparation method thereof.
  • Resistive memory is a new type of non-volatile memory technology. It has the advantages of simple structure, low operating voltage and easy integration. It has important application prospects in non-volatile storage, logic circuits and neuromorphic computing.
  • the conductive filaments in the dielectric layer of the resistive memory are formed and broken, so the resistance value of the resistive memory can be cyclically switched between a high-resistance state and a low-resistance state.
  • the formation and breakage of the conductive filaments correspond to the writing and erasing operations of the resistive memory, respectively.
  • the problem of reverse breakdown is prone to occur, resulting in the failure of the device.
  • a resistive memory including: a resistive layer, an upper electrode and a potential barrier structure, the resistive layer is disposed on a substrate, and is used to make the device perform a writing or erasing operation so that The device generates a high-resistance state or a low-resistance state; the upper electrode is arranged on the resistive switching layer and is used as a lead-out electrode of the device; the potential barrier structure is arranged between the resistive switching layer and the upper electrode, and is used to perform an erasing operation on the device When the electrons pass through the conduction band of the potential barrier structure, the formation of defects in the resistive switching layer is avoided, resulting in reverse breakdown of the resistive switching layer.
  • the potential barrier structure includes: a potential barrier layer and an intercalation layer, the potential barrier layer is disposed on the resistive switching layer, and is used as a storage layer for oxygen ions when the device performs an erasing operation, so that electrons can flow from The conduction band of the barrier layer passes through; the intercalation layer is arranged between the barrier layer and the upper electrode, and is used as an auxiliary storage layer for oxygen ions when the device performs an erasing operation, so as to further prevent the oxygen ions from directly entering the upper electrode.
  • the resistive layer material is Ta 2 O 5 ;
  • the barrier layer material is TaO x , where x ⁇ [1.1, 1.8];
  • the intercalation material is Ta, Ti, metal oxide, amorphous silicon , at least one of amorphous carbon and graphene, wherein the thickness of the intercalation layer is 2nm-20nm; wherein, the potential barrier between the barrier layer and the resistive switching layer is 0.45eV-0.65eV.
  • the resistive memory also includes: a lower electrode disposed between the resistive layer and the substrate and used as another lead-out electrode of the device.
  • the material of the lower electrode is at least one of TiN and TaN; the material of the upper electrode is at least one of Ir, Al, Ru, Pd, TiN, and TaN; wherein the thickness of the lower electrode and the upper electrode is 20 nm -500nm.
  • Another aspect of the present disclosure provides a preparation method for preparing the above-mentioned resistive memory, including: forming a resistive layer on a substrate; forming a barrier structure on the resistive layer; forming on the barrier structure The upper electrode; wherein, the potential barrier structure is used for electrons to pass through the conduction band of the potential barrier structure when the device performs an erasing operation, so as to avoid the formation of defects in the resistive switching layer and cause reverse breakdown of the resistive switching layer.
  • forming a potential barrier structure on the resistive switching layer includes: forming a potential barrier layer on the resistive switching layer, where the potential barrier layer is used as a storage layer for oxygen ions when the device performs an erasing operation, In order to make electrons pass through the conduction band of the barrier layer; an intercalation layer is formed on the barrier layer, and the intercalation layer is used as an auxiliary storage layer for oxygen ions when the device performs an erasing operation to further prevent oxygen ions from directly entering the upper electrode.
  • the preparation conditions of the reactive sputtering process further include: the substrate temperature is room temperature, the power is 400W, and the gas pressure is 3mtorr.
  • forming the intercalation layer on the barrier layer includes: preparing the intercalation layer through a sputtering process, an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process.
  • forming the resistive switching layer on the substrate includes: preparing the resistive switching layer through a reactive sputtering process, an atomic layer deposition process, a thermal oxidation process, a magnetron sputtering process or an ion beam sputtering process.
  • the method before the resistive switching layer is formed on the substrate, the method further includes: forming a lower electrode on the substrate; wherein, the preparation process of the lower electrode and the upper electrode is a sputtering process, an atomic layer deposition process, a physical vapor phase process Deposition process or chemical vapor deposition process.
  • FIG. 1 schematically shows a structural composition diagram of a resistive memory according to an embodiment of the present disclosure
  • FIG. 2A schematically shows a working principle diagram of a resistive memory according to an embodiment of the present disclosure
  • FIG. 2B schematically shows a working principle diagram of a barrier layer according to an embodiment of the present disclosure
  • FIG. 3 schematically shows a flowchart of a method for manufacturing a resistive memory according to an embodiment of the present disclosure
  • FIG. 4 schematically shows a standard IV characteristic curve diagram of a resistive memory according to an embodiment of the present disclosure
  • FIG. 5 schematically shows a graph of the number of resistance switching cycles of the resistive memory according to the embodiment of the present disclosure.
  • modules in the device in the embodiment can be adaptively changed and placed in one or more devices different from the embodiment.
  • the modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore they may be divided into multiple sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method so disclosed may be employed in any combination unless at least some of such features and/or procedures or elements are mutually exclusive. All processes or units of equipment are combined.
  • Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
  • a unit claim enumerating several means several of these means can be embodied by one and the same item of hardware.
  • the present disclosure provides a resistive memory and a preparation method thereof.
  • an aspect of the present disclosure provides a resistive memory 100 , which includes: a resistive switching layer 120 , an upper electrode 150 and a potential barrier structure, and the resistive switching layer 120 is disposed on a substrate
  • the upper electrode is used to make the device generate a high resistance state or a low resistance state when the device performs a writing or erasing operation
  • the upper electrode 150 is arranged on the resistive switching layer 120 and is used as an extraction electrode of the device
  • the barrier structure is arranged Between the resistive switching layer 120 and the upper electrode 150 , when the device performs an erasing operation, electrons pass through the conduction band of the potential barrier structure, so as to prevent the resistive switching layer 120 from forming defects and causing reverse breakdown of the resistive switching layer 120 .
  • the barrier structure has an oxide layer with an incomplete ratio. Since the barrier structure is formed between the resistive switching layer 120 and the upper electrode 150, during the erasing operation of the device, when the applied erasing voltage gradually increases When increasing, the conduction band energy level of the resistive switching layer 120 will be leveled with the conduction band energy level of the oxide layer, and electrons pass through the conduction band of the potential barrier structure, avoiding the formation of excessive defects in the resistive switching layer 120. Therefore, There is no reverse breakdown of the device, so that the durability of the device can be further improved.
  • the barrier structure includes: a barrier layer 130 and an intercalation layer 140 .
  • the intercalation layer 140 acts as a storage layer for oxygen ions, so that electrons pass through the conduction band of the barrier layer 130; the intercalation layer 140 is arranged between the barrier layer 130 and the upper electrode 150, and is used when the device performs the erasing operation.
  • as an auxiliary storage layer for oxygen ions to further prevent oxygen ions from directly entering the upper electrode 150 .
  • the oxygen ions in the resistive switching layer 120 migrate to the upper electrode 150 under the action of the electric field, and are stored in the barrier layer 130 and the intercalation layer 140 of the barrier structure, Finally, conductive filaments composed of oxygen vacancies are formed in the resistive switching layer 120, the device becomes a low resistance state (ie, LRS), and the writing operation is completed.
  • LRS low resistance state
  • the oxygen ions stored in the barrier layer 130 and the intercalation layer 140 migrate back to the resistive switching layer 120 under the action of the electric field, and recombine with the oxygen vacancies, so that the above-mentioned oxygen vacancy conductive filaments are broken , the device returns to the high-impedance state (ie, HRS), and the erase operation is completed.
  • HRS high-impedance state
  • the reverse voltage borne by the electrolyte layer of the resistive layer 120 is too high, which will directly cause the resistive layer
  • the electrolyte layer of 120 is reversely broken down, resulting in device failure.
  • the material of the resistive switching layer 120 is Ta 2 O 5 ; the material of the barrier layer 130 is TaO x , where x ⁇ [1.1, 1.8]; the material of the intercalation layer 140 It is at least one of Ta, Ti, metal oxide, amorphous silicon, amorphous carbon, and graphene, wherein the thickness of the intercalation layer 140 is 2nm-20nm; The barrier is 0.45eV-0.65eV.
  • the O/Ar flow ratio is 3 sccm: 50 sccm to 6 sccm: 50 sccm, so that the TaO x material of the barrier layer 130 is obtained as an oxide with an incomplete ratio thing.
  • a potential barrier of 0.45eV-0.65eV exists between the TaO x material of the barrier layer 130 and the Ta 2 O 5 material of the resistive switching layer 120 .
  • the device when the device is under the reverse erasing voltage after the erasing operation is performed, the device electrons are injected from the upper electrode 150 and enter Ta 2 through the TaO x barrier layer 130 to overcome the potential barrier. O 5 in the resistive layer 120 .
  • the applied reverse voltage gradually increases, the shallow energy level defects in the Ta 2 O 5 resistive switching layer 120 are gradually filled, and the conduction band energy level thereof gradually decreases.
  • the electrons migrated from the TaO x barrier layer 130 can directly pass through the conduction band energy level of the Ta 2 O 5 resistive switching layer 120, forming a comparison large current.
  • the conduction band energy level of the Ta 2 O 5 resistive switching layer 120 is raised, electrons cannot pass through, and the device returns to a high resistance state (HRS). Due to the modulation effect of the conduction band energy level between the Ta 2 O 5 resistive switching layer 120 and the TaO x barrier layer 130 , the formation of excessive defects in the Ta 2 O 5 resistive switching layer 120 is avoided, thus avoiding the erasing process. reverse breakdown problem.
  • the role played by the intercalation layer 140 in the above-mentioned process is similar to that of the TaO x barrier layer 130 , so as to further convect the oxygen ions flowing to the upper electrode 150 on the basis of the oxygen ions stored in the TaO x barrier layer 130
  • the oxygen ion-assisted storage layer as the barrier structure achieves the effect of further avoiding the direction breakdown of the Ta 2 O 5 resistive layer 120 during the erasing and writing operations.
  • the TaO x barrier layer 130 can be immediately the oxygen ion main storage layer of the barrier structure of the embodiment of the present disclosure.
  • the resistive memory 100 further includes: a lower electrode 110 .
  • the lower electrode 110 is disposed between the resistive layer 120 and the substrate, and is used as another lead of the device. electrode.
  • the material of the lower electrode is at least one of TiN and TaN; the material of the upper electrode is at least one of Ir, Al, Ru, Pd, TiN, and TaN; wherein the thickness of the lower electrode and the upper electrode is 20 nm -500nm. Therefore, both the upper and lower electrodes have a conductive effect to serve as the upper and lower lead-out electrodes of the device.
  • another aspect of the present disclosure provides a preparation method for preparing the above-mentioned resistive memory 100, which includes steps S101-S103.
  • step S101 a resistive switching layer 120 is formed on the substrate;
  • step S102 a potential barrier structure is formed on the resistive switching layer 120;
  • step S103 an upper electrode 150 is formed on the barrier structure
  • the potential barrier structure is used for electrons to pass through the conduction band of the potential barrier structure when the device performs an erasing operation, so as to prevent the resistive switching layer 120 from forming defects and causing reverse breakdown of the resistive switching layer 120 .
  • the barrier structure has an oxide layer with an incomplete ratio. Since the barrier structure is formed between the resistive switching layer 120 and the upper electrode 150, during the erasing operation of the device, when the applied erasing voltage gradually increases When increasing, the conduction band energy level of the resistive switching layer 120 will be leveled with the conduction band energy level of the oxide layer, and electrons pass through the conduction band of the potential barrier structure, avoiding the formation of excessive defects in the resistive switching layer 120. Therefore, There is no reverse breakdown of the device, so that the durability of the device can be further improved.
  • the step S102 : forming a barrier structure on the resistive switching layer 120 includes: forming a potential barrier layer 130 on the resistive switching layer 120 .
  • the device When the device performs an erasing operation, it acts as a storage layer for oxygen ions, so that electrons pass through the conduction band of the barrier layer 130; an intercalation layer 140 is formed on the barrier layer 130, and the intercalation layer 140 is used to perform erasing on the device. In operation, it acts as an auxiliary storage layer for oxygen ions to further prevent oxygen ions from directly entering the upper electrode 150 .
  • the inert gas may be Ar.
  • the preparation conditions of the reactive sputtering process further include: the substrate temperature is room temperature, the power is 400W, and the gas pressure is 3mtorr.
  • a TaO x barrier layer 130 is prepared on the Ta 2 O 5 resistive layer 120 .
  • the content of oxygen in the TaO x barrier layer 130 needs to be precisely controlled, and the value of x ranges from 1.1 to 1.8.
  • the oxygen content in the TaO x barrier layer 130 is adjusted by changing the oxygen flow ratio during the reactive sputtering process.
  • the reaction parameters of the specific reactive sputtering process are: the substrate temperature is room temperature, the O/Ar flow ratio is 2sccm:50sccm: 8sccm:50sccm, the power is 400W, and the gas pressure is 3mtorr; the TaO x barrier is precisely controlled
  • the content of oxygen in the layer 130 can adjust the height of the barrier between the TaO x barrier layer 130 and the Ta 2 O 5 resistive switching layer 120 to a desired range.
  • forming the intercalation layer 140 on the barrier layer 130 includes: preparing the intercalation layer through a sputtering process, an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process.
  • An intercalation layer 140 is formed on the upper surface of the barrier layer 130 of the resistive switching layer 120.
  • the intercalation material may be a metal, such as Ta or Ti, or a semiconductor material such as metal oxide, amorphous silicon, amorphous C or graphite. ene, etc.
  • the intercalation layer 140 can be prepared by a sputtering process (eg reactive sputtering process), atomic layer deposition process, physical vapor deposition process or chemical vapor deposition process.
  • the thickness of the intercalation layer 140 may be 2nm-20nm, and the intercalation layer 140 is mainly used as an auxiliary storage layer for oxygen ions to further prevent oxygen ions from entering the upper electrode 150, resulting in failure of the retention characteristics of the device.
  • step S101 forming a resistive switching layer 120 on a substrate, including: reactive sputtering process, atomic layer deposition process, thermal oxidation process, magnetron sputtering process
  • the resistive switching layer 120 is prepared in a process or an ion beam sputtering process.
  • the inert gas may be Ar.
  • the resistive layer 120 can also be prepared by atomic layer deposition (Atomic Layer Deposition) process, thermal oxidation (thermal oxidation) process, etc.; method to prepare.
  • the method before step S101 : forming the resistive switching layer 120 on the substrate, the method further includes: forming a lower electrode 110 on the substrate; wherein the lower electrode 110 and the upper electrode 110 are formed on the substrate.
  • the preparation process of the electrode 150 is a sputtering process, an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process.
  • the lower electrode 110 is formed by preparing metal materials such as TiN or TaN on the substrate by magnetron sputtering, and the preparation method is sputtering, atomic layer deposition, physical vapor deposition or chemical vapor deposition.
  • the thickness of the lower electrode 110 is 20 nm-500 nm, and has a conductive function.
  • the upper electrode 150 is formed on the intercalation layer 140.
  • the material of the upper electrode 150 is not limited, and can be Ir, Al, Ru, Pd, TiN or TaN, etc.
  • the thickness of the upper electrode 150 is 20nm-500nm. Connectivity.
  • the device has obvious threshold transition characteristics during the erasing process, and the maximum current value can reach 4 mA.
  • the resistance state of the device does not change. Therefore, by using the barrier structure of the resistive memory according to the embodiment of the present disclosure, the problem of reverse breakdown of the resistive device can be avoided, thereby improving the durability of the device.
  • the device also increases the selection range of the erasing voltage and improves the uniformity of the high resistance state.
  • the resistive memory of the embodiment of the present disclosure can avoid the overprogramming problem during the erasing process through the barrier layer and the intercalation layer of the barrier structure, and the device has good durability and can be stably cycled for 10 More than ten thousand times, and the distribution of high and low resistance states of the device is uniform.
  • the resistive memory and the preparation method thereof provided by the present disclosure, by adding a non-completely proportioned oxide layer between the resistive layer and the upper electrode as a potential barrier structure, in the device
  • the conduction band energy level of the resistive layer will be leveled with the conduction band energy level of the oxide layer, and electrons pass through the conduction band of the barrier structure, avoiding Therefore, excessive defects are formed in the resistive layer, so the device will not have reverse breakdown, so that the durability of the device can be further improved.

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Abstract

本公开提供了一种阻变存储器及其制备方法，其中阻变存储器包括：阻变层、上电极和势垒结构，阻变层设置于衬底上；上电极设置于阻变层上；势垒结构设置于阻变层和上电极之间，用于在器件执行擦除操作时，电子从势垒结构的导带通过，避免阻变层形成缺陷，造成阻变层的反向击穿。通过在阻变层和上电极之间增加一层非完全配比的氧化层作为势垒结构，在该器件的擦除操作过程中，当施加的擦除电压逐渐增大时，阻变层的导带能级会与该氧化层的导带能级拉平，电子从势垒结构的导带中通过，避免了阻变层中形成过多的缺陷，因此器件不会出现反向击穿，使得器件的耐久性得以进一步提高。

Description

阻变存储器及其制备方法 技术领域
本公开涉及存储器技术领域，特别涉及一种阻变存储器及其制备方法。
背景技术
阻变存储器是一种新型的非易失性存储器技术，具有结构简单、操作电压低且易于集成等优势，在非易失性存储、逻辑电路和神经形态计算中有重要的应用前景。
在外加电场激励下，会使得阻变存储器的介电层中的导电细丝形成和断裂，因此阻变存储器的电阻值可以在高阻态和低阻态之间循环切换。其中，导电细丝的形成和断裂分别对应该阻变存储器的写入和擦除操作。然而，器件在擦除过程，由于流经器件上的电流比较大，易于出现反向击穿的问题，导致器件的失效。
发明内容
本公开的一个方面提供了一种阻变存储器，其中包括：阻变层、上电极和势垒结构，阻变层设置于衬底上，用于在器件执行写入或擦除操作时，使得器件产生高阻态或低阻态；上电极设置于阻变层上，用于作为器件的一引出电极；势垒结构设置于阻变层和上电极之间，用于在器件执行擦除操作时，电子从势垒结构的导带通过，避免阻变层形成缺陷，造成阻变层的反向击穿。
根据本公开的实施例，势垒结构包括：势垒层和插层，势垒层设置于阻变层上，用于在器件执行擦除操作时，作为氧离子的储蓄层，以使得电子从势垒层的导带通过；插层设置于势垒层和上电极之间，用于在器件执行擦除操作时，作为氧离子的辅助储蓄层，以进一步防止氧离子直接进入上电极。
根据本公开的实施例，阻变层材料为Ta 2O 5；势垒层材料为TaO x，其中，x∈[1.1，1.8]；插层材料为Ta、Ti、金属氧化物、非晶硅、非晶碳、石墨烯中至少一种，其中，插层的厚度为2nm-20nm；其中，所述势垒层与阻变层之间的势垒为0.45eV-0.65eV。
根据本公开的实施例，阻变存储器还包括：下电极，下电极设置于阻 变层和衬底之间，用于作为器件的另一引出电极。
根据本公开的实施例，下电极材料为TiN、TaN中至少一种；上电极材料为Ir、Al、Ru、Pd、TiN、TaN中至少一种；其中，下电极和上电极的厚度为20nm-500nm。
本公开的另一方面提供了一种用于制备上述的阻变存储器的制备方法，其中包括：在衬底上形成阻变层；在阻变层上形成势垒结构；在势垒结构上形成上电极；其中，势垒结构用于在器件执行擦除操作时，电子从势垒结构的导带通过，避免阻变层形成缺陷，造成阻变层的反向击穿。
根据本公开的实施例，在阻变层上形成势垒结构中，包括：在阻变层上形成势垒层，势垒层用于在器件执行擦除操作时，作为氧离子的储蓄层，以使得电子从势垒层的导带通过；在势垒层上形成插层，插层用于在器件执行擦除操作时，作为氧离子的辅助储蓄层，以进一步防止氧离子直接进入上电极。
根据本公开的实施例，在阻变层上形成势垒层中，包括：通过调节反应溅射工艺的氧气流量比制备势垒层；其中，氧气流量比为氧气流量sccm O和惰性气体流量sccm D之间的比值r，其中，r∈[r 1，r 2]，r 1＝sccm O∶sccm D＝2sccm∶50sccm，r 2＝sccm O∶sccm D＝8sccm∶50sccm。
根据本公开的实施例，反应溅射工艺的制备条件还包括：衬底温度为室温，功率为400W，气压为3mtorr。
根据本公开的实施例，在势垒层上形成插层，包括：通过溅射工艺、原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺制备插层。
根据本公开的实施例，在衬底上形成阻变层，包括：通过反应溅射工艺、原子层沉积工艺、热氧化工艺、磁控溅射工艺或离子束溅射工艺中制备阻变层。
根据本公开的实施例，在反应溅射工艺的制备条件包括：氧气流量比为氧气流量sccm O和惰性气体流量sccm D之间的比值s，其中，s∈[s 1，s 2]，s 1＝sccm O∶sccm D＝12sccm∶50sccm，s 2＝sccmO∶sccmD＝20sccm∶50sccm；衬底温度为室温，功率为400W，气压＝3mtorr。
根据本公开的实施例，在衬底上形成阻变层之前，还包括：在衬底上形成下电极；其中，下电极和上电极的制备工艺为溅射工艺、原子层沉积 工艺、物理气相沉积工艺或化学气相沉积工艺。
附图说明
图1示意性示出了本公开实施例的阻变存储器的结构组成图；
图2A示意性示出了本公开实施例的阻变存储器的工作原理图；
图2B示意性示出了本公开实施例的势垒层的工作原理图；
图3示意性示出了本公开实施例的阻变存储器的制备方法的流程图；
图4示意性示出了本公开实施例的阻变存储器的标准IV特性曲线图；
图5示意性示出了本公开实施例的阻变存储器的电阻切换循换次数图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。
还需要说明的是，实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本公开的保护范围。贯穿附图，相同的元素由相同或相近的附图标记来表示。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。
并且图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。另外，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。
再者，单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。
说明书与权利要求中所使用的序数例如“第一”、“第二”、“第三”等的用词，以修饰相应的元件，其本身并不意味着该元件有任何的序数，也不代表某一元件与另一元件的顺序或是制造方法上的顺序，这些序数的使用仅用来使具有某命名的一元件得以和另一具有相同命名的元件能做出清楚区分。
本领域那些技术人员可以理解，可以对实施例中的设备中的模块进行 自适应性地改变并且把他们设置在与该实施例不同的一个或多个设备中。可以把实施例中的模块或单元或组件组合成一个模块或单元或组件，以及此外可以把他们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的代替特征来代替。并且，在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。
类似地，应当理解，为了精简本公开并帮助理解各个公开方面的一个或多个，在上面对本公开的示例性实施例的描述中，本公开的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本公开要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如下面的权利要求书所反映的那样，公开方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本公开的单独实施例。
为解决现有技术中的阻变存储器在擦除过程中因流经电流较大易于出现反向击穿从而造成器件失效的技术问题，本公开提供了一种阻变存储器及其制备方法。
如图1、图2A和图2B所示，本公开的一个方面提供了一种阻变存储器100，其中包括：阻变层120、上电极150和势垒结构，阻变层120设置于衬底上，用于在器件执行写入或擦除操作时，使得器件产生高阻态或低阻态；上电极150设置于阻变层120上，用于作为器件的一引出电极；势垒结构设置于阻变层120和上电极150之间，用于在器件执行擦除操作时，电子从势垒结构的导带通过，避免阻变层120形成缺陷，造成阻变层120的反向击穿。
其中，势垒结构具有非完全配比的氧化层，由于势垒结构形成于在阻变层120和上电极150之间，使得在该器件的擦除操作过程中，当施加的 擦除电压逐渐增大时，阻变层120的导带能级会与该氧化层的导带能级拉平，电子从势垒结构的导带中通过，避免了阻变层120中形成过多的缺陷，因此器件不会出现反向击穿，使得器件的耐久性得以进一步提高。
如图1、图2A和图2B所示，根据本公开的实施例，势垒结构包括：势垒层130和插层140，势垒层130设置于阻变层120上，用于在器件执行擦除操作时，作为氧离子的储蓄层，以使得电子从势垒层130的导带通过；插层140设置于势垒层130和上电极150之间，用于在器件执行擦除操作时，作为氧离子的辅助储蓄层，以进一步防止氧离子直接进入上电极150。
如图2A所示，在上电极150上施加正向电压时，阻变层120中的氧离子在电场作用下向上电极150迁移，存储在势垒结构的势垒层130和插层140中，最终在阻变层120中形成由氧空位所构成的导电细丝，器件变为低阻态(即LRS)，完成写入操作。在上电极150上施加反向电压时，势垒层130和插层140中存储的氧离子在电场作用下迁移回阻变层120中，与氧空位复合，使得上述的氧空位导电细丝断裂，器件恢复到高阻态(即HRS)，完成擦除操作。
对于缺乏本公开实施例的势垒结构的阻变存储器而言，一般当施加的reset复位电压过大时，阻变层120的电解质层承受的反向电压过高，则会直接导致阻变层120的电解质层被反向击穿，导致器件失效。
如图1-图2B所示，根据本公开的实施例，阻变层120材料为Ta 2O 5；势垒层130材料为TaO x，其中，x∈[1.1，1.8]；插层140材料为Ta、Ti、金属氧化物、非晶硅、非晶碳、石墨烯中至少一种，其中，插层140的厚度为2nm-20nm；其中，所述势垒层与阻变层之间的势垒为0.45eV-0.65eV。在本公开的实施例中，在形成TaO x的势垒层130时，采用O/Ar流量比为3sccm∶50sccm到6sccm∶50sccm，得到势垒层130的TaO x材料为非完全配比的氧化物。其中，势垒层130的TaO x材料与阻变层120的Ta 2O 5材料之间存在0.45eV-0.65eV的势垒。
因此，如图2B-(a)所示，当器件在执行擦除操作之后，处于反向擦写电压下，器件电子从上电极150注入，经过TaO x势垒层130克服势垒进入Ta 2O 5阻变层120中。随着施加的反向电压慢慢增大，在Ta 2O 5阻变 层120中的浅能级缺陷被逐渐填充，其导带能级逐渐降低。如图2B-(b)所示，当施加的电压到一定值时，从TaO x势垒层130迁移的电子可以直接从Ta 2O 5阻变层120的导带能级中通过，形成比较大的电流。撤掉电压之后，Ta 2O 5阻变层120的导带能级抬高，电子无法通过，器件恢复到高阻态(HRS)。由于Ta 2O 5阻变层120与TaO x势垒层130之间导带能级的调制作用，避免了Ta 2O 5阻变层120中形成过多的缺陷，因此避免了擦除过程中的反向击穿问题。
需要说明的是，插层140在上述过程中所起到的作用与TaO x势垒层130近似，以在TaO x势垒层130的存储氧离子的基础上，进一步对流向上电极150的氧离子作进一步的存储，以作为势垒结构的氧离子辅助储蓄层达到进一步避免在擦写操作过程中对Ta 2O 5阻变层120的方向击穿的效果。其中，TaO x势垒层130可以立即为本公开实施例的势垒结构的氧离子主储蓄层。
如图1-图2B所示，根据本公开的实施例，阻变存储器100还包括：下电极110，下电极110设置于阻变层120和衬底之间，用于作为器件的另一引出电极。根据本公开的实施例，下电极材料为TiN、TaN中至少一种；上电极材料为Ir、Al、Ru、Pd、TiN、TaN中至少一种；其中，下电极和上电极的厚度为20nm-500nm。因此，上下电极均具有导电效果，以作为器件的上下引出电极。
如图1、图3所示，本公开的另一方面提供了一种用于制备上述的阻变存储器100的制备方法，其中包括步骤S101-S103。
在步骤S101中，在衬底上形成阻变层120；
在步骤S102中，在阻变层120上形成势垒结构；
在步骤S103中，在势垒结构上形成上电极150；
其中，势垒结构用于在器件执行擦除操作时，电子从势垒结构的导带通过，避免阻变层120形成缺陷，造成阻变层120的反向击穿。
其中，势垒结构具有非完全配比的氧化层，由于势垒结构形成于在阻变层120和上电极150之间，使得在该器件的擦除操作过程中，当施加的擦除电压逐渐增大时，阻变层120的导带能级会与该氧化层的导带能级拉平，电子从势垒结构的导带中通过，避免了阻变层120中形成过多的缺陷， 因此器件不会出现反向击穿，使得器件的耐久性得以进一步提高。
如图1、图3所示，根据本公开的实施例，在步骤S102：阻变层120上形成势垒结构中，包括：在阻变层120上形成势垒层130，势垒层130用于在器件执行擦除操作时，作为氧离子的储蓄层，以使得电子从势垒层130的导带通过；在势垒层130上形成插层140，插层140用于在器件执行擦除操作时，作为氧离子的辅助储蓄层，以进一步防止氧离子直接进入上电极150。
如图1、图3所示，根据本公开的实施例，在阻变层120上形成势垒层130中，包括：通过调节反应溅射工艺的氧气流量比制备势垒层130；其中，氧气流量比为氧气流量sccm O和惰性气体流量sccm D之间的比值r，其中，r∈[r 1，r 2]，r 1＝sccm O∶sccm D＝2sccm∶50sccm，r 2＝sccm O∶sccm D＝8sccm∶50sccm。其中，惰性气体可以是氩气Ar。
根据本公开的实施例，反应溅射工艺的制备条件还包括：衬底温度为室温，功率为400W，气压为3mtorr。
具体地，在Ta 2O 5阻变层120上制备TaO x势垒层130，TaO x势垒层130中氧的含量需要实现精确控制，且x取值范围为1.1-1.8。其中，TaO x势垒层130中氧的含量通过改变反应溅射过程中的氧气流量比来调节。具体反应溅射工艺的反应参数(即反应制备条件)为：衬底温度为室温，O/Ar流量比为2sccm∶50sccm到8sccm∶50sccm，功率为400W，气压为3mtorr；精确控制TaO x势垒层130中氧的含量可以将TaO x势垒层130与Ta 2O 5阻变层120之间的势垒高度调节到预期范围。
根据本公开的实施例，在势垒层130上形成插层140，包括：通过溅射工艺、原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺制备插层。
在阻变层120的势垒层130上表面上形成插层140，插层材料可以是金属，如Ta或Ti等，也可以为半导体材料如金属氧化物、非晶硅、非晶C或石墨烯等。插层140的制备可采用溅射工艺(如反应溅射工艺)、原子层沉积工艺、物理气相沉积工艺或者化学气相沉积工艺等制备。该插层140的厚度可以为2nm-20nm，该插层140主要作为氧离子的辅助储蓄层，以进一步防止氧离子进入上电极150，造成器件的保持特性失效。
如图1和图3所示，根据本公开的实施例，在步骤S101：衬底上形成阻变层120，包括：通过反应溅射工艺、原子层沉积工艺、热氧化工艺、磁控溅射工艺或离子束溅射工艺中制备阻变层120。
根据本公开的实施例，在反应溅射工艺的制备条件包括：氧气流量比为氧气流量sccm O和惰性气体流量sccm D之间的比值s，其中，s∈[s 1，s 2]，s 1＝sccm O∶sccm D＝12sccm∶50sccm，s 2＝sccmO∶sccmD＝20sccm∶50sccm；衬底温度为室温，功率为400W，气压＝3mtorr。其中，惰性气体可以为氩气Ar。
在下电极110上制备Ta 2O 5阻变层120，可以采用反应溅射(Reactive Sputtering)工艺制备，其中，反应溅射工艺的制备条件为：衬底温度为室温，O/Ar流量比为12sccm∶50sccm-20sccm∶50sccm，功率为400W，气压＝3mtorr。该阻变层120还可以采用原子层沉积(Atomic Layer Deposition)工艺、热氧化(thermal oxidation)工艺等进行制备；或者通过磁控溅射工艺、离子束溅射工艺溅射Ta 2O 5靶的方法来制备。
如图1和图3所示，根据本公开的实施例，在步骤S101：在衬底上形成阻变层120之前，还包括：在衬底上形成下电极110；其中，下电极110和上电极150的制备工艺为溅射工艺、原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺。
在衬底上采用磁控溅射的方法制备TiN或者TaN等金属材料形成下电极110，制备方法为溅射工艺、原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺等。下电极110的厚度为20nm-500nm，具有导电作用。
在插层140上形成上电极150，上电极150材料不受限制，可以是Ir、Al、Ru、Pd、TiN或TaN等，上电极150厚度为20nm-500nm，作为器件的导电电极，具有导电连通作用。
如图4所示，依据本公开实施例的阻变存储器的标准IV特性曲线，在擦除过程中器件具有明显的阈值转变特性，最大的电流值可以达到4mA。但是在读取电压下，器件的阻态不会发生改变。因此，采用本公开实施例的阻变存储器的势垒结构，可以避免阻变器件反向击穿的问题，从而提高了器件耐久性。同时，利用该器件还增大了擦除电压的选择范围，提高了高阻态的均一性。
如图5所示，可见，本公开实施例的阻变存储器通过势垒结构的势垒层和插层，能够避免擦除过程中的过编程问题，器件具有良好的耐久性，可以稳定循环10万次以上，且器件高低阻态分布均一。
从上述实施例可以看出，本公开提供的这种阻变存储器及其制备方法，通过在阻变层和上电极之间增加一层非完全配比的氧化层作为势垒结构，在该器件的擦除操作过程中，当施加的擦除电压逐渐增大时，阻变层的导带能级会与该氧化层的导带能级拉平，电子从势垒结构的导带中通过，避免了阻变层中形成过多的缺陷，因此器件不会出现反向击穿，使得器件的耐久性得以进一步提高。
至此，已经结合附图对本公开实施例进行了详细描述。依据以上描述，本领域技术人员应当对本公开有了清楚的认识。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (13)

  1. 一种阻变存储器，其中，包括：
    阻变层，设置于衬底上，用于在器件执行写入或擦除操作时，使得器件产生高阻态或低阻态；
    上电极，设置于所述阻变层上，用于作为器件的一引出电极；
    势垒结构，设置于所述阻变层和上电极之间，用于在器件执行擦除操作时，电子从所述势垒结构的导带通过，避免所述阻变层形成缺陷，造成阻变层的反向击穿。
  2. 根据权利要求1所述的阻变存储器，其中，所述势垒结构包括：
    势垒层，设置于所述阻变层上，用于在器件执行擦除操作时，作为氧离子的储蓄层，以使得电子从所述势垒层的导带通过；
    插层，设置于所述势垒层和所述上电极之间，用于在器件执行擦除操作时，作为氧离子的辅助储蓄层，以进一步防止氧离子直接进入所述上电极。
  3. 根据权利要求2所述的阻变存储器，其中，
    所述阻变层材料为Ta 2O 5；
    所述势垒层材料为TaO x，其中，x∈[1.1，1.8]；
    所述插层材料为Ta、Ti、金属氧化物、非晶硅、非晶碳、石墨烯中至少一种，其中，所述插层的厚度为2nm-20nm；
    其中，所述势垒层与阻变层之间的势垒为0.45eV-0.65eV。
  4. 根据权利要求1所述的阻变存储器，其中，还包括：
    下电极，设置于所述阻变层和衬底之间，用于作为器件的另一引出电极。
  5. 根据权利要求4所述的阻变存储器，其中，
    所述下电极材料为TiN、TaN中至少一种；
    所述上电极材料为Ir、Al、Ru、Pd、TiN、TaN中至少一种；
    其中，所述下电极和上电极的厚度为20nm-500nm。
  6. 一种用于制备权利要求1-5中任一项所述的阻变存储器的制备方法， 其中，包括：
    在衬底上形成阻变层；
    在所述阻变层上形成势垒结构；
    在所述势垒结构上形成上电极；
    其中，所述势垒结构用于在器件执行擦除操作时，电子从所述势垒结构的导带通过，避免所述阻变层形成缺陷，造成阻变层的反向击穿。
  7. 根据权利要求6所述的制备方法，其中，所述在所述阻变层上形成势垒结构中，包括：
    在所述阻变层上形成势垒层，所述势垒层用于在器件执行擦除操作时，作为氧离子的储蓄层，以使得电子从所述势垒层的导带通过；
    在所述势垒层上形成插层，所述插层用于在器件执行擦除操作时，作为氧离子的辅助储蓄层，以进一步防止氧离子直接进入所述上电极。
  8. 根据权利要求7所述的制备方法，其中，所述在所述阻变层上形成势垒层中，包括：
    通过调节反应溅射工艺的氧气流量比制备所述势垒层；
    其中，所述氧气流量比为氧气流量sccm O和惰性气体流量sCCm D之间的比值r，其中，r∈[r 1，r 2]，r 1＝sccm O∶sCCm D＝2sccm∶50sccm，r 2＝sccm O∶sCCm D＝8sccm∶50sccm。
  9. 根据权利要求8所述的制备方法，其中，所述反应溅射工艺的制备条件还包括：衬底温度为室温，功率为400W，气压为3mtorr。
  10. 根据权利要求7所述的制备方法，其中，所述在所述势垒层上形成插层，包括：
    通过溅射工艺、原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺制备所述插层。
  11. 根据权利要求6所述的制备方法，其中，所述在衬底上形成阻变层，包括：
    通过反应溅射工艺、原子层沉积工艺、热氧化工艺、磁控溅射工艺或离子束溅射工艺中制备所述阻变层。
  12. 根据权利要求11所述的制备方法，其中，在所述反应溅射工艺的制备条件包括：
    所述氧气流量比为氧气流量sccm O和惰性气体流量sCCm D之间的比值s，其中，s∈[s 1，s 2]，s 1＝sCCm O∶sCCm D＝12sccm∶50sccm，s 2＝sccmO∶sccmD＝20sccm∶50sccm；衬底温度为室温，功率为400W，气压＝3mtorr。
  13. 根据权利要求6所述的制备方法，其中，所述在衬底上形成阻变层之前，还包括：
    在衬底上形成下电极；
    其中，所述下电极和上电极的制备工艺为溅射工艺、原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺。
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CN103117359A (zh) * 2013-02-07 2013-05-22 北京大学 一种高可靠性非挥发存储器及其制备方法
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CN103117359A (zh) * 2013-02-07 2013-05-22 北京大学 一种高可靠性非挥发存储器及其制备方法
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