Classifications

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  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
  • H01L23/3135—Double encapsulation or coating and encapsulation
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  • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
  • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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Definitions

• a semiconductor device and a power semiconductor module comprising such a semiconductor device are provided.
• a method for manufacturing such a power semiconductor module is also provided .
• a problem to be solved is to provide a power semiconductor module that can be used for high voltages and that can efficiently be manufactured.
• the power semiconductor module comprises a plurality of semiconductor devices , each of which includes a semiconductor chip .
• a spacer body is used to cover the semiconductor devices .
• a large thickness of the spacer body of , for example , at least 0 . 2 mm can be achieved by using prefabricated contact pieces running through the spacer body .
• the semiconductor device for the power semiconductor module comprises :
• the semiconductor chip configured for voltages of at least 0 . 6 kV, the semiconductor chip comprises at least one top contact on a chip top side ,
• the semiconductor chip or the semiconductor chips of the semiconductor device are configured for voltages of at least 650 V or of at least 1 . 0 kV or of at least 1 . 2 kV or of at least 1 . 6 kV .
• the at least one semiconductor chip may be configured for currents of at least 1 A or of at least 10 A or of at least 50 A.
• the chip top side may be a main side of the at least one semiconductor chip, that is , a largest side .
• the top contact or the top contacts can be reali zed, for example , by metalli zations applied to a semiconductor body of the semiconductor chip .
• the at least one top contact is configured to feed current into the semiconductor body .
• there can be one or more additional contacts for example , on a chip bottom side opposite the chip top side .
• the cover body can be a molded or casted body . Further, embedding technology can be used so that the cover body can be produced by lamination of , for example , one or of multiple prepag layers , for example , comprising Cu and FR4 .
• the cover body is of a polymer like an epoxy, optionally together with at least one metall .
• the term 'prepreg' means pre-impregnated and refers , for example , to composite fibers where a thermoset polymer matrix material , such as epoxy, or a thermoplastic resin is already present around the fibers .
• the fibers may take the form of a weave and the matrix is used to bond them together and to other components during manufacture .
• thermoset matrix is only partially cured to allow easy handling .
• using a prepreg allows one to impregnate the fibers on a flat workable surface , or rather in an industrial process , and then later form the impregnated fibers to a shape which could otherwise prove to be problematic .
• the contact pedestals can be vias running completely through the cover body .
• the contact pedestals can be metalli zations formed by, for example , sputtering and subsequent plating .
• the contact pedestals may be formed in holes previously created in the cover body by, for example , drilling like laser drilling . Otherwise , the contact pedestals can be pre-manufactured metallic bodies bonded to the respective semiconductor chip and then embedded in the cover body by casting or molding .
• the contact pedestals are completely located within the respective top contact .
• the contact pedestals can be limited to the chip top side and do not laterally proj ect beyond the chip top side .
• 'Laterally' may refer to a direction in parallel with the chip top side .
• Top view' does not require the respective face to be indeed visible , but may primarily refer to a line-of-sight , for example , to a proj ection along a direction perpendicular with the chip top side .
• a fan-out could properly be done in order to be able to scale-up the maximum possible voltage . That is , by using a conductive layer or sub-layer atop the contact pedestals , for example , on top of the cover body a first conductive layer configured for an intermediate wiring can be reali zed so that an area of an electric wiring and/or a si ze of electric contacts as present directly on the chip top side can be expanded . Hence , for example , a gate pad of the semiconductor chip can be made larger atop the cover body by reducing the area of other electric contacts on the chip top side towards atop the cover body .
• the first conductive layer and/or the intermediate wiring is , for example , completely located within the chip top side , seen in top view of the chip top side .
• the first conductive layer and/or the intermediate wiring may not proceed closer towards outer edges of the chip top side than the top contacts of the semiconductor chip, seen in top view .
• the first conductive layer and/or the intermediate wiring does not exceed the respective top contact in the direction of the edge of the chip top side so as not to overlap with a chip termination area, seen in top view of the chip top side.
• the at least one semiconductor is selected from the following group: a metal- oxide-semiconductor field-effect transistor (MOSFET) , a metal-insulator-semiconductor field-effect transistor (MISFET) , an insulated-gate bipolar transistor (IGBT) , a bipolar junction transistor (BJT) , a thyristor, a gate turnoff thyristor (GTO) , a gate commutated thyristor (GCT) , a junction gate field-effect transistor (JFET) , and a diode.
• MOSFET metal- oxide-semiconductor field-effect transistor
• MISFET metal-insulator-semiconductor field-effect transistor
• IGBT insulated-gate bipolar transistor
• BJT bipolar junction transistor
• GTO gate turnoff thyristor
• GCT gate commutated thyristor
• JFET junction gate field-effect transistor
• a power semiconductor module is additionally provided.
• the power semiconductor module includes a semiconductor device as indicated in connection with at least one of the above-stated embodiments. Features of the power semiconductor module are therefore also disclosed for the semiconductor device and vice versa.
• the power semiconductor module comprises :
• the present application may refer to a high-power module assembly based on chip-scale packaged semiconductors .
• Chip-Scale Packages originate from conventional PCB manufacturing and have originally been conceived for the integration of miniaturi zed and heterogeneous microelectronic/optical components , also referred to as System in Package , SiP for short , mostly for consumer electronics .
• SiP System in Package
• Such an approach is extended to the packaging of semiconductor devices of a voltage class of , for example , at least 1 . 2 kV .
• the power semiconductor module described herein provides a solution to enable usage of CSPs for voltage classes much higher than 1 . 2 kV .
• Chip scale packaging may of fer various advantages over TO- like , QFN and other surface mounted packages like better heat extraction, no-wire bonding, and lower electromagnetic parasitics , and may provide an alternative route to the assembly of power modules , for example , in a cleanroom-less manner .
• Another key advantage of such embedded solutions can be the design freedom to fan-out bond pads and to integrate multi-layer signal routing to any shape and complexity as needed . This can allow to reali ze low-inductance interconnections , to integrate sensors and controllers with a multitude of I /O channels , and to reali ze ultra-compact packages without the need of wire bonds leading to flat layouts and geometries beneficial also for double sidecooling designs .
• the development of such a technology may impact the semiconductor-power module value chain : chip manufacturers could adopt the technology and disrupt the current state of the art in the design and assembly of power modules .
• the CSP design used in the semiconductor device described herein may be manufactured by a series of steps like : i ) Bonding, for example , sintering, the semiconductor chip onto a leadframe of , for example , copper, ii ) Embedding the combined semiconductor chip and leadframe by lamination with a foil of , for example , copper, and prepreg and cut prepreg, or as an alternative process use compression molding with a polymer like an epoxy, iii ) Fabricating holes via drilling, iv) Performing electroplating with, for example , copper, and structuring .
• Prepreg' refers to pre-impregnated composite fibers where a thermoset polymer matrix material , such as epoxy, or a thermoplastic resin is already present .
• the fibers may take the form of a weave and the matrix is used to bond them together and to other components during manufacture .
• the thermoset matrix is only partially cured to allow easy handling . Hence , the structures built of the prepreg may require an oven or autoclave to cure .
• Prepreg allows to impregnate the fibers on a flat workable surface , and then later form the impregnated fibers to a shape which could prove to be problematic for the hot inj ection process .
• the thickness of the prepreg foils may define the maximum voltage the CSP can withstand .
• Standard materials for the prepreg are FR4 and epoxy, which have a breakdown field of , for example , 1 kV per 100 pm .
• the proper embedding of a 1 . 2 kV semiconductor chip would typically require a 100 pm thick insulating layer between the semiconductor chip and a top side layer on a source or a gate potential . So far, technological limitations , like lamination and drilling of thick or multi-layer insulating layers , and conformal plating for such deep via structures , have hindered the scaling of CSP to signi ficantly higher voltages .
• the technological gap to reali ze a power module based on prepackaged CSPs for voltage classes higher than 1 . 2 kV can be bridged, and usage of CSPs for voltage classes >> 1 . 2 kV is enabled .
• the proposed solution comprises using a maximum via height of , for example , 100 pm to 150 pm for a bond pad " fan- in" layout that allows bonding of the contact pieces , like press- fit pins or other pins , so that the bond pads do nor overlap or come too close to die edges/edge termination areas of the semiconductor chip on a drain potential , that is , are arranged not to increase the electric fields around the semiconductor chip edges .
• the contact pieces are acting as spacers that allow to fix a planar carrier, like a printed circuit board, PCB for short , in suf ficient distance .
• the contact pieces can be connected to a multi-layer PCB that can provide flexible re-routing and distribution of power and control signals .
• the space between CSP and PCB is insulated with, for example , a polymer like a silicone gel to form the spacer body .
• the contact to the chip-si ze packaged semiconductor chip in the semiconductor device is established by a pin or spring grid array that can be an integral part of the circuit board .
• the individual springs or pins could form a dry contact to the bond pads of the CSP, that is , to the contact pedestals or to the first conductive layer and/or to the intermediate wiring, or the contact pieces would be bonded, for example , by soldering or sintering, to the bond pads of the CSP .
• the bond pads of the CSP enable a safe contacting of the semiconductor device , avoiding possible damage to the sensitive chip top side metalli zation, that is , to the top contacts , and can hence reduce subsequent yield losses .
• the enlarged fan-in bond pad area simpli fies the contacting of small gate pads on the semiconductor chip saving more die area for active cells .
• the term 'power semiconductor module ' means , for example , that the module is configured for high currents and/or voltages .
• the power semiconductor module is configured to handle a maximum current of at least 1 A or of at least 10 A or of at least 100 A or of at least 500 A.
• the module is configured for voltages of at least 0 . 6 kV or of at least 1 . 2 kV or of at least 2 k V .
• the semiconductor device is a chip-si zed package device , that is , a CSP device .
• a footprint of the semiconductor device is , for example , at most twice or thrice a footprint of the at least one semiconductor chip included in the semiconductor device , seen in top view of the at least one chip top side .
• the spacer body is arranged in direct contact with the at least one cover body .
• there may be an intermediate layer between the cover body and the spacer body for example , a metallic layer or a metallic layer stack .
• the spacer body is of constant thickness in an area atop the cover body .
• the contact pieces are in direct contact with the spacer body .
• the spacer body is formed around the already mounted contact pieces .
• the contact pieces may be pre- fabricated so that a shape of the contact pieces is defined outside the power semiconductor module and prior to arranging in the latter .
• the contact pieces may completely run through the spacer body . It is possible that the contact pieces are limited to the assigned semiconductor chip, seen in top view of the respective chip top side .
• the contact pieces are in direct contact with the contact pedestals . Otherwise , there may be the electrically conductive intermediate wiring between the contact pieces and the respective contact pedestals .
• the electric contact faces are in direct contact with the contact pieces and are located on a side of the spacer body remote from the cover body . This can mean that there is at most an electrical connection means , like a solder or a sinter body, between the respective electric contact face and the at least one assigned contact piece . Otherwise , the electric contact faces and the contact pieces are distant from one another .
• the cover body of the at least one semiconductor device is made of a prepreg .
• the cover body may comprise a fiber reinforcement embedded in an organic material .
• the organic material is , for example , selected from the following group : polytetrafluoroethylene (PTFE ) , FR-2 (phenolic cotton paper ) , FR-3 ( cotton paper and epoxy) , FR-4 (woven glass and epoxy) , FR-5 (woven glass and epoxy) , FR- 6 (matte glass and polyester ) , G- 10 (woven glass and epoxy) , CEM- 1 ( cotton paper and epoxy) , CEM-2 ( cotton paper and epoxy) , CEM-3 (non-woven glass and epoxy) , CEM-4 (woven glass and epoxy) , CEM-5 (woven glass and polyester ) .
• the power semiconductor module further comprises a circuit board like a printed circuit board, RGB for short . All the electric contact faces can be integrated in the circuit board .
• the power semiconductor module is configured to be externally electrically contacted by means of the circuit board . That is , the power semiconductor module may be electrically only contacted by means of the circuit board .
• the only external faces of the power semiconductor module in electric contact with the at least one semiconductor chip may therefore be on the circuit board .
• Such external faces can be reali zed by, for example , metallic electric terminals .
• metallic leadframes and/or metallic terminals can be used that may act as electrical interconnects .
• the circuit board partially or completely covers the at least one semiconductor device and/or the spacer body, seen in top view of the at least one chip top side .
• the spacer body and the circuit board could be congruent with each other .
• the at least one semiconductor device can be completely surrounded by the circuit board and/or by the spacer body, seen in top view of the chip top side .
• the circuit board further comprises electric lines .
• the electric terminals can be electrically connected to the contact pieces by means of the electric lines and by means of the electric contact faces . It is possible that the electric terminals are electrically directly connected with the electric lines to the electric contact faces and that the electric contact faces are in direct contact with the contact pieces .
• At least one intermediate electronics like an integrated circuit for control and/or sensor purposes .
• the electric terminals are partially or completely located outside the at least one semiconductor device .
• the electric terminals may not or only partially overlap with the at least one chip top side and/or with the at least one semiconductor device .
• some of the contact pieces together are electrically assigned to only one of the top contacts .
• the respective top contact or the respective top contacts are electrically connected by a plurality of the contact pieces .
• the contact pieces are completely located within the top contact and/or within the first conductive layer they are assigned to.
• small footprints can be realized.
• all or some of the contact pieces are press-fit pins or springs or stacked stud bumps. All the contact pieces can be of the same type. Otherwise, different types of contact pieces can be combined within the power semiconductor module.
• all or some of the contact pieces are each assigned to exactly one of the contact pedestals. Hence, there can be a one-to-one assignment between the contact pieces and the contact pedestals. Thus, an adjustable wiring design can be achieved.
• one, some or all of the contact pieces are configured as a conductive block that is assigned to a plurality of the contact pedestals.
• the conductive block may be of a metal like copper.
• the conductive block can be of cuboid or cylinder shape or may have a more complex shape like an L-shape or an U-shape when seen in top view of the chip top side.
• a thickness of the spacer body atop the at least one chip top side is at least 0.2 mm or at least 0.4 mm and/or at most 2 mm or at most 5 mm.
• the power semiconductor module further comprises at least one intermediate wiring.
• the at least one intermediate wiring is embedded between the at least one cover body and the spacer body.
• the intermediate wiring may be of one or of a plurality of metallic layers .
• the contact pedestals and the contact pieces can ef ficiently be connected . That is , the intermediate wiring could consist of the first conductive layer or may comprise at least one further conductive layer .
• some or all of the contact pedestals and some or all of the respective contact pieces are electrically connected by means of the intermediate wiring .
• Both the respective contact pedestals and contact pieces can be in direct contact with the intermediate wiring so that at most an electric connection means like a solder or a sinter layer is located between the contact pieces and the intermediate wiring .
• the intermediate wiring comprises the first conductive layer and a second conductive layer .
• the first conductive layer is included in the at least one semiconductor device .
• the second conductive layer may be no part of the at least one semiconductor device , but only of the power semiconductor module .
• the first conductive layer and the second conductive layer together form a plurality of electric intermediate contacts .
• the electric intermediate contacts and the respectively assigned top contacts can have di f ferent si zes , seen in top view of the at least one chip top side , or otherwise can have the same si ze .
• the power semiconductor module further comprises a substrate .
• the substrate is a direct bonded copper substrate comprising a central insulating layer of for example , a ceramic like AI2O3 , and at least one metalli zation on each main side of the insulating layer .
• the substrate is an active metal brazed substrate , AMB substrate for short .
• the substrate can be used for cooling the power semiconductor module .
• the at least one semiconductor device is mounted on a top metalli zation of the substrate .
• the top metalli zation can be a plane layer .
• the at least one semiconductor device is electrically connected with the top metalli zation .
• the at least one semiconductor device can be embedded between the substrate and the spacer layer .
• the at least one semiconductor device may completely be surrounded all around by the substrate together with the spacer layer and together with the contact pieces .
• the power semiconductor module further comprises additional contact pieces .
• the additional contact pieces may run from the top metalli zation through the spacer layer . Seen in top view of the at least one chip top side , as an option, the additional contact pieces are located adj acent to the at least one semiconductor device . Hence , the additional contact pieces and the at least one semiconductor device may not overlap .
• the power semiconductor module comprises a plurality of the semiconductor devices .
• the chip top sides of all or of some of the semiconductor devices are arranged in parallel with each other . That is , all the top sides face into the same direction .
• ' in parallel ' refers to the geometric arrangements of the semiconductor devices and not to the electric wiring .
• some or all of the chip top sides are located in a common plane .
• the semiconductor devices are arranged next to one another and/or in a non-overlapping manner . Hence , there are no stacks of semiconductor devices in the power semiconductor module .
• all the semiconductor devices are covered by the spacer body .
• all the semiconductor devices are embedded between the substrate and the spacer body .
• the power semiconductor module is , for example , a power module to convert direct current from a battery to alternating current for an electric motor, for example , in vehicles like hybrid vehicles or plug-in electric vehicles .
• a method for manufacturing the power semiconductor module is additionally provided .
• a power semiconductor module is produced as indicated in connection with at least one of the above-stated embodiments .
• Features of the power semiconductor module are therefore also disclosed for the method and vice versa .
• the method is for manufacturing the power semiconductor module and comprises the following method steps , for example , in the stated order :
• Method step C ) may also precede method step B ) so that the order of the steps is A) > C ) > B ) > D) . Further, method steps C ) /B ) and D) may be interchanged so that the order of the method steps could also be A) > B ) > D) > C ) or
• the produced power semiconductor module comprises the circuit board and a plurality of the semiconductor devices so that in method step A) the plurality of the semiconductor devices is provided .
• the contact pieces are electrically connected with the circuit board .
• the contact pieces may first be connected to the intermediate wiring or to the contact pedestals and then to the circuit board, or alternatively the contact pieces may first be connected to the circuit board and then to the intermediate wiring or to the contact pedestals .
• the circuit board in method step D) is part of a mold to form the spacer body .
• the substrate can be present when the spacer body is formed, and the substrate then can also be part of the mold to form the spacer body .
• the circuit board and optionally the substrate can thus be both a mold for the spacer body and an integral component of the power semiconductor module .
• Figure 1 is a schematic sectional view perpendicular with a chip top side of an exemplary embodiment of a semiconductor device described herein,
• Figure 2 is a schematic sectional view parallel with the chip top side of the semiconductor device of Figure 1 ,
• Figure 3 is a schematic sectional view perpendicular with a chip top side of an exemplary embodiment of a power semiconductor module described herein,
• Figure 4 is a schematic sectional view in parallel with the chip top side of the power semiconductor module of Figure 3
• Figure 5 is a schematic block diagram of an exemplary embodiment of a method to produce power semiconductor modules described herein
• Figure 6 is a schematic sectional view perpendicular with a chip top side of a method step of an exemplary embodiment of a method to produce power semiconductor modules described herein,
• Figure 7 is a schematic sectional view perpendicular with a chip top side of an exemplary embodiment of a power semiconductor module described herein,
• Figure 8 is a schematic sectional view in parallel with chip top sides of a modi fied power semiconductor module .
• Figure 9 is a schematic sectional view in parallel with chip top sides of an exemplary embodiment of a power semiconductor module described herein, and
• Figure 10 is a schematic representation of thermal and electric properties of exemplary embodiments of power semiconductor module described herein and of modi fied power semiconductor modules .
• FIGS 1 and 2 illustrate an exemplary embodiment of a semiconductor device 1 .
• the semiconductor device 1 comprises a semiconductor chip 2 that is , for example , a MOSFET , a MISFET , an IGBT , a BJT , a GTO, a GCT , or a JFET .
• the semiconductor chip 2 can be a high voltage class chip and may be configured for voltages of at least 1 . 2 kV .
• the semiconductor device 1 may contain only one semiconductor chip 2 as shown in Figure 1 , but there can also be a plurality of semiconductor chips 2, for example, at most five semiconductor chips 2, of the same or also of different types .
• the semiconductor device 1 contains a cover body 23.
• the cover body 23 is a prepreg or a molded body containing a polymer like an epoxy.
• the cover body 23 is in direct contact with chip side walls and also with a chip top side 20.
• a thickness T of the cover body 23 atop the chip top side 20 is, for example, 0.1 mm to enable efficient manufacture of contact pedestals 22 through the cover body 23, see Figure 1.
• top contacts 21 see Figure 2, also referred to as bond pads.
• the top contacts 21 can be metallizations in direct contact with a semiconductor body of the semiconductor chip 2.
• the top contacts 21 can have different sizes and/or silhouettes.
• the contact pedestals 22 start from the top contacts 21. There can be more than one contact pedestal 22 per top contact 21. As an option, the larger top contact 21, for example, a source or drain contact, is provided with a plurality of the contact pedestals 22, while the smaller top contact 21, for example, a gate contact, is provided with only one contact pedestal 22. Deviating from Figures 1 and 2, there can be three or more than three top contacts 21, or also only one top contact 21.
• the contact pedestals 22 can be manufactured by drilling holes into the previously finished cover body 23, for example, by laser drilling. Then, a metal seed layer may be sputtered, not shown. Then, by means of, for example, plating the holes are filled and the contact pedestals 22 , also referred to as vias , result .
• the contact pedestals 22 can first be bonded to the chip top side 20 and subsequently the cover body 23 is formed, for example , by means of molding .
• the contact pedestals 22 can be metal bodies mounted on the respective contact 21 by soldering or sintering .
• a first conductive layer 61 configured for an intermediate wiring 6 can be present on a cover body top side 26 of the cover body 23 remote from the semiconductor chip 2 .
• the first conductive layer 61 may be a metallic layer or also a metallic layer stack .
• the first conductive layer 61 proj ects above the cover body 23 .
• the first conductive layer 61 is electrically structured analogously to the top contacts 21 .
• per top contact 21 there can be exactly one electric intermediate contact of the first conductive layer 61 .
• the respective electric intermediate contact and the assigned top contact 21 may have di f ferent footprints , compare also Figure 4 below .
• contact faces can be formed which do not necessarily have the shapes and/or si zes of the top contacts 21 .
• contact faces formed by the intermediate wiring 6 in particular by the first conductive layer 61 , may have a minimum distance towards edges of the chip top side 20 that is at least a minimum distance towards edges of the chip top side 20 of the top contacts 21 , seen in top view .
• the first conductive layer 61 and, for example , the overall intermediate wiring 6 is more distant than, or at most as distant as , the respective top contact 21 towards the chip top side edges .
• the semiconductor device 1 can be a chip-si zed package , CSP for short .
• lateral dimensions of the overall semiconductor device 1 are comparable with lateral dimensions of the semiconductor chip 2 .
• a width of the cover body 23 at the side walls of the semiconductor chip 2 is at most 50% or at most 25% of an edge length of the chip top side 20 .
• the edge length of the chip top side 20 is , for example , at least 1 mm or at least 2 mm and/or at most 2 cm or at most 1 cm .
• the semiconductor chip 2 and/or the cover body 23 can have a rectangular or square shape .
• the semiconductor device 1 includes a chip carrier 24 at which the at least one semiconductor chip 2 is mounted, for example , by means of soldering or sintering .
• the chip carrier 24 can be a metallic leadframe , for example , made of copper or a copper alloy .
• a thickness of the chip carrier 24 is , for example , at least 0 . 1 mm and/or at most 1 mm . In the lateral direction, the chip carrier 24 may terminate flush with the cover body 23 .
• a device bottom side 25 remote from the cover body top side 26 can thus be formed by the chip carrier 24 .
• FIG 3 shows an exemplary embodiment of a power semiconductor module 10 .
• the power semiconductor module 10 includes at least one semiconductor device 1 that can be configured as described in connection with Figures 1 and 2 .
• the power semiconductor module 10 comprises a spacer body 4.
• the spacer body 4 is, for example, of a silicone gel or also of a plastic like epoxy.
• the spacer body 4 might be manufactured by casting or molding.
• the spacer body 4 has a comparably large thickness S that effectively adds to the thickness T of the cover body 23.
• the spacer body 4 is directly bonded onto the cover body 23.
• the thickness S of the spacer body 4 is between 0.2 mm and 3 mm inclusive or between 0.3 mm and 2 mm inclusive.
• the power semiconductor module 10 also comprises contact pieces 3.
• the contact pieces 3 are, for example, press-fit pins. Accordingly, the contact pieces 3 can have a large extent in the direction away from the chip top side 20 and can completely run through the spacer body 4.
• a diameter of the contact pieces 3 is, for example, at least 0.1 mm and/or at most 1 mm.
• the intermediate wiring 6 can comprise the first conductive layer 61 described in connection with Figures 1 and 2.
• the intermediate wiring 6 also can comprise a second conductive layer 62.
• the second conductive layer 62 is a layer to improve soldering or sintering of the contact pieces 3 to the intermediate wiring 6. That is, the second conductive layer 62 can be applied to the first conductive layer 61 of the semiconductor component 1, for example, in a congruent manner, to create the intermediate wiring 6.
• the intermediate wiring 6 is located within the chip top side 20, seen in top view of the chip top side.
• the si zes of the first conductive layer 61 at the semiconductor chip 2 can be changed relative to the second conductive layer 62 at the cover body top side 26 , wherein all the conductive layers 61 , 62 are located within the chip top side 20 and do not laterally protrude over the semiconductor chip 2 .
• the power semiconductor module 10 also includes electric contact faces 51 .
• the electric contact faces 51 can be part of a circuit board 5 that may be in direct contact with the spacer body 4 on a side remote from the cover body 23 .
• the contact pieces 3 are electrically connected with the electric contact faces 51 , for example , by means of a dry contact in case of using press- fit pins , or alternatively by means of soldering .
• the electric contact faces 51 can be exterior surfaces of the circuit board 5 configured for a surface mount technology like soldering, or the electric contact faces 51 can be interior surfaces of the circuit board 5 like a female connector configured for receiving the contact pieces 3 .
• the circuit board 5 is a PCB and may also comprise electric lines 52 for internal wiring and/or electric terminals 53 for externally connecting the power semiconductor module 10 with, for example , an external plate , not shown .
• the circuit board 5 can be a multi-layer PCB .
• the power semiconductor module 10 can ef ficiently be configured for high voltages of , for example , 1 . 7 kV or more .
• the design of the contact pieces 3 can be quite independent of the design of the top contacts 21 and of the contact pedestals 22 .
• the smallest electric intermediate contact of the intermediate wiring 6 see Figure 4
• a footprint area of the smallest top contact 21 is increased by at least a factor of two or by at least a factor of four compared with the footprint area of the assigned electric intermediate contact of the intermediate wiring 6 .
• a method for producing power semiconductor modules 10 is schematically shown .
• the at least one semiconductor device 1 is provided, wherein also a plurality of the semiconductor devices 1 can be provided .
• the semiconductor devices 1 could be bonded to a common substrate . It is possible that the semiconductor devices 1 are applied in a geometric arrangement present in the finished power semiconductor modules 10 . Hence , after method step Ml relative positions of the semiconductor devices 1 may remain the same .
• method step Ml can include providing the second conductive layer 62 .
• the contact pieces 3 are bonded to the at least one semiconductor device 1 .
• the contact pieces 3 are soldered or sintered to the contact pedestals 22 or to the intermediate wiring 6 .
• the electric contact faces 51 are electrically connected with the contact pieces 3 , for example , by soldering, sintering, pressing or clamping .
• the spacer body 4 is formed .
• the circuit board 5 and/or the substrate 7 may serve as a mold 8 to shape the spacer body 4 , compare also Figure 6 .
• the spacer body 4 is formed before the contact pieces 3 are bonded to the electric contact faces 51 so that the steps are performed in the order Ml > M2 > M4 > M3 .
• the order of the steps can also be Ml > M3 > M2 > M4 or Ml > M3 > M4 > M2 , so that the spacer body 4 can be formed prior or after bonding of the contact pieces 3 to the contact pedestals 22 or the intermediate wiring 6 .
• di f ferent orders of the steps are indicated in Figure 5 by di f ferent schemes of the arrows between the boxes assigned to the method steps .
• the substrate 7 and/or the circuit board 5 can serve as the mold 8 to form the spacer body 4 .
• the power semiconductor module 10 comprises a plurality of the semiconductor devices 1 , for example , two semiconductor devices 1 . Concerning the semiconductor devices 1 , the same as to Figures 1 and 2 also applies to Figure 6 .
• the power semiconductor module 10 includes the substrate 7 .
• the substrate 7 is a direct bonded copper substrate , DBC substrate for short .
• the substrate 7 comprises a top metalli zation 71 , an insulating layer 72 and a bottom metalli zation 73 .
• the bottom metalli zation 73 is electrically insulated from the semiconductor devices 1 by means of the insulating layer 72 .
• the bottom metalli zation 73 can be configured to mount the power semiconductor module 10 onto a heat sink, not shown .
• the power semiconductor module 10 also comprises further contact pieces 37 that are electrically connected with the circuit board 5 , too .
• the further contact pieces 37 start at the top metalli zation 71 and completely run through the spacer body 4 that is also located between adj acent semiconductor devices 1 and, thus , reaches the substrate 7 .
• the further contact pieces 37 and the contact pieces 3 can be of the same type , for example , can all be press- fit pins , or can be of di f ferent types , for example , press- fit pins combined with stud bumps .
• the top metalli zation 71 can be used to establish an electric wiring scheme within the power semiconductor module 10 .
• a first one of the semiconductor devices 1 can form a high side H
• a second one of the semiconductor devices 1 can form a low side L
• the further contact pieces 37 can form an alternating current terminal AC of a direct current to alternating current converter reali zed by the power semiconductor module 10 .
• all the circuit board 5 , the substrate 7 and the spacer body 4 may terminate flush on sides of the power semiconductor module 10 .

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Wire Bonding (AREA)

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Citations (6)

• 2020
  • 2020-11-18 JP JP2023600070U patent/JP3244200U/ja active Active
  • 2020-11-18 DE DE212020000842.6U patent/DE212020000842U1/de active Active
  • 2020-11-18 CN CN202090001224.3U patent/CN220509968U/zh active Active
  • 2020-11-18 WO PCT/EP2020/082533 patent/WO2022105994A1/en active Application Filing

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