CN220509968U - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN220509968U
CN220509968U CN202090001224.3U CN202090001224U CN220509968U CN 220509968 U CN220509968 U CN 220509968U CN 202090001224 U CN202090001224 U CN 202090001224U CN 220509968 U CN220509968 U CN 220509968U
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power semiconductor
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G·塞尔瓦托
J·舒德雷尔
柳春雷
S·基辛
F·莫恩
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Hitachi Energy Co ltd
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Hitachi Energy Co ltd
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Abstract

在一个实施例中，功率半导体模块(1)包括：‑至少一个芯片大小的封装的半导体器件(1)，‑电绝缘间隔体(4)，该电绝缘间隔体布置在至少一个半导体器件(1)的至少一个盖体(23)上，‑多个接触件(3)，该多个接触件在背离芯片顶侧(20)的方向上延伸穿过间隔体(4)并且与触头基座(22)电接触，以及‑多个电接触面(51)，该多个电接触面与接触件(3)电连接并且位于间隔体(4)的远离至少一个半导体器件(1)的侧面上。

Description

半导体模块
技术领域
提供了一种半导体器件和包括这种半导体器件的功率半导体模块。还提供了一种用于制造这种功率半导体模块的方法。
背景技术
2019年5月7日至2019年5月9日在德国纽伦堡市举行的PCIM欧洲会议2019：电力电子、智能运动、可再生能源和能源管理国际展览及会议中，C.Marczok等人的文献“具有直接冷却的低电感SiC模具模块”讨论了用于半导体芯片的芯片大小的封装。
2014年6月在美国夏威夷威可洛亚举行的2014年IEEE第26届功率半导体器件与IC国际研讨会(ISPSD)中，N.Nashida等人的文献“用于光伏功率调节系统的全SiC功率模块”讨论了基于SiC的半导体模块的模块缩小。
实用新型内容
要解决的问题是提供一种可以用于高电压并且可以高效地制造的功率半导体模块。
该目的尤其通过如独立专利权利要求中所定义的半导体器件、功率半导体模块以及方法来实现。示例性进一步的拓展构成从属权利要求的主题。
例如，功率半导体模块包括多个半导体器件，每个半导体器件包括半导体芯片。为了使功率半导体模块能够以例如高于1kV的高电压工作，间隔体被用来覆盖半导体器件。通过使用延伸穿过间隔体的预制接触件，可以获得例如至少0.2mm的大厚度的间隔体。
在至少一个实施例中，用于功率半导体模块的半导体器件包括：
-至少一个半导体芯片，该至少一个半导体芯片被配置用于至少0.6kV的电压，该半导体芯片包括在芯片顶侧上的至少一个顶部触头，
-多个触头基座，该多个触头基座与该至少一个顶部触头电接触，以及
-电绝缘盖体，该半导体芯片和这些触头基座嵌入该电绝缘盖体中，这些触头基座在背离该芯片顶侧的方向上延伸穿过该盖体。
例如，半导体器件的一个或多个半导体芯片被配置用于至少650V的电压、或至少1.0kV的电压、或至少1.2kV的电压、或至少1.6kV的电压。此外，至少一个半导体芯片可以被配置用于至少1A的电流、或至少10A的电流、或至少50A的电流。
芯片顶侧可以是至少一个半导体芯片的主侧，即最大侧。一个或多个顶部触头可以例如通过施加到半导体芯片的半导体本体的金属化部(metallization)来实现。因此，至少一个顶部触头被配置成将电流馈送到半导体本体中。除了该至少一个顶部触头之外，例如在与芯片顶侧相反的芯片底侧上可以存在一个或多个附加触头。
盖体可以是模制体或铸造体。此外，可以使用嵌入技术，使得可以通过对例如包含Cu和FR4的一个或多个预浸料层进行层压来生产盖体。例如，盖体由聚合物(如环氧树脂)可选地与至少一种金属一起制成。术语“预浸料”意味着预浸渍的并且例如是指复合纤维，其中热固性聚合物基质材料(诸如环氧树脂)或热塑性树脂已经存在于纤维周围。纤维可以采取织造物的形式，并且基质用于在制造期间将纤维接合在一起并将纤维与其它部件接合。首先，热固性基质仅部分固化以便于处理。因此，使用预浸料允许人们在平坦的可加工表面上浸渍纤维或者更确切地说在工业过程中浸渍纤维，接着稍后将浸渍的纤维形成为可能另外证明是不确定的(problematic)形状。
触头基座可以是延伸完全穿过盖体的通孔。因此，触头基座可以是通过例如溅射以及随后的电镀形成的金属化部。触头基座可以通过例如钻孔(如激光钻孔)形成在先前在盖体中创建的孔中。另外，触头基座可以是接合到相应的半导体芯片、然后通过铸造或模制而嵌入盖体中的预制金属体。
根据至少一个实施例，从芯片顶侧的俯视图中看，触头基座完全位于相应的顶部触头内。因此，触头基座可以被限制在芯片顶侧，并且不会横向地突出超过芯片顶侧。“横向地”可以指与芯片顶侧平行的方向。“俯视图”并不要求相应的面确实可见，而是可以主要指视线，例如指沿着与芯片顶侧垂直的方向的投影。
相应地，可以适当地进行扇出，以便能够按比例放大最大可能的电压。即，通过在触头基座顶上(例如，在盖体的顶部上)使用导电层或子层，可以实现被配置用于中间布线的第一导电层，使得可以扩展直接存在于芯片顶侧上的电布线的面积和/或电触头的大小。因此，例如，通过减小芯片顶侧上的朝向盖体顶上的其它电触头的面积，可以使半导体芯片的栅极焊盘在盖体顶上较大。
然而，从芯片顶侧的俯视图中看，同样在盖体顶上，第一导电层和/或中间布线例如完全位于芯片顶侧内。此外，从俯视图中看，与半导体芯片的顶部触头相比，第一导电层和/或中间布线可以不较靠近芯片顶侧的外边缘。例如，从芯片顶侧的俯视图中看，第一导电层和/或中间布线在芯片顶侧的边缘方向上不超过相应的顶部触头，以便不与芯片末端区域重叠。
根据至少一个实施例，至少一个半导体选自以下组：金属-氧化物-半导体场效应晶体管(MOSFET)、金属-绝缘体-半导体场效应晶体管(MISFET)、绝缘栅双极晶体管(IGBT)、双极结型晶体管(BJT)、晶闸管、门极关断晶闸管(GTO)、门极换流晶闸管(GCT)、结型栅极场效应晶体管(JFET)和二极管。如果存在多个半导体芯片，则所有半导体芯片可以是相同类型的，或者存在不同类型的半导体芯片。
附加地，提供了功率半导体模块。功率半导体模块包括如结合至少一个上述实施例所指示的半导体器件。因此，对于该半导体器件，也公开了用于功率半导体模块的特征，且反之亦然。
在至少一个实施例中，功率半导体模块包括：
-至少一个半导体器件，
-电绝缘间隔体，该电绝缘间隔体布置在该至少一个半导体器件的至少一个盖体上，
-多个接触件，该多个接触件在背离芯片顶侧的方向上延伸穿过间隔体并且与触头基座电接触，以及
-多个电接触面，该多个电接触面与接触件电连接并且位于间隔体的远离该至少一个半导体器件的侧面上。
因此，本申请可以涉及基于芯片级封装的半导体的高功率模块组件。
芯片级封装(简称CSP)起源于传统的PCB制造并且最初被设想用于小型化的和异构的微电子部件/光学部件的集成，也称为系统级封装(简称SiP)，主要用于消费性电子器件。这里，这种方法被扩展到例如至少1.2kV的电压等级的半导体器件的封装。因此，本文描述的功率半导体模块提供了使得能够将CSP用于远高于1.2kV的电压等级的解决方案。
芯片级封装可以提供优于类TO封装、QFN封装和其它表面安装封装的各种优点(比如更好的热提取、无引线接合、以及较低的电磁寄生效应)，并且可以例如以无洁净室的方式为功率模块的组装提供替代路线。这种嵌入式解决方案的另一个关键优点可以是用于扇出接合焊盘、并根据需要将多层信号路由集成到任何形状和复杂度的设计自由度。这可以允许实现低电感互连、将传感器和控制器与多个I/O通道集成、以及在不需要引线接合的情况下实现超紧凑封装，从而导致也有益于双侧冷却设计的平坦布局和几何形状。最后，这种技术的发展可能会影响半导体功率模块的价值链：芯片制造商可以采用该技术并且在功率模块的设计和组装方面打破目前的技术水平。
本文描述的半导体器件中所使用的CSP设计可以通过一系列步骤来制造，该一系列步骤比如是：
i)将半导体芯片接合(例如烧结)到例如铜制的引线框架上，
ii)通过用例如铜制的箔、以及预浸料和切割的预浸料进行层压，或者作为替代工艺使用聚合物(如环氧树脂)进行压缩模制来嵌入组合的半导体芯片和引线框架，
iii)通过钻孔来制造孔，
iv)用例如铜执行电镀、并且执行结构化。
“预浸料”是指已经存在热固性聚合物基质材料(诸如环氧树脂)或热塑性树脂的预浸渍的复合纤维。纤维可以采取织造物的形式，并且基质用于在制造期间将纤维接合在一起并将纤维与其它部件接合。热固性基质仅部分地固化以便于处理。因此，由预浸料构建的结构可能需要烘箱或高压釜来固化。预浸料允许在平坦的可加工表面上浸渍纤维，接着稍后将浸渍的纤维形成可能证明对热注射工艺不确定的形状。
预浸料箔的厚度可以限定CSP可以承受的最大电压。用于预浸料的标准材料是具有例如1kV/100μm的击穿场的FR4和环氧树脂。包括安全裕度在内，1.2kV半导体芯片的适当嵌入将通常需要在半导体芯片与源极或栅极电位上的顶侧层之间有100μm厚的绝缘层。到目前为止，技术限制(如对厚的或多层绝缘层的层压和钻孔、以及对于这种深通孔结构的保形电镀)阻碍了CSP向显著更高的电压扩展。
利用本文描述的功率半导体模块，可以弥补用于实现基于用于高于1.2kV的电压等级的预封装CSP的功率模块的技术差距，并且使得能够将CSP用于>>1.2kV的电压等级。
所提出的解决方案包括使用例如100μm至150μm的最大通孔高度用于接合焊盘“扇入”布局，该布局允许接触件(如压配合管脚或其它管脚)的接合，使得接合焊盘在漏极电位上不重叠或太靠近半导体芯片的管芯边缘/边缘末端区域，即，被布置成不增加半导体芯片边缘周围的电场。接触件充当间隔件，间隔件允许将平面载体(如印刷电路板，简称PCB)固定在足够的距离内。
接触件可以连接到多层PCB，该多层PCB可以提供功率信号和控制信号的灵活的重新路由和分配。最后，CSP与PCB之间的空间用例如聚合物(如硅凝胶)绝缘，以形成间隔体。
在替代实施例中，与半导体器件中的芯片大小封装的半导体芯片的接触通过可以是电路板的组成部分的管脚或弹簧栅格阵列来建立。各个弹簧或管脚可以形成与CSP的接合焊盘的干式接触，即，与触头基座或与第一导电层和/或与中间布线的干式接触，或者接触件将例如通过焊接或烧结而接合到CSP的接合焊盘。在该方法中，CSP的接合焊盘使得能够安全地接触半导体器件，从而避免对敏感芯片顶侧金属化部(即，对顶部触头)的可能损坏，并且因此可以减少随后的产率损失。此外，扩大的扇入接合焊盘面积简化了半导体芯片上的小栅极焊盘的接触，从而为有源单元节省了更多的管芯面积。
术语“功率半导体模块”意味着例如模块被配置用于高电流和/或电压。例如，功率半导体模块被配置成处理至少1A的最大电流、或至少10A的最大电流、或至少100A的最大电流、或至少500A的最大电流。替代地或附加地，该模块被配置用于至少0.6kV的电压、或至少1.2kV的电压、或至少2kV的电压。
根据至少一个实施例，半导体器件是芯片大小的封装器件，即CSP器件。因此，从至少一个芯片顶侧的俯视图中看，半导体器件的占用面积例如是半导体器件中所包括的至少一个半导体芯片的占用面积的至多两倍或三倍。
根据至少一个实施例，间隔体布置成与至少一个盖体直接接触。另外，在盖体与间隔体之间可以存在中间层，例如金属层或金属层叠层。可选地，在盖体顶上的区域中，间隔体具有恒定的厚度。
根据至少一个实施例，接触件与间隔体直接接触。例如，间隔体形成在已经安装的接触件周围。接触件可以是预制的，使得接触件的形状被限定在功率半导体模块的外部并且在布置在功率半导体模块中之前被限定。接触件可以延伸完全穿过间隔体。从相应的芯片顶侧的俯视图中看，接触件可以限于分配的半导体芯片。
根据至少一个实施例，接触件与触头基座直接接触。另外，在接触件与相应的触头基座之间可以存在导电的中间布线。
根据至少一个实施例，电接触面与接触件直接接触，并且电接触面位于间隔体的远离盖体的侧面上。这可以意味着在相应的电接触面与至少一个分配的接触件之间至多存在电连接装置(如焊料或烧结体)。另外，电接触面和接触件彼此远离。
根据至少一个实施例，至少一个半导体器件的盖体由预浸料制成。因此，盖体可以包括嵌入有机材料中的纤维增强件。有机材料例如选自以下组：聚四氟乙烯(PTFE)、FR-2(酚醛棉纸)、FR-3(棉纸和环氧树脂)、FR-4(织造玻璃和环氧树脂)、FR-5(织造玻璃和环氧树脂)、FR-6(哑光玻璃和聚酯)、G-10(织造玻璃和环氧树脂)、CEM-1(棉纸和环氧树脂)、CEM-2(棉纸和环氧树脂)、CEM-3(非织造玻璃和环氧树脂)、CEM-4(织造玻璃和环氧树脂)、CEM-5(织造玻璃和聚酯)。
根据至少一个实施例，功率半导体模块进一步包括电路板(如印刷电路板，简称PCB)。所有电接触面可以集成在电路板中。
根据至少一个实施例，功率半导体模块被配置成借助于电路板进行外部电接触。即，功率半导体模块可以仅借助于电路板进行电接触。因此，与至少一个半导体芯片电接触的功率半导体模块的仅外部面可以位于电路板上。这种外部面可以通过例如金属电端子来实现。
作为电路板的补充或替代，可以使用可以充当电互连部的金属引线框架和/或金属端子。
根据至少一个实施例，从至少一个芯片顶侧的俯视图中看，电路板部分地或完全地覆盖至少一个半导体器件和/或间隔体。间隔体和电路板可以彼此一致。从芯片顶侧的俯视图中看，至少一个半导体器件可以被电路板和/或间隔体完全包围。
根据至少一个实施例，电路板进一步包括电线。电端子可以借助于电线以及借助于电接触面电连接到接触件。电端子可以通过电线直接电连接到电接触面，并且电接触面可以与接触件直接接触。另外，可以存在用于控制目的和/或传感器目的至少一个中间电子器件(如集成电路)。
根据至少一个实施例，从至少一个芯片顶侧的俯视图中看，电端子部分或完全位于至少一个半导体器件的外部。因此，电端子可以不与至少一个芯片顶侧和/或不与至少一个半导体器件重叠、或仅与至少一个芯片顶侧和/或与至少一个半导体器件部分重叠。
根据至少一个实施例，一些接触件一起被电分配给仅一个顶部触头。因此，一个或多个相应的顶部触头通过多个接触件电连接。
根据至少一个实施例，从至少一个芯片顶侧的俯视图中看，接触件完全位于顶部触头内和/或完全位于接触件所分配到的第一导电层内。因此，可以实现小的占用面积。
根据至少一个实施例，所有或一些接触件是压配合管脚或弹簧或堆叠的柱状凸块。所有接触件可以是相同类型的。另外，不同类型的接触件可以组合在功率半导体模块内。
根据至少一个实施例，所有或一些接触件各自被分配给恰好一个触头基座。因此，在接触件与触头基座之间可以存在一对一的分配。因此，可以实现可调节的布线设计。
根据至少一个实施例，一个、一些或所有接触件被配置为分配给多个触头基座的导电块。导电块可以是金属(比如铜)的。当从芯片顶侧的俯视图中看时，导电块可以是长方体或圆柱体形状的，或者可以具有更复杂的形状(如L形或U形)。
根据至少一个实施例，间隔体在至少一个芯片顶侧上的厚度为至少0.2mm或至少0.4mm和/或至多2mm或至多5mm。因此，通过使用接触件，可以获得相当厚的间隔体。
根据至少一个实施例，功率半导体模块进一步包括至少一个中间布线。该至少一个中间布线嵌入在至少一个盖体与间隔体之间。中间布线可以是一个或多个金属层。借助于中间布线，可以高效地连接触头基座和接触件。即，中间布线可以由第一导电层构成，或者可以包括至少一个另外的导电层。
根据至少一个实施例，一些或所有触头基座以及一些或所有相应的接触件借助于中间布线电连接。相应的触头基座和接触件这两者均可以与中间布线直接接触，使得至多电连接装置(如焊料或烧结层)位于接触件与中间布线之间。
根据至少一个实施例，中间布线包括第一导电层和第二导电层。例如，第一导电层包括在至少一个半导体器件中。第二导电层可以不是至少一个半导体器件的一部分，而仅仅是功率半导体模块的一部分。
根据至少一个实施例，第一导电层和第二导电层一起形成多个电中间触头。从至少一个芯片顶侧的俯视图中看，电中间触头以及相应地分配的顶部触头可以具有不同的大小，或者不然可以具有相同的大小。
根据至少一个实施例，功率半导体模块进一步包括衬底。例如，衬底是直接接合的铜衬底，包括例如陶瓷(如Al2O3)制的中心绝缘层、以及在绝缘层的每个主侧上的至少一个金属化部。作为替代，衬底是活性金属钎焊衬底，简称AMB衬底。因此，衬底可以用于对功率半导体模块进行冷却。
根据至少一个实施例，至少一个半导体器件安装在衬底的顶部金属化部上。顶部金属化部可以是平面层。
根据至少一个实施例，至少一个半导体器件与顶部金属化部电连接。此外，至少一个半导体器件可以嵌入在衬底与间隔层之间。因此，至少一个半导体器件可以被衬底连同间隔层以及连同接触件一起完全包围。
根据至少一个实施例，功率半导体模块进一步包括附加接触件。附加接触件可以从顶部金属化部延伸穿过间隔层。从至少一个芯片顶侧的俯视图中看，作为一个选择，附加接触件位于该至少一个半导体器件附近。因此，附加接触件与该至少一个半导体器件可以不重叠。
根据至少一个实施例，功率半导体模块包括多个半导体器件。例如，存在至少两个或至少四个或至少八个半导体器件。替代地或附加地，存在至多40个或至多20个或至多十二个半导体器件。
根据至少一个实施例，所有或一些半导体器件的芯片顶侧相互平行地布置。即，所有顶侧朝向同一方向。因此，在这种情况下，“平行”是指半导体器件的几何布置，而不是指电布线。例如，一些或所有芯片顶侧位于公共平面中。
根据至少一个实施例，从芯片顶侧的俯视图中看，半导体器件彼此相邻地布置和/或以非重叠的方式布置。因此，在功率半导体模块中不存在半导体器件的堆叠。
根据至少一个实施例，所有半导体器件被间隔体覆盖。例如，所有半导体器件嵌入在衬底与间隔体之间。
例如在车辆(如混合动力车辆或插电式电动车辆)中，功率半导体模块例如是用于将来自电池的直流电转换为用于电动机的交流电的功率模块。
另外提供了一种用于制造功率半导体模块的方法。借助于该方法，生产如结合至少一个上述实施例所指示的功率半导体模块。因此，对于该方法，也公开了功率半导体模块的特征，且反之亦然。
在至少一个实施例中，该方法用于制造功率半导体模块并且包括例如按所述顺序的以下方法步骤：
A)提供至少一个半导体器件，
B)将接触件接合到该至少一个半导体器件，
C)将电接触面与接触件电连接，以及
D)形成间隔体。
方法步骤C)也可以在方法步骤B)之前进行，使得步骤的顺序是A)>C)>B)>D)。另外，方法步骤C)/B)和D)可以互换，使得方法步骤的顺序也可以是A)>B)>D)>C)或A)>C)>D)>B)。
根据至少一个实施例，所生产的功率半导体模块包括电路板和多个半导体器件，使得在方法步骤A)中提供多个半导体器件。
根据至少一个实施例，在方法步骤C)中，将接触件与电路板电连接。在这种情况下，可以将接触件首先连接到中间布线或触头基座，然后连接到电路板，或者替代地，可以将接触件首先连接到电路板，然后连接到中间布线或触头基座。
根据至少一个实施例，在方法步骤D)中，电路板是用于形成间隔体的模具的一部分。可选地，当形成间隔体时也可以存在衬底，并且衬底于是也可以是用于形成间隔体的模具的一部分。因此，电路板以及可选地衬底既可以是用于间隔体的模具，也可以是功率半导体模块的集成部件。
附图说明
下面参考附图通过示例性实施例更详细地解释本文描述的半导体器件、功率半导体模块和方法。各个图中相同的元件用相同的附图标记指示。然而，元件之间的关系未按比例示出，而是各个元件可以夸大地示出以帮助理解。
在图中：
图1是与本文描述的半导体器件的示例性实施例的芯片顶侧垂直的示意性截面图，
图2是与图1的半导体器件的芯片顶侧平行的示意性截面图，
图3是与本文描述的功率半导体模块的示例性实施例的芯片顶侧垂直的示意性截面图，
图4是与图3的功率半导体模块的芯片顶侧平行的示意性截面图，
图5是用于生产本文描述的功率半导体模块的方法的示例性实施例的示意性框图，
图6是用于生产本文描述的功率半导体模块的方法的示例性实施例的方法步骤的与芯片顶侧垂直的示意性截面图，
图7是与本文描述的功率半导体模块的示例性实施例的芯片顶侧垂直的示意性截面图，
图8是与修改的功率半导体模块的芯片顶侧平行的示意性截面图，
图9是与本文描述的功率半导体模块的示例性实施例的芯片顶侧平行的示意性截面图，以及
图10是本文描述的功率半导体模块的、以及修改的功率半导体模块的示例性实施例的热特性和电特性的示意性表示。
具体实施方式
图1和图2图示了半导体器件1的示例性实施例。半导体器件1包括半导体芯片2，该半导体芯片是例如MOSFET、MISFET、IGBT、BJT、GTO、GCT或JFET。半导体芯片2可以是高电压类芯片，并且可以被配置用于至少1.2kV的电压。半导体器件1可以如图1所示仅包含一个半导体芯片2，但是也可以存在多个半导体芯片2，例如至多五个相同或不同类型的半导体芯片2。
此外，半导体器件1包含盖体23。例如，盖体23是包含聚合物(如环氧树脂)的预浸料或模制体。盖体23与芯片侧壁直接接触并且还与芯片顶侧20直接接触。参见图1，盖体23在芯片顶侧20顶上的厚度T例如为0.1mm，以使得能够有效地制造穿过盖体23的触头基座22。
参见图2，在芯片顶侧20处，存在顶部触头21，也称为接合焊盘。顶部触头21可以是与半导体芯片2的半导体本体直接接触的金属化部。顶部触头21可以具有不同的尺寸和/或轮廓。触头基座22从顶部触头21开始。每个顶部触头21可以有多于一个的触头基座22。作为选择，较大的顶部触头21(例如，源极或漏极触头)设置有多个触头基座22，而较小的顶部触头21(例如，栅极触头)设置有仅一个触头基座22。与图1和图2不同，可以存在三个或多于三个的顶部触头21，或者也可以存在仅一个顶部触头21。
触头基座22可以通过在先前完成的盖体23中钻孔(例如，通过激光钻孔)来制造。然后，可以溅射金属种子层(未示出)。然后，借助于例如电镀来填充孔，并且产生触头基座22(也称为通孔)。
作为替代方案，可以首先将触头基座22接合到芯片顶侧20，随后例如借助于模制来形成盖体23。在这种情况下，触头基座22可以是通过焊接或烧结安装在相应的触头21上的金属体。
作为选择，被配置用于中间布线6的第一导电层61可以存在于盖体23的远离半导体芯片2的盖体顶侧26上。第一导电层61可以是金属层或者也可以是金属层叠层。第一导电层61突出到盖体23的上方。
例如，第一导电层61类似于顶部触头21被电结构化。因此，每个顶部触头21可以有第一导电层61的恰好一个电中间触头。然而，相应的电中间触头和分配的顶部触头21可以具有不同的占用面积，也对照下面的图4。
因此，借助于中间布线6，可以形成不一定具有顶部触头21的形状和/或大小的接触面。然而，从俯视图中看，由中间布线6、特别是由第一导电层61形成的接触面可以具有朝向芯片顶侧20的边缘的最小距离，该最小距离至少是朝向顶部触头21的芯片顶侧20的边缘的最小距离。换句话说，从顶部触头21的俯视图中看，第一导电层61以及例如整个中间布线6与相应的顶部触头21相比朝向芯片顶侧边缘更远或者至多一样远。
半导体器件1可以是芯片大小的封装，简称CSP。因此，整个半导体器件1的横向尺寸与半导体芯片2的横向尺寸相当。例如，盖体23在半导体芯片2的侧壁处的宽度是芯片顶侧20的边缘长度的至多50％或至多25％。芯片顶侧20的边缘长度例如为至少1mm或至少2mm和/或至多2cm或至多1cm。从俯视图中看，半导体芯片2和/或盖体23可以具有矩形形状或正方形形状。
可选地，半导体器件1包括芯片载体24，至少一个半导体芯片2例如借助于焊接或烧结安装在该芯片载体处。芯片载体24可以是例如由铜或铜合金制成的金属引线框架。芯片载体24的厚度例如为至少0.1mm和/或至多1mm。在横向方向上，芯片载体24可以与盖体23齐平地终止。因此，远离盖体顶侧26的器件底侧25可以由芯片载体24形成。
图3示出了功率半导体模块10的示例性实施例。功率半导体模块10包括至少一个半导体器件1，该至少一个半导体器件可以如结合图1和图2描述的那样进行配置。
此外，功率半导体模块10包括间隔体4。间隔体4例如由硅凝胶制成，或者也由塑料(如环氧树脂)制成。间隔体4可以通过铸造或模制来制造。此外，间隔体4具有相当大的厚度S，这有效地增加了盖体23的厚度T。间隔体4直接接合到盖体23上。例如，间隔体4的厚度S在0.2mm与3mm之间(包括端值)，或者在0.3mm与2mm之间(包括端值)。
功率半导体模块10还包括接触件3。接触件3是例如压配合管脚。相应地，接触件3可以在背离芯片顶侧20的方向上具有大的范围，并且可以延伸完全穿过间隔体4。接触件3的直径例如至少为0.1mm和/或至多为1mm。
为了改善接触件3与触头基座22之间的粘附性，作为选择，存在中间布线6。中间布线6可以包括结合图1和图2描述的第一导电层61。作为另一选择，中间布线6还可以包括第二导电层62。例如，第二导电层62是用于改善接触件3与中间布线6的焊接或烧结的层。即，第二导电层62可以例如以一致的方式施加到半导体部件1的第一导电层61上，以创建中间布线6。
例如，从芯片顶侧的俯视图中看，中间布线6位于芯片顶侧20内。因此，借助于中间布线6，可以相对于盖体顶侧26处的第二导电层62来改变半导体芯片2处的第一导电层61的大小，其中所有导电层61、62位于芯片顶侧20内并且不在半导体芯片2上方横向突出。
功率半导体模块10还包括电接触面51。电接触面51可以是电路板5的一部分，该电路板可以与间隔体4在远离盖体23的一侧上直接接触。接触件3例如在使用压配合管脚的情况下借助于干式接触、或者替代地借助于焊接与电接触面51电连接。因此，电接触面51可以是电路板5的被配置用于表面安装技术(如焊接)的外表面，或者电接触面51可以是电路板5(如母连接器)的被配置用于接收接触件3的内表面。
例如，电路板5是PCB并且还可以包括：电线52，用于内部布线；和/或电端子53，用于将功率半导体模块10与例如未示出的外部板进行外部连接。因此，电路板5可以是多层PCB。
借助于间隔体4与接触件3的组合，电路板5与顶部触头21之间的距离可以显著增加超过通过使用通过钻孔和电镀制造的触头基座22设定的极限。因此，功率半导体模块10可以高效地被配置用于例如1.7kV或更高的高电压。
此外，通过将接触件3与CSP半导体器件1一起使用，不需要在功率半导体模块10内使用接合线。因此，基本上可以确保间隔体4和半导体器件1内的垂直电流流动，并且如果电接触面51以及电端子53相应地定位，则可以确保电路板5中的垂直电流流动。相应地，需要更少的空间来容纳至少一个半导体芯片2。
如图4所图示，通过具有可选的中间布线6，在中间布线6的水平处，可以实现更适合于接触件3的更大的电中间触头。因此，通过具有中间布线6，接触件3的设计可以完全独立于顶部触头21的设计以及触头基座22的设计。特别地，与最小顶部触头21(参见图3)相比，中间布线6的最小电中间触头(参见图4)可以相对较大。例如，与中间布线6的分配的电中间触头的占用面积相比，最小顶部触头21的占用面积增加至少两倍或至少四倍。
在图5中，示意性地示出了用于生产功率半导体模块10的方法。在方法步骤M1中，提供至少一个半导体器件1，其中还可以提供多个半导体器件1。作为示例，半导体器件1可以接合到公共衬底。可以存在于成品功率半导体模块10中的几何布置来应用半导体器件1。因此，在方法步骤M1之后，半导体器件1的相对位置可以保持相同。
如果存在中间布线6并且中间布线6包括第二导电层62，则方法步骤M1可以包括提供第二导电层62。
在随后的方法步骤M2中，将接触件3接合到至少一个半导体器件1。例如，将接触件3焊接或烧结到触头基座22或中间布线6。
然后，在方法步骤M3中，例如通过焊接、烧结、压制或夹持将电接触面51与接触件3电连接。
最后，在方法步骤M4中，形成间隔体4。在该步骤中，电路板5和/或衬底7可以用作模具8来使间隔体4成形，也对照图6。
相应地，这些方法步骤的顺序可以是M1>M2>M3>M4。然而，也可以在接触件3接合到电接触面51之前形成间隔体4，使得以M1>M2>M4>M3的顺序执行这些步骤。如果将接触件3首先接合到电接触面51，然后接合到触头基座22或接合到中间布线6，则这些步骤的顺序也可以是M1>M3>M2>M4或M1>M3>M4>M2，使得可以在接触件3接合到触头基座22或中间布线6之前或之后形成间隔体4。
这些不同的步骤顺序在图5中由分配给方法步骤的框之间的不同箭头方案指示。取决于这些方法步骤的顺序，衬底7和/或电路板5可以用作模具8以形成间隔体4。
在图6中，示出了功率半导体模块10的另一示例性实施例，并且还示出了图5的根据方案M1>M2>M4>M3的方法的方法步骤。因此，将接触件3接合到可选的中间布线6，然后形成间隔体4，然后施加电路板5。在图6中，电路板5尚未完全施加以帮助理解该方法。
功率半导体模块10包括多个半导体器件1(例如，两个半导体器件1)。关于半导体器件1，与图1和图2相同的情况也适用于图6。
作为进一步的选择，功率半导体模块10包括衬底7。例如，衬底7是直接接合的铜衬底，简称DBC衬底。因此，衬底7包括顶部金属化部71、绝缘层72和底部金属化部73。底部金属化部73借助于绝缘层72与半导体器件1电绝缘。底部金属化部73可以被配置成将功率半导体模块10安装到散热器(未示出)上。
此外，功率半导体模块10还可以包括也与电路板5电连接的另外的接触件37。例如，另外的接触件37从顶部金属化部71开始，并且延伸完全穿过同样位于相邻半导体器件1之间的间隔体4，并因此到达衬底7。另外的接触件37和接触件3可以是相同类型的、例如可以全部是压配合管脚，或者可以是不同类型的、例如与柱状凸块组合的压配合管脚。
因此，借助于另外的接触件37，顶部金属化部71可以用于在功率半导体模块10内建立电布线方案。以这种方式，例如，这些半导体器件1中的第一半导体器件可以形成高侧H，这些半导体器件1中的第二半导体器件可以形成低侧L，并且另外的接触件37可以形成由功率半导体模块10实现的直流到交流转换器的交流端子AC。
与图6所示相反，所有电路板5、衬底7和间隔体4可以在功率半导体模块10的侧面上齐平地终止。
另外，与图1至图5相同的情况也适用于图6。
在图7的功率半导体模块10中，在左侧图示了：在可选中间布线6的较大的电中间触头处，可以存在仅一个接触件3。该接触件3可以由适当形状的大块金属块形成。另外，代替压配合管脚，弹簧也可以用于接触件3，如图7中右侧所图示。在所有其它示例性实施例中，接触件3的这些不同实现方式以及任何组合也是可能的。
另外，与图1至图6相同的内容适用于图7。
在图8至图10中图示出：通过使用与间隔体4和CSP半导体器件1连接的接触件3，可以实现改善的热特性，并且半导体芯片2需要更少的空间。在修改的功率模块9中，使用接合线92代替接触件3。因此，电流也在很大程度上在横向方向上流动，并且只有2×2半导体芯片2和所分配的另外的半导体芯片29(如二极管)可以容纳在特定的DBC衬底7上。
与此相反，参见图9，使用本配置，4×4半导体芯片2和所分配的另外的半导体芯片29可以容纳在同一DBC衬底7上。
此外，参见图10，对于绝缘层72的380μm、320μm和150μm的层厚度，从左到右看，在例如150℃的特定温度处，与图8的修改的功率模块9相比，在图9的功率半导体模块10中，可以实现较低的热电阻Rth并相应地实现较高的电流I。
这里描述的实用新型内容不受参考示例性实施例给出的描述的限制。相反，本实用新型涵盖任何新颖特征和特征的任何组合，特别是包括权利要求中的特征的任何组合，即使该特征或该组合本身没有在权利要求或示例性实施例中明确指示。
附图标记清单
1 半导体器件
10 功率半导体模块
2 半导体芯片
20 芯片顶侧
21 半导体芯片的顶部触头
22 触头基座
23 盖体
24 芯片载体
25 器件底侧
26 盖体顶侧
29 另外的半导体芯片
3 接触件
37 附加接触件
4 间隔体
5 电路板
51 电接触面
52 电线
53 电端子
6 中间布线
61 第一导电层
62 第二导电层
7 衬底
71 顶部金属化部
72 绝缘层
73 底部金属化部
8 模具
9 修改的功率模块
91 衬底接触面
92 接合线
AC AC端子
H 高侧
I 电流
L 低侧
M… 方法步骤
Rth 热阻
S 间隔体在芯片顶侧顶上的厚度
T 盖体在芯片顶侧顶上的厚度

Claims (11)

1.一种功率半导体模块(10)，其特征在于，包括：
-至少一个半导体器件(1)，
-电绝缘间隔体(4)，所述电绝缘间隔体布置在所述至少一个盖体(23)上，
-多个接触件(3)，所述多个接触件在背离所述至少一个芯片顶侧(20)的方向上延伸穿过所述间隔体(4)并且与所述触头基座(22)电接触，以及
-多个电接触面(51)，所述多个电接触面与所述接触件(3)电连接，并且所述多个电接触面位于所述间隔体(4)的远离所述至少一个半导体器件(1)的侧面上，
其中
-所述半导体器件(1)包括半导体芯片(2)，所述半导体芯片被配置用于至少0.6kV的电压，所述半导体芯片(2)具有位于芯片顶侧(20)上的顶部触头(21)，
-所述半导体器件(1)还包括多个触头基座(22)以及电绝缘盖体(23)，所述多个触头基座与所述顶部触头(21)电连接，并且所述半导体芯片(2)和所述触头基座(22)嵌入所述电绝缘盖体中，其中所述触头基座(22)在背离所述芯片顶侧(20)的方向上延伸穿过所述盖体(23)，以及
-所述半导体器件(1)还包括第一导电层(61)，所述第一导电层被配置用于在远离所述半导体芯片(2)的盖体顶侧(26)处的中间布线(6)并且与所述触头基座(22)电接触，以及
-至少一些所述接触件(3)是压配合管脚或弹簧或柱状凸块，以及所述接触件(3)各自被分配给恰好一个所述触头基座(22)。
2.根据权利要求1所述的功率半导体模块(10)，其特征在于，
进一步包括电路板(5)，
其中所述电接触面(51)集成在所述电路板(5)中，
其中所述功率半导体模块(1)被配置成借助于所述电路板(5)进行外部电接触，以及
其中从所述至少一个芯片顶侧(20)的俯视图中看，所述电路板(5)完全覆盖所述至少一个半导体器件(1)和所述间隔体(4)。
3.根据权利要求2所述的功率半导体模块(10)，其特征在于，
其中所述电接触面(51)与相应的接触件(3)直接接触，
其中所述电路板(5)进一步包括电线(52)和电端子(53)，
其中所述电端子(53)借助于所述电线(52)与所述接触件(3)电连接并且被配置作为所述电路板(5)的外部电触头，并因此被配置作为所述功率半导体模块(10)的外部电触头，以及
其中从所述至少一个芯片顶侧(20)的俯视图中看，所述电端子(53)至少部分地位于所述至少一个半导体器件(1)的外部。
4.根据权利要求1至3中任一项所述的功率半导体模块(10)，其特征在于，
从所述芯片顶侧(20)的俯视图中看，所述触头基座(22)完全位于相应的顶部触头(21)内，以及
从所述芯片顶侧(20)的俯视图中看，所述中间布线(6)距所述芯片顶侧(20)的边缘与至少一个所分配的顶部触头(21)距所述芯片顶侧的边缘至少一样远，使得所述中间布线(6)是以下中的至少一项：
-完全位于所述芯片顶侧(20)内，
-远离所述芯片顶侧(20)的边缘，以及
-远离所述半导体芯片(2)的末端区域。
5.根据权利要求1至3中任一项所述的功率半导体模块(10)，其特征在于，
其中一些所述接触件(3)一起被电分配给仅一个所述顶部触头(21)，
其中从所述至少一个芯片顶侧(20)的俯视图中看，所述接触件(3)完全位于所分配的第一导电层(61)内。
6.根据权利要求1至3中任一项所述的功率半导体模块(10)，其特征在于，
其中至少一个所述接触件(3)是分配给多个所述触头基座(22)的导电块。
7.根据权利要求1至3中任一项所述的功率半导体模块(10)，其特征在于，
其中所述间隔体(4)在所述至少一个芯片顶侧(20)顶上的厚度是至少0.2mm且至多2mm，以及
其中所述间隔体(4)包含硅凝胶。
8.根据权利要求1至3中任一项所述的功率半导体模块(10)，其特征在于，
其中所述中间布线嵌入在所述至少一个盖体(23)与所述间隔体(4)之间，
其中所述触头基座(22)和所述接触件(3)借助于所述中间布线(6)电连接。
9.根据权利要求8所述的功率半导体模块(10)，其特征在于，
其中所述中间布线(6)包括所述第一导电层(61)以及第二导电层(62)，所述第二导电层位于所述第一导电层(61)的远离所述至少一个半导体器件(1)的侧面上，
其中所述第一导电层(61)和所述第二导电层(62)一起形成多个电中间触头，以及
其中从所述至少一个芯片顶侧(20)的俯视图中看，所述电中间触头和相应地所分配的顶部触头(21)具有不同的大小。
10.根据权利要求1至3中任一项所述的功率半导体模块(10)，其特征在于，
进一步包括衬底(7)和附加接触件(37)，其中，
-所述至少一个半导体器件(1)安装在所述衬底(7)上并且位于所述衬底(7)与所述间隔层(4)之间，
-所述衬底(7)包括顶部金属化部(71)，所述顶部金属化部面对所述至少一个半导体器件(1)并且与所述至少一个半导体器件电接触，以及
-所述附加接触件(37)从所述顶部金属化部(71)延伸穿过所述间隔层(4)，并且从所述至少一个芯片顶侧(20)的俯视图中看，所述附加接触件位于所述至少一个半导体器件(1)附近。
11.根据权利要求1至3中任一项所述的功率半导体模块(10)，其特征在于，
包括多个半导体器件(1)，
其中所述半导体器件(1)的芯片顶侧(20)在几何上相互平行地布置，并且从所述芯片顶侧(20)的俯视图中看，所述半导体器件(1)以非重叠的方式彼此相邻地布置，以及
其中所述半导体器件(1)全部一起被所述间隔体(4)覆盖。
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