JP7233621B1 - 熱性能が向上したパワーモジュールデバイス - Google Patents
熱性能が向上したパワーモジュールデバイス Download PDFInfo
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- JP7233621B1 JP7233621B1 JP2022559653A JP2022559653A JP7233621B1 JP 7233621 B1 JP7233621 B1 JP 7233621B1 JP 2022559653 A JP2022559653 A JP 2022559653A JP 2022559653 A JP2022559653 A JP 2022559653A JP 7233621 B1 JP7233621 B1 JP 7233621B1
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- layer
- power module
- module device
- insulating layer
- insulating
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Abstract
Description
発明の分野
本発明は、パワーエレクトロニクス(PE)の分野に関し、より詳細には、パワー半導体デバイスが組み込まれたパワーモジュールデバイスに関する。
従来のパワーモジュールでは、絶縁ゲートバイポーラトランジスタ(IGBT)チップ、パワー金属酸化膜半導体電界効果トランジスタ(MOSFET)チップ、またはパワーダイオードチップなどのパワー半導体チップは、良好な熱接触および熱拡散を保証するために直接接合銅(DBC)基板上にはんだ付けされる。セラミックコア層と、セラミックコア層の両側に銅(Cu)層とを含むDBC基板は、それらの優れた熱伝導率および導電率ならびに良好な機械的特性で知られている。DBC基板を製造するために、セラミックコア層への銅箔の直接接合は、通常1000℃を超える高温で行われる。製造中のDBC基板の曲げを回避するために、同じ厚さを有する銅箔がセラミックコア層の両側に接合される。したがって、DBC基板は対称的なCu/セラミック/Cu構造を有する。DBC基板上にはんだ付けされた半導体チップは、一般にワイヤボンディングによって接触され、シリコーンゲルは、典型的には、電気絶縁ならびに機械的および環境的保護を提供するために使用される。市販のDBC基板のセラミックコア層は、少なくとも250μmの層厚を有し、DBC基板の熱抵抗に関する制限をもたらす。
本発明の目的は、熱性能が改善されたパワー半導体デバイスが埋め込まれた信頼性の高いパワーモジュールデバイスおよびその製造方法を提供することである。
例示的な実施形態では、セラミック層は、酸化アルミニウム(Al2O3)または窒化アルミニウム(AlN)または窒化ケイ素(Si3N4)などの20W/(m×K)を超える熱伝導率を有する電気絶縁セラミック層を備える。20W/(m×K)を超える熱伝導率は、今日利用可能なすべてのプリプレグまたはPCB材料の熱伝導率よりも著しく高い。
上記で説明した実施形態のいずれかのパワーモジュールデバイスは、請求項16に記載の方法によって製造することができる。
本発明の主題は、添付の図面を参照して実施形態の以下の詳細な説明から当業者には明らかになるであろう。
以下、第1の実施形態によるパワーモジュールデバイス100について説明する。図1Aは、パワーモジュールデバイス100の断面図を示す。図2A~図2Dは、図1Aのパワーモジュールデバイス100の製造方法の例示的な実施形態における方法ステップを示す。パワーモジュールデバイス100は、第1の主面102と、第1の主面102とは反対側の第2の主面104とを有する。第1の主面102から第2の主面104へと順に、パワーモジュールデバイス100は、ベースプレート110と、電気絶縁セラミック層120と、電気絶縁第1の絶縁層130と、導電性リードフレーム140と、パワー半導体デバイス150と、電気絶縁第2の絶縁層160と、導電層180とを備える。
2,2’,2’’ 第1のビア
2a 第1の孔
4,4’,4’’ 第2のビア
4a 第2の孔
6,6’,6’’ 第3のビア
6a 第3の孔
100,200,300,400,500,600 パワーモジュールデバイス
102 第1の主面
104 第2の主面
110 ベースプレート
120 セラミック層
125 接着層
130 第1の絶縁層
130a 第1のプリプレグ層
140,140’,140’’ リードフレーム
142,142’ 凹部
144,144’,144’’ 上部実質的に平坦面
150 パワー半導体デバイス
151 底部メタライゼーション層
152 頂部メタライゼーション層
160,160’,160’’ 第2の絶縁層
160a,160b,160c 第2のプリプレグ層
170 接触層/接合層
180 導電層
180a (導電層180の)第1の部分
180b (導電層180の)第2の部分
180c (導電層180の)第3の部分
d1 (凹部142の)深さ
d2 (セラミック層120の)層厚
d3 (接着層125の)層厚
d4 (第1の絶縁層130の)層厚
d5 (ベースプレート110の)層厚
Claims (15)
- 第1の主面(102)と前記第1の主面(102)とは反対側の第2の主面(104)とを有するパワーモジュールデバイス(100、200、300、400、500、600)であって、前記パワーモジュールデバイス(100、200、300、400、500、600)は、前記第1の主面(102)から前記第2の主面(104)へと順に、
ベースプレート(110)と、
前記ベースプレート(110)上の電気絶縁セラミック層(120)と、
前記セラミック層(120)上の電気絶縁性の第1の絶縁層(130)であって、プリプレグ材料を備える第1の絶縁層(130)と、
前記第1の絶縁層(130)上の導電性リードフレーム(140、140’、140’’)であって、前記ベースプレート(110)から電気的に絶縁されている、導電性リードフレーム(140、140’、140’’)と、
パワー半導体デバイス(150)と、
電気絶縁性の第2の絶縁層(160、160’、160’’)であって、前記リードフレーム(140)と前記第2の絶縁層(160、160’、160’’)との間に前記パワー半導体デバイス(150)が埋め込まれるように前記パワー半導体デバイス(150)上にある、電気絶縁性の第2の絶縁層(160、160’、160’’)とを備え、
前記パワー半導体デバイス(150)は、前記リードフレーム(140、140’、140’’)上に配置され、
前記第1の絶縁層(130)の層厚(d4)は100μm未満である、パワーモジュールデバイス(100、200、300、400、500、600)。 - 前記第1の絶縁層(130)は、前記リードフレーム(140、140’、140’’)と直接接触している、請求項1に記載のパワーモジュールデバイス(100、200、300、400、500、600)。
- 前記ベースプレート(110)は、導電性材料または金属もしくは銅を備える、請求項1または2に記載のパワーモジュールデバイス(100、200、300、400、500、600)。
- 前記第2の絶縁層(160、160’、160’’)はプリプレグ材料を備える、請求項1から3のいずれか1項に記載のパワーモジュールデバイス(100、200、300、400、500、600)。
- 前記第1の絶縁層(130)の層厚(d4)は70μm未満である、請求項1から4のいずれか1項に記載のパワーモジュールデバイス(100、200、300、400、500、600)。
- 前記セラミック層(120)は、20W/(m×K)を超える熱伝導率を有する、請求項1から5のいずれか1項に記載のパワーモジュールデバイス(100、200、300、400、500、600)。
- 前記リードフレーム(140、140’)の前記第1の絶縁層(130)とは反対側に凹部(142、142’)が形成され、前記パワー半導体デバイス(150)の少なくとも一部は前記凹部(142、142’)内に配置されている、請求項1から6のいずれか1項に記載のパワーモジュールデバイス(100、200、300、400)。
- 前記セラミック層(120)の層厚(d2)は、200μm以下、または100μm以下、または50μmから200μmの範囲、または50μmから100μmの範囲である、請求項1から7のいずれか1項に記載のパワーモジュールデバイス(100、200、300、400、500、600)。
- 前記パワー半導体デバイス(150)は底面を有する半導体チップであり、前記底面に底部メタライゼーション層(151)が形成され、前記底部メタライゼーション層(151)は前記リードフレーム(140、140’、140’’)に電気的に接続されている、請求項1から8のいずれか1項に記載のパワーモジュールデバイス(100、200、300、400、500、600)。
- 前記パワー半導体デバイス(150)は、絶縁ゲートバイポーラトランジスタ、サイリスタ、金属-絶縁体-半導体電界効果トランジスタ、金属酸化物-半導体電界効果トランジスタ、接合電界効果トランジスタ、ダイオード、およびショットキーダイオードのうちの少なくとも1つを備える、請求項1から9のいずれか1項に記載のパワーモジュールデバイス(100、200、300、400、500、600)。
- 前記セラミック層(120)と前記第1の絶縁層(130)との間に接着層(125)を備え、前記接着層(125)は金属層または銅層を備える、請求項1から10のいずれか1項に記載のパワーモジュールデバイス(200、400、600)。
- 前記接着層(125)の層厚(d3)は、50μm未満または25μm未満または10μm未満である、請求項11に記載のパワーモジュールデバイス(200、400、600)。
- 前記第1の絶縁層(130)は前記接着層(125)と直接接触している、請求項11または12に記載のパワーモジュールデバイス(200、400、600)。
- 前記第1の絶縁層(130)は前記セラミック層(120)と直接接触している、請求項1から10のいずれか1項に記載のパワーモジュールデバイス(100、300、500)。
- 請求項1から14のいずれか1項に記載のパワーモジュールデバイス(100、200、300、400、500、600)の製造方法であって、
(i)リードフレーム(140、140’、140’’)を提供するステップと、
(ii)パワー半導体デバイス(150)を前記リードフレームに取り付けるステップと、
(iii)ベースプレート(110)を基板として使用して前記ベースプレート(110)上に電気絶縁セラミック層(120)を形成するステップと、
(iv)前記セラミック層(120)が上に形成された前記ベースプレート(110)と、第1のプリプレグ層(130a)と、前記パワー半導体デバイス(150)が取り付けられた前記リードフレーム(140、140’、140’’)と、第2のプリプレグ層(160a、160b、160c)と、をこの順に層スタックに配置するステップと、
(v)前記層スタックに熱および圧力を加えるステップであって、前記第1のプリプレグ層(130a)が100μm未満の層厚(d4)を有する前記第1の絶縁層(130)に変質する、ステップと、
を少なくとも含む、方法。
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