WO2022104805A1 - Structure de test et procédé de test - Google Patents

Structure de test et procédé de test Download PDF

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Publication number
WO2022104805A1
WO2022104805A1 PCT/CN2020/130937 CN2020130937W WO2022104805A1 WO 2022104805 A1 WO2022104805 A1 WO 2022104805A1 CN 2020130937 W CN2020130937 W CN 2020130937W WO 2022104805 A1 WO2022104805 A1 WO 2022104805A1
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WO
WIPO (PCT)
Prior art keywords
resistor
resistance
test structure
resistors
test
Prior art date
Application number
PCT/CN2020/130937
Other languages
English (en)
Chinese (zh)
Inventor
廖昱程
邱青松
张明丰
Original Assignee
江苏时代全芯存储科技股份有限公司
江苏时代芯存半导体有限公司
塞席尔商使命科技控股有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏时代全芯存储科技股份有限公司, 江苏时代芯存半导体有限公司, 塞席尔商使命科技控股有限公司 filed Critical 江苏时代全芯存储科技股份有限公司
Priority to PCT/CN2020/130937 priority Critical patent/WO2022104805A1/fr
Priority to CN202080099894.8A priority patent/CN115485833A/zh
Publication of WO2022104805A1 publication Critical patent/WO2022104805A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/08—Measuring resistance by measuring both voltage and current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Definitions

  • the present invention relates to the field of semiconductor testing, in particular to a testing structure and a testing method.
  • FIG. 1 shows the arrangement between the two heaters and the phase change material layer in the prior art.
  • the technical problem to be solved by the present invention is to provide a test structure and a test method, which can accurately measure the resistance value of the resistor formed by the heater and the phase change material layer.
  • the present invention provides a test structure, comprising: a first resistor; and at least one second resistor electrically connected in series with the first resistor, the number of the second resistors is M ⁇ N, the M and N are positive integers, and all of the second resistors are electrically connected in parallel with each other.
  • the present invention provides a test method, which includes the following steps: setting a first test structure, the first test structure includes a first resistor, and at least one second resistor electrically connected in series with the first resistor , the number of the second resistors is 1 ⁇ 1, and all the second resistors are electrically connected in parallel with each other; a second test structure is provided, the second test structure includes a first resistor, and is electrically connected to the first resistor Connect at least one second resistor in series, and the number of the second resistors is 2 ⁇ 2; measure the resistance values of the first test structure and the second test structure, and calculate the difference; The resistance value of the second resistor is calculated based on the difference of the resistance values of the second resistor; the resistance value of the first resistor is calculated according to the obtained resistance value of the second resistor and combined with the resistance value of the first test structure or the second test structure.
  • the present invention obtains the resistance difference by setting different numbers of resistances, thereby accurately calculating the resistance values of the phase change material and the heater.
  • FIG. 1 shows the arrangement between the two heaters and the phase change material layer in the prior art.
  • FIG. 2 is a schematic diagram of a test structure according to a specific embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a test structure according to a specific embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a test structure according to a specific embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the implementation steps of the testing method according to a specific embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a specific implementation manner of applying current to the resistance test of the first test structure and the second test structure using the method shown in FIG. 5 .
  • FIG. 2 is a schematic structural diagram of another specific embodiment of the test structure of the present invention, which includes: a first resistor 21 and at least one second resistor 22 electrically connected in series with the first resistor.
  • the number of the second resistors is M ⁇ N, and the M and N are positive integers.
  • FIG 3 is a schematic structural diagram of another specific embodiment of the test structure of the present invention, which includes: a first resistor 21 and at least one second resistor 22 electrically connected in series with the first resistor.
  • the number of the second resistors is M ⁇ N, and the M and N are positive integers.
  • the above structure is used to test the resistance value R GST of the first resistor 21 and the resistance value R ch of the second resistor 22 . Since the number of the second resistors 22 used in the above-mentioned test structures is different, any two test structures in the above-mentioned specific embodiments are used to measure the total series resistances Rth 1 and R th2 of the above-mentioned structures, respectively.
  • Rth 1 is the total series resistance of the test structure in FIG. 2
  • Rth 1 R ch +R GST +R PAS
  • R PAS is the sum of electrode resistance and background parasitic resistance.
  • R th3 is the total series resistance of the test structure in FIG. 3
  • Rth 2 R ch /2+R GST +R PAS .
  • R th1 -R th2 is regarded as the resistance change caused by the change of the number of the second resistors 22 , and the resistance value R ch of the second resistor 22 can be calculated.
  • FIG. 4 is a schematic diagram of the structure of this specific embodiment, including: a first resistor 21 and at least one second resistor 22 electrically connected in series with the first resistor.
  • the test structure is used to test the variable resistance structure of the phase change memory
  • the first resistance is a phase change material layer, such as GST material
  • the second resistance is a heater.
  • the number of the second resistors is M ⁇ N, and M and N are positive integers. All the second resistors are electrically connected in parallel with each other, and are preferably arranged in an array with equal spacing in M rows and N columns.
  • M being equal to N is that all the second resistors 22 can be placed in the same electrical environment, thereby reducing the systematic error between the resistors due to process and electric field distribution.
  • the second resistor 22 is disposed in an insulating dielectric layer 23 , the distance between the second resistor 22 and the boundary of the insulating dielectric layer 13 is d, and the distance between the second resistor 22 and the boundary of the insulating dielectric layer 13 is d. The distance between them is 2d. This can ensure that the electrical environment of each resistor is consistent, and reduce the systematic error between the resistors due to process and electric field distribution.
  • FIG. 5 is a schematic diagram of the implementation steps of the method according to this specific embodiment, including: step S51, setting a first test structure, the first test structure includes a first resistor, and a first resistor is electrically connected in series.
  • At least one second resistor the number of the second resistors is M1 ⁇ N1, the M1 and N1 are positive integers, and all the second resistors are electrically connected in parallel with each other; step S52, set up a second test structure, all The second test structure includes a first resistor, and at least one second resistor electrically connected in series with the first resistor, the number of the second resistors is M2 ⁇ N2, the M2 and N2 are positive integers, and all the The second resistors are electrically connected in parallel with each other, and the value of M1 ⁇ N1 is not equal to the value of M2 ⁇ N2; step S53, measure the resistance values of the first test structure and the second test structure, and calculate the difference Step S54, according to the difference of the calculated resistance value, in conjunction with the difference of the value of M1 ⁇ N1 and the value of M2 ⁇ N2, calculate the resistance value of the second resistance; Step S55, according to the obtained resistance of the second resistance The resistance value of the first resistor is calculated in combination with the resistance
  • the current flow direction is set to One resistance flows to the second resistance, and from the second resistance to the first resistance, the resistance values in the above two cases are respectively tested, and the average value is taken as the resistance of the first test structure. This counteracts systematic errors due to process and electric field distribution in the resistor's environment.
  • a first test structure is set up, the first test structure includes a first resistor, and at least one second resistor electrically connected in series with the first resistor, and the number of the second resistors is M1 ⁇ N1 , the M1 and N1 are positive integers, all the second resistors are electrically connected in parallel with each other, and are arranged in an equidistant array in the form of M1 rows and N1 columns;
  • a second test structure is set up, and the second test structure Including a first resistor, and at least one second resistor electrically connected in series with the first resistor, the number of the second resistors is M2 ⁇ N2, the M2 and N2 are positive integers, and all the second resistors are mutually They are electrically connected in parallel and arranged in an array with equal spacing in the form of M1 rows and N1 columns, and the value of M1 ⁇ N1 is not equal to the value of M2 ⁇ N2.
  • This step may adopt any two of the specific implementation manners of the

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

La présente invention concerne une structure de test et un procédé de test. La structure de test comprend : une première résistance (21) ; et au moins une seconde résistance (22) électriquement connectée en série avec la première résistance (21), le nombre de secondes résistances (22) étant M × N, M et N étant des entiers positifs, et toutes les secondes résistances (22) étant électriquement connectées en parallèle les unes aux autres. Une valeur de différence de résistance est obtenue en fournissant différents nombres de résistances, ce qui permet de calculer avec précision les valeurs de résistance d'un matériau à changement de phase et d'un dispositif de chauffage.
PCT/CN2020/130937 2020-11-23 2020-11-23 Structure de test et procédé de test WO2022104805A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2020/130937 WO2022104805A1 (fr) 2020-11-23 2020-11-23 Structure de test et procédé de test
CN202080099894.8A CN115485833A (zh) 2020-11-23 2020-11-23 测试结构以及测试方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/130937 WO2022104805A1 (fr) 2020-11-23 2020-11-23 Structure de test et procédé de test

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WO2022104805A1 true WO2022104805A1 (fr) 2022-05-27

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CN (1) CN115485833A (fr)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116381345A (zh) * 2022-07-21 2023-07-04 微龛(广州)半导体有限公司 薄膜电阻测量结构、测量方法及测量系统

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101271873A (zh) * 2007-03-19 2008-09-24 台湾积体电路制造股份有限公司 半导体晶粒与封装结构
US20120062268A1 (en) * 2010-09-14 2012-03-15 Stmicroelectronics Pvt Ltd. Method and device for measuring the reliability of an integrated circuit
CN103187403A (zh) * 2011-12-31 2013-07-03 中芯国际集成电路制造(上海)有限公司 半导体失效分析结构及形成方法、检测失效时间的方法
CN104051021A (zh) * 2014-06-10 2014-09-17 华中科技大学 一种相变存储器热串扰测试方法
CN104779238A (zh) * 2014-01-10 2015-07-15 中芯国际集成电路制造(上海)有限公司 一种晶圆接合质量的检测结构及检测方法
CN211743145U (zh) * 2020-02-12 2020-10-23 江苏时代全芯存储科技股份有限公司 测试结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101271873A (zh) * 2007-03-19 2008-09-24 台湾积体电路制造股份有限公司 半导体晶粒与封装结构
US20120062268A1 (en) * 2010-09-14 2012-03-15 Stmicroelectronics Pvt Ltd. Method and device for measuring the reliability of an integrated circuit
CN103187403A (zh) * 2011-12-31 2013-07-03 中芯国际集成电路制造(上海)有限公司 半导体失效分析结构及形成方法、检测失效时间的方法
CN104779238A (zh) * 2014-01-10 2015-07-15 中芯国际集成电路制造(上海)有限公司 一种晶圆接合质量的检测结构及检测方法
CN104051021A (zh) * 2014-06-10 2014-09-17 华中科技大学 一种相变存储器热串扰测试方法
CN211743145U (zh) * 2020-02-12 2020-10-23 江苏时代全芯存储科技股份有限公司 测试结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116381345A (zh) * 2022-07-21 2023-07-04 微龛(广州)半导体有限公司 薄膜电阻测量结构、测量方法及测量系统
CN116381345B (zh) * 2022-07-21 2023-10-31 微龛(广州)半导体有限公司 薄膜电阻测量结构、测量方法及测量系统

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